Add support for board based on the popular Altera Cyclone V SoC. This board has the following properties: - 1 GiB of DRAM - 1 Gigabit ethernet - 1 USB gadget port - 1 USB host port with an on-board hub - 2 QSPI NORs connected to the Cadence QSPI core - Multiple I2C EEPROMs and one I2C temperature sensor Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> --- V2: Update the defconfig as per Tom's requestmaster
parent
8b528709c5
commit
569a191a86
@ -0,0 +1,113 @@ |
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/* |
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* Copyright (C) 2015 Marek Vasut <marex@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include "socfpga_cyclone5.dtsi" |
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/ { |
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model = "samtec VIN|ING FPGA"; |
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compatible = "altr,socfpga-cyclone5", "altr,socfpga"; |
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chosen { |
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bootargs = "console=ttyS0,115200"; |
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}; |
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aliases { |
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ethernet0 = &gmac1; |
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udc0 = &usb0; |
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}; |
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memory { |
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name = "memory"; |
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device_type = "memory"; |
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reg = <0x0 0x40000000>; /* 1GB */ |
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}; |
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soc { |
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u-boot,dm-pre-reloc; |
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}; |
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}; |
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&gmac1 { |
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status = "okay"; |
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phy-mode = "rgmii"; |
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rxd0-skew-ps = <0>; |
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rxd1-skew-ps = <0>; |
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rxd2-skew-ps = <0>; |
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rxd3-skew-ps = <0>; |
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txen-skew-ps = <0>; |
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txc-skew-ps = <2600>; |
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rxdv-skew-ps = <0>; |
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rxc-skew-ps = <2000>; |
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}; |
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&gpio0 { |
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status = "okay"; |
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}; |
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&gpio1 { |
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status = "okay"; |
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}; |
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&gpio2 { |
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status = "okay"; |
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}; |
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&i2c0 { |
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status = "okay"; |
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rtc: rtc@68 { |
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compatible = "stm,m41t82"; |
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reg = <0x68>; |
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}; |
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}; |
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|
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&qspi { |
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status = "okay"; |
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u-boot,dm-pre-reloc; |
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flash0: n25q128@0 { |
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u-boot,dm-pre-reloc; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "n25q128", "spi-flash"; |
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reg = <0>; /* chip select */ |
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spi-max-frequency = <50000000>; |
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m25p,fast-read; |
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page-size = <256>; |
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block-size = <16>; /* 2^16, 64KB */ |
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read-delay = <4>; /* delay value in read data capture register */ |
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tshsl-ns = <50>; |
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tsd2d-ns = <50>; |
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tchsh-ns = <4>; |
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tslch-ns = <4>; |
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}; |
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flash1: n25q00@1 { |
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u-boot,dm-pre-reloc; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "n25q00", "spi-flash"; |
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reg = <1>; /* chip select */ |
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spi-max-frequency = <50000000>; |
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m25p,fast-read; |
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page-size = <256>; |
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block-size = <16>; /* 2^16, 64KB */ |
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read-delay = <4>; /* delay value in read data capture register */ |
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tshsl-ns = <50>; |
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tsd2d-ns = <50>; |
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tchsh-ns = <4>; |
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tslch-ns = <4>; |
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}; |
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}; |
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&usb0 { |
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status = "okay"; |
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}; |
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&usb1 { |
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status = "okay"; |
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}; |
@ -0,0 +1,5 @@ |
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VINING FPGA BOARD |
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M: Marek Vasut <marex@denx.de> |
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S: Maintained |
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F: include/configs/socfpga_vining_fpga.h |
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F: configs/socfpga_vining_fpga_defconfig |
@ -0,0 +1,9 @@ |
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#
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# (C) Copyright 2001-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := socfpga.o
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@ -0,0 +1,660 @@ |
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/*
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* Altera SoCFPGA IOCSR configuration |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#ifndef __SOCFPGA_IOCSR_CONFIG_H__ |
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#define __SOCFPGA_IOCSR_CONFIG_H__ |
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#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 |
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#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 |
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#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 |
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#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 |
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const unsigned long iocsr_scan_chain0_table[] = { |
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0x00000000, |
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0x00000000, |
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0x0FF00000, |
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0xC0000000, |
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0x0000003F, |
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0x00008000, |
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0x00060180, |
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0x18060000, |
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0x18000000, |
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0x00018060, |
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0x00000000, |
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0x00004000, |
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0x000300C0, |
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0x0C030000, |
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0x0C000000, |
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0x00000030, |
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0x0000C030, |
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0x00002000, |
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0x00018060, |
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0x06018000, |
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0x06000000, |
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0x00000018, |
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0x00006018, |
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0x00001000, |
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}; |
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const unsigned long iocsr_scan_chain1_table[] = { |
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0x00000000, |
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0x300C0000, |
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0x000000C0, |
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0x00000000, |
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0x00000000, |
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0x00008000, |
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0x00060180, |
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0x18060000, |
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0x18000000, |
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0x00000060, |
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0x00018060, |
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0x00004000, |
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0x000300C0, |
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0x0C030000, |
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0x0C000000, |
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0x00000030, |
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0x0000C030, |
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0x00002000, |
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0x06018060, |
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0x06018000, |
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0x01FE0000, |
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0xF8000000, |
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0x00000007, |
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0x00001000, |
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0x0000C030, |
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0x0300C000, |
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0x03000000, |
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0x0000300C, |
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0x0000300C, |
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0x00000800, |
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0x00000000, |
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0x00000000, |
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0x01800000, |
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0x00000006, |
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0x00601806, |
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0x00000400, |
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0x00000000, |
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0x00C03000, |
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0x00000003, |
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0x00000000, |
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0x00000000, |
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0x00000200, |
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0x00601806, |
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0x00000000, |
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0x80600000, |
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0x80000601, |
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0x00000601, |
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0x00000100, |
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0x00300C03, |
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0xC0300C00, |
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0xC0300000, |
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0xC0000300, |
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0x000C0300, |
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0x00000080, |
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}; |
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const unsigned long iocsr_scan_chain2_table[] = { |
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0x300C0300, |
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0x300C0000, |
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0x0FF00000, |
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0x00000000, |
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0x000300C0, |
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0x00008000, |
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0x18060180, |
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0x18060000, |
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0x00000000, |
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0x00000000, |
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0x00018060, |
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0x00004000, |
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0x000300C0, |
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0x0C030000, |
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0x00000030, |
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0x00000000, |
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0x0300C030, |
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0x00002000, |
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0x00018060, |
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0x06018000, |
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0x06000000, |
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0x00000018, |
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0x00006018, |
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0x00001000, |
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0x0000C030, |
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0x00000000, |
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0x03000000, |
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0x0000000C, |
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0x00C0300C, |
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0x00000800, |
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}; |
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const unsigned long iocsr_scan_chain3_table[] = { |
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0x0C420D80, |
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0x082000FF, |
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0x0A804001, |
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0x07900000, |
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0x08020000, |
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0x00100000, |
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0x0A800000, |
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0x07900000, |
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0x08020000, |
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0x00100000, |
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0xC8800000, |
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0x00003001, |
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0x00C00722, |
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0x00000000, |
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0x00000021, |
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0x82000004, |
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0x05400000, |
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0x03C80000, |
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0x04010000, |
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0x00080000, |
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0x05400000, |
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0x03C80000, |
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0x05400000, |
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0x03C80000, |
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0xE4400000, |
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0x00001800, |
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0x00600391, |
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0x800E4400, |
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0x00000001, |
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0x40000002, |
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0x02A00000, |
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0x01E40000, |
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0x02A00000, |
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0x01E40000, |
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0x02A00000, |
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0x01E40000, |
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0x02A00000, |
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0x01E40000, |
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0x72200000, |
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0x80000C00, |
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0x003001C8, |
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0xC0072200, |
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0x1C880000, |
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0x20000300, |
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0x00040000, |
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0x50670000, |
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0x00000010, |
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0x24590000, |
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0x00001000, |
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0xA0000034, |
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0x0D000001, |
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0x40680A28, |
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0x41034051, |
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0x12481A00, |
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0x80A280D0, |
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0x34051406, |
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0x01A02490, |
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0x080D0000, |
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0x51406802, |
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0x02490340, |
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0xD000001A, |
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0x0680A280, |
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0x10040000, |
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0x00200000, |
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0x10040000, |
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0x00200000, |
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0x15000000, |
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0x0F200000, |
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0x15000000, |
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0x0F200000, |
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0x01FE0000, |
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0x00000000, |
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0x01800E44, |
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0x00391000, |
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0x007F8006, |
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0x00000000, |
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0x0A800001, |
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0x07900000, |
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0x0A800000, |
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0x07900000, |
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0x0A800000, |
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0x07900000, |
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0x08020000, |
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0x00100000, |
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0xC8800000, |
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0x00003001, |
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0x00C00722, |
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0x00000FF0, |
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0x72200000, |
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0x80000C00, |
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0x05400000, |
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0x02480000, |
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0x04000000, |
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0x00080000, |
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0x05400000, |
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0x03C80000, |
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0x05400000, |
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0x03C80000, |
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0x6A1C0000, |
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0x00001800, |
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0x00600391, |
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0x800E4400, |
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0x1A870001, |
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0x40000600, |
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0x02A00040, |
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0x01E40000, |
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0x02A00000, |
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0x01E40000, |
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0x02A00000, |
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0x01E40000, |
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0x02A00000, |
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0x01E40000, |
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0x72200000, |
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0x80000C00, |
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0x003001C8, |
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0xC0072200, |
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0x1C880000, |
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0x20000300, |
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0x00040000, |
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0x50670000, |
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0x00000010, |
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0x24590000, |
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0x00001000, |
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0xA0000034, |
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0x0D000001, |
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0x40680208, |
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0x49034051, |
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0x12481A02, |
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0x80A280D0, |
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0x34030C06, |
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0x01A00040, |
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0x280D0002, |
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0x5140680A, |
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0x02490340, |
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0xD012481A, |
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0x0680A280, |
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0x10040000, |
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0x00200000, |
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0x10040000, |
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0x00200000, |
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0x15000000, |
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0x0F200000, |
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0x15000000, |
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0x0F200000, |
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0x01FE0000, |
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0x00000000, |
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0x01800E44, |
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0x00391000, |
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0x007F8006, |
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0x00000000, |
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0x99300001, |
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0x34343400, |
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0xAA0D4000, |
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0x01C3A800, |
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0xAA0D4000, |
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0x01C3A800, |
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0xAA0D4000, |
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0x01C3A800, |
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0x00040100, |
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0x00000800, |
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0x00000000, |
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0x00001208, |
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0x00482000, |
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0x01000000, |
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0x00000000, |
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0x00410482, |
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0x0006A000, |
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0x0001B400, |
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0x00020000, |
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0x00000400, |
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0x0002A000, |
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0x0001E400, |
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0x5506A000, |
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0x00E1D400, |
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0x00000000, |
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0xC880090C, |
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0x00003001, |
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0x90400000, |
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0x00000000, |
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0x2020C243, |
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0x2A835000, |
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0x0070EA00, |
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0x2A835000, |
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0x0070EA00, |
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0x2A835000, |
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0x0070EA00, |
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0x00010040, |
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0x00000200, |
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0x00000000, |
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0x00000482, |
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0x00120800, |
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0x00002000, |
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0x80000000, |
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0x00104120, |
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0x00000200, |
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0xAC0D5F80, |
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0x7FFFFFFF, |
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0x14F36080, |
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0x1A041404, |
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0x00D00000, |
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0x14864000, |
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0x59647A05, |
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0x8A28A3D5, |
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0xF6D1451E, |
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0x034AD348, |
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0x821A0000, |
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0x0000D000, |
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0x05140680, |
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0xD569A47A, |
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0x1E8A28A3, |
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0x48F6D145, |
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0x00035292, |
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0x00080200, |
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0x00001000, |
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0x00080200, |
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0x00001000, |
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0x000A8000, |
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0x00075000, |
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0x541A8000, |
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0x03875001, |
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0x10000000, |
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0x00000000, |
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0x0080C000, |
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0x41000000, |
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0x00003FC2, |
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0x00820000, |
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0xAA0D4000, |
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0x01C3A800, |
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0xAA0D4000, |
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0x01C3A800, |
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0xAA0D4000, |
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0x01C3A800, |
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0x00040100, |
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0x00000800, |
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0x00000000, |
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0x00001208, |
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0x00482000, |
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0x00008000, |
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0x00000000, |
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0x00410482, |
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0x0006A000, |
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0x0001B400, |
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0x00020000, |
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0x00000400, |
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0x00020080, |
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0x00000400, |
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0x5506A000, |
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0x00E1D400, |
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0x00000000, |
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0x0000090C, |
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0x00000010, |
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0x90400000, |
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0x00000000, |
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0x2020C243, |
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0x2A835000, |
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0x0070EA00, |
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0x2A835000, |
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0x0070EA00, |
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0x2A835000, |
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0x0070EA00, |
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0x00015000, |
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0x0000F200, |
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0x00000000, |
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0x00000482, |
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0x00120800, |
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0x00600391, |
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0x80000000, |
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0x00104120, |
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0x00000200, |
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0xAC0D5F80, |
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0x7FFFFFFF, |
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0x14F36080, |
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0x1A041404, |
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0x00D00000, |
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0x14864000, |
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0x59647A05, |
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0x8A28A3D5, |
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0xF4D1451E, |
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0x034AD348, |
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0x821A0186, |
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0x0000D000, |
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0x00000680, |
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0xD569A47A, |
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0x1EF228A3, |
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0x48F4D145, |
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0x00034AD3, |
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0x00080200, |
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0x00001000, |
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0x00080200, |
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0x00001000, |
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0x000A8000, |
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0x00075000, |
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0x541A8000, |
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0x03875001, |
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0x10000000, |
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0x00000000, |
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0x0080C000, |
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0x41000000, |
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0x04000002, |
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0x00820000, |
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0xAA0D4000, |
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0x01C3A800, |
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0xAA0D4000, |
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0x01C3A800, |
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0xAA0D4000, |
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0x01C3A800, |
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0x00040100, |
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0x00000800, |
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0x00000000, |
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0x00001208, |
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0x00482000, |
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0x00008000, |
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0x00000000, |
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0x00410482, |
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0x0006A000, |
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0x0001B400, |
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0x00020000, |
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0x00000400, |
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0x0002A000, |
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0x0001E400, |
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0x5506A000, |
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0x00E1D400, |
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0x00000000, |
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0xC880090C, |
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0x00003001, |
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0x90400000, |
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0x00000000, |
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0x2020C243, |
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0x2A835000, |
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0x0070EA00, |
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0x2A835000, |
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0x0070EA00, |
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0x2A835000, |
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0x0070EA00, |
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0x00010040, |
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0x00000200, |
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0x00000000, |
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0x00000482, |
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0x00120800, |
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0x00002000, |
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0x80000000, |
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0x00104120, |
||||
0x00000200, |
||||
0xAC0D5F80, |
||||
0x7FFFFFFF, |
||||
0x14F36080, |
||||
0x1A041404, |
||||
0x00D00000, |
||||
0x0C864000, |
||||
0x59647A03, |
||||
0xCB2CA3DD, |
||||
0xF6D9651E, |
||||
0x034AD348, |
||||
0x821A0000, |
||||
0x0000D000, |
||||
0x00000680, |
||||
0xDD59647A, |
||||
0x1E8A28A3, |
||||
0x48F6D965, |
||||
0x00034AD3, |
||||
0x00080200, |
||||
0x00001000, |
||||
0x00080200, |
||||
0x00001000, |
||||
0x000A8000, |
||||
0x00075000, |
||||
0x541A8000, |
||||
0x03875001, |
||||
0x10000000, |
||||
0x00000000, |
||||
0x0080C000, |
||||
0x41000000, |
||||
0x04000002, |
||||
0x00820000, |
||||
0xAA0D4000, |
||||
0x01C3A800, |
||||
0xAA0D4000, |
||||
0x01C3A800, |
||||
0xAA0D4000, |
||||
0x01C3A800, |
||||
0x00040100, |
||||
0x00000800, |
||||
0x00000000, |
||||
0x00001208, |
||||
0x00482000, |
||||
0x00008000, |
||||
0x00000000, |
||||
0x00410482, |
||||
0x0006A000, |
||||
0x0001B400, |
||||
0x00020000, |
||||
0x00000400, |
||||
0x00020080, |
||||
0x00000400, |
||||
0x5506A000, |
||||
0x00E1D400, |
||||
0x00000000, |
||||
0x0000090C, |
||||
0x00000010, |
||||
0x90400000, |
||||
0x00000000, |
||||
0x2020C243, |
||||
0x2A835000, |
||||
0x0070EA00, |
||||
0x2A835000, |
||||
0x0070EA00, |
||||
0x2A835000, |
||||
0x0070EA00, |
||||
0x00010040, |
||||
0x00000200, |
||||
0x00000000, |
||||
0x00000482, |
||||
0x00120800, |
||||
0x00400000, |
||||
0x80000000, |
||||
0x00104120, |
||||
0x00000200, |
||||
0xAC0D5F80, |
||||
0x7FFFFFFF, |
||||
0x14F16080, |
||||
0x1A041404, |
||||
0x00D00000, |
||||
0x04864000, |
||||
0x69A47A01, |
||||
0xF228A3D5, |
||||
0xF4D1451E, |
||||
0x03529248, |
||||
0x821A0000, |
||||
0x0000D000, |
||||
0x00000680, |
||||
0xD559647A, |
||||
0x1E8A28A3, |
||||
0x48F6D145, |
||||
0x00034AD3, |
||||
0x00080200, |
||||
0x00001000, |
||||
0x00080200, |
||||
0x00001000, |
||||
0x000A8000, |
||||
0x00075000, |
||||
0x541A8000, |
||||
0x03875001, |
||||
0x10000000, |
||||
0x00000000, |
||||
0x0080C000, |
||||
0x41000000, |
||||
0x04000002, |
||||
0x00820000, |
||||
0x00489800, |
||||
0x801A1A1A, |
||||
0x00000200, |
||||
0x80000004, |
||||
0x00000200, |
||||
0x80000004, |
||||
0x00000200, |
||||
0x80000004, |
||||
0x00000200, |
||||
0x00000004, |
||||
0x00040000, |
||||
0x10000000, |
||||
0x00000000, |
||||
0x00000040, |
||||
0x00010000, |
||||
0x40002000, |
||||
0x00000100, |
||||
0x40000002, |
||||
0x00000100, |
||||
0x40000002, |
||||
0x00000100, |
||||
0x40000002, |
||||
0x00000100, |
||||
0x00000002, |
||||
0x00020000, |
||||
0x08000000, |
||||
0x00000000, |
||||
0x00000020, |
||||
0x00008000, |
||||
0x20001000, |
||||
0x00000080, |
||||
0x20000001, |
||||
0x00000080, |
||||
0x20000001, |
||||
0x00000080, |
||||
0x20000001, |
||||
0x00000080, |
||||
0x00000001, |
||||
0x00010000, |
||||
0x04000000, |
||||
0x00FF0000, |
||||
0x00000000, |
||||
0x00004000, |
||||
0x00000800, |
||||
0xC0000001, |
||||
0x00041419, |
||||
0x40000000, |
||||
0x04000816, |
||||
0x000D0000, |
||||
0x00006800, |
||||
0x00000340, |
||||
0xD000001A, |
||||
0x06800000, |
||||
0x00340000, |
||||
0x0001A000, |
||||
0x00000D00, |
||||
0x40000068, |
||||
0x1A000003, |
||||
0x00D00000, |
||||
0x00068000, |
||||
0x00003400, |
||||
0x000001A0, |
||||
0x00000401, |
||||
0x00000008, |
||||
0x00000401, |
||||
0x00000008, |
||||
0x00000401, |
||||
0x00000008, |
||||
0x00000401, |
||||
0x80000008, |
||||
0x0000007F, |
||||
0x20000000, |
||||
0x00000000, |
||||
0xE0000080, |
||||
0x0000001F, |
||||
0x00004000, |
||||
}; |
||||
|
||||
|
||||
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ |
@ -0,0 +1,219 @@ |
||||
/*
|
||||
* Altera SoCFPGA PinMux configuration |
||||
* |
||||
* SPDX-License-Identifier: BSD-3-Clause |
||||
*/ |
||||
|
||||
#ifndef __SOCFPGA_PINMUX_CONFIG_H__ |
||||
#define __SOCFPGA_PINMUX_CONFIG_H__ |
||||
|
||||
const u8 sys_mgr_init_table[] = { |
||||
0, /* EMACIO0 */ |
||||
2, /* EMACIO1 */ |
||||
2, /* EMACIO2 */ |
||||
2, /* EMACIO3 */ |
||||
2, /* EMACIO4 */ |
||||
2, /* EMACIO5 */ |
||||
2, /* EMACIO6 */ |
||||
2, /* EMACIO7 */ |
||||
2, /* EMACIO8 */ |
||||
0, /* EMACIO9 */ |
||||
2, /* EMACIO10 */ |
||||
2, /* EMACIO11 */ |
||||
2, /* EMACIO12 */ |
||||
2, /* EMACIO13 */ |
||||
0, /* EMACIO14 */ |
||||
0, /* EMACIO15 */ |
||||
0, /* EMACIO16 */ |
||||
0, /* EMACIO17 */ |
||||
0, /* EMACIO18 */ |
||||
0, /* EMACIO19 */ |
||||
2, /* FLASHIO0 */ |
||||
2, /* FLASHIO1 */ |
||||
2, /* FLASHIO2 */ |
||||
2, /* FLASHIO3 */ |
||||
2, /* FLASHIO4 */ |
||||
2, /* FLASHIO5 */ |
||||
2, /* FLASHIO6 */ |
||||
2, /* FLASHIO7 */ |
||||
2, /* FLASHIO8 */ |
||||
2, /* FLASHIO9 */ |
||||
2, /* FLASHIO10 */ |
||||
2, /* FLASHIO11 */ |
||||
0, /* GENERALIO0 */ |
||||
1, /* GENERALIO1 */ |
||||
1, /* GENERALIO2 */ |
||||
1, /* GENERALIO3 */ |
||||
1, /* GENERALIO4 */ |
||||
0, /* GENERALIO5 */ |
||||
0, /* GENERALIO6 */ |
||||
1, /* GENERALIO7 */ |
||||
1, /* GENERALIO8 */ |
||||
3, /* GENERALIO9 */ |
||||
3, /* GENERALIO10 */ |
||||
3, /* GENERALIO11 */ |
||||
3, /* GENERALIO12 */ |
||||
0, /* GENERALIO13 */ |
||||
0, /* GENERALIO14 */ |
||||
2, /* GENERALIO15 */ |
||||
2, /* GENERALIO16 */ |
||||
0, /* GENERALIO17 */ |
||||
0, /* GENERALIO18 */ |
||||
0, /* GENERALIO19 */ |
||||
0, /* GENERALIO20 */ |
||||
0, /* GENERALIO21 */ |
||||
0, /* GENERALIO22 */ |
||||
0, /* GENERALIO23 */ |
||||
0, /* GENERALIO24 */ |
||||
0, /* GENERALIO25 */ |
||||
0, /* GENERALIO26 */ |
||||
0, /* GENERALIO27 */ |
||||
0, /* GENERALIO28 */ |
||||
0, /* GENERALIO29 */ |
||||
0, /* GENERALIO30 */ |
||||
0, /* GENERALIO31 */ |
||||
2, /* MIXED1IO0 */ |
||||
2, /* MIXED1IO1 */ |
||||
2, /* MIXED1IO2 */ |
||||
2, /* MIXED1IO3 */ |
||||
2, /* MIXED1IO4 */ |
||||
2, /* MIXED1IO5 */ |
||||
2, /* MIXED1IO6 */ |
||||
2, /* MIXED1IO7 */ |
||||
2, /* MIXED1IO8 */ |
||||
2, /* MIXED1IO9 */ |
||||
2, /* MIXED1IO10 */ |
||||
2, /* MIXED1IO11 */ |
||||
2, /* MIXED1IO12 */ |
||||
2, /* MIXED1IO13 */ |
||||
2, /* MIXED1IO14 */ |
||||
3, /* MIXED1IO15 */ |
||||
3, /* MIXED1IO16 */ |
||||
3, /* MIXED1IO17 */ |
||||
3, /* MIXED1IO18 */ |
||||
3, /* MIXED1IO19 */ |
||||
3, /* MIXED1IO20 */ |
||||
0, /* MIXED1IO21 */ |
||||
0, /* MIXED2IO0 */ |
||||
0, /* MIXED2IO1 */ |
||||
0, /* MIXED2IO2 */ |
||||
0, /* MIXED2IO3 */ |
||||
0, /* MIXED2IO4 */ |
||||
0, /* MIXED2IO5 */ |
||||
0, /* MIXED2IO6 */ |
||||
0, /* MIXED2IO7 */ |
||||
0, /* GPLINMUX48 */ |
||||
0, /* GPLINMUX49 */ |
||||
0, /* GPLINMUX50 */ |
||||
0, /* GPLINMUX51 */ |
||||
0, /* GPLINMUX52 */ |
||||
0, /* GPLINMUX53 */ |
||||
0, /* GPLINMUX54 */ |
||||
0, /* GPLINMUX55 */ |
||||
0, /* GPLINMUX56 */ |
||||
0, /* GPLINMUX57 */ |
||||
0, /* GPLINMUX58 */ |
||||
0, /* GPLINMUX59 */ |
||||
0, /* GPLINMUX60 */ |
||||
0, /* GPLINMUX61 */ |
||||
0, /* GPLINMUX62 */ |
||||
0, /* GPLINMUX63 */ |
||||
0, /* GPLINMUX64 */ |
||||
0, /* GPLINMUX65 */ |
||||
0, /* GPLINMUX66 */ |
||||
0, /* GPLINMUX67 */ |
||||
0, /* GPLINMUX68 */ |
||||
0, /* GPLINMUX69 */ |
||||
0, /* GPLINMUX70 */ |
||||
1, /* GPLMUX0 */ |
||||
1, /* GPLMUX1 */ |
||||
1, /* GPLMUX2 */ |
||||
1, /* GPLMUX3 */ |
||||
1, /* GPLMUX4 */ |
||||
1, /* GPLMUX5 */ |
||||
1, /* GPLMUX6 */ |
||||
1, /* GPLMUX7 */ |
||||
1, /* GPLMUX8 */ |
||||
1, /* GPLMUX9 */ |
||||
1, /* GPLMUX10 */ |
||||
1, /* GPLMUX11 */ |
||||
1, /* GPLMUX12 */ |
||||
1, /* GPLMUX13 */ |
||||
1, /* GPLMUX14 */ |
||||
1, /* GPLMUX15 */ |
||||
1, /* GPLMUX16 */ |
||||
1, /* GPLMUX17 */ |
||||
1, /* GPLMUX18 */ |
||||
1, /* GPLMUX19 */ |
||||
1, /* GPLMUX20 */ |
||||
1, /* GPLMUX21 */ |
||||
1, /* GPLMUX22 */ |
||||
1, /* GPLMUX23 */ |
||||
1, /* GPLMUX24 */ |
||||
1, /* GPLMUX25 */ |
||||
1, /* GPLMUX26 */ |
||||
1, /* GPLMUX27 */ |
||||
1, /* GPLMUX28 */ |
||||
1, /* GPLMUX29 */ |
||||
1, /* GPLMUX30 */ |
||||
1, /* GPLMUX31 */ |
||||
1, /* GPLMUX32 */ |
||||
1, /* GPLMUX33 */ |
||||
1, /* GPLMUX34 */ |
||||
1, /* GPLMUX35 */ |
||||
1, /* GPLMUX36 */ |
||||
1, /* GPLMUX37 */ |
||||
1, /* GPLMUX38 */ |
||||
1, /* GPLMUX39 */ |
||||
1, /* GPLMUX40 */ |
||||
1, /* GPLMUX41 */ |
||||
1, /* GPLMUX42 */ |
||||
1, /* GPLMUX43 */ |
||||
1, /* GPLMUX44 */ |
||||
1, /* GPLMUX45 */ |
||||
1, /* GPLMUX46 */ |
||||
1, /* GPLMUX47 */ |
||||
1, /* GPLMUX48 */ |
||||
1, /* GPLMUX49 */ |
||||
1, /* GPLMUX50 */ |
||||
1, /* GPLMUX51 */ |
||||
1, /* GPLMUX52 */ |
||||
1, /* GPLMUX53 */ |
||||
1, /* GPLMUX54 */ |
||||
1, /* GPLMUX55 */ |
||||
1, /* GPLMUX56 */ |
||||
1, /* GPLMUX57 */ |
||||
1, /* GPLMUX58 */ |
||||
1, /* GPLMUX59 */ |
||||
1, /* GPLMUX60 */ |
||||
1, /* GPLMUX61 */ |
||||
1, /* GPLMUX62 */ |
||||
1, /* GPLMUX63 */ |
||||
1, /* GPLMUX64 */ |
||||
1, /* GPLMUX65 */ |
||||
1, /* GPLMUX66 */ |
||||
1, /* GPLMUX67 */ |
||||
1, /* GPLMUX68 */ |
||||
1, /* GPLMUX69 */ |
||||
1, /* GPLMUX70 */ |
||||
0, /* NANDUSEFPGA */ |
||||
0, /* UART0USEFPGA */ |
||||
0, /* RGMII1USEFPGA */ |
||||
1, /* SPIS0USEFPGA */ |
||||
0, /* CAN0USEFPGA */ |
||||
0, /* I2C0USEFPGA */ |
||||
0, /* SDMMCUSEFPGA */ |
||||
0, /* QSPIUSEFPGA */ |
||||
1, /* SPIS1USEFPGA */ |
||||
1, /* RGMII0USEFPGA */ |
||||
0, /* UART1USEFPGA */ |
||||
0, /* CAN1USEFPGA */ |
||||
0, /* USB1USEFPGA */ |
||||
0, /* I2C3USEFPGA */ |
||||
0, /* I2C2USEFPGA */ |
||||
0, /* I2C1USEFPGA */ |
||||
0, /* SPIM1USEFPGA */ |
||||
0, /* USB0USEFPGA */ |
||||
0 /* SPIM0USEFPGA */ |
||||
}; |
||||
#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ |
@ -0,0 +1,91 @@ |
||||
/*
|
||||
* Altera SoCFPGA Clock and PLL configuration |
||||
* |
||||
* SPDX-License-Identifier: BSD-3-Clause |
||||
*/ |
||||
|
||||
#ifndef __SOCFPGA_PLL_CONFIG_H__ |
||||
#define __SOCFPGA_PLL_CONFIG_H__ |
||||
|
||||
#define CONFIG_HPS_DBCTRL_STAYOSC1 1 |
||||
|
||||
#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 |
||||
#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 |
||||
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 |
||||
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 |
||||
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 |
||||
#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 |
||||
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 |
||||
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 |
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 |
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 |
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 |
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 |
||||
#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 |
||||
#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 |
||||
#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 |
||||
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 |
||||
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 |
||||
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 |
||||
#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 |
||||
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 |
||||
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 |
||||
#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 |
||||
#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 |
||||
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511 |
||||
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 |
||||
#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 |
||||
#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 |
||||
#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 |
||||
#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 |
||||
#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 |
||||
#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 |
||||
#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 |
||||
#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 |
||||
#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 |
||||
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 |
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 |
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 |
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 |
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 |
||||
#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 |
||||
#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 |
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 |
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 |
||||
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 |
||||
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 |
||||
|
||||
#define CONFIG_HPS_CLK_OSC1_HZ 25000000 |
||||
#define CONFIG_HPS_CLK_OSC2_HZ 25000000 |
||||
#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 |
||||
#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 |
||||
#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 |
||||
#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 |
||||
#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 |
||||
#define CONFIG_HPS_CLK_OSC1_HZ 25000000 |
||||
#define CONFIG_HPS_CLK_OSC2_HZ 25000000 |
||||
#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 |
||||
#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 |
||||
#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 |
||||
#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 |
||||
#define CONFIG_HPS_CLK_EMAC0_HZ 250000000 |
||||
#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 |
||||
#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 |
||||
#define CONFIG_HPS_CLK_NAND_HZ 488281 |
||||
#define CONFIG_HPS_CLK_SDMMC_HZ 1953125 |
||||
#define CONFIG_HPS_CLK_QSPI_HZ 400000000 |
||||
#define CONFIG_HPS_CLK_SPIM_HZ 200000000 |
||||
#define CONFIG_HPS_CLK_CAN0_HZ 12500000 |
||||
#define CONFIG_HPS_CLK_CAN1_HZ 12500000 |
||||
#define CONFIG_HPS_CLK_GPIODB_HZ 32000 |
||||
#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 |
||||
#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 |
||||
|
||||
#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 |
||||
#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 |
||||
#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 |
||||
|
||||
|
||||
#endif /* __SOCFPGA_PLL_CONFIG_H__ */ |
@ -0,0 +1,341 @@ |
||||
/*
|
||||
* Altera SoCFPGA SDRAM configuration |
||||
* |
||||
* SPDX-License-Identifier: BSD-3-Clause |
||||
*/ |
||||
|
||||
#ifndef __SOCFPGA_SDRAM_CONFIG_H__ |
||||
#define __SOCFPGA_SDRAM_CONFIG_H__ |
||||
|
||||
/* SDRAM configuration */ |
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A |
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 6 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 6 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 |
||||
#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 |
||||
|
||||
/* Sequencer auto configuration */ |
||||
#define RW_MGR_ACTIVATE_0_AND_1 0x0D |
||||
#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E |
||||
#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 |
||||
#define RW_MGR_ACTIVATE_1 0x0F |
||||
#define RW_MGR_CLEAR_DQS_ENABLE 0x49 |
||||
#define RW_MGR_GUARANTEED_READ 0x4C |
||||
#define RW_MGR_GUARANTEED_READ_CONT 0x54 |
||||
#define RW_MGR_GUARANTEED_WRITE 0x18 |
||||
#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B |
||||
#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F |
||||
#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 |
||||
#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D |
||||
#define RW_MGR_IDLE 0x00 |
||||
#define RW_MGR_IDLE_LOOP1 0x7B |
||||
#define RW_MGR_IDLE_LOOP2 0x7A |
||||
#define RW_MGR_INIT_RESET_0_CKE_0 0x6F |
||||
#define RW_MGR_INIT_RESET_1_CKE_0 0x74 |
||||
#define RW_MGR_LFSR_WR_RD_BANK_0 0x22 |
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 |
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 |
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 |
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 |
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 |
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 |
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 |
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 |
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 |
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 |
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 |
||||
#define RW_MGR_MRS0_DLL_RESET 0x02 |
||||
#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 |
||||
#define RW_MGR_MRS0_USER 0x07 |
||||
#define RW_MGR_MRS0_USER_MIRR 0x0C |
||||
#define RW_MGR_MRS1 0x03 |
||||
#define RW_MGR_MRS1_MIRR 0x09 |
||||
#define RW_MGR_MRS2 0x04 |
||||
#define RW_MGR_MRS2_MIRR 0x0A |
||||
#define RW_MGR_MRS3 0x05 |
||||
#define RW_MGR_MRS3_MIRR 0x0B |
||||
#define RW_MGR_PRECHARGE_ALL 0x12 |
||||
#define RW_MGR_READ_B2B 0x59 |
||||
#define RW_MGR_READ_B2B_WAIT1 0x61 |
||||
#define RW_MGR_READ_B2B_WAIT2 0x6B |
||||
#define RW_MGR_REFRESH_ALL 0x14 |
||||
#define RW_MGR_RETURN 0x01 |
||||
#define RW_MGR_SGLE_READ 0x7D |
||||
#define RW_MGR_ZQCL 0x06 |
||||
|
||||
/* Sequencer defines configuration */ |
||||
#define AFI_RATE_RATIO 1 |
||||
#define CALIB_LFIFO_OFFSET 7 |
||||
#define CALIB_VFIFO_OFFSET 5 |
||||
#define ENABLE_SUPER_QUICK_CALIBRATION 0 |
||||
#define IO_DELAY_PER_DCHAIN_TAP 25 |
||||
#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 |
||||
#define IO_DELAY_PER_OPA_TAP 312 |
||||
#define IO_DLL_CHAIN_LENGTH 8 |
||||
#define IO_DQDQS_OUT_PHASE_MAX 0 |
||||
#define IO_DQS_EN_DELAY_MAX 31 |
||||
#define IO_DQS_EN_DELAY_OFFSET 0 |
||||
#define IO_DQS_EN_PHASE_MAX 7 |
||||
#define IO_DQS_IN_DELAY_MAX 31 |
||||
#define IO_DQS_IN_RESERVE 4 |
||||
#define IO_DQS_OUT_RESERVE 4 |
||||
#define IO_IO_IN_DELAY_MAX 31 |
||||
#define IO_IO_OUT1_DELAY_MAX 31 |
||||
#define IO_IO_OUT2_DELAY_MAX 0 |
||||
#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 |
||||
#define MAX_LATENCY_COUNT_WIDTH 5 |
||||
#define READ_VALID_FIFO_SIZE 16 |
||||
#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c |
||||
#define RW_MGR_MEM_ADDRESS_MIRRORING 0 |
||||
#define RW_MGR_MEM_DATA_MASK_WIDTH 4 |
||||
#define RW_MGR_MEM_DATA_WIDTH 32 |
||||
#define RW_MGR_MEM_DQ_PER_READ_DQS 8 |
||||
#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 |
||||
#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 |
||||
#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 |
||||
#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 |
||||
#define RW_MGR_MEM_NUMBER_OF_RANKS 1 |
||||
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 |
||||
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 |
||||
#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 |
||||
#define TINIT_CNTR0_VAL 99 |
||||
#define TINIT_CNTR1_VAL 32 |
||||
#define TINIT_CNTR2_VAL 32 |
||||
#define TRESET_CNTR0_VAL 99 |
||||
#define TRESET_CNTR1_VAL 99 |
||||
#define TRESET_CNTR2_VAL 10 |
||||
|
||||
/* Sequencer ac_rom_init configuration */ |
||||
const u32 ac_rom_init[] = { |
||||
0x20700000, |
||||
0x20780000, |
||||
0x10080421, |
||||
0x10080520, |
||||
0x10090046, |
||||
0x100a0088, |
||||
0x100b0000, |
||||
0x10380400, |
||||
0x10080441, |
||||
0x100804c0, |
||||
0x100a0026, |
||||
0x10090110, |
||||
0x100b0000, |
||||
0x30780000, |
||||
0x38780000, |
||||
0x30780000, |
||||
0x10680000, |
||||
0x106b0000, |
||||
0x10280400, |
||||
0x10480000, |
||||
0x1c980000, |
||||
0x1c9b0000, |
||||
0x1c980008, |
||||
0x1c9b0008, |
||||
0x38f80000, |
||||
0x3cf80000, |
||||
0x38780000, |
||||
0x18180000, |
||||
0x18980000, |
||||
0x13580000, |
||||
0x135b0000, |
||||
0x13580008, |
||||
0x135b0008, |
||||
0x33780000, |
||||
0x10580008, |
||||
0x10780000 |
||||
}; |
||||
|
||||
/* Sequencer inst_rom_init configuration */ |
||||
const u32 inst_rom_init[] = { |
||||
0x80000, |
||||
0x80680, |
||||
0x8180, |
||||
0x8200, |
||||
0x8280, |
||||
0x8300, |
||||
0x8380, |
||||
0x8100, |
||||
0x8480, |
||||
0x8500, |
||||
0x8580, |
||||
0x8600, |
||||
0x8400, |
||||
0x800, |
||||
0x8680, |
||||
0x880, |
||||
0xa680, |
||||
0x80680, |
||||
0x900, |
||||
0x80680, |
||||
0x980, |
||||
0xa680, |
||||
0x8680, |
||||
0x80680, |
||||
0xb68, |
||||
0xcce8, |
||||
0xae8, |
||||
0x8ce8, |
||||
0xb88, |
||||
0xec88, |
||||
0xa08, |
||||
0xac88, |
||||
0x80680, |
||||
0xce00, |
||||
0xcd80, |
||||
0xe700, |
||||
0xc00, |
||||
0x20ce0, |
||||
0x20ce0, |
||||
0x20ce0, |
||||
0x20ce0, |
||||
0xd00, |
||||
0x680, |
||||
0x680, |
||||
0x680, |
||||
0x680, |
||||
0x60e80, |
||||
0x61080, |
||||
0x61080, |
||||
0x61080, |
||||
0xa680, |
||||
0x8680, |
||||
0x80680, |
||||
0xce00, |
||||
0xcd80, |
||||
0xe700, |
||||
0xc00, |
||||
0x30ce0, |
||||
0x30ce0, |
||||
0x30ce0, |
||||
0x30ce0, |
||||
0xd00, |
||||
0x680, |
||||
0x680, |
||||
0x680, |
||||
0x680, |
||||
0x70e80, |
||||
0x71080, |
||||
0x71080, |
||||
0x71080, |
||||
0xa680, |
||||
0x8680, |
||||
0x80680, |
||||
0x1158, |
||||
0x6d8, |
||||
0x80680, |
||||
0x1168, |
||||
0x7e8, |
||||
0x7e8, |
||||
0x87e8, |
||||
0x40fe8, |
||||
0x410e8, |
||||
0x410e8, |
||||
0x410e8, |
||||
0x1168, |
||||
0x7e8, |
||||
0x7e8, |
||||
0xa7e8, |
||||
0x80680, |
||||
0x40e88, |
||||
0x41088, |
||||
0x41088, |
||||
0x41088, |
||||
0x40f68, |
||||
0x410e8, |
||||
0x410e8, |
||||
0x410e8, |
||||
0xa680, |
||||
0x40fe8, |
||||
0x410e8, |
||||
0x410e8, |
||||
0x410e8, |
||||
0x41008, |
||||
0x41088, |
||||
0x41088, |
||||
0x41088, |
||||
0x1100, |
||||
0xc680, |
||||
0x8680, |
||||
0xe680, |
||||
0x80680, |
||||
0x0, |
||||
0x8000, |
||||
0xa000, |
||||
0xc000, |
||||
0x80000, |
||||
0x80, |
||||
0x8080, |
||||
0xa080, |
||||
0xc080, |
||||
0x80080, |
||||
0x9180, |
||||
0x8680, |
||||
0xa680, |
||||
0x80680, |
||||
0x40f08, |
||||
0x80680 |
||||
}; |
||||
|
||||
#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ |
@ -0,0 +1,100 @@ |
||||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/reset_manager.h> |
||||
#include <asm/io.h> |
||||
#include <asm/gpio.h> |
||||
#include <i2c.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/*
|
||||
* Miscellaneous platform dependent initialisations |
||||
*/ |
||||
int board_late_init(void) |
||||
{ |
||||
const unsigned int phy_nrst_gpio = 0; |
||||
const unsigned int usb_nrst_gpio = 35; |
||||
int ret; |
||||
|
||||
status_led_set(1, STATUS_LED_ON); |
||||
status_led_set(2, STATUS_LED_ON); |
||||
|
||||
/* Address of boot parameters for ATAG (if ATAG is used) */ |
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
||||
|
||||
ret = gpio_request(phy_nrst_gpio, "phy_nrst_gpio"); |
||||
if (!ret) |
||||
gpio_direction_output(phy_nrst_gpio, 1); |
||||
else |
||||
printf("Cannot remove PHY from reset!\n"); |
||||
|
||||
ret = gpio_request(usb_nrst_gpio, "usb_nrst_gpio"); |
||||
if (!ret) |
||||
gpio_direction_output(usb_nrst_gpio, 1); |
||||
else |
||||
printf("Cannot remove USB from reset!\n"); |
||||
|
||||
mdelay(50); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifndef CONFIG_SPL_BUILD |
||||
int misc_init_r(void) |
||||
{ |
||||
uchar data[128]; |
||||
char str[32]; |
||||
u32 serial; |
||||
int ret; |
||||
|
||||
/* EEPROM is at bus 0. */ |
||||
ret = i2c_set_bus_num(0); |
||||
if (ret) { |
||||
puts("Cannot select EEPROM I2C bus.\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/* EEPROM is at address 0x50. */ |
||||
ret = eeprom_read(0x50, 0, data, sizeof(data)); |
||||
if (ret) { |
||||
puts("Cannot read I2C EEPROM.\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/* Check EEPROM signature. */ |
||||
if (!(data[0] == 0xa5 && data[1] == 0x5a)) { |
||||
puts("Invalid I2C EEPROM signature.\n"); |
||||
setenv("unit_serial", "invalid"); |
||||
setenv("unit_ident", "VINing-xxxx-STD"); |
||||
setenv("hostname", "vining-invalid"); |
||||
return 0; |
||||
} |
||||
|
||||
/* If 'unit_serial' is already set, do nothing. */ |
||||
if (!getenv("unit_serial")) { |
||||
/* This field is Big Endian ! */ |
||||
serial = (data[0x54] << 24) | (data[0x55] << 16) | |
||||
(data[0x56] << 8) | (data[0x57] << 0); |
||||
memset(str, 0, sizeof(str)); |
||||
sprintf(str, "%07i", serial); |
||||
setenv("unit_serial", str); |
||||
} |
||||
|
||||
if (!getenv("unit_ident")) { |
||||
memset(str, 0, sizeof(str)); |
||||
memcpy(str, &data[0x2e], 18); |
||||
setenv("unit_ident", str); |
||||
} |
||||
|
||||
/* Set ethernet address from EEPROM. */ |
||||
if (!getenv("ethaddr") && is_valid_ethaddr(&data[0x62])) |
||||
eth_setenv_enetaddr("ethaddr", &data[0x62]); |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
@ -0,0 +1,55 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_SOCFPGA=y |
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000 |
||||
CONFIG_SPL_DM=y |
||||
CONFIG_DM_GPIO=y |
||||
CONFIG_TARGET_SOCFPGA_SAMTEC_VINING_FPGA=y |
||||
CONFIG_SPL_STACK_R_ADDR=0x00800000 |
||||
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_vining_fpga" |
||||
CONFIG_SPL=y |
||||
CONFIG_SPL_STACK_R=y |
||||
CONFIG_FIT=y |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_CMD_BOOTZ=y |
||||
# CONFIG_CMD_IMLS is not set |
||||
CONFIG_CMD_ASKENV=y |
||||
CONFIG_CMD_GREPENV=y |
||||
# CONFIG_CMD_FLASH is not set |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_SF=y |
||||
CONFIG_CMD_SPI=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_USB=y |
||||
CONFIG_CMD_DFU=y |
||||
CONFIG_CMD_USB_MASS_STORAGE=y |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_MII=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_CMD_TIME=y |
||||
CONFIG_CMD_EXT4=y |
||||
CONFIG_CMD_EXT4_WRITE=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_CMD_FS_GENERIC=y |
||||
CONFIG_NET_RANDOM_ETHADDR=y |
||||
CONFIG_SPL_DM_SEQ_ALIAS=y |
||||
CONFIG_DWAPB_GPIO=y |
||||
CONFIG_DM_MMC=y |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_SPI_FLASH_SPANSION=y |
||||
CONFIG_SPI_FLASH_STMICRO=y |
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set |
||||
CONFIG_DM_ETH=y |
||||
CONFIG_ETH_DESIGNWARE=y |
||||
CONFIG_SYS_NS16550=y |
||||
CONFIG_CADENCE_QSPI=y |
||||
CONFIG_DESIGNWARE_SPI=y |
||||
CONFIG_USB=y |
||||
CONFIG_DM_USB=y |
||||
CONFIG_USB_GADGET=y |
||||
CONFIG_USB_GADGET_DWC2_OTG=y |
||||
CONFIG_USB_GADGET_DOWNLOAD=y |
||||
CONFIG_G_DNL_MANUFACTURER="samtec" |
||||
CONFIG_G_DNL_VENDOR_NUM=0x0525 |
||||
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 |
@ -0,0 +1,231 @@ |
||||
/*
|
||||
* Copyright (C) 2015 Marek Vasut <marex@denx.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#ifndef __CONFIG_SAMTEC_VINING_FPGA_H__ |
||||
#define __CONFIG_SAMTEC_VINING_FPGA_H__ |
||||
|
||||
#include <asm/arch/base_addr_ac5.h> |
||||
|
||||
/* U-Boot Commands */ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_DOS_PARTITION |
||||
#define CONFIG_FAT_WRITE |
||||
#define CONFIG_HW_WATCHDOG |
||||
|
||||
#define CONFIG_CMD_EEPROM |
||||
#define CONFIG_CMD_LED |
||||
|
||||
/* Memory configurations */ |
||||
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on VINING_FPGA */ |
||||
|
||||
/* Booting Linux */ |
||||
#define CONFIG_BOOTDELAY 5 |
||||
#define CONFIG_BOOTFILE "openwrt-socfpga-socfpga_cyclone5_vining_fpga-fit-uImage.itb" |
||||
#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) |
||||
#define CONFIG_BOOTCOMMAND "run selboot" |
||||
#define CONFIG_LOADADDR 0x01000000 |
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
||||
|
||||
/* I2C EEPROM */ |
||||
#ifdef CONFIG_CMD_EEPROM |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
||||
#define CONFIG_SYS_I2C_EEPROM_BUS 0 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 |
||||
#endif |
||||
|
||||
/*
|
||||
* Status LEDs: |
||||
* 0 ... Top Green |
||||
* 1 ... Top Red |
||||
* 2 ... Bottom Green |
||||
* 3 ... Bottom Red |
||||
*/ |
||||
#define CONFIG_STATUS_LED |
||||
#define CONFIG_GPIO_LED |
||||
#define CONFIG_BOARD_SPECIFIC_LED |
||||
#define STATUS_LED_BIT 48 |
||||
#define STATUS_LED_STATE STATUS_LED_OFF |
||||
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) |
||||
#define STATUS_LED_BIT1 53 |
||||
#define STATUS_LED_STATE1 STATUS_LED_OFF |
||||
#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) |
||||
#define STATUS_LED_BIT2 54 |
||||
#define STATUS_LED_STATE2 STATUS_LED_OFF |
||||
#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2) |
||||
#define STATUS_LED_BIT3 65 |
||||
#define STATUS_LED_STATE3 STATUS_LED_OFF |
||||
#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2) |
||||
|
||||
/* Ethernet on SoC (EMAC) */ |
||||
#if defined(CONFIG_CMD_NET) |
||||
#define CONFIG_BOOTP_SEND_HOSTNAME |
||||
/* PHY */ |
||||
#define CONFIG_PHY_MICREL |
||||
#define CONFIG_PHY_MICREL_KSZ9021 |
||||
#endif |
||||
|
||||
/* Extra Environment */ |
||||
#define CONFIG_HOSTNAME socfpga_vining_fpga |
||||
|
||||
/*
|
||||
* Active LOW GPIO buttons: |
||||
* A: GPIO 77 ... the button between USB B and ethernet |
||||
* B: GPIO 78 ... the button between USB A ports |
||||
* |
||||
* The logic: |
||||
* if button B is not pressed, boot normal Linux system immediatelly |
||||
* if button B is pressed, wait $bootdelay and boot recovery system |
||||
*/ |
||||
#define CONFIG_PREBOOT \ |
||||
"setenv hostname vining-${unit_serial} ; " \
|
||||
"setenv PS1 \"${unit_ident} (${unit_serial}) => \" ; " \
|
||||
"if gpio input 78 ; then " \
|
||||
"setenv bootdelay 10 ; " \
|
||||
"setenv boottype rcvr ; " \
|
||||
"else " \
|
||||
"setenv bootdelay 5 ; " \
|
||||
"setenv boottype norm ; " \
|
||||
"fi" |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"verify=n\0" \
|
||||
"consdev=ttyS0\0" \
|
||||
"baudrate=115200\0" \
|
||||
"bootscript=boot.scr\0" \
|
||||
"ubimtdnr=5\0" \
|
||||
"ubimtd=rootfs\0" \
|
||||
"ubipart=ubi0:rootfs\0" \
|
||||
"ubisfcs=1\0" /* Default is flash at CS#1 */ \
|
||||
"netdev=eth0\0" \
|
||||
"hostname=vining_fpga\0" \
|
||||
"kernel_addr_r=0x10000000\0" \
|
||||
"mtdparts_0=ff705000.spi.0:" \
|
||||
"1m(u-boot)," \
|
||||
"64k(env1)," \
|
||||
"64k(env2)," \
|
||||
"256k(samtec1)," \
|
||||
"256k(samtec2)," \
|
||||
"-(rcvrfs)\0" /* Recovery */ \
|
||||
"mtdparts_1=ff705000.spi.1:" \
|
||||
"32m(rootfs)," \
|
||||
"-(userfs)\0" \
|
||||
"update_filename=u-boot-with-spl-dtb.sfp\0" \
|
||||
"update_qspi_offset=0x0\0" \
|
||||
"update_qspi=" /* Update the QSPI firmware */ \
|
||||
"if sf probe ; then " \
|
||||
"if tftp ${update_filename} ; then " \
|
||||
"sf update ${loadaddr} ${update_qspi_offset} ${filesize} ; " \
|
||||
"fi ; " \
|
||||
"fi\0" \
|
||||
"fpga_filename=output_file.rbf\0" \
|
||||
"load_fpga=" /* Load FPGA bitstream */ \
|
||||
"if tftp ${fpga_filename} ; then " \
|
||||
"fpga load 0 $loadaddr $filesize ; " \
|
||||
"bridge enable ; " \
|
||||
"fi\0" \
|
||||
"addcons=" \
|
||||
"setenv bootargs ${bootargs} " \
|
||||
"console=${consdev},${baudrate}\0" \
|
||||
"addip=" \
|
||||
"setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:" \
|
||||
"${netmask}:${hostname}:${netdev}:off\0" \
|
||||
"addmisc=" \
|
||||
"setenv bootargs ${bootargs} ${miscargs}\0" \
|
||||
"addmtd=" \
|
||||
"setenv mtdparts \"${mtdparts_0};${mtdparts_1}\" ; " \
|
||||
"setenv bootargs ${bootargs} mtdparts=${mtdparts}\0" \
|
||||
"addargs=run addcons addmtd addmisc\0" \
|
||||
"ubiload=" \
|
||||
"ubi part ${ubimtd} ; ubifsmount ${ubipart} ; " \
|
||||
"ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \
|
||||
"netload=" \
|
||||
"tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
|
||||
"miscargs=nohlt panic=1\0" \
|
||||
"ubiargs=" \
|
||||
"setenv bootargs ubi.mtd=${ubimtdnr} " \
|
||||
"root=${ubipart} rootfstype=ubifs\0" \
|
||||
"nfsargs=" \
|
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath},v3,tcp\0" \
|
||||
"ubi_sfsel=" \
|
||||
"if test \"${boottype}\" = \"rcvr\" ; then " \
|
||||
"setenv ubisfcs 0 ; " \
|
||||
"setenv ubimtd rcvrfs ; " \
|
||||
"setenv ubimtdnr 5 ; " \
|
||||
"setenv mtdparts mtdparts=${mtdparts_0} ; " \
|
||||
"setenv mtdids nor0=ff705000.spi.0 ; " \
|
||||
"setenv ubipart ubi0:rootfs ; " \
|
||||
"else " \
|
||||
"setenv ubisfcs 1 ; " \
|
||||
"setenv ubimtd rootfs ; " \
|
||||
"setenv ubimtdnr 6 ; " \
|
||||
"setenv mtdparts mtdparts=${mtdparts_1} ; " \
|
||||
"setenv mtdids nor0=ff705000.spi.1 ; " \
|
||||
"setenv ubipart ubi0:rootfs ; " \
|
||||
"fi ; " \
|
||||
"sf probe 0:${ubisfcs}\0" \
|
||||
"ubi_ubi=" \
|
||||
"run ubi_sfsel ubiload ubiargs addargs ; " \
|
||||
"bootm ${kernel_addr_r}\0" \
|
||||
"ubi_nfs=" \
|
||||
"run ubiload nfsargs addip addargs ; " \
|
||||
"bootm ${kernel_addr_r}\0" \
|
||||
"net_ubi=" \
|
||||
"run netload ubiargs addargs ; " \
|
||||
"bootm ${kernel_addr_r}\0" \
|
||||
"net_nfs=" \
|
||||
"run netload nfsargs addip addargs ; " \
|
||||
"bootm ${kernel_addr_r}\0" \
|
||||
"selboot=" /* Select from where to boot. */ \
|
||||
"if test \"${bootmode}\" = \"qspi\" ; then " \
|
||||
"led all off ; " \
|
||||
"if test \"${boottype}\" = \"rcvr\" ; then " \
|
||||
"echo \"Booting recovery system\" ; " \
|
||||
"led 3 on ; " /* Bottom RED */ \
|
||||
"fi ; " \
|
||||
"led 1 on ; " /* Top RED */ \
|
||||
"run ubi_ubi ; " \
|
||||
"else echo \"Unsupported boot mode: \"${bootmode} ; " \
|
||||
"fi\0" \
|
||||
|
||||
#define CONFIG_CMD_UBI |
||||
#define CONFIG_CMD_UBIFS |
||||
#define CONFIG_MTD_UBI_FASTMAP |
||||
#define CONFIG_RBTREE |
||||
#define CONFIG_LZO |
||||
#define MTDPARTS_DEFAULT \ |
||||
"mtdparts=ff705000.spi.0:" \
|
||||
"1m(u-boot)," \
|
||||
"64k(env1)," \
|
||||
"64k(env2)," \
|
||||
"256k(samtec1)," \
|
||||
"256k(samtec2)," \
|
||||
"-(rcvrfs);" /* Recovery */ \
|
||||
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH |
||||
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT |
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
||||
#define CONFIG_ENV_SECT_SIZE (64 * 1024) |
||||
#define CONFIG_ENV_OFFSET 0x100000 |
||||
#define CONFIG_ENV_OFFSET_REDUND \ |
||||
(CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) |
||||
|
||||
#define CONFIG_MISC_INIT_R |
||||
#define CONFIG_BOARD_LATE_INIT |
||||
|
||||
/* Enable DFU to SF and RAM */ |
||||
#define CONFIG_DFU_RAM |
||||
#define CONFIG_DFU_SF |
||||
|
||||
/* Support changing the prompt string */ |
||||
#define CONFIG_CMDLINE_PS_SUPPORT |
||||
|
||||
/* The rest of the configuration is shared */ |
||||
#include <configs/socfpga_common.h> |
||||
|
||||
#endif /* __CONFIG_SAMTEC_VINING_FPGA_H__ */ |
Loading…
Reference in new issue