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@ -11,6 +11,8 @@ |
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#include <asm/arch/omap.h> |
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#include <malloc.h> |
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#include <spi.h> |
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#include <asm/gpio.h> |
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#include <asm/omap_gpio.h> |
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/* ti qpsi register bit masks */ |
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#define QSPI_TIMEOUT 2000000 |
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@ -39,7 +41,8 @@ |
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#define MM_SWITCH 0x01 |
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#define MEM_CS 0x100 |
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#define MEM_CS_UNSELECT 0xfffff0ff |
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#define MMAP_START_ADDR 0x5c000000 |
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#define MMAP_START_ADDR_DRA 0x5c000000 |
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#define MMAP_START_ADDR_AM43x 0x30000000 |
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#define CORE_CTRL_IO 0x4a002558 |
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#define QSPI_CMD_READ (0x3 << 0) |
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@ -99,7 +102,11 @@ static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave) |
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struct spi_slave *slave = &qslave->slave; |
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u32 memval = 0; |
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slave->memory_map = (void *)MMAP_START_ADDR; |
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#ifdef CONFIG_DRA7XX |
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slave->memory_map = (void *)MMAP_START_ADDR_DRA; |
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#else |
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slave->memory_map = (void *)MMAP_START_ADDR_AM43x; |
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#endif |
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memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES | |
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QSPI_SETUP0_NUM_D_BYTES_NO_BITS | |
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@ -165,6 +172,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, |
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{ |
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struct ti_qspi_slave *qslave; |
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#ifdef CONFIG_AM43XX |
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gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio"); |
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gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1); |
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#endif |
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qslave = spi_alloc_slave(struct ti_qspi_slave, bus, cs); |
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if (!qslave) { |
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printf("SPI_error: Fail to allocate ti_qspi_slave\n"); |
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@ -229,7 +241,11 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, |
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const uchar *txp = dout; |
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uchar *rxp = din; |
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uint status; |
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int timeout, val; |
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int timeout; |
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#ifdef CONFIG_DRA7XX |
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int val; |
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#endif |
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debug("spi_xfer: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n", |
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slave->bus, slave->cs, bitlen, words, flags); |
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@ -237,15 +253,19 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, |
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/* Setup mmap flags */ |
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if (flags & SPI_XFER_MMAP) { |
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writel(MM_SWITCH, &qslave->base->memswitch); |
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#ifdef CONFIG_DRA7XX |
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val = readl(CORE_CTRL_IO); |
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val |= MEM_CS; |
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writel(val, CORE_CTRL_IO); |
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#endif |
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return 0; |
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} else if (flags & SPI_XFER_MMAP_END) { |
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writel(~MM_SWITCH, &qslave->base->memswitch); |
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#ifdef CONFIG_DRA7XX |
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val = readl(CORE_CTRL_IO); |
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val &= MEM_CS_UNSELECT; |
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writel(val, CORE_CTRL_IO); |
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#endif |
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return 0; |
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} |
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