From 63063cc7ae690b418b1dae1cb21004587361369e Mon Sep 17 00:00:00 2001
From: Kim Phillips <kim.phillips@freescale.com>
Date: Sun, 14 Aug 2011 23:09:39 -0500
Subject: [PATCH 01/31] mpc83xx: fix global timer structure definition
The byte address distance between GTCFR2 and GTMDR1 is 11, not 10.
Reported-by: Shawn Bai <programassem@hotmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
arch/powerpc/include/asm/immap_83xx.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index 8d4c9cb..2daddeb 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -113,7 +113,7 @@ typedef struct gtm83xx {
u8 cfr1; /* Timer1/2 Configuration */
u8 res0[3];
u8 cfr2; /* Timer3/4 Configuration */
- u8 res1[10];
+ u8 res1[11];
u16 mdr1; /* Timer1 Mode Register */
u16 mdr2; /* Timer2 Mode Register */
u16 rfr1; /* Timer1 Reference Register */
From e792affe21686788ee7fdbabbb5fc1bcc799eaa8 Mon Sep 17 00:00:00 2001
From: Holger Brunck <holger.brunck@keymile.com>
Date: Wed, 14 Sep 2011 10:54:12 +0200
Subject: [PATCH 02/31] powerpc/83xx: move km 83xx specific i2c code to
km83xx_i2c
The common code should be valid for more than one architecture.
Therefore this code was reorganized and moved to the new
file km83xx_i2c.c
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
board/keymile/common/common.c | 71 +++----------------------------
board/keymile/common/common.h | 3 ++
board/keymile/km83xx/Makefile | 2 +-
board/keymile/km83xx/km83xx_i2c.c | 88 +++++++++++++++++++++++++++++++++++++++
4 files changed, 98 insertions(+), 66 deletions(-)
create mode 100644 board/keymile/km83xx/km83xx_i2c.c
diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
index 612dd2a..f262306 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -39,7 +39,10 @@
#include <i2c.h>
#endif
+#if !defined(CONFIG_MPC83xx)
static void i2c_write_start_seq(void);
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
/*
@@ -89,9 +92,7 @@ int set_km_env(void)
return 0;
}
-#define DELAY_ABORT_SEQ 62 /* @200kHz 9 clocks = 44us, 62us is ok */
-#define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000))
-
+#if defined(CONFIG_SYS_I2C_INIT_BOARD)
#if !defined(CONFIG_MPC83xx)
static void i2c_write_start_seq(void)
{
@@ -171,68 +172,6 @@ int i2c_make_abort(void)
#endif
return ret;
}
-#endif /* !MPC83xx */
-
-#if defined(CONFIG_MPC83xx)
-static void i2c_write_start_seq(void)
-{
- struct fsl_i2c *dev;
- dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
- udelay(DELAY_ABORT_SEQ);
- out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
- udelay(DELAY_ABORT_SEQ);
- out_8(&dev->cr, (I2C_CR_MEN));
-}
-
-int i2c_make_abort(void)
-{
- struct fsl_i2c *dev;
- dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
- uchar dummy;
- uchar last;
- int nbr_read = 0;
- int i = 0;
- int ret = 0;
-
- /* wait after each operation to finsh with a delay */
- out_8(&dev->cr, (I2C_CR_MSTA));
- udelay(DELAY_ABORT_SEQ);
- out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
- udelay(DELAY_ABORT_SEQ);
- dummy = in_8(&dev->dr);
- udelay(DELAY_ABORT_SEQ);
- last = in_8(&dev->dr);
- nbr_read++;
-
- /*
- * do read until the last bit is 1, but stop if the full eeprom is
- * read.
- */
- while (((last & 0x01) != 0x01) &&
- (nbr_read < CONFIG_SYS_IVM_EEPROM_MAX_LEN)) {
- udelay(DELAY_ABORT_SEQ);
- last = in_8(&dev->dr);
- nbr_read++;
- }
- if ((last & 0x01) != 0x01)
- ret = -2;
- if ((last != 0xff) || (nbr_read > 1))
- printf("[INFO] i2c abort after %d bytes (0x%02x)\n",
- nbr_read, last);
- udelay(DELAY_ABORT_SEQ);
- out_8(&dev->cr, (I2C_CR_MEN));
- udelay(DELAY_ABORT_SEQ);
- /* clear status reg */
- out_8(&dev->sr, 0);
-
- for (i = 0; i < 5; i++)
- i2c_write_start_seq();
- if (ret != 0)
- printf("[ERROR] i2c abort failed after %d bytes (0x%02x)\n",
- nbr_read, last);
-
- return ret;
-}
#endif
/**
@@ -244,6 +183,8 @@ void i2c_init_board(void)
/* Now run the AbortSequence() */
i2c_make_abort();
}
+#endif
+
#if !defined(MACH_TYPE_KM_KIRKWOOD)
int ethernet_present(void)
diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h
index 0fb19cf..6c1f640 100644
--- a/board/keymile/common/common.h
+++ b/board/keymile/common/common.h
@@ -136,6 +136,9 @@ int fdt_get_node_and_value(void *blob,
char *propname,
void **var);
+#define DELAY_ABORT_SEQ 62 /* @200kHz 9 clocks = 44us, 62us is ok */
+#define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000))
+
int i2c_soft_read_pin(void);
int i2c_make_abort(void);
#endif /* __KEYMILE_COMMON_H */
diff --git a/board/keymile/km83xx/Makefile b/board/keymile/km83xx/Makefile
index 72945e2..472768a 100644
--- a/board/keymile/km83xx/Makefile
+++ b/board/keymile/km83xx/Makefile
@@ -28,7 +28,7 @@ endif
LIB = $(obj)lib$(BOARD).o
-COBJS += $(BOARD).o ../common/common.o ../common/ivm.o
+COBJS += $(BOARD).o ../common/common.o ../common/ivm.o $(BOARD)_i2c.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/keymile/km83xx/km83xx_i2c.c b/board/keymile/km83xx/km83xx_i2c.c
new file mode 100644
index 0000000..be17775
--- /dev/null
+++ b/board/keymile/km83xx/km83xx_i2c.c
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2011
+ * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <linux/ctype.h>
+#include "../common/common.h"
+
+static void i2c_write_start_seq(void)
+{
+ struct fsl_i2c *dev;
+ dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
+ udelay(DELAY_ABORT_SEQ);
+ out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
+ udelay(DELAY_ABORT_SEQ);
+ out_8(&dev->cr, (I2C_CR_MEN));
+}
+
+int i2c_make_abort(void)
+{
+ struct fsl_i2c *dev;
+ dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
+ uchar dummy;
+ uchar last;
+ int nbr_read = 0;
+ int i = 0;
+ int ret = 0;
+
+ /* wait after each operation to finsh with a delay */
+ out_8(&dev->cr, (I2C_CR_MSTA));
+ udelay(DELAY_ABORT_SEQ);
+ out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
+ udelay(DELAY_ABORT_SEQ);
+ dummy = in_8(&dev->dr);
+ udelay(DELAY_ABORT_SEQ);
+ last = in_8(&dev->dr);
+ nbr_read++;
+
+ /*
+ * do read until the last bit is 1, but stop if the full eeprom is
+ * read.
+ */
+ while (((last & 0x01) != 0x01) &&
+ (nbr_read < CONFIG_SYS_IVM_EEPROM_MAX_LEN)) {
+ udelay(DELAY_ABORT_SEQ);
+ last = in_8(&dev->dr);
+ nbr_read++;
+ }
+ if ((last & 0x01) != 0x01)
+ ret = -2;
+ if ((last != 0xff) || (nbr_read > 1))
+ printf("[INFO] i2c abort after %d bytes (0x%02x)\n",
+ nbr_read, last);
+ udelay(DELAY_ABORT_SEQ);
+ out_8(&dev->cr, (I2C_CR_MEN));
+ udelay(DELAY_ABORT_SEQ);
+ /* clear status reg */
+ out_8(&dev->sr, 0);
+
+ for (i = 0; i < 5; i++)
+ i2c_write_start_seq();
+ if (ret != 0)
+ printf("[ERROR] i2c abort failed after %d bytes (0x%02x)\n",
+ nbr_read, last);
+
+ return ret;
+}
From 4e8b750c53cc2624ecef59abfd999fae97ad8142 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Mon, 26 Sep 2011 13:36:53 +0200
Subject: [PATCH 03/31] cosmetic, powerpc, mpc83xx: checkpatch cleanup
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
include/mpc83xx.h | 389 ++++++++++++++++++++++++++++++++++++------------------
1 file changed, 257 insertions(+), 132 deletions(-)
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 8292018..d345c85 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -19,27 +19,34 @@
#include <asm/e300.h>
#endif
-/* MPC83xx cpu provide RCR register to do reset thing specially
+/*
+ * MPC83xx cpu provide RCR register to do reset thing specially
*/
#define MPC83xx_RESET
-/* System reset offset (PowerPC standard)
+/*
+ * System reset offset (PowerPC standard)
*/
#define EXC_OFF_SYS_RESET 0x0100
#define _START_OFFSET EXC_OFF_SYS_RESET
-/* IMMRBAR - Internal Memory Register Base Address
+/*
+ * IMMRBAR - Internal Memory Register Base Address
*/
#ifndef CONFIG_DEFAULT_IMMR
-#define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */
+/* Default IMMR base address */
+#define CONFIG_DEFAULT_IMMR 0xFF400000
#endif
-#define IMMRBAR 0x0000 /* Register offset to immr */
-#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */
+/* Register offset to immr */
+#define IMMRBAR 0x0000
+#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base addr. mask */
#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR)
-/* LAWBAR - Local Access Window Base Address Register
+/*
+ * LAWBAR - Local Access Window Base Address Register
*/
-#define LBLAWBAR0 0x0020 /* Register offset to immr */
+/* Register offset to immr */
+#define LBLAWBAR0 0x0020
#define LBLAWAR0 0x0024
#define LBLAWBAR1 0x0028
#define LBLAWAR1 0x002C
@@ -47,9 +54,10 @@
#define LBLAWAR2 0x0034
#define LBLAWBAR3 0x0038
#define LBLAWAR3 0x003C
-#define LAWBAR_BAR 0xFFFFF000 /* Base address mask */
+#define LAWBAR_BAR 0xFFFFF000 /* Base addr. mask */
-/* SPRIDR - System Part and Revision ID Register
+/*
+ * SPRIDR - System Part and Revision ID Register
*/
#define SPRIDR_PARTID 0xFFFF0000 /* Part Id */
#define SPRIDR_REVID 0x0000FFFF /* Revision Id */
@@ -88,42 +96,56 @@
#define SPR_8378 0x80C4
#define SPR_8379 0x80C2
-/* SPCR - System Priority Configuration Register
+/*
+ * SPCR - System Priority Configuration Register
*/
-#define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */
+/* PCI Highest Priority Enable */
+#define SPCR_PCIHPE 0x10000000
#define SPCR_PCIHPE_SHIFT (31-3)
-#define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */
+/* PCI bridge system bus request priority */
+#define SPCR_PCIPR 0x03000000
#define SPCR_PCIPR_SHIFT (31-7)
#define SPCR_OPT 0x00800000 /* Optimize */
#define SPCR_OPT_SHIFT (31-8)
-#define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */
+/* E300 PowerPC core time base unit enable */
+#define SPCR_TBEN 0x00400000
#define SPCR_TBEN_SHIFT (31-9)
-#define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */
+/* E300 PowerPC Core system bus request priority */
+#define SPCR_COREPR 0x00300000
#define SPCR_COREPR_SHIFT (31-11)
#if defined(CONFIG_MPC834x)
/* SPCR bits - MPC8349 specific */
-#define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority */
+/* TSEC1 data priority */
+#define SPCR_TSEC1DP 0x00003000
#define SPCR_TSEC1DP_SHIFT (31-19)
-#define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority */
+/* TSEC1 buffer descriptor priority */
+#define SPCR_TSEC1BDP 0x00000C00
#define SPCR_TSEC1BDP_SHIFT (31-21)
-#define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority */
+/* TSEC1 emergency priority */
+#define SPCR_TSEC1EP 0x00000300
#define SPCR_TSEC1EP_SHIFT (31-23)
-#define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority */
+/* TSEC2 data priority */
+#define SPCR_TSEC2DP 0x00000030
#define SPCR_TSEC2DP_SHIFT (31-27)
-#define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority */
+/* TSEC2 buffer descriptor priority */
+#define SPCR_TSEC2BDP 0x0000000C
#define SPCR_TSEC2BDP_SHIFT (31-29)
-#define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */
+/* TSEC2 emergency priority */
+#define SPCR_TSEC2EP 0x00000003
#define SPCR_TSEC2EP_SHIFT (31-31)
#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
defined(CONFIG_MPC837x)
/* SPCR bits - MPC8308, MPC831x and MPC837x specific */
-#define SPCR_TSECDP 0x00003000 /* TSEC data priority */
+/* TSEC data priority */
+#define SPCR_TSECDP 0x00003000
#define SPCR_TSECDP_SHIFT (31-19)
-#define SPCR_TSECBDP 0x00000C00 /* TSEC buffer descriptor priority */
+/* TSEC buffer descriptor priority */
+#define SPCR_TSECBDP 0x00000C00
#define SPCR_TSECBDP_SHIFT (31-21)
-#define SPCR_TSECEP 0x00000300 /* TSEC emergency priority */
+/* TSEC emergency priority */
+#define SPCR_TSECEP 0x00000300
#define SPCR_TSECEP_SHIFT (31-23)
#endif
@@ -369,26 +391,39 @@
#define SICRH_TSOBI2_V2P5 (1 << 0)
#endif
-/* SWCRR - System Watchdog Control Register
+/*
+ * SWCRR - System Watchdog Control Register
*/
-#define SWCRR 0x0204 /* Register offset to immr */
-#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */
-#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */
-#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */
-#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */
-#define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
-
-/* SWCNR - System Watchdog Counter Register
+/* Register offset to immr */
+#define SWCRR 0x0204
+/* Software Watchdog Time Count */
+#define SWCRR_SWTC 0xFFFF0000
+/* Watchdog Enable bit */
+#define SWCRR_SWEN 0x00000004
+/* Software Watchdog Reset/Interrupt Select bit */
+#define SWCRR_SWRI 0x00000002
+/* Software Watchdog Counter Prescale bit */
+#define SWCRR_SWPR 0x00000001
+#define SWCRR_RES (~(SWCRR_SWTC | SWCRR_SWEN | \
+ SWCRR_SWRI | SWCRR_SWPR))
+
+/*
+ * SWCNR - System Watchdog Counter Register
*/
-#define SWCNR 0x0208 /* Register offset to immr */
-#define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */
+/* Register offset to immr */
+#define SWCNR 0x0208
+/* Software Watchdog Count mask */
+#define SWCNR_SWCN 0x0000FFFF
#define SWCNR_RES ~(SWCNR_SWCN)
-/* SWSRR - System Watchdog Service Register
+/*
+ * SWSRR - System Watchdog Service Register
*/
-#define SWSRR 0x020E /* Register offset to immr */
+/* Register offset to immr */
+#define SWSRR 0x020E
-/* ACR - Arbiter Configuration Register
+/*
+ * ACR - Arbiter Configuration Register
*/
#define ACR_COREDIS 0x10000000 /* Core disable */
#define ACR_COREDIS_SHIFT (31-7)
@@ -403,23 +438,29 @@
#define ACR_PARKM 0x0000000F /* Parking master */
#define ACR_PARKM_SHIFT (31-31)
-/* ATR - Arbiter Timers Register
+/*
+ * ATR - Arbiter Timers Register
*/
#define ATR_DTO 0x00FF0000 /* Data time out */
#define ATR_DTO_SHIFT 16
#define ATR_ATO 0x000000FF /* Address time out */
#define ATR_ATO_SHIFT 0
-/* AER - Arbiter Event Register
+/*
+ * AER - Arbiter Event Register
*/
#define AER_ETEA 0x00000020 /* Transfer error */
-#define AER_RES 0x00000010 /* Reserved transfer type */
-#define AER_ECW 0x00000008 /* External control word transfer type */
-#define AER_AO 0x00000004 /* Address Only transfer type */
+/* Reserved transfer type */
+#define AER_RES 0x00000010
+/* External control word transfer type */
+#define AER_ECW 0x00000008
+/* Address Only transfer type */
+#define AER_AO 0x00000004
#define AER_DTO 0x00000002 /* Data time out */
#define AER_ATO 0x00000001 /* Address time out */
-/* AEATR - Arbiter Event Address Register
+/*
+ * AEATR - Arbiter Event Address Register
*/
#define AEATR_EVENT 0x07000000 /* Event type */
#define AEATR_EVENT_SHIFT 24
@@ -432,7 +473,8 @@
#define AEATR_TTYPE 0x0000001F /* Transfer Type */
#define AEATR_TTYPE_SHIFT 0
-/* HRCWL - Hard Reset Configuration Word Low
+/*
+ * HRCWL - Hard Reset Configuration Word Low
*/
#define HRCWL_LBIUCM 0x80000000
#define HRCWL_LBIUCM_SHIFT 31
@@ -540,7 +582,8 @@
#define HRCWL_SVCOD_DIV_1 0x30000000
#endif
-/* HRCWH - Hardware Reset Configuration Word High
+/*
+ * HRCWH - Hardware Reset Configuration Word High
*/
#define HRCWH_PCI_HOST 0x80000000
#define HRCWH_PCI_HOST_SHIFT 31
@@ -641,7 +684,8 @@
#define HRCWH_LDP_SET 0x00000000
#define HRCWH_LDP_CLEAR 0x00000002
-/* RSR - Reset Status Register
+/*
+ * RSR - Reset Status Register
*/
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
defined(CONFIG_MPC837x)
@@ -653,45 +697,61 @@
#endif
#define RSR_BSF 0x00010000 /* Boot seq. fail */
#define RSR_BSF_SHIFT 16
-#define RSR_SWSR 0x00002000 /* software soft reset */
+/* software soft reset */
+#define RSR_SWSR 0x00002000
#define RSR_SWSR_SHIFT 13
-#define RSR_SWHR 0x00001000 /* software hard reset */
+/* software hard reset */
+#define RSR_SWHR 0x00001000
#define RSR_SWHR_SHIFT 12
#define RSR_JHRS 0x00000200 /* jtag hreset */
#define RSR_JHRS_SHIFT 9
-#define RSR_JSRS 0x00000100 /* jtag sreset status */
+/* jtag sreset status */
+#define RSR_JSRS 0x00000100
#define RSR_JSRS_SHIFT 8
-#define RSR_CSHR 0x00000010 /* checkstop reset status */
+/* checkstop reset status */
+#define RSR_CSHR 0x00000010
#define RSR_CSHR_SHIFT 4
-#define RSR_SWRS 0x00000008 /* software watchdog reset status */
+/* software watchdog reset status */
+#define RSR_SWRS 0x00000008
#define RSR_SWRS_SHIFT 3
-#define RSR_BMRS 0x00000004 /* bus monitop reset status */
+/* bus monitop reset status */
+#define RSR_BMRS 0x00000004
#define RSR_BMRS_SHIFT 2
#define RSR_SRS 0x00000002 /* soft reset status */
#define RSR_SRS_SHIFT 1
#define RSR_HRS 0x00000001 /* hard reset status */
#define RSR_HRS_SHIFT 0
-#define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\
- RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\
- RSR_BMRS | RSR_SRS | RSR_HRS)
-/* RMR - Reset Mode Register
+#define RSR_RES (~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | \
+ RSR_SWHR | RSR_JHRS | \
+ RSR_JSRS | RSR_CSHR | \
+ RSR_SWRS | RSR_BMRS | \
+ RSR_SRS | RSR_HRS))
+/*
+ * RMR - Reset Mode Register
*/
-#define RMR_CSRE 0x00000001 /* checkstop reset enable */
+/* checkstop reset enable */
+#define RMR_CSRE 0x00000001
#define RMR_CSRE_SHIFT 0
#define RMR_RES ~(RMR_CSRE)
-/* RCR - Reset Control Register
+/*
+ * RCR - Reset Control Register
*/
-#define RCR_SWHR 0x00000002 /* software hard reset */
-#define RCR_SWSR 0x00000001 /* software soft reset */
+/* software hard reset */
+#define RCR_SWHR 0x00000002
+/* software soft reset */
+#define RCR_SWSR 0x00000001
#define RCR_RES ~(RCR_SWHR | RCR_SWSR)
-/* RCER - Reset Control Enable Register
+/*
+ * RCER - Reset Control Enable Register
*/
-#define RCER_CRE 0x00000001 /* software hard reset */
+/* software hard reset */
+#define RCER_CRE 0x00000001
#define RCER_RES ~(RCER_CRE)
-/* SPMR - System PLL Mode Register
+/*
+ * SPMR - System PLL Mode Register
*/
#define SPMR_LBIUCM 0x80000000
#define SPMR_LBIUCM_SHIFT 31
@@ -710,7 +770,8 @@
#define SPMR_CEPMF 0x0000001F
#define SPMR_CEPMF_SHIFT 0
-/* OCCR - Output Clock Control Register
+/*
+ * OCCR - Output Clock Control Register
*/
#define OCCR_PCICOE0 0x80000000
#define OCCR_PCICOE1 0x40000000
@@ -732,7 +793,8 @@
#define OCCR_PCI2CR 0x00000001
#define OCCR_PCICR OCCR_PCI1CR
-/* SCCR - System Clock Control Register
+/*
+ * SCCR - System Clock Control Register
*/
#define SCCR_ENCCM 0x03000000
#define SCCR_ENCCM_SHIFT 24
@@ -894,14 +956,16 @@
#define SCCR_PCIEXP2CM_2 0x00080000
#define SCCR_PCIEXP2CM_3 0x000c0000
-/* CSn_BDNS - Chip Select memory Bounds Register
+/*
+ * CSn_BDNS - Chip Select memory Bounds Register
*/
#define CSBNDS_SA 0x00FF0000
#define CSBNDS_SA_SHIFT 8
#define CSBNDS_EA 0x000000FF
#define CSBNDS_EA_SHIFT 24
-/* CSn_CONFIG - Chip Select Configuration Register
+/*
+ * CSn_CONFIG - Chip Select Configuration Register
*/
#define CSCONFIG_EN 0x80000000
#define CSCONFIG_AP 0x00800000
@@ -920,7 +984,8 @@
#define CSCONFIG_COL_BIT_10 0x00000002
#define CSCONFIG_COL_BIT_11 0x00000003
-/* TIMING_CFG_0 - DDR SDRAM Timing Configuration 0
+/*
+ * TIMING_CFG_0 - DDR SDRAM Timing Configuration 0
*/
#define TIMING_CFG0_RWT 0xC0000000
#define TIMING_CFG0_RWT_SHIFT 30
@@ -939,7 +1004,8 @@
#define TIMING_CFG0_MRS_CYC 0x0000000F
#define TIMING_CFG0_MRS_CYC_SHIFT 0
-/* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
+/*
+ * TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
*/
#define TIMING_CFG1_PRETOACT 0x70000000
#define TIMING_CFG1_PRETOACT_SHIFT 28
@@ -965,14 +1031,16 @@
#define TIMING_CFG1_CASLAT_45 0x00080000 /* CAS latency = 4.5 */
#define TIMING_CFG1_CASLAT_50 0x00090000 /* CAS latency = 5.0 */
-/* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
+/*
+ * TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
*/
#define TIMING_CFG2_CPO 0x0F800000
#define TIMING_CFG2_CPO_SHIFT 23
#define TIMING_CFG2_ACSM 0x00080000
#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
-#define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */
+/* default (= CASLAT + 1) */
+#define TIMING_CFG2_CPO_DEF 0x00000000
#define TIMING_CFG2_ADD_LAT 0x70000000
#define TIMING_CFG2_ADD_LAT_SHIFT 28
@@ -985,7 +1053,8 @@
#define TIMING_CFG2_FOUR_ACT 0x0000003F
#define TIMING_CFG2_FOUR_ACT_SHIFT 0
-/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
+/*
+ * DDR_SDRAM_CFG - DDR SDRAM Control Configuration
*/
#define SDRAM_CFG_MEM_EN 0x80000000
#define SDRAM_CFG_SREN 0x40000000
@@ -1003,40 +1072,55 @@
#define SDRAM_CFG_HSE 0x00000008
#define SDRAM_CFG_BI 0x00000001
-/* DDR_SDRAM_MODE - DDR SDRAM Mode Register
+/*
+ * DDR_SDRAM_MODE - DDR SDRAM Mode Register
*/
#define SDRAM_MODE_ESD 0xFFFF0000
#define SDRAM_MODE_ESD_SHIFT 16
#define SDRAM_MODE_SD 0x0000FFFF
#define SDRAM_MODE_SD_SHIFT 0
-#define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */
-#define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */
+/* select extended mode reg */
+#define DDR_MODE_EXT_MODEREG 0x4000
+/* operating mode, mask */
+#define DDR_MODE_EXT_OPMODE 0x3FF8
#define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */
-#define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */
-#define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */
-#define DDR_MODE_WEAK 0x0002 /* weak drivers */
-#define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */
-#define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */
+/* QFC / compatibility, mask */
+#define DDR_MODE_QFC 0x0004
+/* compatible to older SDRAMs */
+#define DDR_MODE_QFC_COMP 0x0000
+/* weak drivers */
+#define DDR_MODE_WEAK 0x0002
+/* disable DLL */
+#define DDR_MODE_DLL_DIS 0x0001
+/* CAS latency, mask */
+#define DDR_MODE_CASLAT 0x0070
#define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */
#define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */
#define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */
#define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */
-#define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */
-#define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */
+/* sequential burst */
+#define DDR_MODE_BTYPE_SEQ 0x0000
+/* interleaved burst */
+#define DDR_MODE_BTYPE_ILVD 0x0008
#define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */
#define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */
-#define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125us */
-#define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */
-#define DDR_MODE_MODEREG 0x0000 /* select mode register */
+/* exact value for 7.8125us */
+#define DDR_REFINT_166MHZ_7US 1302
+/* use 256 cycles as a starting point */
+#define DDR_BSTOPRE 256
+/* select mode register */
+#define DDR_MODE_MODEREG 0x0000
-/* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register
+/*
+ * DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register
*/
#define SDRAM_INTERVAL_REFINT 0x3FFF0000
#define SDRAM_INTERVAL_REFINT_SHIFT 16
#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF
#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0
-/* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register
+/*
+ * DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register
*/
#define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000
#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000
@@ -1044,50 +1128,76 @@
#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000
#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000
-/* ECC_ERR_INJECT - Memory data path error injection mask ECC
+/*
+ * ECC_ERR_INJECT - Memory data path error injection mask ECC
*/
-#define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */
-#define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */
-#define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */
+/* ECC Mirror Byte */
+#define ECC_ERR_INJECT_EMB (0x80000000 >> 22)
+/* Error Injection Enable */
+#define ECC_ERR_INJECT_EIEN (0x80000000 >> 23)
+/* ECC Erroe Injection Enable */
+#define ECC_ERR_INJECT_EEIM (0xff000000 >> 24)
#define ECC_ERR_INJECT_EEIM_SHIFT 0
-/* CAPTURE_ECC - Memory data path read capture ECC
+/*
+ * CAPTURE_ECC - Memory data path read capture ECC
*/
-#define CAPTURE_ECC_ECE (0xff000000>>24)
+#define CAPTURE_ECC_ECE (0xff000000 >> 24)
#define CAPTURE_ECC_ECE_SHIFT 0
-/* ERR_DETECT - Memory error detect
+/*
+ * ERR_DETECT - Memory error detect
*/
-#define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */
-#define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */
-#define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */
-#define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */
+/* Multiple Memory Errors */
+#define ECC_ERROR_DETECT_MME (0x80000000 >> 0)
+/* Multiple-Bit Error */
+#define ECC_ERROR_DETECT_MBE (0x80000000 >> 28)
+/* Single-Bit ECC Error Pickup */
+#define ECC_ERROR_DETECT_SBE (0x80000000 >> 29)
+/* Memory Select Error */
+#define ECC_ERROR_DETECT_MSE (0x80000000 >> 31)
-/* ERR_DISABLE - Memory error disable
+/*
+ * ERR_DISABLE - Memory error disable
*/
-#define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */
-#define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */
-#define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */
-#define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\
- ECC_ERROR_DISABLE_MBED)
-/* ERR_INT_EN - Memory error interrupt enable
+/* Multiple-Bit ECC Error Disable */
+#define ECC_ERROR_DISABLE_MBED (0x80000000 >> 28)
+/* Sinle-Bit ECC Error disable */
+#define ECC_ERROR_DISABLE_SBED (0x80000000 >> 29)
+/* Memory Select Error Disable */
+#define ECC_ERROR_DISABLE_MSED (0x80000000 >> 31)
+#define ECC_ERROR_ENABLE (~(ECC_ERROR_DISABLE_MSED | \
+ ECC_ERROR_DISABLE_SBED | \
+ ECC_ERROR_DISABLE_MBED))
+
+/*
+ * ERR_INT_EN - Memory error interrupt enable
*/
-#define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */
-#define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */
-#define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */
-#define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\
- ECC_ERR_INT_EN_MSEE)
-/* CAPTURE_ATTRIBUTES - Memory error attributes capture
+/* Multiple-Bit ECC Error Interrupt Enable */
+#define ECC_ERR_INT_EN_MBEE (0x80000000 >> 28)
+/* Single-Bit ECC Error Interrupt Enable */
+#define ECC_ERR_INT_EN_SBEE (0x80000000 >> 29)
+/* Memory Select Error Interrupt Enable */
+#define ECC_ERR_INT_EN_MSEE (0x80000000 >> 31)
+#define ECC_ERR_INT_DISABLE (~(ECC_ERR_INT_EN_MBEE | \
+ ECC_ERR_INT_EN_SBEE | \
+ ECC_ERR_INT_EN_MSEE))
+
+/*
+ * CAPTURE_ATTRIBUTES - Memory error attributes capture
*/
-#define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */
+/* Data Beat Num */
+#define ECC_CAPT_ATTR_BNUM (0xe0000000 >> 1)
#define ECC_CAPT_ATTR_BNUM_SHIFT 28
-#define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */
+/* Transaction Size */
+#define ECC_CAPT_ATTR_TSIZ (0xc0000000 >> 6)
#define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0
#define ECC_CAPT_ATTR_TSIZ_ONE_DW 1
#define ECC_CAPT_ATTR_TSIZ_TWO_DW 2
#define ECC_CAPT_ATTR_TSIZ_THREE_DW 3
#define ECC_CAPT_ATTR_TSIZ_SHIFT 24
-#define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */
+/* Transaction Source */
+#define ECC_CAPT_ATTR_TSRC (0xf8000000 >> 11)
#define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0
#define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2
#define ECC_CAPT_ATTR_TSRC_TSEC1 0x4
@@ -1100,21 +1210,26 @@
#define ECC_CAPT_ATTR_TSRC_PCI2 0xE
#define ECC_CAPT_ATTR_TSRC_DMA 0xF
#define ECC_CAPT_ATTR_TSRC_SHIFT 16
-#define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */
+/* Transaction Type */
+#define ECC_CAPT_ATTR_TTYP (0xe0000000 >> 18)
#define ECC_CAPT_ATTR_TTYP_WRITE 0x1
#define ECC_CAPT_ATTR_TTYP_READ 0x2
#define ECC_CAPT_ATTR_TTYP_R_M_W 0x3
#define ECC_CAPT_ATTR_TTYP_SHIFT 12
-#define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */
+#define ECC_CAPT_ATTR_VLD (0x80000000 >> 31) /* Valid */
-/* ERR_SBE - Single bit ECC memory error management
+/*
+ * ERR_SBE - Single bit ECC memory error management
*/
-#define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */
+/* Single-Bit Error Threshold 0..255 */
+#define ECC_ERROR_MAN_SBET (0xff000000 >> 8)
#define ECC_ERROR_MAN_SBET_SHIFT 16
-#define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */
+/* Single Bit Error Counter 0..255 */
+#define ECC_ERROR_MAN_SBEC (0xff000000 >> 24)
#define ECC_ERROR_MAN_SBEC_SHIFT 0
-/* CONFIG_ADDRESS - PCI Config Address Register
+/*
+ * CONFIG_ADDRESS - PCI Config Address Register
*/
#define PCI_CONFIG_ADDRESS_EN 0x80000000
#define PCI_CONFIG_ADDRESS_BN_SHIFT 16
@@ -1126,18 +1241,22 @@
#define PCI_CONFIG_ADDRESS_RN_SHIFT 0
#define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc
-/* POTAR - PCI Outbound Translation Address Register
+/*
+ * POTAR - PCI Outbound Translation Address Register
*/
#define POTAR_TA_MASK 0x000fffff
-/* POBAR - PCI Outbound Base Address Register
+/*
+ * POBAR - PCI Outbound Base Address Register
*/
#define POBAR_BA_MASK 0x000fffff
-/* POCMR - PCI Outbound Comparision Mask Register
+/*
+ * POCMR - PCI Outbound Comparision Mask Register
*/
#define POCMR_EN 0x80000000
-#define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */
+/* 0-memory space 1-I/O space */
+#define POCMR_IO 0x40000000
#define POCMR_SE 0x20000000 /* streaming enable */
#define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */
#define POCMR_CM_MASK 0x000fffff
@@ -1163,16 +1282,19 @@
#define POCMR_CM_8K 0x000FFFFE
#define POCMR_CM_4K 0x000FFFFF
-/* PITAR - PCI Inbound Translation Address Register
+/*
+ * PITAR - PCI Inbound Translation Address Register
*/
#define PITAR_TA_MASK 0x000fffff
-/* PIBAR - PCI Inbound Base/Extended Address Register
+/*
+ * PIBAR - PCI Inbound Base/Extended Address Register
*/
#define PIBAR_MASK 0xffffffff
#define PIEBAR_EBA_MASK 0x000fffff
-/* PIWAR - PCI Inbound Windows Attributes Register
+/*
+ * PIWAR - PCI Inbound Windows Attributes Register
*/
#define PIWAR_EN 0x80000000
#define PIWAR_PF 0x20000000
@@ -1204,11 +1326,13 @@
#define PIWAR_IWS_1G 0x0000001D
#define PIWAR_IWS_2G 0x0000001E
-/* PMCCR1 - PCI Configuration Register 1
+/*
+ * PMCCR1 - PCI Configuration Register 1
*/
#define PMCCR1_POWER_OFF 0x00000020
-/* DDRCDR - DDR Control Driver Register
+/*
+ * DDRCDR - DDR Control Driver Register
*/
#define DDRCDR_DHC_EN 0x80000000
#define DDRCDR_EN 0x40000000
@@ -1229,8 +1353,9 @@
#define DDRCDR_M_ODR 0x00000002
#define DDRCDR_Q_DRN 0x00000001
-/* PCIE Bridge Register
-*/
+/*
+ * PCIE Bridge Register
+ */
#define PEX_CSB_CTRL_OBPIOE 0x00000001
#define PEX_CSB_CTRL_IBPIOE 0x00000002
#define PEX_CSB_CTRL_WDMAE 0x00000004
From f1ccd10672dc7f17c08fe9708c50878d479d6a7b Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Mon, 26 Sep 2011 13:36:54 +0200
Subject: [PATCH 04/31] powerpc, mpc83xx: add DDR SDRAM Timing Configuration 3
definitions
Signed-off-by: Heiko Schocher <hs@denx.de>
Added its mask, too, for intra-file consistency.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
include/mpc83xx.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index d345c85..aa9ce8d 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -1054,6 +1054,12 @@
#define TIMING_CFG2_FOUR_ACT_SHIFT 0
/*
+ * TIMING_CFG_3 - DDR SDRAM Timing Configuration 3
+ */
+#define TIMING_CFG3_EXT_REFREC 0x00070000
+#define TIMING_CFG3_EXT_REFREC_SHIFT 16
+
+/*
* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
*/
#define SDRAM_CFG_MEM_EN 0x80000000
From 4713db666c1cc2861df8caf7fd8486b6793028ef Mon Sep 17 00:00:00 2001
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Tue, 11 Oct 2011 21:46:04 -0500
Subject: [PATCH 05/31] mpc83xx: Fix ipic structure definition
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Added siprr_{b,c} and sepcr for completeness.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
arch/powerpc/include/asm/immap_83xx.h | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index 2daddeb..2ba502a 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -150,11 +150,12 @@ typedef struct ipic83xx {
u32 sipnr_h; /* System Internal Interrupt Pending Register - High */
u32 sipnr_l; /* System Internal Interrupt Pending Register - Low */
u32 siprr_a; /* System Internal Interrupt Group A Priority Register */
- u8 res0[8];
+ u32 siprr_b; /* System Internal Interrupt Group B Priority Register */
+ u32 siprr_c; /* System Internal Interrupt Group C Priority Register */
u32 siprr_d; /* System Internal Interrupt Group D Priority Register */
u32 simsr_h; /* System Internal Interrupt Mask Register - High */
u32 simsr_l; /* System Internal Interrupt Mask Register - Low */
- u8 res1[4];
+ u32 sicnr; /* System Internal Interrupt Control Register */
u32 sepnr; /* System External Interrupt Pending Register */
u32 smprr_a; /* System Mixed Interrupt Group A Priority Register */
u32 smprr_b; /* System Mixed Interrupt Group B Priority Register */
@@ -163,14 +164,14 @@ typedef struct ipic83xx {
u32 sersr; /* System Error Status Register */
u32 sermr; /* System Error Mask Register */
u32 sercr; /* System Error Control Register */
- u8 res2[4];
+ u32 sepcr; /* System External Interrupt Polarity Control Register */
u32 sifcr_h; /* System Internal Interrupt Force Register - High */
u32 sifcr_l; /* System Internal Interrupt Force Register - Low */
u32 sefcr; /* System External Interrupt Force Register */
u32 serfr; /* System Error Force Register */
u32 scvcr; /* System Critical Interrupt Vector Register */
u32 smvcr; /* System Management Interrupt Vector Register */
- u8 res3[0x98];
+ u8 res[0x98];
} ipic83xx_t;
/*
From 7c3a4f986c6a2a300ed711b2df7b62fd991feafa Mon Sep 17 00:00:00 2001
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Tue, 11 Oct 2011 23:57:08 -0500
Subject: [PATCH 06/31] mpc83xx: cosmetic: MERGERBOX.h checkpatch compliance
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
include/configs/MERGERBOX.h | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/include/configs/MERGERBOX.h b/include/configs/MERGERBOX.h
index da924c8..100d6f7 100644
--- a/include/configs/MERGERBOX.h
+++ b/include/configs/MERGERBOX.h
@@ -177,7 +177,7 @@
*/
#define CONFIG_MTD_NAND_VERIFY_WRITE 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_NAND_FSL_ELBC 1
+#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BASE 0xE0600000
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | (2<<BR_DECC_SHIFT) |\
@@ -473,7 +473,7 @@
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_SIZE 0x4000
/*
@@ -530,8 +530,8 @@
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_RESET_TO_RETRY 1000
-#define MV_CI MergerBox
-#define MV_VCI MergerBox
+#define MV_CI "MergerBox"
+#define MV_VCI "MergerBox"
#define MV_FPGA_DATA 0xfc100000
#define MV_FPGA_SIZE 0x00200000
@@ -570,8 +570,8 @@
"mv_version=" U_BOOT_VERSION "\0"\
"mtdids=" MTDIDS_DEFAULT "\0"\
"mtdparts=" MTDPARTS_DEFAULT "\0"\
- "dhcp_client_id=" MK_STR(MV_CI) "\0"\
- "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0"\
+ "dhcp_client_id=" MV_CI "\0"\
+ "dhcp_vendor-class-identifier=" MV_VCI "\0"\
"upd_uboot=dhcp;tftp bdi2000/u-boot-mergerbox-xp.bin;"\
"protect off all;erase $uboota +0xC0000;"\
"cp.b $loadaddr $uboota $filesize\0"\
From 34f819685ca875c3a0d06ac5ce291431921f3ad2 Mon Sep 17 00:00:00 2001
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Tue, 11 Oct 2011 23:57:09 -0500
Subject: [PATCH 07/31] mpc83xx: cosmetic: MPC8308RDB.h checkpatch compliance
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
include/configs/MPC8308RDB.h | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index 210b602..3979aa0 100644
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -212,7 +212,7 @@
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
@@ -262,19 +262,19 @@
/*
* NAND Flash on the Local Bus
*/
-#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
-#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \
+#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
+ | BR_PS_8 /* 8 bit port */ \
| BR_MS_FCM /* MSEL = FCM */ \
- | BR_V ) /* valid */
-#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 /* length 32K */ \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
| OR_FCM_SCY_1 \
| OR_FCM_TRLX \
- | OR_FCM_EHTR )
+ | OR_FCM_EHTR)
/* 0xFFFF8396 */
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
@@ -323,7 +323,7 @@
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {{0x51}} /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } /* Don't probe these addrs */
#define CONFIG_SYS_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C2_OFFSET 0x3100
From 261c07bc670e3df007ff7fdd516c4af7e5a4fa51 Mon Sep 17 00:00:00 2001
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Tue, 11 Oct 2011 23:57:10 -0500
Subject: [PATCH 08/31] mpc83xx: cosmetic: MPC8313ERDB.h checkpatch compliance
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
include/configs/MPC8313ERDB.h | 248 ++++++++++++++++++++++++------------------
1 file changed, 142 insertions(+), 106 deletions(-)
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index d8e384a..31289a9 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -121,7 +121,7 @@
/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
@@ -129,121 +129,126 @@
* Manually set up DDR parameters, as this board does not
* seem to have the SPD connected to I2C.
*/
-#define CONFIG_SYS_DDR_SIZE 128 /* MB */
-#define CONFIG_SYS_DDR_CONFIG ( CSCONFIG_EN \
- | 0x00010000 /* TODO */ \
- | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
+#define CONFIG_SYS_DDR_SIZE 128 /* MB */
+#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \
+ | 0x00010000 /* TODO */ \
+ | CSCONFIG_ROW_BIT_13 \
+ | CSCONFIG_COL_BIT_10)
/* 0x80010102 */
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
- | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
- | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
- | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
- | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
- | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
- | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
- | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
+#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
+ | (0 << TIMING_CFG0_WRT_SHIFT) \
+ | (0 << TIMING_CFG0_RRT_SHIFT) \
+ | (0 << TIMING_CFG0_WWT_SHIFT) \
+ | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+ | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+ | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+ | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
/* 0x00220802 */
-#define CONFIG_SYS_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
- | ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
- | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
- | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
- | (10 << TIMING_CFG1_REFREC_SHIFT ) \
- | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
- | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
- | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
+#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
+ | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+ | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
+ | (5 << TIMING_CFG1_CASLAT_SHIFT) \
+ | (10 << TIMING_CFG1_REFREC_SHIFT) \
+ | (3 << TIMING_CFG1_WRREC_SHIFT) \
+ | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+ | (2 << TIMING_CFG1_WRTORD_SHIFT))
/* 0x3835a322 */
-#define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
- | ( 5 << TIMING_CFG2_CPO_SHIFT ) \
- | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
- | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
- | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
- | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
- | ( 6 << TIMING_CFG2_FOUR_ACT_SHIFT) )
+#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
+ | (5 << TIMING_CFG2_CPO_SHIFT) \
+ | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+ | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+ | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+ | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+ | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
/* 0x129048c6 */ /* P9-45,may need tuning */
-#define CONFIG_SYS_DDR_INTERVAL ( ( 1296 << SDRAM_INTERVAL_REFINT_SHIFT ) \
- | ( 1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
+#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
+ | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
/* 0x05100500 */
#if defined(CONFIG_DDR_2T_TIMING)
-#define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \
+#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_2T_EN \
- | SDRAM_CFG_DBW_32 )
+ | SDRAM_CFG_DBW_32)
#else
-#define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \
+#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_32_BE )
+ | SDRAM_CFG_32_BE)
/* 0x43080000 */
#endif
#define CONFIG_SYS_SDRAM_CFG2 0x00401000
/* set burst length to 8 for 32-bit data path */
-#define CONFIG_SYS_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
- | ( 0x0632 << SDRAM_MODE_SD_SHIFT ) )
+#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
+ | (0x0632 << SDRAM_MODE_SD_SHIFT))
/* 0x44480632 */
-#define CONFIG_SYS_DDR_MODE_2 0x8000C000
+#define CONFIG_SYS_DDR_MODE_2 0x8000C000
#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
/*0x02000000*/
-#define CONFIG_SYS_DDRCDR_VALUE ( DDRCDR_EN \
+#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
| DDRCDR_PZ_NOMZ \
| DDRCDR_NZ_NOMZ \
- | DDRCDR_M_ODR )
+ | DDRCDR_M_ODR)
/*
* FLASH on the Local Bus
*/
-#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
-#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
-
-#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \
- (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
- BR_V) /* valid */
-#define CONFIG_SYS_NOR_OR_PRELIM ( 0xFF800000 /* 8 MByte */ \
+#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
+#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
+
+#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
+ | (2 << BR_PS_SHIFT) /* 16 bit port */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_NOR_OR_PRELIM (0xFF800000 /* 8 MByte */ \
| OR_GPCM_XACS \
| OR_GPCM_SCY_9 \
| OR_GPCM_EHTR \
- | OR_GPCM_EAD )
+ | OR_GPCM_EAD)
/* 0xFF006FF7 TODO SLOW 16 MB flash size */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* window base at flash base */
+ /* window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && !defined(CONFIG_NAND_SPL)
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
+ !defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
/*
* Local Bus LCRR and LBCR regs
*/
#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR ( 0x00040000 /* TODO */ \
- | (0xFF << LBCR_BMT_SHIFT) \
- | 0xF ) /* 0x0004ff0f */
+#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
+ | (0xFF << LBCR_BMT_SHIFT) \
+ | 0xF) /* 0x0004ff0f */
-#define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */
+ /* LB refresh timer prescal, 266MHz/32 */
+#define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */
/* drivers/mtd/nand/nand.c */
#ifdef CONFIG_NAND_SPL
@@ -256,7 +261,7 @@
#define CONFIG_MTD_PARTITION
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT "nand0=e2800000.flash"
-#define MTDPARTS_DEFAULT \
+#define MTDPARTS_DEFAULT \
"mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
#define CONFIG_SYS_MAX_NAND_DEVICE 1
@@ -266,18 +271,18 @@
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
-#define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \
+#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
+ | BR_PS_8 /* 8 bit port */ \
| BR_MS_FCM /* MSEL = FCM */ \
- | BR_V ) /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
| OR_FCM_SCY_1 \
| OR_FCM_TRLX \
- | OR_FCM_EHTR )
+ | OR_FCM_EHTR)
/* 0xFFFF8396 */
#ifdef CONFIG_NAND_U_BOOT
@@ -310,10 +315,14 @@
#ifdef CONFIG_VSC7385_ENET
-#define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */
-#define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE/* Access window base at VSC7385 base */
-#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */
+ /* VSC7385 Base address */
+#define CONFIG_SYS_BR2_PRELIM 0xf0000801
+ /* VSC7385, 128K bytes*/
+#define CONFIG_SYS_OR2_PRELIM 0xfffe09ff
+ /* Access window base at VSC7385 base */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
+ /* Access window size 128K */
+#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010
#endif
@@ -344,11 +353,11 @@
#define CONFIG_HARD_I2C /* I2C with hardware support*/
#define CONFIG_FSL_I2C
#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
/*
* General PCI
@@ -412,10 +421,12 @@
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
#define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
- #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
+ #define CONFIG_ENV_OFFSET_REDUND \
+ (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
#elif !defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+ #define CONFIG_ENV_ADDR \
+ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
#define CONFIG_ENV_SIZE 0x2000
@@ -466,17 +477,21 @@
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+ /* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+ /* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
+ /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
@@ -534,7 +549,7 @@
/* System IO Config */
#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
-#define CONFIG_SYS_SICRL SICRL_USBDR_10 /* Enable Internal USB Phy */
+#define CONFIG_SYS_SICRL SICRL_USBDR_10 /* Enable Internal USB Phy */
#define CONFIG_SYS_HID0_INIT 0x000000000
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
@@ -547,13 +562,25 @@
/* DDR @ 0x00000000 */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
/* PCI @ 0x80000000 */
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
/* PCI2 not supported on 8313 */
#define CONFIG_SYS_IBAT3L (0)
@@ -562,8 +589,14 @@
#define CONFIG_SYS_IBAT4U (0)
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
@@ -594,15 +627,17 @@
*/
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_NETDEV eth1
+#define CONFIG_NETDEV "eth1"
#define CONFIG_HOSTNAME mpc8313erdb
#define CONFIG_ROOTPATH "/nfs/root/path"
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-#define CONFIG_FDTFILE mpc8313erdb.dtb
+ /* U-Boot image on TFTP server */
+#define CONFIG_UBOOTPATH "u-boot.bin"
+#define CONFIG_FDTFILE "mpc8313erdb.dtb"
-#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
+ /* default location for tftp and bootm */
+#define CONFIG_LOADADDR 800000
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#define CONFIG_BAUDRATE 115200
@@ -610,22 +645,23 @@
#define MK_STR(x) XMK_STR(x)
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
+ "netdev=" CONFIG_NETDEV "\0" \
"ethprime=TSEC1\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "uboot=" CONFIG_UBOOTPATH "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+ "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
+ "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "\
+ "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
+ "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\
"fdtaddr=780000\0" \
- "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
+ "fdtfile=" CONFIG_FDTFILE "\0" \
"console=ttyS0\0" \
"setbootargs=setenv bootargs " \
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
+ "$netdev:off " \
"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
#define CONFIG_NFSBOOTCOMMAND \
From 6f681b734942036d538a61fdcc9989328515cfa2 Mon Sep 17 00:00:00 2001
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Tue, 11 Oct 2011 23:57:11 -0500
Subject: [PATCH 09/31] mpc83xx: cosmetic: MPC8315ERDB.h checkpatch compliance
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
include/configs/MPC8315ERDB.h | 253 ++++++++++++++++++++++++------------------
1 file changed, 145 insertions(+), 108 deletions(-)
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index ec86949..69a906b 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -118,8 +118,8 @@
* Arbiter Setup
*/
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
+#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
+#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
/*
* DDR Setup
@@ -128,11 +128,11 @@
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
-#define CONFIG_SYS_DDRCDR_VALUE ( DDRCDR_EN \
+#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
| DDRCDR_PZ_LOZ \
| DDRCDR_NZ_LOZ \
| DDRCDR_ODT \
- | DDRCDR_Q_DRN )
+ | DDRCDR_Q_DRN)
/* 0x7b880001 */
/*
* Manually set up DDR parameters
@@ -140,49 +140,50 @@
*/
#define CONFIG_SYS_DDR_SIZE 128 /* MB */
#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
-#define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \
+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| 0x00010000 /* ODT_WR to CSn */ \
- | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
+ | CSCONFIG_ROW_BIT_13 \
+ | CSCONFIG_COL_BIT_10)
/* 0x80010102 */
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
- | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
- | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
- | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
- | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
- | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
- | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
- | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
+#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
+ | (0 << TIMING_CFG0_WRT_SHIFT) \
+ | (0 << TIMING_CFG0_RRT_SHIFT) \
+ | (0 << TIMING_CFG0_WWT_SHIFT) \
+ | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+ | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+ | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+ | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
/* 0x00220802 */
-#define CONFIG_SYS_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
- | ( 7 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
- | ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
- | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
- | ( 6 << TIMING_CFG1_REFREC_SHIFT ) \
- | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
- | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
- | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
+#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
+ | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+ | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
+ | (5 << TIMING_CFG1_CASLAT_SHIFT) \
+ | (6 << TIMING_CFG1_REFREC_SHIFT) \
+ | (2 << TIMING_CFG1_WRREC_SHIFT) \
+ | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+ | (2 << TIMING_CFG1_WRTORD_SHIFT))
/* 0x27256222 */
-#define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
- | ( 4 << TIMING_CFG2_CPO_SHIFT ) \
- | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
- | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
- | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
- | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
- | ( 5 << TIMING_CFG2_FOUR_ACT_SHIFT) )
+#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
+ | (4 << TIMING_CFG2_CPO_SHIFT) \
+ | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+ | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+ | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+ | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+ | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
/* 0x121048c5 */
-#define CONFIG_SYS_DDR_INTERVAL ( ( 0x0360 << SDRAM_INTERVAL_REFINT_SHIFT ) \
- | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
+#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
+ | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
/* 0x03600100 */
-#define CONFIG_SYS_DDR_SDRAM_CFG ( SDRAM_CFG_SREN \
+#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_32_BE )
+ | SDRAM_CFG_32_BE)
/* 0x43080000 */
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
-#define CONFIG_SYS_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \
- | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
+#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
+ | (0x0232 << SDRAM_MODE_SD_SHIFT))
/* ODT 150ohm CL=3, AL=1 on SDRAM */
-#define CONFIG_SYS_DDR_MODE2 0x00000000
+#define CONFIG_SYS_DDR_MODE2 0x00000000
/*
* Memory test
@@ -194,8 +195,8 @@
/*
* The reserved memory
*/
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
/*
* Initial RAM Base Address Setup
@@ -203,7 +204,8 @@
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Local Bus Configuration & Clock Setup
@@ -221,15 +223,16 @@
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
-#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
+#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
+#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
+ /* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */
#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
- | (2 << BR_PS_SHIFT) /* 16 bit port size */ \
- | BR_V ) /* valid */
+ | (2 << BR_PS_SHIFT) /* 16 bit port */ \
+ | BR_V) /* valid */
#define CONFIG_SYS_NOR_OR_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
@@ -238,10 +241,11 @@
| OR_GPCM_SCY_15 \
| OR_GPCM_TRLX \
| OR_GPCM_EHTR \
- | OR_GPCM_EAD )
+ | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 135 /* 127 64KB sectors and 8 8KB top sectors per device */
+/* 127 64KB sectors and 8 8KB top sectors per device */
+#define CONFIG_SYS_MAX_FLASH_SECT 135
#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
@@ -261,7 +265,7 @@
#define CONFIG_MTD_PARTITION
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT "nand0=e0600000.flash"
-#define MTDPARTS_DEFAULT \
+#define MTDPARTS_DEFAULT \
"mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
#define CONFIG_SYS_MAX_NAND_DEVICE 1
@@ -278,16 +282,16 @@
#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
+ | BR_PS_8 /* 8 bit port */ \
| BR_MS_FCM /* MSEL = FCM */ \
- | BR_V ) /* valid */
+ | BR_V) /* valid */
#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
| OR_FCM_SCY_1 \
| OR_FCM_TRLX \
- | OR_FCM_EHTR )
+ | OR_FCM_EHTR)
/* 0xFFFF8396 */
#ifdef CONFIG_NAND_U_BOOT
@@ -325,7 +329,7 @@
#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
@@ -344,9 +348,9 @@
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_FSL_I2C
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave addr */
#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
#define CONFIG_SYS_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C2_OFFSET 0x3100
@@ -365,9 +369,9 @@
* General PCI
* Addresses are mapped 1-1.
*/
-#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
-#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
+#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
@@ -415,7 +419,7 @@
#define CONFIG_USB_STORAGE
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
-#define CONFIG_USB_PHY_TYPE "utmi"
+#define CONFIG_USB_PHY_TYPE "utmi"
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
/*
@@ -423,9 +427,9 @@
*/
#define CONFIG_TSEC_ENET /* TSEC ethernet support */
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
+#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
/*
* TSEC ethernet configuration
@@ -454,12 +458,12 @@
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1_OFFSET 0x18000
-#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
+#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
#define CONFIG_SATA2
#define CONFIG_SYS_SATA2_OFFSET 0x19000
-#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
-#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
+#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
+#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
#ifdef CONFIG_FSL_SATA
#define CONFIG_LBA48
@@ -482,11 +486,12 @@
CONFIG_ENV_RANGE)
#elif !defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+ #define CONFIG_ENV_ADDR \
+ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
#define CONFIG_ENV_SIZE 0x2000
#else
- #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
+ #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
@@ -520,7 +525,7 @@
#endif
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -537,17 +542,19 @@
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+ /* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+ /* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
/*
* Core HID Setup
@@ -564,42 +571,71 @@
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
+ | BATU_BL_128M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
+ | BATU_BL_8M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
+ | BATU_BL_32M \
+ | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
/* Stack in dcache: cacheable, no memory coherence */
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \
+ | BATU_BL_128K \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
@@ -637,31 +673,32 @@
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=1000000\0" \
- "ramdiskfile=ramfs.83xx\0" \
- "fdtaddr=780000\0" \
- "fdtfile=mpc8315erdb.dtb\0" \
- "usb_phy_type=utmi\0" \
- ""
+ "netdev=eth0\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=1000000\0" \
+ "ramdiskfile=ramfs.83xx\0" \
+ "fdtaddr=780000\0" \
+ "fdtfile=mpc8315erdb.dtb\0" \
+ "usb_phy_type=utmi\0" \
+ ""
#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
+ "$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
From 4dde49d8cbc153963b705550c9ec33bdf436ed91 Mon Sep 17 00:00:00 2001
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Tue, 11 Oct 2011 23:57:12 -0500
Subject: [PATCH 10/31] mpc83xx: cosmetic: MPC8323ERDB.h checkpatch compliance
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
include/configs/MPC8323ERDB.h | 253 +++++++++++++++++++++++++-----------------
1 file changed, 150 insertions(+), 103 deletions(-)
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 5cc9160..f310423 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -68,16 +68,17 @@
* System performance
*/
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
-#define CONFIG_SYS_SPCR_OPT 1 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
+#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
+/* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
+#define CONFIG_SYS_SPCR_OPT 1
/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
+#define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
#undef CONFIG_SPD_EEPROM
#if defined(CONFIG_SPD_EEPROM)
@@ -87,51 +88,52 @@
#else
/* Manually set up DDR parameters
*/
-#define CONFIG_SYS_DDR_SIZE 64 /* MB */
-#define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \
+#define CONFIG_SYS_DDR_SIZE 64 /* MB */
+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| CSCONFIG_ODT_WR_ACS \
- | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9 )
+ | CSCONFIG_ROW_BIT_13 \
+ | CSCONFIG_COL_BIT_9)
/* 0x80010101 */
-#define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
- | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
- | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
- | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
- | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
- | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
- | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
- | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
+#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
+ | (0 << TIMING_CFG0_WRT_SHIFT) \
+ | (0 << TIMING_CFG0_RRT_SHIFT) \
+ | (0 << TIMING_CFG0_WWT_SHIFT) \
+ | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+ | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+ | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+ | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
/* 0x00220802 */
-#define CONFIG_SYS_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
- | ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
- | ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
- | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
- | ( 3 << TIMING_CFG1_REFREC_SHIFT ) \
- | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
- | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
- | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
+#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
+ | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+ | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
+ | (5 << TIMING_CFG1_CASLAT_SHIFT) \
+ | (3 << TIMING_CFG1_REFREC_SHIFT) \
+ | (2 << TIMING_CFG1_WRREC_SHIFT) \
+ | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+ | (2 << TIMING_CFG1_WRTORD_SHIFT))
/* 0x26253222 */
-#define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
- | (31 << TIMING_CFG2_CPO_SHIFT ) \
- | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
- | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
- | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
- | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
- | ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) )
+#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
+ | (31 << TIMING_CFG2_CPO_SHIFT) \
+ | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+ | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+ | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+ | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+ | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
/* 0x1f9048c7 */
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
/* 0x02000000 */
-#define CONFIG_SYS_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
- | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
+#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
+ | (0x0232 << SDRAM_MODE_SD_SHIFT))
/* 0x44480232 */
-#define CONFIG_SYS_DDR_MODE2 0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \
- | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
+#define CONFIG_SYS_DDR_MODE2 0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
+ | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
/* 0x03200064 */
#define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
-#define CONFIG_SYS_DDR_SDRAM_CFG ( SDRAM_CFG_SREN \
+#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_32_BE )
+ | SDRAM_CFG_32_BE)
/* 0x43080000 */
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
#endif
@@ -155,16 +157,17 @@
#endif
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/*
* Initial RAM Base Address Setup
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Local Bus Configuration & Clock Setup
@@ -178,30 +181,31 @@
*/
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
+#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
+ /* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
- (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
- BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
+ | (2 << BR_PS_SHIFT) /* 16 bit port */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
/*
* SDRAM on the Local Bus
*/
-#undef CONFIG_SYS_LB_SDRAM /* The board has not SRDAM on local bus */
+#undef CONFIG_SYS_LB_SDRAM /* The board has not SRDAM on local bus */
#ifdef CONFIG_SYS_LB_SDRAM
-#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
+#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base addr */
#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
@@ -226,7 +230,8 @@
* the top 17 bits of BR2.
*/
-#define CONFIG_SYS_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */
+ /*Port size=32bit, MSEL=SDRAM */
+#define CONFIG_SYS_BR2_PRELIM 0xf0001861
/*
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
@@ -244,8 +249,10 @@
#define CONFIG_SYS_OR2_PRELIM 0xfc006901
-#define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
+ /* LB sdram refresh timer, about 6us */
+#define CONFIG_SYS_LBC_LSRT 0x32000000
+ /* LB refresh timer prescal, 266MHz/32 */
+#define CONFIG_SYS_LBC_MRTPR 0x20000000
#define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723
@@ -254,7 +261,8 @@
/*
* Windows to access PIB via local bus
*/
-#define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */
+ /* windows base 0xf8008000 */
+#define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8008000
#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */
/*
@@ -267,7 +275,7 @@
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
@@ -361,11 +369,12 @@
*/
#ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+ #define CONFIG_ENV_ADDR \
+ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x2000
#else
- #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
+ #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
@@ -405,9 +414,9 @@
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
@@ -415,17 +424,20 @@
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+ /* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+ /* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
+ /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
/*
* Core HID Setup
@@ -441,23 +453,40 @@
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
/* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
+ | BATU_BL_4M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
+ | BATU_BL_32M \
+ | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
#define CONFIG_SYS_IBAT3L (0)
@@ -467,20 +496,33 @@
/* Stack in dcache: cacheable, no memory coherence */
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \
+ | BATU_BL_128K \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
#else
@@ -510,22 +552,26 @@
*/
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
-#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
+#define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
+#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
-/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */
-#define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00 /* MAC address offset in I2C EEPROM */
+/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
+ * (see CONFIG_SYS_I2C_EEPROM) */
+ /* MAC address offset in I2C EEPROM */
+#define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00
-#define CONFIG_NETDEV eth1
+#define CONFIG_NETDEV "eth1"
#define CONFIG_HOSTNAME mpc8323erdb
#define CONFIG_ROOTPATH "/nfsroot"
-#define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-#define CONFIG_FDTFILE mpc832x_rdb.dtb
+ /* U-Boot image on TFTP server */
+#define CONFIG_UBOOTPATH "u-boot.bin"
+#define CONFIG_FDTFILE "mpc832x_rdb.dtb"
+#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
-#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
+ /* default location for tftp and bootm */
+#define CONFIG_LOADADDR 800000
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#define CONFIG_BAUDRATE 115200
@@ -533,23 +579,24 @@
#define MK_STR(x) XMK_STR(x)
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "netdev=" CONFIG_NETDEV "\0" \
+ "uboot=" CONFIG_UBOOTPATH "\0" \
"tftpflash=tftp $loadaddr $uboot;" \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+ "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
+ "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "\
+ "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
+ "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\
"fdtaddr=780000\0" \
- "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
+ "fdtfile=" CONFIG_FDTFILE "\0" \
"ramdiskaddr=1000000\0" \
- "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \
+ "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
"console=ttyS0\0" \
"setbootargs=setenv bootargs " \
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
+ "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
+ "$netdev:off "\
"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
#define CONFIG_NFSBOOTCOMMAND \
From 989091acb02a58dba5e50a3eead168f50020a095 Mon Sep 17 00:00:00 2001
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Tue, 11 Oct 2011 23:57:13 -0500
Subject: [PATCH 11/31] mpc83xx: cosmetic: MPC832XEMDS.h checkpatch compliance
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
include/configs/MPC832XEMDS.h | 229 ++++++++++++++++++++++++++----------------
1 file changed, 141 insertions(+), 88 deletions(-)
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 823b9f1..2a86262 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -97,10 +97,10 @@
/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
+#define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
#undef CONFIG_SPD_EEPROM
#if defined(CONFIG_SPD_EEPROM)
@@ -112,15 +112,15 @@
*/
#define CONFIG_SYS_DDR_SIZE 128 /* MB */
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80840102
-#define CONFIG_SYS_DDR_TIMING_0 0x00220802
-#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
-#define CONFIG_SYS_DDR_TIMING_2 0x0f9048ca
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
+#define CONFIG_SYS_DDR_TIMING_0 0x00220802
+#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
+#define CONFIG_SYS_DDR_TIMING_2 0x0f9048ca
+#define CONFIG_SYS_DDR_TIMING_3 0x00000000
+#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
#define CONFIG_SYS_DDR_MODE 0x44400232
#define CONFIG_SYS_DDR_MODE2 0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL 0x03200064
-#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
+#define CONFIG_SYS_DDR_INTERVAL 0x03200064
+#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080000
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
#endif
@@ -144,16 +144,17 @@
#endif
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/*
* Initial RAM Base Address Setup
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Local Bus Configuration & Clock Setup
@@ -166,38 +167,42 @@
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
-#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
+#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
+ /* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
- (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
- BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
+ | (2 << BR_PS_SHIFT) /* 16 bit port */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
/*
* BCSR on the Local Bus
*/
-#define CONFIG_SYS_BCSR 0xF8000000
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */
-#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
+#define CONFIG_SYS_BCSR 0xF8000000
+ /* Access window base at BCSR base */
+#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
+ /* Access window size 32K */
+#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */
+ /* Port size=8bit, MSEL=GPCM */
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801)
#define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
/*
* SDRAM on the Local Bus
*/
-#undef CONFIG_SYS_LB_SDRAM /* The board has not SRDAM on local bus */
+#undef CONFIG_SYS_LB_SDRAM /* The board has not SRDAM on local bus */
#ifdef CONFIG_SYS_LB_SDRAM
#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
@@ -243,8 +248,10 @@
#define CONFIG_SYS_OR2_PRELIM 0xfc006901
-#define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
+ /* LB sdram refresh timer, about 6us */
+#define CONFIG_SYS_LBC_LSRT 0x32000000
+ /* LB refresh timer prescal, 266MHz/32 */
+#define CONFIG_SYS_LBC_MRTPR 0x20000000
#define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723
@@ -253,20 +260,26 @@
/*
* Windows to access PIB via local bus
*/
-#define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */
-#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */
+ /* windows base 0xf8008000 */
+#define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8008000
+ /* windows size 64KB */
+#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000f
/*
* CS2 on Local Bus, to PIB
*/
-#define CONFIG_SYS_BR2_PRELIM 0xf8008801 /* CS2 base address at 0xf8008000 */
-#define CONFIG_SYS_OR2_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
+ /* CS2 base address at 0xf8008000 */
+#define CONFIG_SYS_BR2_PRELIM 0xf8008801
+ /* size 32KB, port size 8bit, GPCM */
+#define CONFIG_SYS_OR2_PRELIM 0xffffe9f7
/*
* CS3 on Local Bus, to PIB
*/
-#define CONFIG_SYS_BR3_PRELIM 0xf8010801 /* CS3 base address at 0xf8010000 */
-#define CONFIG_SYS_OR3_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
+ /* CS3 base address at 0xf8010000 */
+#define CONFIG_SYS_BR3_PRELIM 0xf8010801
+ /* size 32KB, port size 8bit, GPCM */
+#define CONFIG_SYS_OR3_PRELIM 0xffffe9f7
/*
* Serial Port
@@ -278,7 +291,7 @@
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
@@ -376,11 +389,12 @@
*/
#ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+ #define CONFIG_ENV_ADDR \
+ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x2000
#else
- #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
+ #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
@@ -422,9 +436,9 @@
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
@@ -432,17 +446,20 @@
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+ /* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+ /* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
+ /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
/*
* Core HID Setup
@@ -459,30 +476,52 @@
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
/* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
+ | BATU_BL_4M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
/* BCSR: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \
+ | BATU_BL_128K \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
+ | BATU_BL_32M \
+ | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
#define CONFIG_SYS_IBAT4L (0)
@@ -492,20 +531,33 @@
/* Stack in dcache: cacheable, no memory coherence */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
+ | BATU_BL_128K \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#else
@@ -541,30 +593,31 @@
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=1000000\0" \
- "ramdiskfile=ramfs.83xx\0" \
- "fdtaddr=780000\0" \
- "fdtfile=mpc832x_mds.dtb\0" \
- ""
+ "netdev=eth0\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=1000000\0" \
+ "ramdiskfile=ramfs.83xx\0" \
+ "fdtaddr=780000\0" \
+ "fdtfile=mpc832x_mds.dtb\0" \
+ ""
#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
+ "$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
From 32795ecad60324d1d64d9a226f45856014463141 Mon Sep 17 00:00:00 2001
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Tue, 11 Oct 2011 23:57:14 -0500
Subject: [PATCH 12/31] mpc83xx: cosmetic: MPC8349EMDS.h checkpatch compliance
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
include/configs/MPC8349EMDS.h | 295 +++++++++++++++++++++++++-----------------
1 file changed, 178 insertions(+), 117 deletions(-)
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 541d2f4..e3052f0 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -66,7 +66,7 @@
#define CONFIG_SYS_IMMR 0xE0000000
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
+#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x00100000
@@ -105,11 +105,11 @@
*/
#undef CONFIG_DDR_32BIT
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
- DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
+ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
#undef CONFIG_DDR_2T_TIMING
/*
@@ -129,31 +129,35 @@
#define CONFIG_SYS_DDR_SIZE 256 /* MB */
#if defined(CONFIG_DDR_II)
#define CONFIG_SYS_DDRCDR 0x80080001
-#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
+#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
#define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102
-#define CONFIG_SYS_DDR_TIMING_0 0x00220802
-#define CONFIG_SYS_DDR_TIMING_1 0x38357322
-#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
+#define CONFIG_SYS_DDR_TIMING_0 0x00220802
+#define CONFIG_SYS_DDR_TIMING_1 0x38357322
+#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
+#define CONFIG_SYS_DDR_TIMING_3 0x00000000
+#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
#define CONFIG_SYS_DDR_MODE 0x47d00432
#define CONFIG_SYS_DDR_MODE2 0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
+#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
#else
-#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \
+ | CSCONFIG_ROW_BIT_13 \
+ | CSCONFIG_COL_BIT_10)
#define CONFIG_SYS_DDR_TIMING_1 0x36332321
#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
-#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
+#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
#if defined(CONFIG_DDR_32BIT)
/* set burst length to 8 for 32-bit data path */
-#define CONFIG_SYS_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */
+ /* DLL,normal,seq,4/2.5, 8 burst len */
+#define CONFIG_SYS_DDR_MODE 0x00000023
#else
/* the default burst length is 4 - for 64-bit data path */
-#define CONFIG_SYS_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */
+ /* DLL,normal,seq,4/2.5, 4 burst len */
+#define CONFIG_SYS_DDR_MODE 0x00000022
#endif
#endif
#endif
@@ -167,24 +171,31 @@
/*
* FLASH on the Local Bus
*/
-#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
-#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
+#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
+#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \
- (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
+ (2 << BR_PS_SHIFT) | /* 16 bit port */ \
BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
- OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
- OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* window base at flash base */
+#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
+ | OR_UPM_XAM \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_ACS_DIV2 \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_TRLX \
+ | OR_GPCM_EHTR \
+ | OR_GPCM_EAD)
+ /* window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
@@ -201,21 +212,25 @@
/*
* BCSR register on local bus 32KB, 8-bit wide for MDS config reg
*/
-#define CONFIG_SYS_BCSR 0xE2400000
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */
-#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */
-#define CONFIG_SYS_OR1_PRELIM 0xFFFFE8F0 /* length 32K */
+#define CONFIG_SYS_BCSR 0xE2400000
+ /* Access window base at BCSR base */
+#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
+ /* Access window size 32K */
+#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E
+ /* Port-size=8bit, MSEL=GPCM */
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801)
+#define CONFIG_SYS_OR1_PRELIM 0xFFFFE8F0 /* length 32K */
#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/*
* Local Bus LCRR and LBCR regs
@@ -223,8 +238,8 @@
* External Local Bus rate is
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
*/
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
+#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR 0x00000000
/*
@@ -253,9 +268,10 @@
* FIXME: the top 17 bits of BR2.
*/
-#define CONFIG_SYS_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
+ /* Port-size=32bit, MSEL=SDRAM */
+#define CONFIG_SYS_BR2_PRELIM 0xF0001861
#define CONFIG_SYS_LBLAWBAR2_PRELIM 0xF0000000
-#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64M */
+#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64M */
/*
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
@@ -273,18 +289,19 @@
#define CONFIG_SYS_OR2_PRELIM 0xFC006901
-#define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
+ /* LB sdram refresh timer, about 6us */
+#define CONFIG_SYS_LBC_LSRT 0x32000000
+ /* LB refresh timer prescal, 266MHz/32 */
+#define CONFIG_SYS_LBC_MRTPR 0x20000000
-#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFEN \
+#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
| LSDMR_BSMA1516 \
| LSDMR_RFCR8 \
| LSDMR_PRETOACT6 \
| LSDMR_ACTTORW3 \
| LSDMR_BL8 \
| LSDMR_WRC3 \
- | LSDMR_CL3 \
- )
+ | LSDMR_CL3)
/*
* SDRAM Controller configuration sequence.
@@ -306,7 +323,7 @@
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
@@ -315,7 +332,7 @@
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
-#ifdef CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif
@@ -325,15 +342,15 @@
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_FSL_I2C
#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
/* SPI */
#define CONFIG_MPC8XXX_SPI
@@ -346,9 +363,9 @@
/* TSEC */
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
+#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
/* USB */
#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
@@ -363,9 +380,9 @@
#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
+#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
@@ -373,9 +390,9 @@
#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
-#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
+#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
+#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
#if defined(CONFIG_PCI)
@@ -406,14 +423,14 @@
/*
* TSEC configuration
*/
-#define CONFIG_TSEC_ENET /* TSEC ethernet support */
+#define CONFIG_TSEC_ENET /* TSEC ethernet support */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_GMII 1 /* MII PHY management */
-#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
@@ -430,15 +447,16 @@
/*
* Configure on-board RTC
*/
-#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
+#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
/*
* Environment
*/
#ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+ #define CONFIG_ENV_ADDR \
+ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CONFIG_ENV_SIZE 0x2000
@@ -447,7 +465,7 @@
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#else
- #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
+ #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
@@ -496,22 +514,25 @@
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
- #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+ /* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+ /* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
+ /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
@@ -564,7 +585,7 @@
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII )
+ HRCWH_TSEC2M_IN_GMII)
#else
#if defined(PCI_64BIT)
#define CONFIG_SYS_HRCW_HIGH (\
@@ -578,7 +599,7 @@
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII )
+ HRCWH_TSEC2M_IN_GMII)
#else
#define CONFIG_SYS_HRCW_HIGH (\
HRCWH_PCI_HOST |\
@@ -591,7 +612,7 @@
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII )
+ HRCWH_TSEC2M_IN_GMII)
#endif /* PCI_64BIT */
#endif /* CONFIG_PCISLAVE */
@@ -599,7 +620,7 @@
* System performance
*/
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
+#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
@@ -610,28 +631,44 @@
#define CONFIG_SYS_SICRL SICRL_LDP_A
#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE)
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
+ | HID0_ENABLE_INSTRUCTION_CACHE)
-/* #define CONFIG_SYS_HID0_FINAL (\
+/* #define CONFIG_SYS_HID0_FINAL (\
HID0_ENABLE_INSTRUCTION_CACHE |\
HID0_ENABLE_M_BIT |\
- HID0_ENABLE_ADDRESS_BROADCAST ) */
+ HID0_ENABLE_ADDRESS_BROADCAST) */
#define CONFIG_SYS_HID2 HID2_HBE
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR @ 0x00000000 */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
/* PCI @ 0x80000000 */
#ifdef CONFIG_PCI
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#else
#define CONFIG_SYS_IBAT1L (0)
#define CONFIG_SYS_IBAT1U (0)
@@ -640,10 +677,21 @@
#endif
#ifdef CONFIG_MPC83XX_PCI2
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#else
#define CONFIG_SYS_IBAT3L (0)
#define CONFIG_SYS_IBAT3U (0)
@@ -652,13 +700,25 @@
#endif
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \
+#define CONFIG_SYS_IBAT6L (0xF0000000 \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE |\
+ \
BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6U (0xF0000000 \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_IBAT7L (0)
#define CONFIG_SYS_IBAT7U (0)
@@ -699,10 +759,10 @@
#define CONFIG_ROOTPATH "/nfsroot/rootfs"
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
+#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_BAUDRATE 115200
@@ -728,28 +788,29 @@
"bootm\0" \
"load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
"update=protect off fe000000 fe03ffff; " \
- "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0" \
+ "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
"upd=run load update\0" \
"fdtaddr=780000\0" \
"fdtfile=mpc834x_mds.dtb\0" \
""
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
+ "$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND "run flash_self"
From 396abba26108218ff398fb6c4366f40d5194e8a0 Mon Sep 17 00:00:00 2001
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Tue, 11 Oct 2011 23:57:15 -0500
Subject: [PATCH 13/31] mpc83xx: cosmetic: MPC8349ITX.h checkpatch compliance
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
include/configs/MPC8349ITX.h | 326 +++++++++++++++++++++++++++----------------
1 file changed, 203 insertions(+), 123 deletions(-)
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index c57facf..0365c22 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -71,7 +71,7 @@
#define CONFIG_SYS_TEXT_BASE 0xFEF00000
#endif
-#define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */
+#define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */
#define CONFIG_MISC_INIT_F
#define CONFIG_MISC_INIT_R
@@ -81,7 +81,8 @@
*/
#ifdef CONFIG_MPC8349ITX
-#define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */
+/* The CF card interface on the back of the board */
+#define CONFIG_COMPACT_FLASH
#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
#define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */
#define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */
@@ -111,19 +112,20 @@
#define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */
#define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
-#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
+#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
/* Don't probe these addresses: */
-#define CONFIG_SYS_I2C_NOPROBES {{1, CONFIG_SYS_I2C_8574_ADDR1}, \
+#define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
{1, CONFIG_SYS_I2C_8574_ADDR2}, \
{1, CONFIG_SYS_I2C_8574A_ADDR1}, \
- {1, CONFIG_SYS_I2C_8574A_ADDR2}}
+ {1, CONFIG_SYS_I2C_8574A_ADDR2} }
/* Bit definitions for the 8574[A] I2C expander */
-#define I2C_8574_REVISION 0x03 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
+ /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
+#define I2C_8574_REVISION 0x03
#define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */
#define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */
#define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */
@@ -146,7 +148,8 @@
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
#define CONFIG_SYS_ATA_STRIDE 2
-#define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */
+/* If a CF card is not inserted, time out quickly */
+#define ATA_RESET_TIME 1
#endif
@@ -183,15 +186,15 @@
/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_83XX_DDR_USES_CS0
-#define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x2000
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
- DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
+ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
@@ -200,9 +203,12 @@
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
#endif
-#ifndef CONFIG_SPD_EEPROM /* No SPD? Then manually set up DDR parameters */
- #define CONFIG_SYS_DDR_SIZE 256 /* Mb */
- #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+/* No SPD? Then manually set up DDR parameters */
+#ifndef CONFIG_SPD_EEPROM
+ #define CONFIG_SYS_DDR_SIZE 256 /* Mb */
+ #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \
+ | CSCONFIG_ROW_BIT_13 \
+ | CSCONFIG_COL_BIT_10)
#define CONFIG_SYS_DDR_TIMING_1 0x26242321
#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */
@@ -212,11 +218,12 @@
*Flash on the Local Bus
*/
-#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_MAX_FLASH_SECT 135 /* 127 64KB sectors + 8 8KB sectors per device */
+/* 127 64KB sectors + 8 8KB sectors per device */
+#define CONFIG_SYS_MAX_FLASH_SECT 135
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
@@ -224,11 +231,12 @@
/* The ITX has two flash chips, but the ITX-GP has only one. To support both
boards, we say we have two, but don't display a message if we find only one. */
#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
-#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */
-#define CONFIG_SYS_FLASH_SIZE_SHIFT 4 /* log2 of the above value */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST \
+ {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
+#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */
+#define CONFIG_SYS_FLASH_SIZE_SHIFT 4 /* log2 of the above value */
+#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
/* Vitesse 7385 */
@@ -248,12 +256,19 @@ boards, we say we have two, but don't display a message if we find only one. */
/* Flash */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
- OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
- OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
+ | OR_UPM_XAM \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_ACS_DIV2 \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_TRLX \
+ | OR_GPCM_EHTR \
+ | OR_GPCM_EAD)
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))
+#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \
+ | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))
/* Vitesse 7385 */
@@ -261,10 +276,15 @@ boards, we say we have two, but don't display a message if we find only one. */
#ifdef CONFIG_VSC7385_ENET
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
- OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
- OR_GPCM_EHTR | OR_GPCM_EAD)
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_SETA \
+ | OR_GPCM_TRLX \
+ | OR_GPCM_EHTR \
+ | OR_GPCM_EAD)
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
@@ -273,20 +293,28 @@ boards, we say we have two, but don't display a message if we find only one. */
/* LED */
-#define CONFIG_SYS_LED_BASE 0xF9000000
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
- OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \
- OR_GPCM_EHTR | OR_GPCM_EAD)
+#define CONFIG_SYS_LED_BASE 0xF9000000
+#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_ACS_DIV2 \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_9 \
+ | OR_GPCM_TRLX \
+ | OR_GPCM_EHTR \
+ | OR_GPCM_EAD)
/* Compact Flash */
#ifdef CONFIG_COMPACT_FLASH
-#define CONFIG_SYS_CF_BASE 0xF0000000
+#define CONFIG_SYS_CF_BASE 0xF0000000
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V)
-#define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
+#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \
+ | BR_PS_16 \
+ | BR_MS_UPMA \
+ | BR_V)
+#define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE
#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
@@ -305,15 +333,16 @@ boards, we say we have two, but don't display a message if we find only one. */
#endif
#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/*
* Local Bus LCRR and LBCR regs
@@ -325,8 +354,10 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR 0x00000000
-#define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/
+ /* LB sdram refresh timer, about 6us */
+#define CONFIG_SYS_LBC_LSRT 0x32000000
+ /* LB refresh timer prescal, 266MHz/32*/
+#define CONFIG_SYS_LBC_MRTPR 0x20000000
/*
* Serial Port
@@ -338,7 +369,7 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_CONSOLE ttyS0
#define CONFIG_BAUDRATE 115200
@@ -365,23 +396,27 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
+#define CONFIG_SYS_PCI1_MMIO_BASE \
+ (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
+#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
#ifdef CONFIG_MPC83XX_PCI2
-#define CONFIG_SYS_PCI2_MEM_BASE (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
+#define CONFIG_SYS_PCI2_MEM_BASE \
+ (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI2_MMIO_BASE (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
+#define CONFIG_SYS_PCI2_MMIO_BASE \
+ (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
-#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
+#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS \
+ (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
+#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
#endif
#define CONFIG_PCI_PNP /* do pci plug-and-play */
@@ -442,15 +477,16 @@ boards, we say we have two, but don't display a message if we find only one. */
#ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_ENV_IS_IN_FLASH
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+ #define CONFIG_ENV_ADDR \
+ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */
- #define CONFIG_ENV_SIZE 0x2000
+ #define CONFIG_ENV_SIZE 0x2000
#else
- #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
+ #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
#undef CONFIG_FLASH_CFI_DRIVER
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
- #define CONFIG_ENV_SIZE 0x2000
+ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
+ #define CONFIG_ENV_SIZE 0x2000
#endif
#define CONFIG_LOADS_ECHO /* echo on for serial download */
@@ -479,30 +515,30 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CONFIG_CMD_SDRAM
#if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
- || defined(CONFIG_USB_STORAGE)
- #define CONFIG_DOS_PARTITION
- #define CONFIG_CMD_FAT
- #define CONFIG_SUPPORT_VFAT
+ || defined(CONFIG_USB_STORAGE)
+ #define CONFIG_DOS_PARTITION
+ #define CONFIG_CMD_FAT
+ #define CONFIG_SUPPORT_VFAT
#endif
#ifdef CONFIG_COMPACT_FLASH
- #define CONFIG_CMD_IDE
+ #define CONFIG_CMD_IDE
#endif
#ifdef CONFIG_SATA_SIL3114
- #define CONFIG_CMD_SATA
+ #define CONFIG_CMD_SATA
#endif
#if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE)
- #define CONFIG_CMD_EXT2
+ #define CONFIG_CMD_EXT2
#endif
#ifdef CONFIG_PCI
- #define CONFIG_CMD_PCI
+ #define CONFIG_CMD_PCI
#endif
#ifdef CONFIG_HARD_I2C
- #define CONFIG_CMD_I2C
+ #define CONFIG_CMD_I2C
#endif
/* Watchdog */
@@ -511,38 +547,41 @@ boards, we say we have two, but don't display a message if we find only one. */
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_CMDLINE_EDITING /* Command-line editing */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
#ifdef CONFIG_MPC8349ITX
-#define CONFIG_SYS_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */
#else
-#define CONFIG_SYS_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */
#endif
#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
- #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+ /* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+ /* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
+ /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_SYS_HRCW_LOW (\
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
@@ -563,7 +602,7 @@ boards, we say we have two, but don't display a message if we find only one. */
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII )
+ HRCWH_TSEC2M_IN_GMII)
#else
#define CONFIG_SYS_HRCW_HIGH (\
HRCWH_PCI_HOST |\
@@ -576,14 +615,14 @@ boards, we say we have two, but don't display a message if we find only one. */
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII )
+ HRCWH_TSEC2M_IN_GMII)
#endif
/*
* System performance
*/
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
+#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
@@ -594,8 +633,10 @@ boards, we say we have two, but don't display a message if we find only one. */
/*
* System IO Config
*/
-#define CONFIG_SYS_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */
-#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) /* USB DR as device + USB MPH as host */
+/* Needed for gigabit to work on TSEC 1 */
+#define CONFIG_SYS_SICRH SICRH_TSOBI1
+ /* USB DR as device + USB MPH as host */
+#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
#define CONFIG_SYS_HID0_INIT 0x00000000
#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE
@@ -604,15 +645,31 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
/* PCI */
#ifdef CONFIG_PCI
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#else
#define CONFIG_SYS_IBAT1L 0
#define CONFIG_SYS_IBAT1U 0
@@ -621,10 +678,21 @@ boards, we say we have two, but don't display a message if we find only one. */
#endif
#ifdef CONFIG_MPC83XX_PCI2
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#else
#define CONFIG_SYS_IBAT3L 0
#define CONFIG_SYS_IBAT3U 0
@@ -633,13 +701,24 @@ boards, we say we have two, but don't display a message if we find only one. */
#endif
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L (0xF0000000 \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT6U (0xF0000000 \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_IBAT7L 0
#define CONFIG_SYS_IBAT7U 0
@@ -672,23 +751,24 @@ boards, we say we have two, but don't display a message if we find only one. */
*/
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_NETDEV eth0
+#define CONFIG_NETDEV "eth0"
#ifdef CONFIG_MPC8349ITX
-#define CONFIG_HOSTNAME mpc8349emitx
+#define CONFIG_HOSTNAME "mpc8349emitx"
#else
-#define CONFIG_HOSTNAME mpc8349emitxgp
+#define CONFIG_HOSTNAME "mpc8349emitxgp"
#endif
/* Default path and filenames */
#define CONFIG_ROOTPATH "/nfsroot/rootfs"
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
+ /* U-Boot image on TFTP server */
+#define CONFIG_UBOOTPATH "u-boot.bin"
#ifdef CONFIG_MPC8349ITX
-#define CONFIG_FDTFILE mpc8349emitx.dtb
+#define CONFIG_FDTFILE "mpc8349emitx.dtb"
#else
-#define CONFIG_FDTFILE mpc8349emitxgp.dtb
+#define CONFIG_FDTFILE "mpc8349emitxgp.dtb"
#endif
#define CONFIG_BOOTDELAY 6
@@ -700,26 +780,26 @@ boards, we say we have two, but don't display a message if we find only one. */
"root=/dev/nfs rw" \
" nfsroot=" MK_STR(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \
" ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \
- MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \
- MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \
+ MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \
+ CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \
" console=" MK_STR(CONFIG_CONSOLE) "," MK_STR(CONFIG_BAUDRATE)
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=" MK_STR(CONFIG_CONSOLE) "\0" \
- "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "netdev=" CONFIG_NETDEV "\0" \
+ "uboot=" CONFIG_UBOOTPATH "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+ "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
+ "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "\
+ "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
+ "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\
"fdtaddr=780000\0" \
- "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"
+ "fdtfile=" CONFIG_FDTFILE "\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
- " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
" console=$console,$baudrate $othbootargs; " \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
From 1f5cb793749f38acbe62922cfb2da41629fda08e Mon Sep 17 00:00:00 2001
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Tue, 11 Oct 2011 23:57:16 -0500
Subject: [PATCH 14/31] mpc83xx: cosmetic: MPC8360EMDS.h checkpatch compliance
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
include/configs/MPC8360EMDS.h | 223 ++++++++++++++++++++++++++----------------
1 file changed, 141 insertions(+), 82 deletions(-)
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index 63034d2..a4dd430 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -101,12 +101,13 @@
/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* + 256M */
+#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
+ /* + 256M */
+#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000)
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
- DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
+ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
#define CONFIG_SYS_83XX_DDR_USES_CS0
@@ -131,24 +132,26 @@
#define CONFIG_SYS_DDR_SIZE 256 /* MB */
#if defined(CONFIG_DDR_II)
#define CONFIG_SYS_DDRCDR 0x80080001
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
+#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80330102
-#define CONFIG_SYS_DDR_TIMING_0 0x00220802
-#define CONFIG_SYS_DDR_TIMING_1 0x38357322
-#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
+#define CONFIG_SYS_DDR_TIMING_0 0x00220802
+#define CONFIG_SYS_DDR_TIMING_1 0x38357322
+#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
+#define CONFIG_SYS_DDR_TIMING_3 0x00000000
+#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
#define CONFIG_SYS_DDR_MODE 0x47d00432
#define CONFIG_SYS_DDR_MODE2 0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
+#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
#else
-#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
+#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \
+ | CSCONFIG_ROW_BIT_13 \
+ | CSCONFIG_COL_BIT_9)
#define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */
-#define CONFIG_SYS_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */
-#define CONFIG_SYS_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */
+#define CONFIG_SYS_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */
+#define CONFIG_SYS_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */
#define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* page mode */
#endif
#endif
@@ -173,8 +176,8 @@
#endif
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/*
* Initial RAM Base Address Setup
@@ -182,34 +185,42 @@
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR 0x00000000
+#define CONFIG_SYS_LBC_LBCR 0x00000000
/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
+ /* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
- (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
- BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
- OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
- OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
+ | (2 << BR_PS_SHIFT) /* 16 bit port */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
+ | OR_UPM_XAM \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_ACS_DIV2 \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_TRLX \
+ | OR_GPCM_EHTR \
+ | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
@@ -219,11 +230,13 @@
/*
* BCSR on the Local Bus
*/
-#define CONFIG_SYS_BCSR 0xF8000000
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */
+#define CONFIG_SYS_BCSR 0xF8000000
+ /* Access window base at BCSR base */
+#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000F /* Access window size 64K */
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */
+ /* Port size=8bit, MSEL=GPCM */
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801)
#define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
/*
@@ -271,8 +284,10 @@
#define CONFIG_SYS_OR2 0xfc006901
-#define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
+ /* LB sdram refresh timer, about 6us */
+#define CONFIG_SYS_LBC_LSRT 0x32000000
+ /* LB refresh timer prescal, 266MHz/32 */
+#define CONFIG_SYS_LBC_MRTPR 0x20000000
#define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723
@@ -315,7 +330,7 @@
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
@@ -419,11 +434,12 @@
#ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+ #define CONFIG_ENV_ADDR \
+ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x2000
#else
- #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
+ #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
@@ -476,17 +492,19 @@
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+ /* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+ /* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
/*
* Core HID Setup
@@ -503,54 +521,94 @@
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR/LBC SDRAM: cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
/* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
+ | BATU_BL_4M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
/* BCSR: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \
+ | BATU_BL_128K \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
+ | BATU_BL_32M \
+ | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
/* DDR/LBC SDRAM next 256M: cacheable */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM_BASE2 | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM_BASE2 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM_BASE2 \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM_BASE2 \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
/* Stack in dcache: cacheable, no memory coherence */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
+ | BATU_BL_128K \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#else
@@ -588,30 +646,31 @@
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=1000000\0" \
- "ramdiskfile=ramfs.83xx\0" \
- "fdtaddr=780000\0" \
- "fdtfile=mpc836x_mds.dtb\0" \
- ""
+ "netdev=eth0\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=1000000\0" \
+ "ramdiskfile=ramfs.83xx\0" \
+ "fdtaddr=780000\0" \
+ "fdtfile=mpc836x_mds.dtb\0" \
+ ""
#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
+ "$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
From 9a9865508f76d512707f4ad8c21f4b9bbeadc5e3 Mon Sep 17 00:00:00 2001
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Tue, 11 Oct 2011 23:57:17 -0500
Subject: [PATCH 15/31] mpc83xx: cosmetic: MPC8360ERDK.h checkpatch compliance
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
include/configs/MPC8360ERDK.h | 282 +++++++++++++++++++++++++-----------------
1 file changed, 169 insertions(+), 113 deletions(-)
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index 705f57a..f565613 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -85,8 +85,8 @@
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
- DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
+ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
#define CONFIG_SYS_83XX_DDR_USES_CS0
@@ -106,13 +106,16 @@
#define CONFIG_DDR_II
#define CONFIG_SYS_DDR_SIZE 256 /* MB */
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \
- CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
-#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | SDRAM_CFG_ECC_EN)
+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
+ | CSCONFIG_ROW_BIT_13 \
+ | CSCONFIG_COL_BIT_10 \
+ | CSCONFIG_ODT_WR_ACS)
+#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 \
+ | SDRAM_CFG_ECC_EN)
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000
-#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#define CONFIG_SYS_DDR_INTERVAL ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
- (1115 << SDRAM_INTERVAL_REFINT_SHIFT))
+#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CONFIG_SYS_DDR_INTERVAL ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) \
+ | (1115 << SDRAM_INTERVAL_REFINT_SHIFT))
#define CONFIG_SYS_DDR_MODE 0x47800432
#define CONFIG_SYS_DDR_MODE2 0x8000c000
@@ -125,14 +128,14 @@
(0 << TIMING_CFG0_WRT_SHIFT) | \
(0 << TIMING_CFG0_RWT_SHIFT))
-#define CONFIG_SYS_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_30) | \
- ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
- ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
- ( 3 << TIMING_CFG1_WRREC_SHIFT) | \
+#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_30) | \
+ (2 << TIMING_CFG1_WRTORD_SHIFT) | \
+ (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+ (3 << TIMING_CFG1_WRREC_SHIFT) | \
(10 << TIMING_CFG1_REFREC_SHIFT) | \
- ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \
- ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
- ( 3 << TIMING_CFG1_PRETOACT_SHIFT))
+ (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+ (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+ (3 << TIMING_CFG1_PRETOACT_SHIFT))
#define CONFIG_SYS_DDR_TIMING_2 ((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
(4 << TIMING_CFG2_CKE_PLS_SHIFT) | \
@@ -163,8 +166,8 @@
#undef CONFIG_SYS_RAMBOOT
#endif
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/*
* Initial RAM Base Address Setup
@@ -172,33 +175,40 @@
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR 0x00000000
+#define CONFIG_SYS_LBC_LBCR 0x00000000
/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use intel Flash protection. */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
+ /* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
- (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
- BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
- OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
- OR_GPCM_XACS | OR_GPCM_SCY_15 | \
- OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
+ | (2 << BR_PS_SHIFT) /* 16 bit port */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
+ | OR_UPM_XAM \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_ACS_DIV2 \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_TRLX \
+ | OR_GPCM_EHTR \
+ | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
@@ -230,8 +240,9 @@
#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* Access window size 64MB */
/* Port size 32 bit, UPMB */
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VIDEO_BASE | 0x000018a1) /* PS=11, UPMB */
-#define CONFIG_SYS_OR2_PRELIM 0xfc000001 /* (64MB, EAD=1) */
+ /* PS=11, UPMB */
+#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VIDEO_BASE | 0x000018a1)
+#define CONFIG_SYS_OR2_PRELIM 0xfc000001 /* (64MB, EAD=1) */
/*
* Serial Port
@@ -243,13 +254,13 @@
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200,}
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef CONFIG_SYS_HUSH_PARSER
@@ -268,9 +279,9 @@
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {{0x52}} /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} } /* Don't probe these addrs */
#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
/*
* General PCI
@@ -284,9 +295,9 @@
#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0xE0300000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
+#define CONFIG_SYS_PCI1_IO_BASE 0xE0300000
+#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
+#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
#ifdef CONFIG_PCI
@@ -312,8 +323,8 @@
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 2
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
#endif
#define CONFIG_UEC_ETH2 /* GETH2 */
@@ -324,8 +335,8 @@
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4
#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR 4
-#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID
-#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
#endif
/*
@@ -334,11 +345,11 @@
#ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CONFIG_ENV_SIZE 0x20000
#else /* CONFIG_SYS_RAMBOOT */
-#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
+#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
@@ -390,17 +401,19 @@
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+ /* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+ /* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
/*
* Core HID Setup
@@ -417,54 +430,95 @@
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
/* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
+ | BATU_BL_4M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
/* NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_NAND_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_NAND_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_NAND_BASE \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_NAND_BASE \
+ | BATU_BL_64M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
+ | BATU_BL_32M \
+ | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR \
+ | BATL_PP_10)
+#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \
+ | BATU_BL_128K \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_VIDEO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | \
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_VIDEO_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_VIDEO_BASE \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_VIDEO_BASE \
+ | BATU_BL_64M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#else /* CONFIG_PCI */
@@ -507,49 +561,51 @@
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0"\
- "consoledev=ttyS0\0"\
- "loadaddr=a00000\0"\
- "fdtaddr=900000\0"\
- "fdtfile=mpc836x_rdk.dtb\0"\
- "fsfile=fs\0"\
- "ubootfile=u-boot.bin\0"\
- "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),-(rootfs)\0"\
- "setbootargs=setenv bootargs console=$consoledev,$baudrate "\
- "$mtdparts panic=1\0"\
- "adddhcpargs=setenv bootargs $bootargs ip=on\0"\
- "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"\
- "$gatewayip:$netmask:$hostname:$netdev:off "\
- "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\
- "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 "\
- "rootfstype=jffs2 rw\0"\
- "tftp_get_uboot=tftp 100000 $ubootfile\0"\
- "tftp_get_kernel=tftp $loadaddr $bootfile\0"\
- "tftp_get_dtb=tftp $fdtaddr $fdtfile\0"\
- "tftp_get_fs=tftp c00000 $fsfile\0"\
- "nand_erase_kernel=nand erase 0 400000\0"\
- "nand_erase_dtb=nand erase 400000 20000\0"\
- "nand_erase_fs=nand erase 420000 3be0000\0"\
- "nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0"\
- "nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0"\
- "nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0"\
- "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0"\
- "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0"\
- "nor_reflash=protect off ff800000 ff87ffff ; erase ff800000 ff87ffff ; "\
- "cp.b 100000 ff800000 $filesize\0"\
- "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel "\
- "nand_write_kernel\0"\
- "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\
- "nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0"\
- "nand_reflash=run nand_reflash_kernel nand_reflash_dtb "\
- "nand_reflash_fs\0"\
- "boot_m=bootm $loadaddr - $fdtaddr\0"\
- "dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\
- "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
- "boot_m\0"\
- "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\
- "boot_m\0"\
- ""
+ "netdev=eth0\0" \
+ "consoledev=ttyS0\0" \
+ "loadaddr=a00000\0" \
+ "fdtaddr=900000\0" \
+ "fdtfile=mpc836x_rdk.dtb\0" \
+ "fsfile=fs\0" \
+ "ubootfile=u-boot.bin\0" \
+ "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),"\
+ "-(rootfs)\0" \
+ "setbootargs=setenv bootargs console=$consoledev,$baudrate " \
+ "$mtdparts panic=1\0" \
+ "adddhcpargs=setenv bootargs $bootargs ip=on\0" \
+ "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:" \
+ "$gatewayip:$netmask:$hostname:$netdev:off " \
+ "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \
+ "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 " \
+ "rootfstype=jffs2 rw\0" \
+ "tftp_get_uboot=tftp 100000 $ubootfile\0" \
+ "tftp_get_kernel=tftp $loadaddr $bootfile\0" \
+ "tftp_get_dtb=tftp $fdtaddr $fdtfile\0" \
+ "tftp_get_fs=tftp c00000 $fsfile\0" \
+ "nand_erase_kernel=nand erase 0 400000\0" \
+ "nand_erase_dtb=nand erase 400000 20000\0" \
+ "nand_erase_fs=nand erase 420000 3be0000\0" \
+ "nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0" \
+ "nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0" \
+ "nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0" \
+ "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0" \
+ "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0" \
+ "nor_reflash=protect off ff800000 ff87ffff ; " \
+ "erase ff800000 ff87ffff ; " \
+ "cp.b 100000 ff800000 $filesize\0" \
+ "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel " \
+ "nand_write_kernel\0" \
+ "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\
+ "nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0" \
+ "nand_reflash=run nand_reflash_kernel nand_reflash_dtb " \
+ "nand_reflash_fs\0" \
+ "boot_m=bootm $loadaddr - $fdtaddr\0" \
+ "dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\
+ "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
+ "boot_m\0" \
+ "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\
+ "boot_m\0" \
+ ""
#define CONFIG_BOOTCOMMAND "run dhcpboot"
From 8d85808fa11c0853cb450f85cdaa7770892a1cd7 Mon Sep 17 00:00:00 2001
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Tue, 11 Oct 2011 23:57:18 -0500
Subject: [PATCH 16/31] mpc83xx: cosmetic: MPC837XEMDS.h checkpatch compliance
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
include/configs/MPC837XEMDS.h | 283 +++++++++++++++++++++++++-----------------
1 file changed, 166 insertions(+), 117 deletions(-)
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 03aedec..76e598d 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -88,17 +88,17 @@
/* Arbiter Configuration Register */
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
+#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
/* System Priority Control Register */
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
+#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
/*
* IP blocks clock configuration
*/
#define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */
#define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */
-#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */
+#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */
/*
* System IO Config
@@ -146,46 +146,47 @@
*/
#define CONFIG_SYS_DDR_SIZE 512 /* MB */
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
-#define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \
+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| 0x00010000 /* ODT_WR to CSn */ \
- | CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10 )
+ | CSCONFIG_ROW_BIT_14 \
+ | CSCONFIG_COL_BIT_10)
/* 0x80010202 */
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
- | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
- | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
- | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
- | ( 6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
- | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
- | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
- | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
+#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
+ | (0 << TIMING_CFG0_WRT_SHIFT) \
+ | (0 << TIMING_CFG0_RRT_SHIFT) \
+ | (0 << TIMING_CFG0_WWT_SHIFT) \
+ | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+ | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+ | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+ | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
/* 0x00620802 */
-#define CONFIG_SYS_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
- | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
- | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
- | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
- | (13 << TIMING_CFG1_REFREC_SHIFT ) \
- | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
- | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
- | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
+#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
+ | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+ | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
+ | (5 << TIMING_CFG1_CASLAT_SHIFT) \
+ | (13 << TIMING_CFG1_REFREC_SHIFT) \
+ | (3 << TIMING_CFG1_WRREC_SHIFT) \
+ | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+ | (2 << TIMING_CFG1_WRTORD_SHIFT))
/* 0x3935d322 */
-#define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
- | ( 6 << TIMING_CFG2_CPO_SHIFT ) \
- | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
- | ( 4 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
- | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
- | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
- | ( 8 << TIMING_CFG2_FOUR_ACT_SHIFT) )
+#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
+ | (6 << TIMING_CFG2_CPO_SHIFT) \
+ | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+ | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+ | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+ | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+ | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
/* 0x131088c8 */
-#define CONFIG_SYS_DDR_INTERVAL ( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \
- | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
+#define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
+ | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
/* 0x03E00100 */
#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
-#define CONFIG_SYS_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \
- | ( 0x1432 << SDRAM_MODE_SD_SHIFT ) )
+#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
+ | (0x1432 << SDRAM_MODE_SD_SHIFT))
/* ODT 150ohm CL=3, AL=1 on SDRAM */
-#define CONFIG_SYS_DDR_MODE2 0x00000000
+#define CONFIG_SYS_DDR_MODE2 0x00000000
#endif
/*
@@ -207,8 +208,8 @@
#endif
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
/*
* Initial RAM Base Address Setup
@@ -216,7 +217,8 @@
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Local Bus Configuration & Clock Setup
@@ -229,19 +231,20 @@
/*
* FLASH on the Local Bus
*/
-#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
+#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
-#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
+#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
+#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
+ /* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
-#define CONFIG_SYS_BR0_PRELIM ( CONFIG_SYS_FLASH_BASE /* Flash Base address */ \
- | (2 << BR_PS_SHIFT) /* 16 bit port size */ \
- | BR_V ) /* valid */
-#define CONFIG_SYS_OR0_PRELIM ( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
+ | (2 << BR_PS_SHIFT) /* 16 bit port */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
@@ -249,7 +252,7 @@
| OR_GPCM_SCY_15 \
| OR_GPCM_TRLX \
| OR_GPCM_EHTR \
- | OR_GPCM_EAD )
+ | OR_GPCM_EAD)
/* 0xFE000FF7 */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
@@ -263,11 +266,13 @@
* BCSR on the Local Bus
*/
#define CONFIG_SYS_BCSR 0xF8000000
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */
+ /* Access window base at BCSR base */
+#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00000801) /* Port size=8bit, MSEL=GPCM */
-#define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
+ /* Port size=8bit, MSEL=GPCM */
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00000801)
+#define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
/*
* NAND Flash on the Local Bus
@@ -275,22 +280,22 @@
#define CONFIG_CMD_NAND 1
#define CONFIG_MTD_NAND_VERIFY_WRITE 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_NAND_FSL_ELBC 1
+#define CONFIG_NAND_FSL_ELBC 1
-#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
-#define CONFIG_SYS_BR3_PRELIM ( CONFIG_SYS_NAND_BASE \
+#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
+#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
+ | BR_PS_8 /* 8 bit port */ \
| BR_MS_FCM /* MSEL = FCM */ \
- | BR_V ) /* valid */
-#define CONFIG_SYS_OR3_PRELIM ( 0xFFFF8000 /* length 32K */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR3_PRELIM (0xFFFF8000 /* length 32K */ \
| OR_FCM_BCTLD \
| OR_FCM_CST \
| OR_FCM_CHT \
| OR_FCM_SCY_1 \
| OR_FCM_RST \
| OR_FCM_TRLX \
- | OR_FCM_EHTR )
+ | OR_FCM_EHTR)
/* 0xFFFF919E */
#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE
@@ -306,7 +311,7 @@
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
@@ -326,11 +331,11 @@
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_FSL_I2C
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
/*
* Config on-board RTC
@@ -342,9 +347,9 @@
* General PCI
* Addresses are mapped 1-1.
*/
-#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
-#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
+#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
@@ -397,9 +402,9 @@ extern int board_pci_host_broken(void);
*/
#define CONFIG_TSEC_ENET /* TSEC ethernet support */
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
+#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
/*
* TSEC ethernet configuration
@@ -435,12 +440,12 @@ extern int board_pci_host_broken(void);
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1_OFFSET 0x18000
-#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
+#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
#define CONFIG_SATA2
#define CONFIG_SYS_SATA2_OFFSET 0x19000
-#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
-#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
+#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
+#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
#ifdef CONFIG_FSL_SATA
#define CONFIG_LBA48
@@ -454,11 +459,12 @@ extern int board_pci_host_broken(void);
*/
#ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+ #define CONFIG_ENV_ADDR \
+ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CONFIG_ENV_SIZE 0x2000
#else
- #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
+ #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
@@ -526,17 +532,19 @@ extern int board_pci_host_broken(void);
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+ /* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+ /* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
/*
* Core HID Setup
@@ -555,53 +563,93 @@ extern int board_pci_host_broken(void);
#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
+ | BATU_BL_8M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
/* BCSR: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \
+ | BATU_BL_128K \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \
+ | BATU_BL_32M \
+ | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
/* Stack in dcache: cacheable, no memory coherence */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
+ | BATU_BL_128K \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#else
@@ -639,30 +687,31 @@ extern int board_pci_host_broken(void);
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=1000000\0" \
- "ramdiskfile=ramfs.83xx\0" \
- "fdtaddr=780000\0" \
- "fdtfile=mpc8379_mds.dtb\0" \
- ""
+ "netdev=eth0\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=1000000\0" \
+ "ramdiskfile=ramfs.83xx\0" \
+ "fdtaddr=780000\0" \
+ "fdtfile=mpc8379_mds.dtb\0" \
+ ""
#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
+ "$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
From 5afe9722b02970445270437e55f78df15f3e5663 Mon Sep 17 00:00:00 2001
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Tue, 11 Oct 2011 23:57:19 -0500
Subject: [PATCH 17/31] mpc83xx: cosmetic: MPC837XERDB.h checkpatch compliance
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
include/configs/MPC837XERDB.h | 249 +++++++++++++++++++++++++-----------------
1 file changed, 149 insertions(+), 100 deletions(-)
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index a26a5bb..4b1d455 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -103,15 +103,15 @@
/* Arbiter Configuration Register */
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
+#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
/* System Priority Control Regsiter */
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */
+#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */
/* System Clock Configuration Register */
#define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
#define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
-#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
+#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
/*
* System IO Config
@@ -197,19 +197,19 @@
/* 0x06090100 */
#if defined(CONFIG_DDR_2T_TIMING)
-#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
- | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
- | SDRAM_CFG_2T_EN \
- | SDRAM_CFG_DBW_32)
+#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
+ | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
+ | SDRAM_CFG_2T_EN \
+ | SDRAM_CFG_DBW_32)
#else
-#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
- | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT)
- /* 0x43000000 */
+#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
+ | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT)
+ /* 0x43000000 */
#endif
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
#define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
- | (0x0442 << SDRAM_MODE_SD_SHIFT))
- /* 0x04400442 */ /* DDR400 */
+ | (0x0442 << SDRAM_MODE_SD_SHIFT))
+ /* 0x04400442 */ /* DDR400 */
#define CONFIG_SYS_DDR_MODE2 0x00000000
/*
@@ -230,8 +230,8 @@
#undef CONFIG_SYS_RAMBOOT
#endif
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
/*
* Initial RAM Base Address Setup
@@ -239,7 +239,8 @@
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Local Bus Configuration & Clock Setup
@@ -257,17 +258,18 @@
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
+#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
+ /* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
- (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
- BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (0xFF800000 /* 8 MByte */ \
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
+ | (2 << BR_PS_SHIFT) /* 16 bit port */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR0_PRELIM (0xFF800000 /* 8 MByte */ \
| OR_GPCM_XACS \
| OR_GPCM_SCY_9 \
| OR_GPCM_EHTR \
@@ -284,19 +286,19 @@
/*
* NAND Flash on the Local Bus
*/
-#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | \
- (2 << BR_DECC_SHIFT) | /* Use HW ECC */ \
- BR_PS_8 | /* Port Size = 8 bit */ \
- BR_MS_FCM | /* MSEL = FCM */ \
- BR_V) /* valid */
-#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 | /* length 32K */ \
- OR_FCM_CSCT | \
- OR_FCM_CST | \
- OR_FCM_CHT | \
- OR_FCM_SCY_1 | \
- OR_FCM_TRLX | \
- OR_FCM_EHTR)
+#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
+ | (2 << BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_PS_8 | /* 8 bit Port */ \
+ | BR_MS_FCM | /* MSEL = FCM */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 /* length 32K */ \
+ | OR_FCM_CSCT \
+ | OR_FCM_CST \
+ | OR_FCM_CHT \
+ | OR_FCM_SCY_1 \
+ | OR_FCM_TRLX \
+ | OR_FCM_EHTR)
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
@@ -306,10 +308,11 @@
#ifdef CONFIG_VSC7385_ENET
-#define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* Base address */
-#define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* 128K bytes*/
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE /* Access Base */
-#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* Access Size 128K */
+#define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* Base address */
+#define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* 128K bytes*/
+ /* Access Base */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
+#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* Access Size 128K */
#endif
@@ -323,7 +326,7 @@
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
@@ -348,11 +351,11 @@
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_FSL_I2C
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
/*
* Config on-board RTC
@@ -364,9 +367,9 @@
* General PCI
* Addresses are mapped 1-1.
*/
-#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
-#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
+#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
@@ -446,12 +449,12 @@
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1_OFFSET 0x18000
-#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
+#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
#define CONFIG_SATA2
#define CONFIG_SYS_SATA2_OFFSET 0x19000
-#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
-#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
+#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
+#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
#ifdef CONFIG_FSL_SATA
#define CONFIG_LBA48
@@ -465,11 +468,12 @@
*/
#ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
+ #define CONFIG_ENV_ADDR \
+ (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */
#define CONFIG_ENV_SIZE 0x4000
#else
- #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
+ #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000)
#define CONFIG_ENV_SIZE 0x2000
@@ -507,7 +511,7 @@
#endif
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -527,9 +531,9 @@
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
@@ -537,24 +541,26 @@
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+ /* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+ /* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
/*
* Core HID Setup
*/
#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE)
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
+ | HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2 HID2_HBE
/*
@@ -567,53 +573,93 @@
#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
+ | BATU_BL_8M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
/* L2 Switch: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE \
+ | BATU_BL_128K \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \
+ | BATU_BL_32M \
+ | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
/* Stack in dcache: cacheable, no memory coherence */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
+ | BATU_BL_128K \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#else
@@ -639,16 +685,18 @@
#define CONFIG_HAS_FSL_DR_USB
-#define CONFIG_NETDEV eth1
+#define CONFIG_NETDEV "eth1"
#define CONFIG_HOSTNAME mpc837x_rdb
#define CONFIG_ROOTPATH "/nfsroot"
-#define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot
+#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-#define CONFIG_FDTFILE mpc8379_rdb.dtb
+ /* U-Boot image on TFTP server */
+#define CONFIG_UBOOTPATH "u-boot.bin"
+#define CONFIG_FDTFILE "mpc8379_rdb.dtb"
-#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
+ /* default location for tftp and bootm */
+#define CONFIG_LOADADDR 800000
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#define CONFIG_BAUDRATE 115200
@@ -656,23 +704,24 @@
#define MK_STR(x) XMK_STR(x)
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "netdev=" CONFIG_NETDEV "\0" \
+ "uboot=" CONFIG_UBOOTPATH "\0" \
"tftpflash=tftp $loadaddr $uboot;" \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+ "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"fdtaddr=780000\0" \
- "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
+ "fdtfile=" CONFIG_FDTFILE "\0" \
"ramdiskaddr=1000000\0" \
- "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \
+ "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
"console=ttyS0\0" \
"setbootargs=setenv bootargs " \
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
+ "$netdev:off " \
"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
#define CONFIG_NFSBOOTCOMMAND \
From b2773a5e1c824085fd46468f9655b529b0c7a4ed Mon Sep 17 00:00:00 2001
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Tue, 11 Oct 2011 23:57:20 -0500
Subject: [PATCH 18/31] mpc83xx: cosmetic: MVBLM7.h checkpatch compliance
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
include/configs/MVBLM7.h | 116 +++++++++++++++++++++++++++++++----------------
1 file changed, 76 insertions(+), 40 deletions(-)
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index 31c85e2..301df63 100644
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -107,13 +107,19 @@
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 256
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
- OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS|\
- OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | \
- OR_GPCM_EAD)
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
+ | OR_UPM_XAM \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_ACS_DIV2 \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_TRLX \
+ | OR_GPCM_EHTR \
+ | OR_GPCM_EAD)
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))
+#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \
+ | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))
/*
* U-Boot memory configuration
@@ -122,10 +128,11 @@
#undef CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
@@ -157,7 +164,7 @@
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_CONSOLE ttyS0
#define CONFIG_BAUDRATE 115200
@@ -177,7 +184,8 @@
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
-#define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
+#define CONFIG_SYS_PCI1_MMIO_BASE \
+ (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
@@ -204,16 +212,16 @@
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_FEC1_PHY_NORXERR
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
#define TSEC1_PHY_ADDR 0x10
#define TSEC1_PHYIDX 0
#define TSEC1_FLAGS (TSEC_GIGABIT|TSEC_REDUCED)
#define CONFIG_HAS_ETH1
-#define CONFIG_TSEC2_NAME "TSEC1"
+#define CONFIG_TSEC2_NAME "TSEC1"
#define CONFIG_FEC2_PHY_NORXERR
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
+#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
#define TSEC2_PHY_ADDR 0x11
#define TSEC2_PHYIDX 0
#define TSEC2_FLAGS (TSEC_GIGABIT|TSEC_REDUCED)
@@ -250,7 +258,7 @@
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x2000
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
#define CONFIG_LOADS_ECHO
#define CONFIG_SYS_LOADS_BAUD_CHANGE
@@ -280,7 +288,7 @@
*/
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
@@ -292,7 +300,8 @@
#define CONFIG_SYS_PROMPT "mvBL-M7> "
#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_HZ 1000
@@ -302,7 +311,8 @@
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
+ /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_SYS_HRCW_LOW 0x0
#define CONFIG_SYS_HRCW_HIGH 0x0
@@ -311,7 +321,7 @@
* System performance
*/
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
+#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
@@ -333,15 +343,30 @@
#define CONFIG_HIGH_BATS 1
/* DDR */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
/* PCI */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
/* no PCI2 */
#define CONFIG_SYS_IBAT3L 0
@@ -350,14 +375,25 @@
#define CONFIG_SYS_IBAT4U 0
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | \
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
-#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \
+#define CONFIG_SYS_IBAT6L (0xF0000000 \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE \
+ | \
BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6U (0xF0000000 \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_IBAT7L 0
#define CONFIG_SYS_IBAT7U 0
@@ -392,8 +428,8 @@
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_RESET_TO_RETRY 1000
-#define MV_CI mvBL-M7
-#define MV_VCI mvBL-M7
+#define MV_CI "mvBL-M7"
+#define MV_VCI "mvBL-M7"
#define MV_FPGA_DATA 0xfff40000
#define MV_FPGA_SIZE 0
#define MV_KERNEL_ADDR 0xff810000
@@ -409,15 +445,15 @@
#define MV_DTB_ADDR_RAM 0x00600000
#define MV_INITRD_ADDR_RAM 0x01000000
-#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; \
- then source ${script_addr}; \
- else source ${script_addr2}; \
- fi;"
+#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; " \
+ "then source ${script_addr}; " \
+ "else source ${script_addr2}; " \
+ "fi;"
#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
#define CONFIG_EXTRA_ENV_SETTINGS \
"console_nr=0\0" \
- "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0" \
+ "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0" \
"stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0" \
@@ -435,8 +471,8 @@
"mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0" \
"dtb_name=" MK_STR(MV_DTB_NAME) "\0" \
"mv_version=" U_BOOT_VERSION "\0" \
- "dhcp_client_id=" MK_STR(MV_CI) "\0" \
- "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \
+ "dhcp_client_id=" MV_CI "\0" \
+ "dhcp_vendor-class-identifier=" MV_VCI "\0" \
"netretry=no\0" \
"use_static_ipaddr=no\0" \
"static_ipaddr=192.168.90.10\0" \
From bb0f5bc92dfe32a7d70211056b9a5fd01f61185c Mon Sep 17 00:00:00 2001
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Tue, 11 Oct 2011 23:57:21 -0500
Subject: [PATCH 19/31] mpc83xx: cosmetic: SIMPC8313.h checkpatch compliance
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
include/configs/SIMPC8313.h | 288 +++++++++++++++++++++++++-------------------
1 file changed, 164 insertions(+), 124 deletions(-)
diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h
index 2f99641..b1ed254 100644
--- a/include/configs/SIMPC8313.h
+++ b/include/configs/SIMPC8313.h
@@ -77,8 +77,8 @@
#define CONFIG_SYS_MEMTEST_START 0x00001000
#define CONFIG_SYS_MEMTEST_END 0x07f00000
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
+#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
+#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
/*
* Device configurations
@@ -88,17 +88,18 @@
/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
+ /* DDR is system memory*/
+#define CONFIG_SYS_DDR_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED (512 << 20)
-#define CONFIG_SYS_DDRCDR ( DDRCDR_EN \
+#define CONFIG_SYS_DDRCDR (DDRCDR_EN \
| DDRCDR_PZ_NOMZ \
| DDRCDR_NZ_NOMZ \
- | DDRCDR_M_ODR )
+ | DDRCDR_M_ODR)
/* 0x73000002 TODO ODR & DRN ? */
/*
@@ -111,15 +112,16 @@
#endif
#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
/*
* Local Bus LCRR and LBCR regs
@@ -129,9 +131,10 @@
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
| (0xFF << LBCR_BMT_SHIFT) \
- | 0xF ) /* 0x0004ff0f */
+ | 0xF) /* 0x0004ff0f */
-#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
+ /* LB refresh timer prescal, 266MHz/32 */
+#define CONFIG_SYS_LBC_MRTPR 0x20000000
/* drivers/mtd/nand/nand.c */
#ifdef CONFIG_NAND_SPL
@@ -144,39 +147,41 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_CMD_NAND 1
+#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
-#define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V ) /* valid */
+#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
+ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_PS_8 /* 8 bit Port */ \
+ | BR_MS_FCM /* MSEL = FCM */ \
+ | BR_V) /* valid */
#ifdef CONFIG_NAND_SP
-#define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \
+#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
| OR_FCM_SCY_1 \
| OR_FCM_TRLX \
- | OR_FCM_EHTR )
+ | OR_FCM_EHTR)
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000000E /* 32KB */
-#define CONFIG_SYS_NAND_PAGE_SIZE (512) /* NAND chip page size */
-#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
+#define CONFIG_SYS_NAND_PAGE_SIZE (512) /* NAND chip page size */
+ /* NAND chip block size */
+#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10)
#define NAND_CACHE_PAGES 32
#elif defined(CONFIG_NAND_LP)
-#define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFC0000 /* length 256K */ \
+#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
| OR_FCM_PGS \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
| OR_FCM_SCY_1 \
| OR_FCM_TRLX \
- | OR_FCM_EHTR )
+ | OR_FCM_EHTR)
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000011 /* 256KB */
-#define CONFIG_SYS_NAND_PAGE_SIZE (2048) /* NAND chip page size */
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */
+#define CONFIG_SYS_NAND_PAGE_SIZE (2048) /* NAND chip page size */
+ /* NAND chip block size */
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
#define NAND_CACHE_PAGES 64
#else
#error Page size of NAND not defined.
@@ -192,11 +197,11 @@
#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM
-#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_FPGA_BASE \
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA_BASE \
| BR_PS_16 \
| BR_MS_UPMA \
- | BR_V )
-#define CONFIG_SYS_OR1_PRELIM ( OR_AM_2MB \
+ | BR_V)
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_2MB \
| OR_UPM_BCTLD)
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA_BASE
@@ -210,7 +215,7 @@
/* mtdparts command line support */
#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define MTDIDS_DEFAULT "nand0=nand0"
#define MTDPARTS_DEFAULT "mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)"
@@ -231,7 +236,7 @@
#endif
#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
@@ -241,14 +246,14 @@
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
#define CONFIG_FSL_I2C
#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
/*
* General PCI
@@ -306,28 +311,30 @@
* Environment
*/
#if defined(CONFIG_NAND_U_BOOT)
- #define CONFIG_ENV_IS_IN_NAND 1
- #define CONFIG_ENV_OFFSET (768 * 1024)
- #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
- #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
- #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
- #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
- #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
+ #define CONFIG_ENV_IS_IN_NAND 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+ #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+ #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+ #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+ #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
+ #define CONFIG_ENV_OFFSET_REDUND \
+ (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
#elif !defined(CONFIG_SYS_RAMBOOT)
- #define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
- #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
- #define CONFIG_ENV_SIZE 0x2000
+ #define CONFIG_ENV_IS_IN_FLASH 1
+ #define CONFIG_ENV_ADDR \
+ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+ #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
+ #define CONFIG_ENV_SIZE 0x2000
/* Address and size of Redundant Environment Sector */
#else
- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
- #define CONFIG_ENV_SIZE 0x2000
+ #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
+ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
+ #define CONFIG_ENV_SIZE 0x2000
#endif
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/*
* BOOTP options
@@ -358,80 +365,82 @@
#undef CONFIG_CMD_LOADS
#endif
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-
-#define CONFIG_SYS_PBSIZE ( CONFIG_SYS_CBSIZE \
- + sizeof(CONFIG_SYS_PROMPT) \
- + 16 ) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ + sizeof(CONFIG_SYS_PROMPT) \
+ + 16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+ /* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
+ /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
+#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-#define CONFIG_SYS_HRCW_LOW ( HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \
- | 0x20000000 /* reserved */ \
- | HRCWL_DDR_TO_SCB_CLK_2X1 \
- | HRCWL_CSB_TO_CLKIN_4X1 \
- | HRCWL_CORE_TO_CSB_2_5X1 )
+#define CONFIG_SYS_HRCW_LOW (HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \
+ | 0x20000000 /* reserved */ \
+ | HRCWL_DDR_TO_SCB_CLK_2X1 \
+ | HRCWL_CSB_TO_CLKIN_4X1 \
+ | HRCWL_CORE_TO_CSB_2_5X1)
-#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 4)
+#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 4)
-#define CONFIG_SYS_HRCW_HIGH_BASE ( HRCWH_PCI_HOST \
- | HRCWH_PCI1_ARBITER_ENABLE \
- | HRCWH_CORE_ENABLE \
- | HRCWH_BOOTSEQ_DISABLE \
- | HRCWH_SW_WATCHDOG_DISABLE \
- | HRCWH_TSEC1M_IN_RGMII \
- | HRCWH_TSEC2M_IN_RGMII \
- | HRCWH_BIG_ENDIAN \
- | HRCWH_LALE_NORMAL )
+#define CONFIG_SYS_HRCW_HIGH_BASE (HRCWH_PCI_HOST \
+ | HRCWH_PCI1_ARBITER_ENABLE \
+ | HRCWH_CORE_ENABLE \
+ | HRCWH_BOOTSEQ_DISABLE \
+ | HRCWH_SW_WATCHDOG_DISABLE \
+ | HRCWH_TSEC1M_IN_RGMII \
+ | HRCWH_TSEC2M_IN_RGMII \
+ | HRCWH_BIG_ENDIAN \
+ | HRCWH_LALE_NORMAL)
#ifdef CONFIG_NAND_LP
-#define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \
- | HRCWH_FROM_0XFFF00100 \
- | HRCWH_ROM_LOC_NAND_LP_8BIT \
+#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE \
+ | HRCWH_FROM_0XFFF00100 \
+ | HRCWH_ROM_LOC_NAND_LP_8BIT \
| HRCWH_RL_EXT_NAND)
#else
-#define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \
- | HRCWH_FROM_0XFFF00100 \
- | HRCWH_ROM_LOC_NAND_SP_8BIT \
- | HRCWH_RL_EXT_NAND )
+#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE \
+ | HRCWH_FROM_0XFFF00100 \
+ | HRCWH_ROM_LOC_NAND_SP_8BIT \
+ | HRCWH_RL_EXT_NAND)
#endif
/* System IO Config */
-#define CONFIG_SYS_SICRH ( SICRH_ETSEC2_B \
+#define CONFIG_SYS_SICRH (SICRH_ETSEC2_B \
| SICRH_ETSEC2_C \
| SICRH_ETSEC2_D \
| SICRH_ETSEC2_E \
| SICRH_ETSEC2_F \
| SICRH_ETSEC2_G \
| SICRH_TSOBI1 \
- | SICRH_TSOBI2 )
-#define CONFIG_SYS_SICRL ( SICRL_LBC \
+ | SICRH_TSOBI2)
+#define CONFIG_SYS_SICRL (SICRL_LBC \
| SICRL_USBDR_10 \
- | SICRL_ETSEC2_A )
+ | SICRL_ETSEC2_A)
#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE | \
- HID0_ENABLE_DYNAMIC_POWER_MANAGMENT )
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
+ | HID0_ENABLE_INSTRUCTION_CACHE \
+ | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
#define CONFIG_SYS_HID2 HID2_HBE
@@ -439,27 +448,54 @@
/* DDR @ 0x00000000 */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATL_PP_10)
-#define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
+ | BATL_PP_10)
+#define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
/* PCI @ 0x80000000 */
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MEM_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MMIO_BASE \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MMIO_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
/* PCI2 not supported on 8313 */
#define CONFIG_SYS_IBAT4L (0)
#define CONFIG_SYS_IBAT4U (0)
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L (0xF0000000 \
+ | BATL_PP_10 \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT6U (0xF0000000 \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_IBAT7L (0)
#define CONFIG_SYS_IBAT7U (0)
@@ -486,41 +522,45 @@
*/
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_NETDEV eth1
+#define CONFIG_NETDEV "eth1"
#define CONFIG_HOSTNAME simpc8313
#define CONFIG_ROOTPATH "/tftpboot/"
#define CONFIG_BOOTFILE "/tftpboot/uImage"
-#define CONFIG_UBOOTPATH u-boot-nand.bin /* U-Boot image on TFTP server */
-#define CONFIG_FDTFILE simpc8313.dtb
+ /* U-Boot image on TFTP server */
+#define CONFIG_UBOOTPATH "u-boot-nand.bin"
+#define CONFIG_FDTFILE "simpc8313.dtb"
-#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
+ /* default location for tftp and bootm */
+#define CONFIG_LOADADDR 500000
#define CONFIG_BOOTDELAY 5 /* 5 second delay */
#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTCOMMAND "nand read $loadaddr kernel 600000;bootm $loadaddr - $fdtaddr"
+#define CONFIG_BOOTCOMMAND "nand read $loadaddr kernel 600000;" \
+ "bootm $loadaddr - $fdtaddr"
#define XMK_STR(x) #x
#define MK_STR(x) XMK_STR(x)
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
+ "netdev=" CONFIG_NETDEV "\0" \
"ethprime=TSEC1\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "uboot=" CONFIG_UBOOTPATH "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+ "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"fdtaddr=ae0000\0" \
- "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
+ "fdtfile=" CONFIG_FDTFILE "\0" \
"console=ttyS0\0" \
"setbootargs=setenv bootargs " \
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
- "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
+ "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
+ "$netdev:off " \
+ "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
"load_uboot=tftp 100000 u-boot-nand.bin\0" \
"burn_uboot=nand erase u-boot 80000; " \
"nand write 100000 u-boot $filesize\0" \
@@ -533,7 +573,7 @@
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
"bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw " \
"console=ttyS0,115200\0" \
""
From df939e1647684982a25e32cb7fdf061ddefa85d9 Mon Sep 17 00:00:00 2001
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Tue, 11 Oct 2011 23:57:22 -0500
Subject: [PATCH 20/31] mpc83xx: cosmetic: TQM834x.h checkpatch compliance
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
include/configs/TQM834x.h | 277 ++++++++++++++++++++++++++++------------------
1 file changed, 169 insertions(+), 108 deletions(-)
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 9370ca8..a7f11d3 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -66,26 +66,27 @@
/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
+ /* DDR is system memory*/
+#define CONFIG_SYS_DDR_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define DDR_CASLAT_25 /* CASLAT set to 2.5 */
-#undef CONFIG_DDR_ECC /* only for ECC DDR module */
-#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
+#define DDR_CASLAT_25 /* CASLAT set to 2.5 */
+#undef CONFIG_DDR_ECC /* only for ECC DDR module */
+#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
+#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x00100000
/*
* FLASH on the Local Bus
*/
-#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */
#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
/*
@@ -93,34 +94,41 @@
*/
/*
- * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash
- * banks has to be determined at runtime and stored in a gloabl variable
- * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is only
- * used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array flash_info, and
- * should be made sufficiently large to accomodate the number of banks that
- * might actually be detected. Since most (all?) Flash related functions use
- * CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on the board, it is
- * defined as tqm834x_num_flash_banks.
+ * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
+ * Flash banks has to be determined at runtime and stored in a gloabl variable
+ * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
+ * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
+ * flash_info, and should be made sufficiently large to accomodate the number
+ * of banks that might actually be detected. Since most (all?) Flash related
+ * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
+ * the board, it is defined as tqm834x_num_flash_banks.
*/
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
-#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) | \
- BR_MS_GPCM | BR_PS_32 | BR_V)
+#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \
+ | BR_MS_GPCM \
+ | BR_PS_32 \
+ | BR_V)
/* FLASH timing (0x0000_0c54) */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | \
- OR_GPCM_SCY_5 | OR_GPCM_TRLX)
+#define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \
+ | OR_GPCM_ACS_DIV4 \
+ | OR_GPCM_SCY_5 \
+ | OR_GPCM_TRLX)
#define CONFIG_SYS_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \
+ | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001D /* 1 GiB window size (2^(size + 1)) */
+ /* 1 GiB window size (2^(size + 1)) */
+#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001D
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
+ /* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
/* disable remaining mappings */
#define CONFIG_SYS_BR1_PRELIM 0x00000000
@@ -150,14 +158,17 @@
#endif
#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB = 3 sect. for Mon */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */
+ /* Reserve 384 kB = 3 sect. for Mon */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
+ /* Reserve 512 kB for malloc */
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
/*
* Serial Port
@@ -169,7 +180,7 @@
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
@@ -177,30 +188,30 @@
/*
* I2C
*/
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_FSL_I2C
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed: 400KHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F /* slave address */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed: 400KHz */
+#define CONFIG_SYS_I2C_SLAVE 0x7F /* slave address */
+#define CONFIG_SYS_I2C_OFFSET 0x3000
/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes per write */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
-#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
+#define CONFIG_SYS_I2C_MULTI_EEPROMS /* more than one eeprom */
/* I2C RTC */
-#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
+#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
/* I2C SYSMON (LM75) */
-#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
-#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
+#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
+#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
#define CONFIG_SYS_DTT_MAX_TEMP 70
#define CONFIG_SYS_DTT_LOW_TEMP -30
-#define CONFIG_SYS_DTT_HYSTERESIS 3
+#define CONFIG_SYS_DTT_HYSTERESIS 3
/*
* TSEC
@@ -209,9 +220,9 @@
#define CONFIG_MII
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
+#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
#if defined(CONFIG_TSEC_ENET)
@@ -219,15 +230,15 @@
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
-#define TSEC1_PHY_ADDR 2
-#define TSEC2_PHY_ADDR 1
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
+#define TSEC1_PHY_ADDR 2
+#define TSEC2_PHY_ADDR 1
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: TSEC[0-1] */
-#define CONFIG_ETHPRIME "TSEC0"
+#define CONFIG_ETHPRIME "TSEC0"
#endif /* CONFIG_TSEC_ENET */
@@ -239,19 +250,20 @@
#if defined(CONFIG_PCI)
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
/* PCI1 host bridge */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x90000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
-#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
-#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
+#define CONFIG_SYS_PCI1_MEM_BASE 0x90000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE \
+ (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
+#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
+#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
+#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
#undef CONFIG_EEPRO100
#define CONFIG_EEPRO100
@@ -270,15 +282,16 @@
/*
* Environment
*/
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */
-#define CONFIG_ENV_SIZE 0x8000 /* 32K max size */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR \
+ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */
+#define CONFIG_ENV_SIZE 0x8000 /* 32K max size */
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/*
* BOOTP options
@@ -319,30 +332,32 @@
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif
#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
- #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+ /* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+ /* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
-#undef CONFIG_WATCHDOG /* watchdog disabled */
+#undef CONFIG_WATCHDOG /* watchdog disabled */
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
@@ -354,7 +369,8 @@
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
+ /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_SYS_HRCW_LOW (\
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
@@ -375,7 +391,7 @@
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII )
+ HRCWH_TSEC2M_IN_GMII)
#else
#define CONFIG_SYS_HRCW_HIGH (\
HRCWH_PCI_HOST |\
@@ -388,7 +404,7 @@
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII )
+ HRCWH_TSEC2M_IN_GMII)
#endif
/* System IO Config */
@@ -404,23 +420,55 @@
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR 0 - 512M */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
/* stack in DCACHE @ 512M (no backing mem) */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \
+ | BATU_BL_128K \
+ | BATU_VS \
+ | BATU_VP)
/* PCI */
#ifdef CONFIG_PCI
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_MEMCOHERENCE | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \
+ | BATU_BL_16M \
+ | BATU_VS \
+ | BATU_VP)
#else
#define CONFIG_SYS_IBAT3L (0)
#define CONFIG_SYS_IBAT3U (0)
@@ -431,12 +479,24 @@
#endif
/* IMMRBAR */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \
+ | BATU_BL_1M \
+ | BATU_VS \
+ | BATU_VP)
/* FLASH */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
@@ -464,10 +524,11 @@
* Environment Configuration
*/
-#define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */
+ /* default location for tftp and bootm */
+#define CONFIG_LOADADDR 400000
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_BAUDRATE 115200
@@ -486,7 +547,7 @@
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
- "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
"flash_nfs_old=run nfsargs addip addcons;" \
"bootm ${kernel_addr}\0" \
"flash_nfs=run nfsargs addip addcons;" \
@@ -530,8 +591,8 @@
#define MTDIDS_DEFAULT "nor0=TQM834x-0"
/* default mtd partition table */
-#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env),"\
- "1m(kernel),2m(initrd),"\
- "-(user);"\
+#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env)," \
+ "1m(kernel),2m(initrd)," \
+ "-(user);" \
#endif /* __CONFIG_H */
From b43b12e6b1e5f238b615f7faaffabe764a4c714a Mon Sep 17 00:00:00 2001
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Tue, 11 Oct 2011 23:57:23 -0500
Subject: [PATCH 21/31] mpc83xx: cosmetic: kmeter1.h checkpatch compliance
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
include/configs/kmeter1.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
index 8639ddd..3ae171b 100644
--- a/include/configs/kmeter1.h
+++ b/include/configs/kmeter1.h
@@ -49,7 +49,7 @@
HRCWL_CSB_TO_CLKIN_4X1 | \
HRCWL_CORE_TO_CSB_2X1 | \
HRCWL_CE_PLL_VCO_DIV_2 | \
- HRCWL_CE_TO_PLL_1X6 )
+ HRCWL_CE_TO_PLL_1X6)
#define CONFIG_SYS_HRCW_HIGH (\
HRCWH_CORE_ENABLE | \
@@ -59,7 +59,7 @@
HRCWH_ROM_LOC_LOCAL_16BIT | \
HRCWH_BIG_ENDIAN | \
HRCWH_LALE_EARLY | \
- HRCWH_LDP_CLEAR )
+ HRCWH_LDP_CLEAR)
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
From 80ae4df9294a04082118da8b6a8d27e7615e306f Mon Sep 17 00:00:00 2001
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Tue, 11 Oct 2011 23:57:24 -0500
Subject: [PATCH 22/31] mpc83xx: cosmetic: mpc8308_p1m.h checkpatch compliance
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
include/configs/mpc8308_p1m.h | 29 ++++++++++++++---------------
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
index 9e61fc1..6784c2e 100644
--- a/include/configs/mpc8308_p1m.h
+++ b/include/configs/mpc8308_p1m.h
@@ -220,7 +220,7 @@
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
@@ -246,10 +246,9 @@
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
-#define CONFIG_SYS_BR0_PRELIM (\
- CONFIG_SYS_FLASH_BASE /* Flash Base address */ |\
- (2 << BR_PS_SHIFT) /* 16 bit port size */ |\
- BR_V) /* valid */
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE /* Flash Base addr */ \
+ | (2 << BR_PS_SHIFT) /* 16 bit port */ \
+ | BR_V) /* valid */
#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
@@ -271,11 +270,11 @@
/*
* SJA1000 CAN controller on Local Bus
*/
-#define CONFIG_SYS_SJA1000_BASE 0xFBFF0000
-#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_SJA1000_BASE \
- | (1 << BR_PS_SHIFT) /* 8 bit port size */ \
- | BR_V ) /* valid */
-#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \
+#define CONFIG_SYS_SJA1000_BASE 0xFBFF0000
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SJA1000_BASE \
+ | (1 << BR_PS_SHIFT) /* 8 bit port */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 /* length 32K */ \
| OR_GPCM_SCY_5 \
| OR_GPCM_EHTR)
/* 0xFFFF8052 */
@@ -286,11 +285,11 @@
/*
* CPLD on Local Bus
*/
-#define CONFIG_SYS_CPLD_BASE 0xFBFF8000
-#define CONFIG_SYS_BR2_PRELIM ( CONFIG_SYS_CPLD_BASE \
- | (1 << BR_PS_SHIFT) /* 8 bit port size */ \
- | BR_V ) /* valid */
-#define CONFIG_SYS_OR2_PRELIM ( 0xFFFF8000 /* length 32K */ \
+#define CONFIG_SYS_CPLD_BASE 0xFBFF8000
+#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_CPLD_BASE \
+ | (1 << BR_PS_SHIFT) /* 8 bit port */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR2_PRELIM (0xFFFF8000 /* length 32K */ \
| OR_GPCM_SCY_4 \
| OR_GPCM_EHTR)
/* 0xFFFF8042 */
From 60e1dc151efd122c75bff60bf1df4c92138f2e78 Mon Sep 17 00:00:00 2001
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Tue, 11 Oct 2011 23:57:25 -0500
Subject: [PATCH 23/31] mpc83xx: cosmetic: sbc8349.h checkpatch compliance
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
include/configs/sbc8349.h | 236 ++++++++++++++++++++++++++++------------------
1 file changed, 143 insertions(+), 93 deletions(-)
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 7de90d5..6d38049 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -71,7 +71,7 @@
#define CONFIG_SYS_IMMR 0xE0000000
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
+#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x00100000
@@ -81,7 +81,7 @@
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
-#define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */
+#define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */
/*
* 32-bit data path mode.
@@ -95,7 +95,7 @@
*/
#undef CONFIG_DDR_32BIT
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
@@ -114,18 +114,22 @@
* NB: manual DDR setup untested on sbc834x
*/
#define CONFIG_SYS_DDR_SIZE 256 /* MB */
-#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \
+ | CSCONFIG_ROW_BIT_13 \
+ | CSCONFIG_COL_BIT_10)
#define CONFIG_SYS_DDR_TIMING_1 0x36332321
#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
-#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
+#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
#if defined(CONFIG_DDR_32BIT)
/* set burst length to 8 for 32-bit data path */
-#define CONFIG_SYS_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */
+ /* DLL,normal,seq,4/2.5, 8 burst len */
+#define CONFIG_SYS_DDR_MODE 0x00000023
#else
/* the default burst length is 4 - for 64-bit data path */
-#define CONFIG_SYS_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */
+ /* DLL,normal,seq,4/2.5, 4 burst len */
+#define CONFIG_SYS_DDR_MODE 0x00000022
#endif
#endif
@@ -133,27 +137,28 @@
* SDRAM on the Local Bus
*/
#define CONFIG_SYS_LBC_SDRAM_BASE 0x10000000 /* Localbus SDRAM */
-#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */
+#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */
/*
* FLASH on the Local Bus
*/
-#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */
#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \
- (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
- BR_V) /* valid */
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
+ | (2 << BR_PS_SHIFT) /* 16 bit port */ \
+ | BR_V) /* valid */
#define CONFIG_SYS_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* window base at flash base */
+ /* window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
@@ -168,14 +173,17 @@
#endif
#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
+ /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
+ /* Size of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/*
* Local Bus LCRR and LBCR regs
@@ -209,7 +217,8 @@
* FIXME: the top 17 bits of BR2.
*/
-#define CONFIG_SYS_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
+ /* Port-size=32bit, MSEL=SDRAM */
+#define CONFIG_SYS_BR2_PRELIM 0xF0001861
#define CONFIG_SYS_LBLAWBAR2_PRELIM 0xF0000000
#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64M */
@@ -229,18 +238,19 @@
#define CONFIG_SYS_OR2_PRELIM 0xFC006901
-#define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
+ /* LB sdram refresh timer, about 6us */
+#define CONFIG_SYS_LBC_LSRT 0x32000000
+ /* LB refresh timer prescal, 266MHz/32 */
+#define CONFIG_SYS_LBC_MRTPR 0x20000000
-#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFEN \
- | LSDMR_BSMA1516 \
- | LSDMR_RFCR8 \
- | LSDMR_PRETOACT6 \
- | LSDMR_ACTTORW3 \
- | LSDMR_BL8 \
- | LSDMR_WRC3 \
- | LSDMR_CL3 \
- )
+#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
+ | LSDMR_BSMA1516 \
+ | LSDMR_RFCR8 \
+ | LSDMR_PRETOACT6 \
+ | LSDMR_ACTTORW3 \
+ | LSDMR_BL8 \
+ | LSDMR_WRC3 \
+ | LSDMR_CL3)
/*
* SDRAM Controller configuration sequence.
@@ -262,7 +272,7 @@
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
@@ -271,7 +281,7 @@
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
-#ifdef CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif
@@ -284,19 +294,19 @@
#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_FSL_I2C
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C1_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C2_OFFSET
+#define CONFIG_SYS_I2C1_OFFSET 0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C2_OFFSET
/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
/* TSEC */
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
+#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
/*
* General PCI
@@ -308,9 +318,9 @@
#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
+#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
@@ -318,9 +328,9 @@
#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
-#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
+#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
+#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
#if defined(CONFIG_PCI)
@@ -386,7 +396,7 @@
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#else
- #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
+ #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
@@ -434,22 +444,25 @@
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
- #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+ /* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+ /* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
+ /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
@@ -502,7 +515,7 @@
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII )
+ HRCWH_TSEC2M_IN_GMII)
#else
#define CONFIG_SYS_HRCW_HIGH (\
HRCWH_PCI_HOST |\
@@ -515,7 +528,7 @@
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII )
+ HRCWH_TSEC2M_IN_GMII)
#endif
/* System IO Config */
@@ -523,13 +536,13 @@
#define CONFIG_SYS_SICRL SICRL_LDP_A
#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE)
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
+ | HID0_ENABLE_INSTRUCTION_CACHE)
-/* #define CONFIG_SYS_HID0_FINAL (\
+/* #define CONFIG_SYS_HID0_FINAL (\
HID0_ENABLE_INSTRUCTION_CACHE |\
HID0_ENABLE_M_BIT |\
- HID0_ENABLE_ADDRESS_BROADCAST ) */
+ HID0_ENABLE_ADDRESS_BROADCAST) */
#define CONFIG_SYS_HID2 HID2_HBE
@@ -537,15 +550,31 @@
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR @ 0x00000000 */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
/* PCI @ 0x80000000 */
#ifdef CONFIG_PCI
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#else
#define CONFIG_SYS_IBAT1L (0)
#define CONFIG_SYS_IBAT1U (0)
@@ -554,10 +583,21 @@
#endif
#ifdef CONFIG_MPC83XX_PCI2
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#else
#define CONFIG_SYS_IBAT3L (0)
#define CONFIG_SYS_IBAT3U (0)
@@ -566,12 +606,20 @@
#endif
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \
- BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT6L (0xF0000000 \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE \
+ | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT7L (0)
@@ -613,10 +661,11 @@
#define CONFIG_ROOTPATH "/tftpboot/rootfs"
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
+ /* default location for tftp and bootm */
+#define CONFIG_LOADADDR 800000
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_BAUDRATE 115200
@@ -638,28 +687,29 @@
"bootm\0" \
"load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \
"update=protect off ff800000 ff83ffff; " \
- "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
+ "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
"upd=run load update\0" \
"fdtaddr=780000\0" \
"fdtfile=sbc8349.dtb\0" \
""
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
+ "$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND "run flash_self"
From be29fa71b05c92ee1326c0e67891fa3eea17da1b Mon Sep 17 00:00:00 2001
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Tue, 11 Oct 2011 23:57:26 -0500
Subject: [PATCH 24/31] mpc83xx: cosmetic: ve8313.h checkpatch compliance
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
include/configs/ve8313.h | 204 +++++++++++++++++++++++++----------------------
1 file changed, 109 insertions(+), 95 deletions(-)
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index 9d37359..479afba 100644
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -70,7 +70,7 @@
/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
@@ -78,59 +78,60 @@
* Manually set up DDR parameters, as this board does not
* have the SPD connected to I2C.
*/
-#define CONFIG_SYS_DDR_SIZE 128 /* MB */
-#define CONFIG_SYS_DDR_CONFIG ( CSCONFIG_EN \
+#define CONFIG_SYS_DDR_SIZE 128 /* MB */
+#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \
| CSCONFIG_AP \
| 0x00040000 /* TODO */ \
- | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
+ | CSCONFIG_ROW_BIT_13 \
+ | CSCONFIG_COL_BIT_10)
/* 0x80840102 */
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
- | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
- | ( 3 << TIMING_CFG0_RRT_SHIFT ) \
- | ( 2 << TIMING_CFG0_WWT_SHIFT ) \
- | ( 7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
- | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
- | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
- | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
+#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
+ | (0 << TIMING_CFG0_WRT_SHIFT) \
+ | (3 << TIMING_CFG0_RRT_SHIFT) \
+ | (2 << TIMING_CFG0_WWT_SHIFT) \
+ | (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+ | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+ | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+ | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
/* 0x0e720802 */
-#define CONFIG_SYS_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
- | ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
- | ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
- | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
- | ( 6 << TIMING_CFG1_REFREC_SHIFT ) \
- | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
- | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
- | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
+#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
+ | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+ | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
+ | (5 << TIMING_CFG1_CASLAT_SHIFT) \
+ | (6 << TIMING_CFG1_REFREC_SHIFT) \
+ | (2 << TIMING_CFG1_WRREC_SHIFT) \
+ | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+ | (2 << TIMING_CFG1_WRTORD_SHIFT))
/* 0x26256222 */
-#define CONFIG_SYS_DDR_TIMING_2 ( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \
- | ( 5 << TIMING_CFG2_CPO_SHIFT ) \
- | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
- | ( 1 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
- | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
- | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
- | ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) )
+#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
+ | (5 << TIMING_CFG2_CPO_SHIFT) \
+ | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+ | (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+ | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+ | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+ | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
/* 0x029028c7 */
-#define CONFIG_SYS_DDR_INTERVAL ( ( 0x320 << SDRAM_INTERVAL_REFINT_SHIFT ) \
- | ( 0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
+#define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \
+ | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
/* 0x03202000 */
-#define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \
+#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_32_BE )
+ | SDRAM_CFG_32_BE)
/* 0x43080000 */
-#define CONFIG_SYS_SDRAM_CFG2 0x00401000
-#define CONFIG_SYS_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \
- | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
+#define CONFIG_SYS_SDRAM_CFG2 0x00401000
+#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
+ | (0x0232 << SDRAM_MODE_SD_SHIFT))
/* 0x44400232 */
-#define CONFIG_SYS_DDR_MODE_2 0x8000C000
+#define CONFIG_SYS_DDR_MODE_2 0x8000C000
#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
/*0x02000000*/
-#define CONFIG_SYS_DDRCDR_VALUE ( DDRCDR_EN \
+#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
| DDRCDR_PZ_NOMZ \
| DDRCDR_NZ_NOMZ \
- | DDRCDR_M_ODR )
+ | DDRCDR_M_ODR)
/* 0x73000002 */
/*
@@ -143,16 +144,16 @@
#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
-#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE | \
- (2 << BR_PS_SHIFT) | /* 16 bit */ \
- BR_V) /* valid */
+#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
+ | (2 << BR_PS_SHIFT) /* 16 bit */ \
+ | BR_V) /* valid */
#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV4 \
- | OR_GPCM_SCY_5 \
- | OR_GPCM_TRLX \
- | OR_GPCM_EAD)
- /* 0xfe000c55 */
+ | OR_GPCM_CSNT \
+ | OR_GPCM_ACS_DIV4 \
+ | OR_GPCM_SCY_5 \
+ | OR_GPCM_TRLX \
+ | OR_GPCM_EAD)
+ /* 0xfe000c55 */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */
@@ -171,10 +172,10 @@
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
@@ -201,19 +202,19 @@
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
-#define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \
- | BR_PS_8 \
- | BR_DECC_CHK_GEN \
- | BR_MS_FCM \
- | BR_V ) /* valid */
- /* 0x61000c21 */
+#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
+ | BR_PS_8 \
+ | BR_DECC_CHK_GEN \
+ | BR_MS_FCM \
+ | BR_V) /* valid */
+ /* 0x61000c21 */
#define CONFIG_SYS_NAND_OR_PRELIM (0xffff8000 \
- | OR_FCM_BCTLD \
- | OR_FCM_CHT \
- | OR_FCM_SCY_2 \
- | OR_FCM_RST \
- | OR_FCM_TRLX)
- /* 0xffff90ac */
+ | OR_FCM_BCTLD \
+ | OR_FCM_CHT \
+ | OR_FCM_SCY_2 \
+ | OR_FCM_RST \
+ | OR_FCM_TRLX)
+ /* 0xffff90ac */
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
@@ -227,27 +228,27 @@
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
/* CS2 NvRAM */
-#define CONFIG_SYS_BR2_PRELIM (0x60000000 \
- | BR_PS_8 \
+#define CONFIG_SYS_BR2_PRELIM (0x60000000 \
+ | BR_PS_8 \
| BR_V)
/* 0x60000801 */
-#define CONFIG_SYS_OR2_PRELIM (0xfffe0000 \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
+#define CONFIG_SYS_OR2_PRELIM (0xfffe0000 \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_XACS \
| OR_GPCM_SCY_3 \
| OR_GPCM_TRLX \
| OR_GPCM_EHTR \
| OR_GPCM_EAD)
/* 0xfffe0937 */
/* local bus read write buffer mapping SRAM@0x64000000 */
-#define CONFIG_SYS_BR3_PRELIM (0x62000000 \
- | BR_PS_16 \
+#define CONFIG_SYS_BR3_PRELIM (0x62000000 \
+ | BR_PS_16 \
| BR_V)
/* 0x62001001 */
-#define CONFIG_SYS_OR3_PRELIM (0xfe000000 \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
+#define CONFIG_SYS_OR3_PRELIM (0xfe000000 \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
| OR_GPCM_TRLX \
| OR_GPCM_EHTR \
@@ -289,9 +290,9 @@
#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
+#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
@@ -320,13 +321,13 @@
* Environment
*/
#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
- CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_ADDR \
+ (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CONFIG_ENV_SIZE 0x4000
/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
- CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_OFFSET_REDUND \
+ (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
@@ -371,7 +372,8 @@
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
+ /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
/* 0x64050000 */
#define CONFIG_SYS_HRCW_LOW (\
@@ -421,18 +423,26 @@
/* DDR @ 0x00000000 */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
- BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#if defined(CONFIG_PCI)
/* PCI @ 0x80000000 */
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
- BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#else
#define CONFIG_SYS_IBAT1L (0)
#define CONFIG_SYS_IBAT1U (0)
@@ -447,10 +457,14 @@
#define CONFIG_SYS_IBAT4U (0)
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | \
- BATU_VP)
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
@@ -495,10 +509,10 @@
"u-boot_addr_r=100000\0" \
"load=tftp ${u-boot_addr_r} ${u-boot}\0" \
"update=protect off " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
- "erase " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
- "cp.b ${u-boot_addr_r} " MK_STR(CONFIG_SYS_FLASH_BASE) \
- " ${filesize};" \
- "protect on " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
+ "erase " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
+ "cp.b ${u-boot_addr_r} " MK_STR(CONFIG_SYS_FLASH_BASE) \
+ " ${filesize};" \
+ "protect on " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
#undef MK_STR
#undef XMK_STR
From c7357a2b90aff93bbc3b8e71867b2e86eb0b73da Mon Sep 17 00:00:00 2001
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Tue, 11 Oct 2011 23:57:27 -0500
Subject: [PATCH 25/31] mpc83xx: cosmetic: vme8349.h checkpatch compliance
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
include/configs/vme8349.h | 35 ++++++++++++++++++-----------------
1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index bdb64ba..7085596 100644
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -151,7 +151,7 @@
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
@@ -191,7 +191,7 @@
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
@@ -217,7 +217,7 @@
#define CONFIG_I2C_CMD_TREE
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {{0, 0x69}} /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
#define CONFIG_SYS_I2C1_OFFSET 0x3000
#define CONFIG_SYS_I2C2_OFFSET 0x3100
#define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C1_OFFSET
@@ -579,22 +579,23 @@
"fdtfile=vme8349.dtb\0" \
""
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
+ "$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND "run flash_self"
From 72cd4087c9644812b0fff9440e88e986d259bf41 Mon Sep 17 00:00:00 2001
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Tue, 11 Oct 2011 23:57:28 -0500
Subject: [PATCH 26/31] mpc83xx: Cleanup usage of BAT constants
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
include/configs/MERGERBOX.h | 14 +++++++-------
include/configs/MPC8308RDB.h | 10 +++++-----
include/configs/MPC8313ERDB.h | 10 +++++-----
include/configs/MPC8315ERDB.h | 14 +++++++-------
include/configs/MPC8323ERDB.h | 14 +++++++-------
include/configs/MPC832XEMDS.h | 16 ++++++++--------
include/configs/MPC8349EMDS.h | 19 +++++++++----------
include/configs/MPC8349ITX.h | 14 +++++++-------
include/configs/MPC8360EMDS.h | 18 +++++++++---------
include/configs/MPC8360ERDK.h | 18 +++++++++---------
include/configs/MPC837XEMDS.h | 18 +++++++++---------
include/configs/MPC837XERDB.h | 18 +++++++++---------
include/configs/MVBLM7.h | 13 ++++++-------
include/configs/SIMPC8313.h | 12 ++++++------
include/configs/TQM834x.h | 16 ++++++++--------
include/configs/km/km83xx-common.h | 14 +++++++-------
include/configs/kmeter1.h | 8 ++++----
include/configs/kmsupx5.h | 4 ++--
include/configs/mpc8308_p1m.h | 10 +++++-----
include/configs/sbc8349.h | 14 +++++++-------
include/configs/suvd3.h | 8 ++++----
include/configs/tuda1.h | 8 ++++----
include/configs/tuxa1.h | 8 ++++----
include/configs/ve8313.h | 12 ++++++------
include/configs/vme8349.h | 16 ++++++++--------
25 files changed, 162 insertions(+), 164 deletions(-)
diff --git a/include/configs/MERGERBOX.h b/include/configs/MERGERBOX.h
index 100d6f7..aa35c1c 100644
--- a/include/configs/MERGERBOX.h
+++ b/include/configs/MERGERBOX.h
@@ -408,7 +408,7 @@
/* DDR: cache cacheable */
#define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM | BATL_PP_10 |\
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM | BATL_PP_RW |\
BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM | BATU_BL_256M | BATU_VS |\
BATU_VP)
@@ -422,7 +422,7 @@
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_10 |\
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_RW |\
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS |\
BATU_VP)
@@ -436,23 +436,23 @@
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 |\
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW |\
BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_64M |\
BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K |\
BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 |\
+#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_RW |\
BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M |\
BATU_VS | BATU_VP)
@@ -460,7 +460,7 @@
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_RW | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M |\
BATU_VS | BATU_VP)
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index 3979aa0..8f0835f 100644
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -463,7 +463,7 @@
*/
/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
BATU_VS | BATU_VP)
@@ -471,7 +471,7 @@
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
BATU_VP)
@@ -479,17 +479,17 @@
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
BATL_CACHEINHIBIT | \
BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 31289a9..b2af4f9 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -561,20 +561,20 @@
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR @ 0x00000000 */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
/* PCI @ 0x80000000 */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
@@ -590,7 +590,7 @@
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
@@ -599,7 +599,7 @@
| BATU_VP)
/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT7L (0)
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 69a906b..2305215 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -572,7 +572,7 @@
/* DDR: cache cacheable */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
| BATU_BL_128M \
@@ -583,7 +583,7 @@
/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
@@ -595,20 +595,20 @@
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
| BATU_BL_32M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \
| BATU_BL_128K \
| BATU_VS \
@@ -618,7 +618,7 @@
/* PCI MEM space: cacheable */
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS \
| BATU_BL_256M \
@@ -629,7 +629,7 @@
/* PCI MMIO space: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS \
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index f310423..b830a98 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -454,7 +454,7 @@
/* DDR: cache cacheable */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
| BATU_BL_256M \
@@ -465,7 +465,7 @@
/* IMMRBAR & PCI IO: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
@@ -477,14 +477,14 @@
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
| BATU_BL_32M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
@@ -495,7 +495,7 @@
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \
| BATU_BL_128K \
| BATU_VS \
@@ -506,7 +506,7 @@
#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS \
| BATU_BL_256M \
@@ -516,7 +516,7 @@
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
/* PCI MMIO space: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS \
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 2a86262..40a1e0e 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -477,7 +477,7 @@
/* DDR: cache cacheable */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
| BATU_BL_256M \
@@ -488,7 +488,7 @@
/* IMMRBAR & PCI IO: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
@@ -500,7 +500,7 @@
/* BCSR: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \
@@ -512,14 +512,14 @@
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
| BATU_BL_32M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
@@ -530,7 +530,7 @@
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
| BATU_BL_128K \
| BATU_VS \
@@ -541,7 +541,7 @@
#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
| BATU_BL_256M \
@@ -551,7 +551,7 @@
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index e3052f0..0c0e904 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -645,7 +645,7 @@
/* DDR @ 0x00000000 */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
| BATU_BL_256M \
@@ -655,14 +655,14 @@
/* PCI @ 0x80000000 */
#ifdef CONFIG_PCI
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
@@ -678,14 +678,14 @@
#ifdef CONFIG_MPC83XX_PCI2
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
@@ -701,7 +701,7 @@
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
@@ -711,10 +711,9 @@
/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
#define CONFIG_SYS_IBAT6L (0xF0000000 \
- | BATL_PP_10 \
- | BATL_MEMCOHERENCE |\
- \
- BATL_GUARDEDSTORAGE)
+ | BATL_PP_RW \
+ | BATL_MEMCOHERENCE \
+ | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U (0xF0000000 \
| BATU_BL_256M \
| BATU_VS \
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 0365c22..3fb558f 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -646,7 +646,7 @@ boards, we say we have two, but don't display a message if we find only one. */
/* DDR */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
| BATU_BL_256M \
@@ -656,14 +656,14 @@ boards, we say we have two, but don't display a message if we find only one. */
/* PCI */
#ifdef CONFIG_PCI
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
@@ -679,14 +679,14 @@ boards, we say we have two, but don't display a message if we find only one. */
#ifdef CONFIG_MPC83XX_PCI2
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
@@ -702,7 +702,7 @@ boards, we say we have two, but don't display a message if we find only one. */
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
@@ -712,7 +712,7 @@ boards, we say we have two, but don't display a message if we find only one. */
/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
#define CONFIG_SYS_IBAT6L (0xF0000000 \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U (0xF0000000 \
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index a4dd430..3a5af2d 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -522,7 +522,7 @@
/* DDR/LBC SDRAM: cacheable */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
| BATU_BL_256M \
@@ -533,7 +533,7 @@
/* IMMRBAR & PCI IO: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
@@ -545,7 +545,7 @@
/* BCSR: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \
@@ -557,21 +557,21 @@
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
| BATU_BL_32M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
/* DDR/LBC SDRAM next 256M: cacheable */
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM_BASE2 \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM_BASE2 \
| BATU_BL_256M \
@@ -581,7 +581,7 @@
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
| BATU_BL_128K \
| BATU_VS \
@@ -592,7 +592,7 @@
#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
| BATU_BL_256M \
@@ -602,7 +602,7 @@
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index f565613..04ea738 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -431,7 +431,7 @@
/* DDR: cache cacheable */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
| BATU_BL_256M \
@@ -442,7 +442,7 @@
/* IMMRBAR & PCI IO: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
@@ -454,7 +454,7 @@
/* NAND: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_NAND_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_NAND_BASE \
@@ -466,21 +466,21 @@
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
| BATU_BL_32M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
/* Stack in dcache: cacheable, no memory coherence */
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR \
- | BATL_PP_10)
+ | BATL_PP_RW)
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \
| BATU_BL_128K \
| BATU_VS \
@@ -489,7 +489,7 @@
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_VIDEO_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_VIDEO_BASE \
@@ -502,7 +502,7 @@
#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
| BATU_BL_256M \
@@ -512,7 +512,7 @@
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 76e598d..dc4d877 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -564,7 +564,7 @@ extern int board_pci_host_broken(void);
#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \
| BATU_BL_256M \
@@ -574,7 +574,7 @@ extern int board_pci_host_broken(void);
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \
| BATU_BL_256M \
@@ -585,7 +585,7 @@ extern int board_pci_host_broken(void);
/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
@@ -597,7 +597,7 @@ extern int board_pci_host_broken(void);
/* BCSR: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \
@@ -609,20 +609,20 @@ extern int board_pci_host_broken(void);
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \
| BATU_BL_32M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
| BATU_BL_128K \
| BATU_VS \
@@ -633,7 +633,7 @@ extern int board_pci_host_broken(void);
#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \
| BATU_BL_256M \
@@ -643,7 +643,7 @@ extern int board_pci_host_broken(void);
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 4b1d455..371fff7 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -574,7 +574,7 @@
#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \
| BATU_BL_256M \
@@ -584,7 +584,7 @@
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \
| BATU_BL_256M \
@@ -595,7 +595,7 @@
/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
@@ -607,7 +607,7 @@
/* L2 Switch: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE \
@@ -619,20 +619,20 @@
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \
| BATU_BL_32M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
| BATU_BL_128K \
| BATU_VS \
@@ -643,7 +643,7 @@
#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \
| BATU_BL_256M \
@@ -653,7 +653,7 @@
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index 301df63..32cc929 100644
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -344,7 +344,7 @@
/* DDR */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
| BATU_BL_256M \
@@ -353,14 +353,14 @@
/* PCI */
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
@@ -376,7 +376,7 @@
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
@@ -386,10 +386,9 @@
/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
#define CONFIG_SYS_IBAT6L (0xF0000000 \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE \
- | \
- BATL_GUARDEDSTORAGE)
+ | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U (0xF0000000 \
| BATU_BL_256M \
| BATU_VS \
diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h
index b1ed254..e7d477d 100644
--- a/include/configs/SIMPC8313.h
+++ b/include/configs/SIMPC8313.h
@@ -447,26 +447,26 @@
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR @ 0x00000000 */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
- | BATL_PP_10)
+ | BATL_PP_RW)
#define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
/* PCI @ 0x80000000 */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MEM_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MMIO_BASE \
@@ -480,7 +480,7 @@
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
@@ -490,7 +490,7 @@
/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
#define CONFIG_SYS_IBAT6L (0xF0000000 \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U (0xF0000000 \
| BATU_BL_256M \
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index a7f11d3..ae296eb 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -421,14 +421,14 @@
/* DDR 0 - 512M */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
| BATU_BL_256M \
@@ -437,7 +437,7 @@
/* stack in DCACHE @ 512M (no backing mem) */
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \
| BATU_BL_128K \
@@ -447,14 +447,14 @@
/* PCI */
#ifdef CONFIG_PCI
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \
@@ -462,7 +462,7 @@
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \
@@ -480,7 +480,7 @@
/* IMMRBAR */
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \
@@ -490,7 +490,7 @@
/* FLASH */
#define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \
diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h
index 2014e37..0d411c2 100644
--- a/include/configs/km/km83xx-common.h
+++ b/include/configs/km/km83xx-common.h
@@ -239,7 +239,7 @@
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
BATU_VS | BATU_VP)
@@ -247,7 +247,7 @@
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
/* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
| BATU_VP)
@@ -255,25 +255,25 @@
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
index 3ae171b..5f68dc9 100644
--- a/include/configs/kmeter1.h
+++ b/include/configs/kmeter1.h
@@ -151,22 +151,22 @@
*/
/* PAXE: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_RW | \
BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | \
BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_RW | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
-#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_MEMCOHERENCE)
#define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT6L CFG_IBAT6L
#define CFG_DBAT6U CFG_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */
-#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
+#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_RW | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT7L CFG_IBAT7L
diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h
index f8cd8e0..ccc1561 100644
--- a/include/configs/kmsupx5.h
+++ b/include/configs/kmsupx5.h
@@ -74,11 +74,11 @@
OR_GPCM_EAD)
/* LPXF: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_RW | \
BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_LPXF_BASE | BATU_BL_256M | \
BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_DBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_RW | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
index 6784c2e..c409acb 100644
--- a/include/configs/mpc8308_p1m.h
+++ b/include/configs/mpc8308_p1m.h
@@ -454,7 +454,7 @@
*/
/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
BATU_VS | BATU_VP)
@@ -462,7 +462,7 @@
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
BATU_VP)
@@ -470,17 +470,17 @@
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
BATL_CACHEINHIBIT | \
BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 6d38049..99f8fb7 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -551,7 +551,7 @@
/* DDR @ 0x00000000 */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
| BATU_BL_256M \
@@ -561,14 +561,14 @@
/* PCI @ 0x80000000 */
#ifdef CONFIG_PCI
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
@@ -584,14 +584,14 @@
#ifdef CONFIG_MPC83XX_PCI2
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
@@ -607,7 +607,7 @@
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
@@ -617,7 +617,7 @@
/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
#define CONFIG_SYS_IBAT6L (0xF0000000 \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h
index 0b59d51..5f2e1e3 100644
--- a/include/configs/suvd3.h
+++ b/include/configs/suvd3.h
@@ -85,19 +85,19 @@
/* APP1: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \
BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
diff --git a/include/configs/tuda1.h b/include/configs/tuda1.h
index 853c00a..7ae7d58 100644
--- a/include/configs/tuda1.h
+++ b/include/configs/tuda1.h
@@ -106,7 +106,7 @@
*/
/* PAXG: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \
- BATL_PP_10 | \
+ BATL_PP_RW | \
BATL_MEMCOHERENCE)
/* 512M should also include APP2... */
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \
@@ -114,21 +114,21 @@
BATU_VS | \
BATU_VP)
#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \
- BATL_PP_10 | \
+ BATL_PP_RW | \
BATL_CACHEINHIBIT | \
BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
/* PINC3: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \
- BATL_PP_10 | \
+ BATL_PP_RW | \
BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | \
BATU_BL_256M | \
BATU_VS | \
BATU_VP)
#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | \
- BATL_PP_10 | \
+ BATL_PP_RW | \
BATL_CACHEINHIBIT | \
BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
diff --git a/include/configs/tuxa1.h b/include/configs/tuxa1.h
index ceeb5a3..815c260 100644
--- a/include/configs/tuxa1.h
+++ b/include/configs/tuxa1.h
@@ -99,20 +99,20 @@
* MMU Setup
*/
/* LPXF: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_RW | \
BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_LPXF_BASE | BATU_BL_256M | \
BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_DBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_RW | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
/* PINC2: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_RW | \
BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PINC2_BASE | BATU_BL_256M | \
BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_DBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_RW | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index 479afba..f657610 100644
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -422,7 +422,7 @@
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR @ 0x00000000 */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
| BATU_BL_256M \
| BATU_VS \
@@ -430,13 +430,13 @@
#if defined(CONFIG_PCI)
/* PCI @ 0x80000000 */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
@@ -458,7 +458,7 @@
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
@@ -467,11 +467,11 @@
| BATU_VP)
/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
/* FPGA, SRAM, NAND @ 0x60000000 */
-#define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT7U (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index 7085596..19b4ad6 100644
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -455,18 +455,18 @@
#define CONFIG_HIGH_BATS /* High BATs supported */
/* DDR @ 0x00000000 */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
BATU_VS | BATU_VP)
/* PCI @ 0x80000000 */
#ifdef CONFIG_PCI
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
BATU_VS | BATU_VP)
@@ -478,11 +478,11 @@
#endif
#ifdef CONFIG_MPC83XX_PCI2
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \
BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
BATU_VS | BATU_VP)
@@ -494,17 +494,17 @@
#endif
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \
BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#if (CONFIG_SYS_DDR_SIZE == 512)
#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
- BATL_PP_10 | BATL_MEMCOHERENCE)
+ BATL_PP_RW | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
BATU_BL_256M | BATU_VS | BATU_VP)
#else
From 2fef402097866b4172d7a966a72397a5ccba5b10 Mon Sep 17 00:00:00 2001
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Tue, 11 Oct 2011 23:57:29 -0500
Subject: [PATCH 27/31] mpc83xx: Cleanup usage of DDR constants
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
arch/powerpc/cpu/mpc83xx/spd_sdram.c | 9 +++++++
include/configs/MPC8308RDB.h | 5 ++--
include/configs/MPC8313ERDB.h | 10 ++++---
include/configs/MPC8315ERDB.h | 5 ++--
include/configs/MPC8323ERDB.h | 2 --
include/configs/MPC832XEMDS.h | 52 ++++++++++++++++++++++++++++++------
include/configs/MPC8360ERDK.h | 9 ++++---
include/configs/MPC837XEMDS.h | 14 ++++++----
include/configs/MPC837XERDB.h | 28 ++++++++++++-------
include/configs/MVBLM7.h | 5 +++-
include/configs/kmeter1.h | 5 ++--
include/configs/mpc8308_p1m.h | 10 ++++---
include/configs/ve8313.h | 5 ++--
include/configs/vme8349.h | 9 ++++---
include/mpc83xx.h | 32 ++++++++++++++++++++--
15 files changed, 150 insertions(+), 50 deletions(-)
diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
index 9b01f0d..3855bfd 100644
--- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c
+++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
@@ -46,10 +46,19 @@ void board_add_ram_info(int use_default)
printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
>> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
+ if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16)
+ puts(", 16-bit");
+ else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32)
+ puts(", 32-bit");
+ else
+ puts(", unknown width");
+#else
if (ddr->sdram_cfg & SDRAM_CFG_32_BE)
puts(", 32-bit");
else
puts(", 64-bit");
+#endif
if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
puts(", ECC on");
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index 8f0835f..334c96e 100644
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -149,7 +149,8 @@
#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
- | 0x00010000 /* ODT_WR to CSn */ \
+ | CSCONFIG_ODT_RD_NEVER \
+ | CSCONFIG_ODT_WR_ONLY_CURRENT \
| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
/* 0x80010102 */
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
@@ -184,7 +185,7 @@
/* 0x03600100 */
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_32_BE)
+ | SDRAM_CFG_DBW_32)
/* 0x43080000 */
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index b2af4f9..93e1b1b 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -131,7 +131,8 @@
*/
#define CONFIG_SYS_DDR_SIZE 128 /* MB */
#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \
- | 0x00010000 /* TODO */ \
+ | CSCONFIG_ODT_RD_NEVER \
+ | CSCONFIG_ODT_WR_ONLY_CURRENT \
| CSCONFIG_ROW_BIT_13 \
| CSCONFIG_COL_BIT_10)
/* 0x80010102 */
@@ -169,12 +170,13 @@
#if defined(CONFIG_DDR_2T_TIMING)
#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_2T_EN \
- | SDRAM_CFG_DBW_32)
+ | SDRAM_CFG_DBW_32 \
+ | SDRAM_CFG_2T_EN)
+ /* 0x43088000 */
#else
#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_32_BE)
+ | SDRAM_CFG_DBW_32)
/* 0x43080000 */
#endif
#define CONFIG_SYS_SDRAM_CFG2 0x00401000
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 2305215..0ae1d99 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -141,7 +141,8 @@
#define CONFIG_SYS_DDR_SIZE 128 /* MB */
#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
- | 0x00010000 /* ODT_WR to CSn */ \
+ | CSCONFIG_ODT_RD_NEVER \
+ | CSCONFIG_ODT_WR_ONLY_CURRENT \
| CSCONFIG_ROW_BIT_13 \
| CSCONFIG_COL_BIT_10)
/* 0x80010102 */
@@ -177,7 +178,7 @@
/* 0x03600100 */
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_32_BE)
+ | SDRAM_CFG_DBW_32)
/* 0x43080000 */
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index b830a98..28c61ca 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -78,7 +78,6 @@
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
#undef CONFIG_SPD_EEPROM
#if defined(CONFIG_SPD_EEPROM)
@@ -90,7 +89,6 @@
*/
#define CONFIG_SYS_DDR_SIZE 64 /* MB */
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
- | CSCONFIG_ODT_WR_ACS \
| CSCONFIG_ROW_BIT_13 \
| CSCONFIG_COL_BIT_9)
/* 0x80010101 */
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 40a1e0e..d552046 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -111,17 +111,53 @@
/* Manually set up DDR parameters
*/
#define CONFIG_SYS_DDR_SIZE 128 /* MB */
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80840102
-#define CONFIG_SYS_DDR_TIMING_0 0x00220802
-#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
-#define CONFIG_SYS_DDR_TIMING_2 0x0f9048ca
+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
+ | CSCONFIG_AP \
+ | CSCONFIG_ODT_WR_CFG \
+ | CSCONFIG_ROW_BIT_13 \
+ | CSCONFIG_COL_BIT_10)
+ /* 0x80840102 */
+#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
+ | (0 << TIMING_CFG0_WRT_SHIFT) \
+ | (0 << TIMING_CFG0_RRT_SHIFT) \
+ | (0 << TIMING_CFG0_WWT_SHIFT) \
+ | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+ | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+ | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+ | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+ /* 0x00220802 */
+#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
+ | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+ | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
+ | (5 << TIMING_CFG1_CASLAT_SHIFT) \
+ | (13 << TIMING_CFG1_REFREC_SHIFT) \
+ | (3 << TIMING_CFG1_WRREC_SHIFT) \
+ | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+ | (2 << TIMING_CFG1_WRTORD_SHIFT))
+ /* 0x3935D322 */
+#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
+ | (31 << TIMING_CFG2_CPO_SHIFT) \
+ | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+ | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+ | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+ | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+ | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
+ /* 0x0F9048CA */
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
-#define CONFIG_SYS_DDR_MODE 0x44400232
+#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+ /* 0x02000000 */
+#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
+ | (0x0232 << SDRAM_MODE_SD_SHIFT))
+ /* 0x44400232 */
#define CONFIG_SYS_DDR_MODE2 0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL 0x03200064
+#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
+ | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+ /* 0x03200064 */
#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
-#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080000
+#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
+ | SDRAM_CFG_SDRAM_TYPE_DDR2 \
+ | SDRAM_CFG_32_BE)
+ /* 0x43080000 */
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
#endif
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index 04ea738..bc574a6 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -96,7 +96,10 @@
/*
* DDRCDR - DDR Control Driver Register
*/
-#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
+#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
+ | DDRCDR_ODT \
+ | DDRCDR_Q_DRN)
+ /* 0x80080001 */
#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */
@@ -105,11 +108,11 @@
*/
#define CONFIG_DDR_II
#define CONFIG_SYS_DDR_SIZE 256 /* MB */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
+#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| CSCONFIG_ROW_BIT_13 \
| CSCONFIG_COL_BIT_10 \
- | CSCONFIG_ODT_WR_ACS)
+ | CSCONFIG_ODT_WR_ONLY_CURRENT)
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_ECC_EN)
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index dc4d877..8c2af08 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -128,7 +128,10 @@
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_83XX_DDR_USES_CS0
-#define CONFIG_SYS_DDRCDR_VALUE 0x80080001 /* ODT 150ohm on SoC */
+#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
+ | DDRCDR_ODT \
+ | DDRCDR_Q_DRN)
+ /* 0x80080001 */ /* ODT 150ohm on SoC */
#undef CONFIG_DDR_ECC /* support DDR ECC function */
#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
@@ -147,10 +150,11 @@
#define CONFIG_SYS_DDR_SIZE 512 /* MB */
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
- | 0x00010000 /* ODT_WR to CSn */ \
- | CSCONFIG_ROW_BIT_14 \
- | CSCONFIG_COL_BIT_10)
- /* 0x80010202 */
+ | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \
+ | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \
+ | CSCONFIG_ROW_BIT_14 \
+ | CSCONFIG_COL_BIT_10)
+ /* 0x80010202 */
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
| (0 << TIMING_CFG0_WRT_SHIFT) \
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 371fff7..bf8a94d 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -165,9 +165,11 @@
* Manually set up DDR parameters
*/
#define CONFIG_SYS_DDR_SIZE 256 /* MB */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ODT_WR_ACS \
- | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
+ | CSCONFIG_ODT_WR_ONLY_CURRENT \
+ | CSCONFIG_ROW_BIT_13 \
+ | CSCONFIG_COL_BIT_10)
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
@@ -178,7 +180,6 @@
| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
- /* 0x00220802 */
/* 0x00260802 */ /* DDR400 */
#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
@@ -188,9 +189,15 @@
| (3 << TIMING_CFG1_WRREC_SHIFT) \
| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
| (2 << TIMING_CFG1_WRTORD_SHIFT))
- /* 0x3935d322 */
/* 0x3937d322 */
-#define CONFIG_SYS_DDR_TIMING_2 0x02984cc8
+#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
+ | (5 << TIMING_CFG2_CPO_SHIFT) \
+ | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+ | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+ | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+ | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+ | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
+ /* 0x02984cc8 */
#define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
| (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
@@ -198,12 +205,13 @@
#if defined(CONFIG_DDR_2T_TIMING)
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
- | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
- | SDRAM_CFG_2T_EN \
- | SDRAM_CFG_DBW_32)
+ | SDRAM_CFG_SDRAM_TYPE_DDR2 \
+ | SDRAM_CFG_32_BE \
+ | SDRAM_CFG_2T_EN)
+ /* 0x43088000 */
#else
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
- | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT)
+ | SDRAM_CFG_SDRAM_TYPE_DDR2)
/* 0x43000000 */
#endif
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index 32cc929..f0d4e80 100644
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -72,7 +72,10 @@
#define CONFIG_SYS_MEMTEST_END (70<<20)
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDRCDR 0x22000001
+#define CONFIG_SYS_DDRCDR (DDRCDR_PZ_HIZ \
+ | DDRCDR_NZ_HIZ \
+ | DDRCDR_Q_DRN)
+ /* 0x22000001 */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_DDR_SIZE 512
diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
index 5f68dc9..c04bde9 100644
--- a/include/configs/kmeter1.h
+++ b/include/configs/kmeter1.h
@@ -72,9 +72,10 @@
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
CSCONFIG_ROW_BIT_13 | \
CSCONFIG_COL_BIT_10 | \
- CSCONFIG_ODT_WR_ACS)
+ CSCONFIG_ODT_WR_ONLY_CURRENT)
-#define CONFIG_SYS_DDRCDR 0x40000001
+#define CONFIG_SYS_DDRCDR (DDRCDR_EN | DDRCDR_Q_DRN)
+ /* 0x40000001 */
#define CONFIG_SYS_DDR_MODE 0x47860452
#define CONFIG_SYS_DDR_MODE2 0x8080c000
diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
index c409acb..fbce800 100644
--- a/include/configs/mpc8308_p1m.h
+++ b/include/configs/mpc8308_p1m.h
@@ -157,9 +157,11 @@
#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
- | 0x00010000 /* ODT_WR to CSn */ \
- | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
- /* 0x80010102 */
+ | CSCONFIG_ODT_RD_NEVER \
+ | CSCONFIG_ODT_WR_ONLY_CURRENT \
+ | CSCONFIG_ROW_BIT_13 \
+ | CSCONFIG_COL_BIT_10)
+ /* 0x80010102 */
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
| (0 << TIMING_CFG0_WRT_SHIFT) \
@@ -192,7 +194,7 @@
/* 0x03600100 */
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_32_BE)
+ | SDRAM_CFG_DBW_32)
/* 0x43080000 */
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index f657610..69f29c7 100644
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -81,7 +81,8 @@
#define CONFIG_SYS_DDR_SIZE 128 /* MB */
#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \
| CSCONFIG_AP \
- | 0x00040000 /* TODO */ \
+ | CSCONFIG_ODT_RD_NEVER \
+ | CSCONFIG_ODT_WR_ALL \
| CSCONFIG_ROW_BIT_13 \
| CSCONFIG_COL_BIT_10)
/* 0x80840102 */
@@ -118,7 +119,7 @@
/* 0x03202000 */
#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_32_BE)
+ | SDRAM_CFG_DBW_32)
/* 0x43080000 */
#define CONFIG_SYS_SDRAM_CFG2 0x00401000
#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index 19b4ad6..8e9b1f0 100644
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -106,10 +106,13 @@
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
- DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
+ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
#define CONFIG_DDR_2T_TIMING
-#define CONFIG_SYS_DDRCDR 0x80080001
+#define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
+ | DDRCDR_ODT \
+ | DDRCDR_Q_DRN)
+ /* 0x80080001 */
/*
* FLASH on the Local Bus
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index aa9ce8d..a78f1a2 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -969,9 +969,29 @@
*/
#define CSCONFIG_EN 0x80000000
#define CSCONFIG_AP 0x00800000
-#define CSCONFIG_ODT_WR_ACS 0x00010000
-#if defined(CONFIG_MPC832x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
+#define CSCONFIG_ODT_RD_NEVER 0x00000000
+#define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000
+#define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000
+#define CSCONFIG_ODT_RD_ALL 0x00400000
+#define CSCONFIG_ODT_WR_NEVER 0x00000000
+#define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000
+#define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000
+#define CSCONFIG_ODT_WR_ALL 0x00040000
+#elif defined(CONFIG_MPC832x)
+#define CSCONFIG_ODT_RD_CFG 0x00400000
#define CSCONFIG_ODT_WR_CFG 0x00040000
+#elif defined(CONFIG_MPC8360) || defined(CONFIG_MPC837x)
+#define CSCONFIG_ODT_RD_NEVER 0x00000000
+#define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000
+#define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000
+#define CSCONFIG_ODT_RD_ONLY_OTHER_DIMM 0x00300000
+#define CSCONFIG_ODT_RD_ALL 0x00400000
+#define CSCONFIG_ODT_WR_NEVER 0x00000000
+#define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000
+#define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000
+#define CSCONFIG_ODT_WR_ONLY_OTHER_DIMM 0x00030000
+#define CSCONFIG_ODT_WR_ALL 0x00040000
#endif
#define CSCONFIG_BANK_BIT_3 0x00004000
#define CSCONFIG_ROW_BIT 0x00000700
@@ -1071,8 +1091,16 @@
#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
#define SDRAM_CFG_DYN_PWR 0x00200000
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
+#define SDRAM_CFG_DBW_MASK 0x00180000
+#define SDRAM_CFG_DBW_16 0x00100000
+#define SDRAM_CFG_DBW_32 0x00080000
+#else
#define SDRAM_CFG_32_BE 0x00080000
+#endif
+#if !defined(CONFIG_MPC8308)
#define SDRAM_CFG_8_BE 0x00040000
+#endif
#define SDRAM_CFG_NCAP 0x00020000
#define SDRAM_CFG_2T_EN 0x00008000
#define SDRAM_CFG_HSE 0x00000008
From 7d6a098219f8473ca4653cce5f7a49672b967f36 Mon Sep 17 00:00:00 2001
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Tue, 11 Oct 2011 23:57:30 -0500
Subject: [PATCH 28/31] mpc83xx: Cleanup usage of LBC constants
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
arch/powerpc/include/asm/fsl_lbc.h | 8 ++-
include/configs/MERGERBOX.h | 14 ++--
include/configs/MPC8308RDB.h | 39 ++++++----
include/configs/MPC8313ERDB.h | 70 ++++++++++++------
include/configs/MPC8315ERDB.h | 35 ++++-----
include/configs/MPC8323ERDB.h | 84 ++++------------------
include/configs/MPC832XEMDS.h | 143 ++++++++++++++++---------------------
include/configs/MPC8349EMDS.h | 55 ++++++++------
include/configs/MPC8349ITX.h | 33 +++++----
include/configs/MPC8360EMDS.h | 93 ++++++++++++++++++------
include/configs/MPC8360ERDK.h | 40 +++++++----
include/configs/MPC837XEMDS.h | 44 +++++++-----
include/configs/MPC837XERDB.h | 42 +++++++----
include/configs/MVBLM7.h | 15 ++--
include/configs/SIMPC8313.h | 14 ++--
include/configs/TQM834x.h | 5 +-
include/configs/km/km83xx-common.h | 14 ++--
include/configs/kmeter1.h | 7 +-
include/configs/kmsupx5.h | 4 +-
include/configs/mpc8308_p1m.h | 32 +++++----
include/configs/sbc8349.h | 55 +++++++++-----
include/configs/suvd3.h | 2 +-
include/configs/tuda1.h | 13 ++--
include/configs/tuxa1.h | 13 ++--
include/configs/ve8313.h | 25 +++----
include/configs/vme8349.h | 55 ++++++++++----
26 files changed, 548 insertions(+), 406 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index 8695a62..bf572b7 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -50,8 +50,10 @@ void lbc_sdram_init(void);
#define BR_MSEL 0x000000E0
#define BR_MSEL_SHIFT 5
#define BR_MS_GPCM 0x00000000 /* GPCM */
+#if !defined(CONFIG_MPC834x) && !defined(CONFIG_MPC8360)
#define BR_MS_FCM 0x00000020 /* FCM */
-#ifdef CONFIG_MPC83xx
+#endif
+#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8360)
#define BR_MS_SDRAM 0x00000060 /* SDRAM */
#elif defined(CONFIG_MPC85xx)
#define BR_MS_SDRAM 0x00000000 /* SDRAM */
@@ -138,8 +140,10 @@ void lbc_sdram_init(void);
#define OR_GPCM_EHTR_SHIFT 1
#define OR_GPCM_EHTR_CLEAR 0x00000000
#define OR_GPCM_EHTR_SET 0x00000002
+#if !defined(CONFIG_MPC8308)
#define OR_GPCM_EAD 0x00000001
#define OR_GPCM_EAD_SHIFT 0
+#endif
/* helpers to convert values into an OR address mask (GPCM mode) */
#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
@@ -196,8 +200,10 @@ void lbc_sdram_init(void);
#define OR_SDRAM_XAM_SHIFT 13
#define OR_SDRAM_COLS 0x00001C00
#define OR_SDRAM_COLS_SHIFT 10
+#define OR_SDRAM_MIN_COLS 7
#define OR_SDRAM_ROWS 0x000001C0
#define OR_SDRAM_ROWS_SHIFT 6
+#define OR_SDRAM_MIN_ROWS 9
#define OR_SDRAM_PMSEL 0x00000020
#define OR_SDRAM_PMSEL_SHIFT 5
#define OR_SDRAM_EAD 0x00000001
diff --git a/include/configs/MERGERBOX.h b/include/configs/MERGERBOX.h
index aa35c1c..8176916 100644
--- a/include/configs/MERGERBOX.h
+++ b/include/configs/MERGERBOX.h
@@ -159,11 +159,13 @@
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 |\
+ BR_MS_GPCM | BR_V)
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_FLASH_BASE | OR_UPM_XAM |\
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 |\
- OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX |\
- OR_GPCM_EHTR | OR_GPCM_EAD)
+ OR_GPCM_XACS | OR_GPCM_SCY_15 |\
+ OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET |\
+ OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 512
@@ -180,14 +182,14 @@
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BASE 0xE0600000
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | (2<<BR_DECC_SHIFT) |\
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | BR_DECC_CHK_GEN |\
BR_PS_8 | BR_MS_FCM | BR_V)
-#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 | OR_FCM_BCTLD | OR_FCM_CST |\
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CST |\
OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST |\
OR_FCM_TRLX | OR_FCM_EHTR)
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E
+#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
/*
* Serial Port
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index 334c96e..47ff2f5 100644
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -239,19 +239,18 @@
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
-#define CONFIG_SYS_BR0_PRELIM (\
- CONFIG_SYS_FLASH_BASE /* Flash Base address */ |\
- (2 << BR_PS_SHIFT) /* 16 bit port size */ |\
- BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
+ | BR_PS_16 /* 16 bit port */ \
+ | BR_MS_GPCM /* MSEL = GPCM */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX \
- | OR_GPCM_EHTR \
- | OR_GPCM_EAD)
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
/* 127 64KB sectors and 8 8KB top sectors per device */
@@ -264,12 +263,13 @@
* NAND Flash on the Local Bus
*/
#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
+#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* 8 bit port */ \
+ | BR_DECC_CHK_GEN /* Use HW ECC */ \
+ | BR_PS_8 /* 8 bit Port */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
-#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 /* length 32K */ \
+#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
@@ -283,9 +283,22 @@
#ifdef CONFIG_VSC7385_ENET
#define CONFIG_TSEC2
+ /* VSC7385 Base address on CS2 */
#define CONFIG_SYS_VSC7385_BASE 0xF0000000
-#define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */
-#define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/
+#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
+#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
+ | BR_PS_8 /* 8-bit port */ \
+ | BR_MS_GPCM /* MSEL = GPCM */ \
+ | BR_V) /* valid */
+ /* 0xF0000801 */
+#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_SETA \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET)
+ /* 0xFFFE09FF */
/* Access window base at VSC7385 base */
#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
/* Access window size 128K */
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 93e1b1b..21771fd 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -205,9 +205,10 @@
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
- | (2 << BR_PS_SHIFT) /* 16 bit port */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_NOR_OR_PRELIM (0xFF800000 /* 8 MByte */ \
+ | BR_PS_16 /* 16 bit port */ \
+ | BR_MS_GPCM /* MSEL = GPCM */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
| OR_GPCM_XACS \
| OR_GPCM_SCY_9 \
| OR_GPCM_EHTR \
@@ -215,7 +216,8 @@
/* 0xFF006FF7 TODO SLOW 16 MB flash size */
/* window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */
+ /* 16 MB window size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
@@ -271,14 +273,16 @@
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
+#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_DECC_CHK_GEN /* Use HW ECC */ \
| BR_PS_8 /* 8 bit port */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \
+#define CONFIG_SYS_NAND_OR_PRELIM \
+ (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
@@ -300,31 +304,57 @@
#endif
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
+#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
-/* local bus read write buffer mapping */
-#define CONFIG_SYS_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */
-#define CONFIG_SYS_OR3_PRELIM 0xFFFF8FF7 /* 32kB */
-#define CONFIG_SYS_LBLAWBAR3_PRELIM 0xFA000000
-#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E /* 32KB */
+/* local bus write LED / read status buffer (BCSR) mapping */
+#define CONFIG_SYS_BCSR_ADDR 0xFA000000
+#define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
+ /* map at 0xFA000000 on LCS3 */
+#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \
+ | BR_PS_8 /* 8 bit port */ \
+ | BR_MS_GPCM /* MSEL = GPCM */ \
+ | BR_V) /* valid */
+ /* 0xFA000801 */
+#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_ACS_DIV2 \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET \
+ | OR_GPCM_EAD)
+ /* 0xFFFF8FF7 */
+#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR
+#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
/* Vitesse 7385 */
-#define CONFIG_SYS_VSC7385_BASE 0xF0000000
-
#ifdef CONFIG_VSC7385_ENET
- /* VSC7385 Base address */
-#define CONFIG_SYS_BR2_PRELIM 0xf0000801
- /* VSC7385, 128K bytes*/
-#define CONFIG_SYS_OR2_PRELIM 0xfffe09ff
+ /* VSC7385 Base address on LCS2 */
+#define CONFIG_SYS_VSC7385_BASE 0xF0000000
+#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
+
+#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
+ | BR_PS_8 /* 8 bit port */ \
+ | BR_MS_GPCM /* MSEL = GPCM */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_SETA \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET \
+ | OR_GPCM_EAD)
+ /* 0xFFFE09FF */
+
/* Access window base at VSC7385 base */
#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
- /* Access window size 128K */
-#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010
+#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
#endif
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 0ae1d99..2ebe6ad 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -229,20 +229,21 @@
/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
- | (2 << BR_PS_SHIFT) /* 16 bit port */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_NOR_OR_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX \
- | OR_GPCM_EHTR \
- | OR_GPCM_EAD)
+ | BR_PS_16 /* 16 bit port */ \
+ | BR_MS_GPCM /* MSEL = GPCM */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+ | OR_UPM_XAM \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_ACS_DIV2 \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET \
+ | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
/* 127 64KB sectors and 8 8KB top sectors per device */
@@ -273,7 +274,8 @@
#define CONFIG_MTD_NAND_VERIFY_WRITE 1
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
+#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
+#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
@@ -282,11 +284,12 @@
#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_DECC_CHK_GEN /* Use HW ECC */ \
| BR_PS_8 /* 8 bit port */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \
+#define CONFIG_SYS_NAND_OR_PRELIM \
+ (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
@@ -308,7 +311,7 @@
#endif
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
+#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 28c61ca..40e9546 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -185,12 +185,22 @@
/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | (2 << BR_PS_SHIFT) /* 16 bit port */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */
+ | BR_PS_16 /* 16 bit port */ \
+ | BR_MS_GPCM /* MSEL = GPCM */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+ | OR_GPCM_XAM \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_ACS_DIV2 \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET \
+ | OR_GPCM_EAD)
+ /* 0xFE006FF7 */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
@@ -198,72 +208,6 @@
#undef CONFIG_SYS_FLASH_CHECKSUM
/*
- * SDRAM on the Local Bus
- */
-#undef CONFIG_SYS_LB_SDRAM /* The board has not SRDAM on local bus */
-
-#ifdef CONFIG_SYS_LB_SDRAM
-#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base addr */
-#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
-
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64MB */
-
-/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
-/*
- * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
- *
- * For BR2, need:
- * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
- * port size = 32-bits = BR2[19:20] = 11
- * no parity checking = BR2[21:22] = 00
- * SDRAM for MSEL = BR2[24:26] = 011
- * Valid = BR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
- *
- * CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
- * the top 17 bits of BR2.
- */
-
- /*Port size=32bit, MSEL=SDRAM */
-#define CONFIG_SYS_BR2_PRELIM 0xf0001861
-
-/*
- * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
- *
- * For OR2, need:
- * 64MB mask for AM, OR2[0:7] = 1111 1100
- * XAM, OR2[17:18] = 11
- * 9 columns OR2[19-21] = 010
- * 13 rows OR2[23-25] = 100
- * EAD set for extra time OR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
- */
-
-#define CONFIG_SYS_OR2_PRELIM 0xfc006901
-
- /* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_LSRT 0x32000000
- /* LB refresh timer prescal, 266MHz/32 */
-#define CONFIG_SYS_LBC_MRTPR 0x20000000
-
-#define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723
-
-#endif
-
-/*
- * Windows to access PIB via local bus
- */
- /* windows base 0xf8008000 */
-#define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8008000
-#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */
-
-/*
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index d552046..4ed5a97 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -210,12 +210,22 @@
/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | (2 << BR_PS_SHIFT) /* 16 bit port */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */
+ | BR_PS_16 /* 16 bit port */ \
+ | BR_MS_GPCM /* MSEL = GPCM */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+ | OR_GPCM_XAM \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_ACS_DIV2 \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET \
+ | OR_GPCM_EAD)
+ /* 0xfe006ff7 */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
@@ -228,94 +238,67 @@
#define CONFIG_SYS_BCSR 0xF8000000
/* Access window base at BCSR base */
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
- /* Access window size 32K */
-#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E
-
- /* Port size=8bit, MSEL=GPCM */
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801)
-#define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
-
-/*
- * SDRAM on the Local Bus
- */
-#undef CONFIG_SYS_LB_SDRAM /* The board has not SRDAM on local bus */
-
-#ifdef CONFIG_SYS_LB_SDRAM
-#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
-#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
-
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64MB */
-
-/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
-/*
- * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
- *
- * For BR2, need:
- * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
- * port size = 32-bits = BR2[19:20] = 11
- * no parity checking = BR2[21:22] = 00
- * SDRAM for MSEL = BR2[24:26] = 011
- * Valid = BR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
- *
- * CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
- * the top 17 bits of BR2.
- */
-
-#define CONFIG_SYS_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */
-
-/*
- * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
- *
- * For OR2, need:
- * 64MB mask for AM, OR2[0:7] = 1111 1100
- * XAM, OR2[17:18] = 11
- * 9 columns OR2[19-21] = 010
- * 13 rows OR2[23-25] = 100
- * EAD set for extra time OR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
- */
-
-#define CONFIG_SYS_OR2_PRELIM 0xfc006901
-
- /* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_LSRT 0x32000000
- /* LB refresh timer prescal, 266MHz/32 */
-#define CONFIG_SYS_LBC_MRTPR 0x20000000
-
-#define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723
-
-#endif
+#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
+
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
+ | BR_PS_8 \
+ | BR_MS_GPCM \
+ | BR_V)
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
+ | OR_GPCM_XAM \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET \
+ | OR_GPCM_EAD)
+ /* 0xFFFFE9F7 */
/*
* Windows to access PIB via local bus
*/
- /* windows base 0xf8008000 */
-#define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8008000
- /* windows size 64KB */
-#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000f
+ /* PIB window base 0xF8008000 */
+#define CONFIG_SYS_PIB_BASE 0xF8008000
+#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
+#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PIB_BASE
+#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
/*
* CS2 on Local Bus, to PIB
*/
- /* CS2 base address at 0xf8008000 */
-#define CONFIG_SYS_BR2_PRELIM 0xf8008801
- /* size 32KB, port size 8bit, GPCM */
-#define CONFIG_SYS_OR2_PRELIM 0xffffe9f7
+#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_PIB_BASE \
+ | BR_PS_8 \
+ | BR_MS_GPCM \
+ | BR_V)
+ /* 0xF8008801 */
+#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
+ | OR_GPCM_XAM \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET \
+ | OR_GPCM_EAD)
+ /* 0xffffe9f7 */
/*
* CS3 on Local Bus, to PIB
*/
- /* CS3 base address at 0xf8010000 */
-#define CONFIG_SYS_BR3_PRELIM 0xf8010801
- /* size 32KB, port size 8bit, GPCM */
-#define CONFIG_SYS_OR3_PRELIM 0xffffe9f7
+#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIB_BASE + \
+ CONFIG_SYS_PIB_WINDOW_SIZE) \
+ | BR_PS_8 \
+ | BR_MS_GPCM \
+ | BR_V)
+ /* 0xF8010801 */
+#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
+ | OR_GPCM_XAM \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET \
+ | OR_GPCM_EAD)
+ /* 0xffffe9f7 */
/*
* Serial Port
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 0c0e904..a6aebb7 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -178,21 +178,23 @@
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
- (2 << BR_PS_SHIFT) | /* 16 bit port */ \
- BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
+ | BR_PS_16 /* 16 bit port */ \
+ | BR_MS_GPCM /* MSEL = GPCM */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX \
- | OR_GPCM_EHTR \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET \
| OR_GPCM_EAD)
+
/* window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
@@ -215,11 +217,19 @@
#define CONFIG_SYS_BCSR 0xE2400000
/* Access window base at BCSR base */
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
- /* Access window size 32K */
-#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E
- /* Port-size=8bit, MSEL=GPCM */
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801)
-#define CONFIG_SYS_OR1_PRELIM 0xFFFFE8F0 /* length 32K */
+#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
+ | BR_PS_8 \
+ | BR_MS_GPCM \
+ | BR_V)
+ /* 0x00000801 */
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
+ | OR_GPCM_XAM \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_TRLX_CLEAR \
+ | OR_GPCM_EHTR_CLEAR)
+ /* 0xFFFFE8F0 */
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
@@ -263,15 +273,15 @@
*
* 0 4 8 12 16 20 24 28
* 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
- *
- * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
- * FIXME: the top 17 bits of BR2.
*/
- /* Port-size=32bit, MSEL=SDRAM */
-#define CONFIG_SYS_BR2_PRELIM 0xF0001861
-#define CONFIG_SYS_LBLAWBAR2_PRELIM 0xF0000000
-#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64M */
+#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
+ | BR_PS_32 /* 32-bit port */ \
+ | BR_MS_SDRAM /* MSEL = SDRAM */ \
+ | BR_V) /* Valid */
+ /* 0xF0001861 */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
+#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
/*
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
@@ -287,7 +297,12 @@
* 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
*/
-#define CONFIG_SYS_OR2_PRELIM 0xFC006901
+#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \
+ | OR_SDRAM_XAM \
+ | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
+ | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
+ | OR_SDRAM_EAD)
+ /* 0xFC006901 */
/* LB sdram refresh timer, about 6us */
#define CONFIG_SYS_LBC_LSRT 0x32000000
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 3fb558f..a2ceba7 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -235,7 +235,6 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CONFIG_SYS_FLASH_BANKS_LIST \
{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */
-#define CONFIG_SYS_FLASH_SIZE_SHIFT 4 /* log2 of the above value */
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
/* Vitesse 7385 */
@@ -256,19 +255,21 @@ boards, we say we have two, but don't display a message if we find only one. */
/* Flash */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
+ | BR_PS_16 \
+ | BR_MS_GPCM \
+ | BR_V)
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX \
- | OR_GPCM_EHTR \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET \
| OR_GPCM_EAD)
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \
- | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))
+#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
/* Vitesse 7385 */
@@ -276,14 +277,17 @@ boards, we say we have two, but don't display a message if we find only one. */
#ifdef CONFIG_VSC7385_ENET
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V)
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \
+ | BR_PS_8 \
+ | BR_MS_GPCM \
+ | BR_V)
#define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \
| OR_GPCM_CSNT \
| OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
| OR_GPCM_SETA \
- | OR_GPCM_TRLX \
- | OR_GPCM_EHTR \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET \
| OR_GPCM_EAD)
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE
@@ -294,14 +298,17 @@ boards, we say we have two, but don't display a message if we find only one. */
/* LED */
#define CONFIG_SYS_LED_BASE 0xF9000000
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE | BR_PS_8 | BR_V)
+#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \
+ | BR_PS_8 \
+ | BR_MS_GPCM \
+ | BR_V)
#define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| OR_GPCM_XACS \
| OR_GPCM_SCY_9 \
- | OR_GPCM_TRLX \
- | OR_GPCM_EHTR \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET \
| OR_GPCM_EAD)
/* Compact Flash */
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index 3a5af2d..aaff93f 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -207,19 +207,20 @@
/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | (2 << BR_PS_SHIFT) /* 16 bit port */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
- | OR_UPM_XAM \
+ | BR_PS_16 /* 16 bit port */ \
+ | BR_MS_GPCM /* MSEL = GPCM */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+ | OR_GPCM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX \
- | OR_GPCM_EHTR \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET \
| OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
@@ -233,11 +234,21 @@
#define CONFIG_SYS_BCSR 0xF8000000
/* Access window base at BCSR base */
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
-#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000F /* Access window size 64K */
-
- /* Port size=8bit, MSEL=GPCM */
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801)
-#define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
+#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
+
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
+ | BR_PS_8 \
+ | BR_MS_GPCM \
+ | BR_V)
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
+ | OR_GPCM_XAM \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET \
+ | OR_GPCM_EAD)
+ /* 0xFFFFE9F7 */
/*
* SDRAM on the Local Bus
@@ -249,7 +260,7 @@
#ifdef CONFIG_SYS_LB_SDRAM
#define CONFIG_SYS_LBLAWBAR2 0
-#define CONFIG_SYS_LBLAWAR2 0x80000019 /* 64MB */
+#define CONFIG_SYS_LBLAWAR2 (LBLAWAR_EN | LBLAWAR_64MB)
/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
/*
@@ -266,7 +277,8 @@
* xxxx xxxx xxxx xxxx x001 1000 0110 0001 = 00001861
*/
-#define CONFIG_SYS_BR2 0x00001861 /*Port size=32bit, MSEL=SDRAM */
+/* Port size=32bit, MSEL=DRAM */
+#define CONFIG_SYS_BR2 (BR_PS_32 | BR_MS_SDRAM | BR_V) /* 0xF0001861 */
/*
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
@@ -282,7 +294,12 @@
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
*/
-#define CONFIG_SYS_OR2 0xfc006901
+#define CONFIG_SYS_OR2 (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
+ | OR_SDRAM_XAM \
+ | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
+ | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
+ | OR_SDRAM_EAD)
+ /* 0xFC006901 */
/* LB sdram refresh timer, about 6us */
#define CONFIG_SYS_LBC_LSRT 0x32000000
@@ -303,22 +320,54 @@
#endif
/*
- * Windows to access PIB via local bus
+ * Windows to access Platform I/O Boards (PIB) via local bus
*/
-#define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8010000 /* windows base 0xf8010000 */
-#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000e /* windows size 32KB */
+#define CONFIG_SYS_PIB_BASE 0xF8008000
+#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
+
+/* [RFC] This LBLAW only covers the 2nd window (CS5) */
+#define CONFIG_SYS_LBLAWBAR3_PRELIM \
+ CONFIG_SYS_PIB_BASE + CONFIG_SYS_PIB_WINDOW_SIZE
+#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
/*
* CS4 on Local Bus, to PIB
*/
-#define CONFIG_SYS_BR4_PRELIM 0xf8008801 /* CS4 base address at 0xf8008000 */
-#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
+ /* CS4 base address at 0xf8008000 */
+#define CONFIG_SYS_BR4_PRELIM (CONFIG_SYS_PIB_BASE \
+ | BR_PS_8 \
+ | BR_MS_GPCM \
+ | BR_V)
+ /* 0xF8008801 */
+#define CONFIG_SYS_OR4_PRELIM (OR_AM_32KB \
+ | OR_GPCM_XAM \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET \
+ | OR_GPCM_EAD)
+ /* 0xffffe9f7 */
/*
* CS5 on Local Bus, to PIB
*/
-#define CONFIG_SYS_BR5_PRELIM 0xf8010801 /* CS5 base address at 0xf8010000 */
-#define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
+ /* CS5 base address at 0xf8010000 */
+#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_PIB_BASE + \
+ CONFIG_SYS_PIB_WINDOW_SIZE) \
+ | BR_PS_8 \
+ | BR_MS_GPCM \
+ | BR_V)
+ /* 0xF8010801 */
+#define CONFIG_SYS_OR5_PRELIM (CONFIG_SYS_PIB_BASE \
+ | OR_GPCM_XAM \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET \
+ | OR_GPCM_EAD)
+ /* 0xffffe9f7 */
/*
* Serial Port
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index bc574a6..ea634a6 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -198,19 +198,20 @@
/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | (2 << BR_PS_SHIFT) /* 16 bit port */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
+ | BR_PS_16 /* 16 bit port */ \
+ | BR_MS_GPCM /* MSEL = GPCM */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX \
- | OR_GPCM_EHTR \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET \
| OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
@@ -228,11 +229,20 @@
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001b /* Access window size 4K */
+/*
+ * [RFC] Comment said 4KB window; code said 256MB window; OR1 says 64MB
+ * ... What's correct?
+ */
+#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
/* Port size 8 bit, UPMA */
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | 0x00000881)
-#define CONFIG_SYS_OR1_PRELIM 0xfc000001
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
+ | BR_PS_8 \
+ | BR_MS_UPMA \
+ | BR_V)
+ /* 0x60000881 */
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_UPM_EAD)
+ /* 0xFC000001 */
/*
* Fujitsu MB86277 (MINT) graphics controller
@@ -240,12 +250,16 @@
#define CONFIG_SYS_VIDEO_BASE 0x70000000
#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VIDEO_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* Access window size 64MB */
+#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
/* Port size 32 bit, UPMB */
- /* PS=11, UPMB */
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VIDEO_BASE | 0x000018a1)
-#define CONFIG_SYS_OR2_PRELIM 0xfc000001 /* (64MB, EAD=1) */
+#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VIDEO_BASE \
+ | BR_PS_32 \
+ | BR_MS_UPMB \
+ | BR_V)
+ /* 0x000018a1 */
+#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB | OR_UPM_EAD)
+ /* 0xFC000001 */
/*
* Serial Port
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 8c2af08..d7ee405 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -243,19 +243,20 @@
/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | (2 << BR_PS_SHIFT) /* 16 bit port */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
+ | BR_PS_16 /* 16 bit port */ \
+ | BR_MS_GPCM /* MSEL = GPCM */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX \
- | OR_GPCM_EHTR \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET \
| OR_GPCM_EAD)
/* 0xFE000FF7 */
@@ -272,11 +273,22 @@
#define CONFIG_SYS_BCSR 0xF8000000
/* Access window base at BCSR base */
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
-#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
-
- /* Port size=8bit, MSEL=GPCM */
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00000801)
-#define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
+#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
+
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
+ | BR_PS_8 \
+ | BR_MS_GPCM \
+ | BR_V)
+ /* 0xF8000801 */
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
+ | OR_GPCM_XAM \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET \
+ | OR_GPCM_EAD)
+ /* 0xFFFFE9F7 */
/*
* NAND Flash on the Local Bus
@@ -286,13 +298,13 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_NAND_FSL_ELBC 1
-#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
+#define CONFIG_SYS_NAND_BASE 0xE0600000
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_DECC_CHK_GEN /* Use HW ECC */ \
| BR_PS_8 /* 8 bit port */ \
| BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR3_PRELIM (0xFFFF8000 /* length 32K */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \
| OR_FCM_BCTLD \
| OR_FCM_CST \
| OR_FCM_CHT \
@@ -303,7 +315,7 @@
/* 0xFFFF919E */
#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E /* 32KB */
+#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
/*
* Serial Port
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index bf8a94d..f249cbb 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -275,14 +275,15 @@
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | (2 << BR_PS_SHIFT) /* 16 bit port */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (0xFF800000 /* 8 MByte */ \
+ | BR_PS_16 /* 16 bit port */ \
+ | BR_MS_GPCM /* MSEL = GPCM */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
| OR_GPCM_XACS \
| OR_GPCM_SCY_9 \
- | OR_GPCM_EHTR \
+ | OR_GPCM_EHTR_SET \
| OR_GPCM_EAD)
- /* 0xFF806FF7 TODO SLOW 8 MB flash size */
+ /* 0xFF800191 */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
@@ -294,13 +295,13 @@
/*
* NAND Flash on the Local Bus
*/
-#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
+#define CONFIG_SYS_NAND_BASE 0xE0600000
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
- | (2 << BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 | /* 8 bit Port */ \
- | BR_MS_FCM | /* MSEL = FCM */ \
+ | BR_DECC_CHK_GEN /* Use HW ECC */ \
+ | BR_PS_8 /* 8 bit port */ \
+ | BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
-#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 /* length 32K */ \
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
@@ -308,7 +309,7 @@
| OR_FCM_TRLX \
| OR_FCM_EHTR)
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
+#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
/* Vitesse 7385 */
@@ -316,11 +317,24 @@
#ifdef CONFIG_VSC7385_ENET
-#define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* Base address */
-#define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* 128K bytes*/
+#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
+ | BR_PS_8 \
+ | BR_MS_GPCM \
+ | BR_V)
+ /* 0xF0000801 */
+#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_SETA \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET \
+ | OR_GPCM_EAD)
+ /* 0xfffe09ff */
+
/* Access Base */
#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* Access Size 128K */
+#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
#endif
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index f0d4e80..8b20f72 100644
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -103,26 +103,27 @@
#define CONFIG_SYS_FLASH_BASE 0xFF800000
#define CONFIG_SYS_FLASH_SIZE 8
-#define CONFIG_SYS_FLASH_SIZE_SHIFT 3
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
#define CONFIG_SYS_FLASH_WRITE_TOUT 500
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 256
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
+ | BR_PS_16 \
+ | BR_MS_GPCM \
+ | BR_V)
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX \
- | OR_GPCM_EHTR \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET \
| OR_GPCM_EAD)
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \
- | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))
+#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
/*
* U-Boot memory configuration
diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h
index e7d477d..77be360 100644
--- a/include/configs/SIMPC8313.h
+++ b/include/configs/SIMPC8313.h
@@ -151,26 +151,26 @@
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_DECC_CHK_GEN /* Use HW ECC */ \
| BR_PS_8 /* 8 bit Port */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#ifdef CONFIG_NAND_SP
-#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \
+#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
| OR_FCM_SCY_1 \
| OR_FCM_TRLX \
| OR_FCM_EHTR)
-#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000000E /* 32KB */
-#define CONFIG_SYS_NAND_PAGE_SIZE (512) /* NAND chip page size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
+#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
/* NAND chip block size */
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10)
#define NAND_CACHE_PAGES 32
#elif defined(CONFIG_NAND_LP)
-#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
+#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB \
| OR_FCM_PGS \
| OR_FCM_CSCT \
| OR_FCM_CST \
@@ -178,8 +178,8 @@
| OR_FCM_SCY_1 \
| OR_FCM_TRLX \
| OR_FCM_EHTR)
-#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000011 /* 256KB */
-#define CONFIG_SYS_NAND_PAGE_SIZE (2048) /* NAND chip page size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256KB)
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048 /* NAND chip page size */
/* NAND chip block size */
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
#define NAND_CACHE_PAGES 64
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index ae296eb..0b53702 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -119,13 +119,12 @@
| OR_GPCM_SCY_5 \
| OR_GPCM_TRLX)
-#define CONFIG_SYS_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */
+#define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \
| CONFIG_SYS_OR_TIMING_FLASH)
- /* 1 GiB window size (2^(size + 1)) */
-#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001D
+#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_1GB)
/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h
index 0d411c2..06ecb8a 100644
--- a/include/configs/km/km83xx-common.h
+++ b/include/configs/km/km83xx-common.h
@@ -103,16 +103,17 @@
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
- (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
+ BR_PS_16 | /* 16 bit port size */ \
+ BR_MS_GPCM | /* MSEL = GPCM */ \
BR_V)
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_5 | \
- OR_GPCM_TRLX | OR_GPCM_EAD)
+ OR_GPCM_TRLX_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
@@ -123,15 +124,16 @@
*/
/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */
+#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \
- (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
+ BR_PS_8 | /* 8 bit port size */ \
+ BR_MS_GPCM | /* MSEL = GPCM */ \
BR_V)
#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_2 | \
- OR_GPCM_TRLX | OR_GPCM_EAD)
+ OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/*
* Serial Port
diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
index c04bde9..6b5a6fe 100644
--- a/include/configs/kmeter1.h
+++ b/include/configs/kmeter1.h
@@ -137,15 +137,16 @@
* PAXE on the local bus CS3
*/
#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */
+#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_512MB)
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PAXE_BASE | \
- (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
+ BR_PS_8 | /* 8 bit port size */ \
+ BR_MS_GPCM | /* MSEL = GPCM */ \
BR_V)
#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_2 | \
- OR_GPCM_TRLX | OR_GPCM_EAD)
+ OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/*
* MMU Setup
diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h
index ccc1561..b0dd88c 100644
--- a/include/configs/kmsupx5.h
+++ b/include/configs/kmsupx5.h
@@ -69,8 +69,8 @@
OR_GPCM_CSNT | \
OR_GPCM_ACS_DIV4 | \
OR_GPCM_SCY_2 | \
- (OR_GPCM_TRLX & \
- (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \
+ OR_GPCM_TRLX_SET | \
+ OR_GPCM_EHTR_CLEAR | \
OR_GPCM_EAD)
/* LPXF: icache cacheable, but dcache-inhibit and guarded */
diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
index fbce800..20fc641 100644
--- a/include/configs/mpc8308_p1m.h
+++ b/include/configs/mpc8308_p1m.h
@@ -248,18 +248,18 @@
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE /* Flash Base addr */ \
- | (2 << BR_PS_SHIFT) /* 16 bit port */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
+ | BR_PS_16 /* 16 bit port */ \
+ | BR_MS_GPCM /* MSEL = GPCM */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| OR_GPCM_XACS \
| OR_GPCM_SCY_4 \
- | OR_GPCM_TRLX \
- | OR_GPCM_EHTR \
- | OR_GPCM_EAD)
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512
@@ -274,11 +274,12 @@
*/
#define CONFIG_SYS_SJA1000_BASE 0xFBFF0000
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SJA1000_BASE \
- | (1 << BR_PS_SHIFT) /* 8 bit port */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 /* length 32K */ \
+ | BR_PS_8 /* 8 bit port size */ \
+ | BR_MS_GPCM /* MSEL = GPCM */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
| OR_GPCM_SCY_5 \
- | OR_GPCM_EHTR)
+ | OR_GPCM_EHTR_SET)
/* 0xFFFF8052 */
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_SJA1000_BASE
@@ -289,11 +290,12 @@
*/
#define CONFIG_SYS_CPLD_BASE 0xFBFF8000
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_CPLD_BASE \
- | (1 << BR_PS_SHIFT) /* 8 bit port */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR2_PRELIM (0xFFFF8000 /* length 32K */ \
+ | BR_PS_8 /* 8 bit port */ \
+ | BR_MS_GPCM /* MSEL = GPCM */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB \
| OR_GPCM_SCY_4 \
- | OR_GPCM_EHTR)
+ | OR_GPCM_EHTR_SET)
/* 0xFFFF8042 */
#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_CPLD_BASE
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 99f8fb7..4812f68 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -136,8 +136,8 @@
/*
* SDRAM on the Local Bus
*/
-#define CONFIG_SYS_LBC_SDRAM_BASE 0x10000000 /* Localbus SDRAM */
-#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */
+#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
/*
* FLASH on the Local Bus
@@ -148,14 +148,25 @@
#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | (2 << BR_PS_SHIFT) /* 16 bit port */ \
- | BR_V) /* valid */
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
+ | BR_PS_16 /* 16 bit port */ \
+ | BR_MS_GPCM /* MSEL = GPCM */ \
+ | BR_V) /* valid */
+
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+ | OR_GPCM_XAM \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_ACS_DIV2 \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET \
+ | OR_GPCM_EAD)
+ /* 0xFF806FF7 */
-#define CONFIG_SYS_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */
/* window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
@@ -212,15 +223,15 @@
*
* 0 4 8 12 16 20 24 28
* 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
- *
- * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
- * FIXME: the top 17 bits of BR2.
*/
- /* Port-size=32bit, MSEL=SDRAM */
-#define CONFIG_SYS_BR2_PRELIM 0xF0001861
-#define CONFIG_SYS_LBLAWBAR2_PRELIM 0xF0000000
-#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64M */
+#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
+ | BR_PS_32 \
+ | BR_MS_SDRAM \
+ | BR_V)
+ /* 0xF0001861 */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
+#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
/*
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
@@ -236,7 +247,12 @@
* 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
*/
-#define CONFIG_SYS_OR2_PRELIM 0xFC006901
+#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
+ | OR_SDRAM_XAM \
+ | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
+ | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
+ | OR_SDRAM_EAD)
+ /* 0xFC006901 */
/* LB sdram refresh timer, about 6us */
#define CONFIG_SYS_LBC_LSRT 0x32000000
@@ -615,12 +631,15 @@
| BATU_VS \
| BATU_VP)
-/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CONFIG_SYS_IBAT6L (0xF0000000 \
+/* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
+#define CONFIG_SYS_IBAT6L (CONFIG_SYS_LBC_SDRAM_BASE \
| BATL_PP_RW \
| BATL_MEMCOHERENCE \
| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6U (CONFIG_SYS_LBC_SDRAM_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_IBAT7L (0)
#define CONFIG_SYS_IBAT7U (0)
diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h
index 5f2e1e3..ae19701 100644
--- a/include/configs/suvd3.h
+++ b/include/configs/suvd3.h
@@ -70,7 +70,7 @@
OR_GPCM_CSNT | \
OR_GPCM_ACS_DIV4 | \
OR_GPCM_SCY_3 | \
- OR_GPCM_TRLX)
+ OR_GPCM_TRLX_SET)
#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
0x0000c000 | \
diff --git a/include/configs/tuda1.h b/include/configs/tuda1.h
index 7ae7d58..577bbd0 100644
--- a/include/configs/tuda1.h
+++ b/include/configs/tuda1.h
@@ -73,8 +73,8 @@
OR_GPCM_CSNT | \
OR_GPCM_ACS_DIV4 | \
OR_GPCM_SCY_2 | \
- (OR_GPCM_TRLX & \
- (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \
+ OR_GPCM_TRLX_SET | \
+ OR_GPCM_EHTR_CLEAR | \
OR_GPCM_EAD)
/*
* PINC3 on the local bus CS3
@@ -91,11 +91,10 @@
#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
OR_GPCM_CSNT | \
- (OR_GPCM_ACS_DIV2 & /* ACS = 11 */\
- (~OR_GPCM_XACS)) | /* XACS = 0 */\
- (OR_GPCM_SCY_2 & \
- (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \
- OR_GPCM_TRLX)
+ OR_GPCM_ACS_DIV2 | \
+ OR_GPCM_SCY_2 | \
+ OR_GPCM_TRLX_SET | \
+ OR_GPCM_EHTR_CLEAR)
#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
0x0000c000 | \
diff --git a/include/configs/tuxa1.h b/include/configs/tuxa1.h
index 815c260..2d9af3f 100644
--- a/include/configs/tuxa1.h
+++ b/include/configs/tuxa1.h
@@ -67,8 +67,8 @@
OR_GPCM_CSNT | \
OR_GPCM_ACS_DIV4 | \
OR_GPCM_SCY_2 | \
- (OR_GPCM_TRLX & \
- (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \
+ OR_GPCM_TRLX_SET | \
+ OR_GPCM_EHTR_CLEAR | \
OR_GPCM_EAD)
/*
* PINC2 on the local bus CS3
@@ -85,11 +85,10 @@
#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PINC2_SIZE) | \
OR_GPCM_CSNT | \
- (OR_GPCM_ACS_DIV2 & /* ACS = 11 */ \
- (~OR_GPCM_XACS)) | /* XACS = 0 */ \
- (OR_GPCM_SCY_2 & \
- (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \
- OR_GPCM_TRLX)
+ OR_GPCM_ACS_DIV2 | \
+ OR_GPCM_SCY_2 | \
+ OR_GPCM_TRLX_SET | \
+ OR_GPCM_EHTR_CLEAR)
#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
0x0000c000 | \
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index 69f29c7..1d45889 100644
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -146,18 +146,19 @@
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
- | (2 << BR_PS_SHIFT) /* 16 bit */ \
- | BR_V) /* valid */
+ | BR_PS_16 /* 16 bit */ \
+ | BR_MS_GPCM /* MSEL = GPCM */ \
+ | BR_V) /* valid */
#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV4 \
| OR_GPCM_SCY_5 \
- | OR_GPCM_TRLX \
+ | OR_GPCM_TRLX_SET \
| OR_GPCM_EAD)
/* 0xfe000c55 */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */
@@ -209,7 +210,7 @@
| BR_MS_FCM \
| BR_V) /* valid */
/* 0x61000c21 */
-#define CONFIG_SYS_NAND_OR_PRELIM (0xffff8000 \
+#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
| OR_FCM_BCTLD \
| OR_FCM_CHT \
| OR_FCM_SCY_2 \
@@ -223,7 +224,7 @@
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
+#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
@@ -233,12 +234,12 @@
| BR_PS_8 \
| BR_V)
/* 0x60000801 */
-#define CONFIG_SYS_OR2_PRELIM (0xfffe0000 \
+#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \
| OR_GPCM_CSNT \
| OR_GPCM_XACS \
| OR_GPCM_SCY_3 \
- | OR_GPCM_TRLX \
- | OR_GPCM_EHTR \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET \
| OR_GPCM_EAD)
/* 0xfffe0937 */
/* local bus read write buffer mapping SRAM@0x64000000 */
@@ -247,12 +248,12 @@
| BR_V)
/* 0x62001001 */
-#define CONFIG_SYS_OR3_PRELIM (0xfe000000 \
+#define CONFIG_SYS_OR3_PRELIM (OR_AM_32MB \
| OR_GPCM_CSNT \
| OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX \
- | OR_GPCM_EHTR \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET \
| OR_GPCM_EAD)
/* 0xfe0009f7 */
diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index 8e9b1f0..67a5c89 100644
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -123,29 +123,56 @@
#define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */
#define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
- (2 << BR_PS_SHIFT) | /* 16bit */ \
- BR_V) /* valid */
-
-#define CONFIG_SYS_OR0_PRELIM 0xffc06ff7 /* 4 MB flash size */
+ BR_PS_16 | /* 16bit */ \
+ BR_MS_GPCM | /* MSEL = GPCM */ \
+ BR_V) /* valid */
+
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+ | OR_GPCM_XAM \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_ACS_DIV2 \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET \
+ | OR_GPCM_EAD)
+ /* 0xffc06ff7 */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000015 /* 4 MB window size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB)
#else
#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
#define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
- (2 << BR_PS_SHIFT) | /* 16bit */ \
- BR_V) /* valid */
-
-#define CONFIG_SYS_OR0_PRELIM 0xf8006ff7 /* 128 MB flash size */
+ BR_PS_16 | /* 16bit */ \
+ BR_MS_GPCM | /* MSEL = GPCM */ \
+ BR_V) /* valid */
+
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+ | OR_GPCM_XAM \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_ACS_DIV2 \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET \
+ | OR_GPCM_EAD)
+ /* 0xf8006ff7 */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001a /* 128 MB window size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
#endif
/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
-#define CONFIG_SYS_BR1_PRELIM (0xf0000000 | 0x00001801)
-#define CONFIG_SYS_OR1_PRELIM (0xfffc0008 | 0x00000200)
-#define CONFIG_SYS_LBLAWBAR1_PRELIM 0xf0000000
-#define CONFIG_SYS_LBLAWAR1_PRELIM (0x80000000 | 0x00000011)
+#define CONFIG_SYS_WINDOW1_BASE 0xf0000000
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \
+ | BR_PS_32 \
+ | BR_MS_GPCM \
+ | BR_V)
+ /* 0xF0001801 */
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \
+ | OR_GPCM_SETA)
+ /* 0xfffc0208 */
+#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
From 2e651b248348e156d193e46f7a5b827d74af90d6 Mon Sep 17 00:00:00 2001
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Tue, 11 Oct 2011 23:57:31 -0500
Subject: [PATCH 29/31] mpc83xx: Rename CONFIG_SYS_DDR_CONFIG and cleanup DDR
csbnds code
Rename CONFIG_SYS_DDR_CONFIG to include which CS it is configuring
Cleanup the setting of the csnbds to respect the setting of
CONFIG_SYS_DDR_SDRAM_BASE
Use __ilog2 instead of writing the code to compute it
Disable unused CS configs
Ensure ddrlaw.bar is configured
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
board/freescale/mpc8313erdb/sdram.c | 10 ++++++--
board/freescale/mpc8349emds/mpc8349emds.c | 27 ++++++++++----------
board/freescale/mpc8349itx/mpc8349itx.c | 28 ++++++++++++---------
board/freescale/mpc8360emds/mpc8360emds.c | 42 +++++++++++++++++++------------
board/sbc8349/sbc8349.c | 27 ++++++++++----------
board/ve8313/ve8313.c | 10 ++++++--
include/configs/MPC8313ERDB.h | 2 +-
include/configs/MPC8349EMDS.h | 2 +-
include/configs/MPC8349ITX.h | 2 +-
include/configs/MPC8360EMDS.h | 7 +++---
include/configs/sbc8349.h | 2 +-
include/configs/ve8313.h | 2 +-
12 files changed, 93 insertions(+), 68 deletions(-)
diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c
index 7aede13..a9a2ba4 100644
--- a/board/freescale/mpc8313erdb/sdram.c
+++ b/board/freescale/mpc8313erdb/sdram.c
@@ -74,8 +74,14 @@ static long fixed_sdram(void)
*/
__udelay(50000);
- im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+ im->ddr.csbnds[0].csbnds =
+ ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
+ CSBNDS_EA);
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
/* Currently we use only one CS, so disable the other bank. */
im->ddr.cs_config[1] = 0;
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index 620540f..ebd5274 100644
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -101,18 +101,10 @@ phys_size_t initdram (int board_type)
int fixed_sdram(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- u32 msize = 0;
- u32 ddr_size;
- u32 ddr_size_log2;
-
- msize = CONFIG_SYS_DDR_SIZE;
- for (ddr_size = msize << 20, ddr_size_log2 = 0;
- (ddr_size > 1);
- ddr_size = ddr_size>>1, ddr_size_log2++) {
- if (ddr_size & 1) {
- return -1;
- }
- }
+ u32 msize = CONFIG_SYS_DDR_SIZE;
+ u32 ddr_size = msize << 20; /* DDR size in bytes */
+ u32 ddr_size_log2 = __ilog2(ddr_size);
+
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
@@ -133,8 +125,15 @@ int fixed_sdram(void)
im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
#else
- im->ddr.csbnds[2].csbnds = 0x0000000f;
- im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG;
+
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+ im->ddr.csbnds[2].csbnds =
+ ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+ CSBNDS_EA_SHIFT) & CSBNDS_EA);
+ im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
/* currently we use only one CS, so disable the other banks */
im->ddr.cs_config[0] = 0;
diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
index 5647579..9cc808e 100644
--- a/board/freescale/mpc8349itx/mpc8349itx.c
+++ b/board/freescale/mpc8349itx/mpc8349itx.c
@@ -43,23 +43,27 @@
int fixed_sdram(void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 ddr_size; /* The size of RAM, in bytes */
- u32 ddr_size_log2 = 0;
-
- for (ddr_size = CONFIG_SYS_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) {
- if (ddr_size & 1) {
- return -1;
- }
- ddr_size_log2++;
- }
+ /* The size of RAM, in bytes */
+ u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20;
+ u32 ddr_size_log2 = __ilog2(ddr_size);
im->sysconf.ddrlaw[0].ar =
LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
- /* Only one CS0 for DDR */
- im->ddr.csbnds[0].csbnds = 0x0000000f;
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+ im->ddr.csbnds[0].csbnds =
+ ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+ CSBNDS_EA_SHIFT) & CSBNDS_EA);
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+
+ /* Only one CS for DDR */
+ im->ddr.cs_config[1] = 0;
+ im->ddr.cs_config[2] = 0;
+ im->ddr.cs_config[3] = 0;
debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
index 51d8035..a0114f6 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -216,19 +216,15 @@ phys_size_t initdram(int board_type)
int fixed_sdram(void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize = 0;
- u32 ddr_size;
- u32 ddr_size_log2;
-
- msize = CONFIG_SYS_DDR_SIZE;
- for (ddr_size = msize << 20, ddr_size_log2 = 0;
- (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
- if (ddr_size & 1) {
- return -1;
- }
- }
+ u32 msize = CONFIG_SYS_DDR_SIZE;
+ u32 ddr_size = msize << 20;
+ u32 ddr_size_log2 = __ilog2(ddr_size);
+ u32 half_ddr_size = ddr_size >> 1;
+
+ im->sysconf.ddrlaw[0].bar =
+ CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar =
- LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+ LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
#if (CONFIG_SYS_DDR_SIZE != 256)
#warning Currenly any ddr size other than 256 is not supported
#endif
@@ -246,11 +242,25 @@ int fixed_sdram(void)
im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
#else
- im->ddr.csbnds[0].csbnds = 0x00000007;
- im->ddr.csbnds[1].csbnds = 0x0008000f;
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
- im->ddr.cs_config[1] = CONFIG_SYS_DDR_CONFIG;
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+ im->ddr.csbnds[0].csbnds =
+ ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size - 1) >>
+ CSBNDS_EA_SHIFT) & CSBNDS_EA);
+ im->ddr.csbnds[1].csbnds =
+ (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size) >>
+ CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+ CSBNDS_EA_SHIFT) & CSBNDS_EA);
+
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+ im->ddr.cs_config[1] = CONFIG_SYS_DDR_CS1_CONFIG;
+
+ im->ddr.cs_config[2] = 0;
+ im->ddr.cs_config[3] = 0;
im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
index 50fae7c..42f4c1e 100644
--- a/board/sbc8349/sbc8349.c
+++ b/board/sbc8349/sbc8349.c
@@ -89,26 +89,25 @@ phys_size_t initdram (int board_type)
int fixed_sdram(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- u32 msize = 0;
- u32 ddr_size;
- u32 ddr_size_log2;
-
- msize = CONFIG_SYS_DDR_SIZE;
- for (ddr_size = msize << 20, ddr_size_log2 = 0;
- (ddr_size > 1);
- ddr_size = ddr_size>>1, ddr_size_log2++) {
- if (ddr_size & 1) {
- return -1;
- }
- }
+ u32 msize = CONFIG_SYS_DDR_SIZE;
+ u32 ddr_size = msize << 20; /* DDR size in bytes */
+ u32 ddr_size_log2 = __ilog2(msize);
+
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
#if (CONFIG_SYS_DDR_SIZE != 256)
#warning Currently any ddr size other than 256 is not supported
#endif
- im->ddr.csbnds[2].csbnds = 0x0000000f;
- im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG;
+
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+ im->ddr.csbnds[2].csbnds =
+ ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+ CSBNDS_EA_SHIFT) & CSBNDS_EA);
+ im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
/* currently we use only one CS, so disable the other banks */
im->ddr.cs_config[0] = 0;
diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c
index 166e459..924d871 100644
--- a/board/ve8313/ve8313.c
+++ b/board/ve8313/ve8313.c
@@ -65,8 +65,14 @@ static long fixed_sdram(void)
*/
__udelay(50000);
- out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
- out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CONFIG);
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+ out_be32(&im->ddr.csbnds[0].csbnds,
+ ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
+ CSBNDS_EA));
+ out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
/* Currently we use only one CS, so disable the other bank. */
out_be32(&im->ddr.cs_config[1], 0);
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 21771fd..31503af 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -130,7 +130,7 @@
* seem to have the SPD connected to I2C.
*/
#define CONFIG_SYS_DDR_SIZE 128 /* MB */
-#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \
+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| CSCONFIG_ODT_RD_NEVER \
| CSCONFIG_ODT_WR_ONLY_CURRENT \
| CSCONFIG_ROW_BIT_13 \
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index a6aebb7..c76455a 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -142,7 +142,7 @@
#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
#else
-#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \
+#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
| CSCONFIG_ROW_BIT_13 \
| CSCONFIG_COL_BIT_10)
#define CONFIG_SYS_DDR_TIMING_1 0x36332321
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index a2ceba7..04f2da9 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -206,7 +206,7 @@
/* No SPD? Then manually set up DDR parameters */
#ifndef CONFIG_SPD_EEPROM
#define CONFIG_SYS_DDR_SIZE 256 /* Mb */
- #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \
+ #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| CSCONFIG_ROW_BIT_13 \
| CSCONFIG_COL_BIT_10)
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index aaff93f..e81f3d4 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -145,9 +145,10 @@
#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
#else
-#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \
- | CSCONFIG_ROW_BIT_13 \
- | CSCONFIG_COL_BIT_9)
+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
+ | CSCONFIG_ROW_BIT_13 \
+ | CSCONFIG_COL_BIT_9)
+#define CONFIG_SYS_DDR_CS1_CONFIG CONFIG_SYS_DDR_CS0_CONFIG
#define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */
#define CONFIG_SYS_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 4812f68..e50d829 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -114,7 +114,7 @@
* NB: manual DDR setup untested on sbc834x
*/
#define CONFIG_SYS_DDR_SIZE 256 /* MB */
-#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \
+#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
| CSCONFIG_ROW_BIT_13 \
| CSCONFIG_COL_BIT_10)
#define CONFIG_SYS_DDR_TIMING_1 0x36332321
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index 1d45889..bf50d09 100644
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -79,7 +79,7 @@
* have the SPD connected to I2C.
*/
#define CONFIG_SYS_DDR_SIZE 128 /* MB */
-#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \
+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| CSCONFIG_AP \
| CSCONFIG_ODT_RD_NEVER \
| CSCONFIG_ODT_WR_ALL \
From d37be07ee57e4390eb4e5529f9a481e334dbbe07 Mon Sep 17 00:00:00 2001
From: Jerry Huang <Chang-Ming.Huang@freescale.com>
Date: Thu, 3 Nov 2011 14:46:12 +0800
Subject: [PATCH 30/31] powerpc/mpc83xx: Add 512MB DDR support for mpc8360emds
The new MPC8360EMDS board supports 512MB DDR since 2008.
For 512MB DDR:
BAT0 is used for the first 256MB memory, BAT4 is used for the second
256MB memory and the address space of SDRAM follows the DDR, so if the
size of DDR is 256MB, the BAT4 will be used for SDRAM and if the size of
DDR is 512MB, the BAT4 will be used for the second 256MB memory and
there is no BAT for SDRAM.
Therefore, if the size of DDR is 512MB, this patch will use BAT6 for
SDRAM and BAT5 will be used for PCI MEM to replace the BAT6 after the
codes relocates to the DDR.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
CC: Kim Phillips <kim.phillips@freescale.com>
---
board/freescale/mpc8360emds/mpc8360emds.c | 27 ++++++++++++++++++++++++++-
include/configs/MPC8360EMDS.h | 3 ++-
2 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
index a0114f6..be76774 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006,2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006,2010-2011 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* See file CREDITS for list of people who contributed to this
@@ -24,6 +24,7 @@
#include <asm/mmu.h>
#include <asm/io.h>
#include <asm/fsl_enet.h>
+#include <asm/mmu.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
@@ -139,9 +140,20 @@ int board_early_init_f(void)
int board_early_init_r(void)
{
+ gd_t *gd;
#ifdef CONFIG_PQ_MDS_PIB
pib_init();
#endif
+ /*
+ * BAT6 is used for SDRAM when DDR size is 512MB or larger than 256MB
+ * So re-setup PCI MEM space used BAT5 after relocated to DDR
+ */
+ gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+ if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
+ write_bat(DBAT5, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L);
+ write_bat(IBAT5, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L);
+ }
+
return 0;
}
@@ -302,6 +314,19 @@ static int sdram_init(unsigned int base)
if (rem)
base = base - rem + sdram_size;
+ /*
+ * Setup BAT6 for SDRAM when DDR size is 512MB or larger than 256MB
+ * After relocated to DDR, reuse BAT5 for PCI MEM space
+ */
+ if (base > CONFIG_MAX_MEM_MAPPED) {
+ unsigned long batl = base | BATL_PP_10 | BATL_MEMCOHERENCE;
+ unsigned long batu = base | BATU_BL_64M | BATU_VS | BATU_VP;
+
+ /* Setup the BAT6 for SDRAM */
+ write_bat(DBAT6, batu, batl);
+ write_bat(IBAT6, batu, batl);
+ }
+
sdram_addr = (uint *)base;
/*
* Setup SDRAM Base and Option Registers
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index e81f3d4..5a1e6f5 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006,2011 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
*
@@ -569,6 +569,7 @@
*/
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+#define CONFIG_BAT_RW
/* DDR/LBC SDRAM: cacheable */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
From 6be55ee2252c364b16d99537bf9fe7d96d5c77b4 Mon Sep 17 00:00:00 2001
From: Jerry Huang <Chang-Ming.Huang@freescale.com>
Date: Mon, 7 Nov 2011 13:20:21 +0800
Subject: [PATCH 31/31] powerpc/mpc83xx: Add 33.33MHz support for mpc8360emds
The new MPC8360EMDS board changes the oscillator to 33.33MHz
in order to support QE 500MHz since 2008.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
boards.cfg | 15 ++++++++++-----
doc/README.mpc8360emds | 18 +++++++++++++-----
include/configs/MPC8360EMDS.h | 27 +++++++++++++++++++++++++++
3 files changed, 50 insertions(+), 10 deletions(-)
diff --git a/boards.cfg b/boards.cfg
index 604becf..1912108 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -542,11 +542,16 @@ MPC8349EMDS powerpc mpc83xx mpc8349emds freesca
MPC8349ITX powerpc mpc83xx mpc8349itx freescale - MPC8349ITX:MPC8349ITX
MPC8349ITXGP powerpc mpc83xx mpc8349itx freescale - MPC8349ITX:MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000
MPC8349ITX_LOWBOOT powerpc mpc83xx mpc8349itx freescale - MPC8349ITX:MPC8349ITX,SYS_TEXT_BASE=0xFE000000
-MPC8360EMDS powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:
-MPC8360EMDS_ATM powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1
-MPC8360EMDS_HOST_33 powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:PCI,PCI_33M,PQ_MDS_PIB=1
-MPC8360EMDS_HOST_66 powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:PCI,PCI_66M,PQ_MDS_PIB=1
-MPC8360EMDS_SLAVE powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:PCI,PCISLAVE
+MPC8360EMDS_66 powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_66MHZ
+MPC8360EMDS_33 powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_33MHZ
+MPC8360EMDS_66_ATM powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_66MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1
+MPC8360EMDS_33_ATM powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_33MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1
+MPC8360EMDS_66_HOST_33 powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_33M,PQ_MDS_PIB=1
+MPC8360EMDS_33_HOST_33 powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_33MHZ,PCI,PCI_33M,PQ_MDS_PIB=1
+MPC8360EMDS_66_HOST_66 powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_66M,PQ_MDS_PIB=1
+MPC8360EMDS_33_HOST_66 powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_33MHZ,PCI,PCI_66M,PQ_MDS_PIB=1
+MPC8360EMDS_66_SLAVE powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_66MHZ,PCI,PCISLAVE
+MPC8360EMDS_33_SLAVE powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_33MHZ,PCI,PCISLAVE
MPC8360ERDK powerpc mpc83xx mpc8360erdk freescale - MPC8360ERDK
MPC8360ERDK_33 powerpc mpc83xx mpc8360erdk freescale - MPC8360ERDK:CLKIN_33MHZ
MPC8360ERDK_66 powerpc mpc83xx mpc8360erdk freescale - MPC8360ERDK
diff --git a/doc/README.mpc8360emds b/doc/README.mpc8360emds
index d65a2a4..2b39160 100644
--- a/doc/README.mpc8360emds
+++ b/doc/README.mpc8360emds
@@ -87,28 +87,36 @@ Freescale MPC8360EMDS Board
4. Compilation
+ MPC8360EMDS shipped with 33.33MHz or 66MHz oscillator(check U41 chip).
+
Assuming you're using BASH shell:
export CROSS_COMPILE=your-cross-compile-prefix
cd u-boot
make distclean
- make MPC8360EMDS_config
+ make MPC8360EMDS_XX_config
make
- MPC8360 support PCI in host and slave mode.
+ MPC8360EMDS support ATM, PCI in host and slave mode.
+
+ To make u-boot support ATM :
+ 1) Make MPC8360EMDS_XX_ATM_config
To make u-boot support PCI host 66M :
1) DIP SW support PCI mode as described in Section 1.1.
- 2) Make MPC8360EMDS_HOST_66_config
+ 2) Make MPC8360EMDS_XX_HOST_66_config
To make u-boot support PCI host 33M :
1) DIP SW setting is similar as Section 1.1, except for SW3[4] is 1
- 2) Make MPC8360EMDS_HOST_33_config
+ 2) Make MPC8360EMDS_XX_HOST_33_config
To make u-boot support PCI slave 66M :
1) DIP SW setting is similar as Section 1.1, except for SW9[3] is 1
- 2) Make MPC8360EMDS_SLAVE_config
+ 2) Make MPC8360EMDS_XX_SLAVE_config
+ (where XX is:
+ 33 - 33.33MHz oscillator
+ 66 - 66MHz oscillator)
5. Downloading and Flashing Images
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index 5a1e6f5..9604fda 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -39,6 +39,18 @@
/*
* System Clock Setup
*/
+#ifdef CONFIG_CLKIN_33MHZ
+#ifdef CONFIG_PCISLAVE
+#define CONFIG_83XX_PCICLK 33330000 /* in HZ */
+#else
+#define CONFIG_83XX_CLKIN 33330000 /* in Hz */
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ 33330000
+#endif
+
+#elif defined(CONFIG_CLKIN_66MHZ)
#ifdef CONFIG_PCISLAVE
#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
#else
@@ -48,10 +60,24 @@
#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ 66000000
#endif
+#else
+#error Unknown oscillator frequency.
+#endif
/*
* Hardware Reset Configuration Word
*/
+#ifdef CONFIG_CLKIN_33MHZ
+#define CONFIG_SYS_HRCW_LOW (\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+ HRCWL_DDR_TO_SCB_CLK_1X1 |\
+ HRCWL_CSB_TO_CLKIN_8X1 |\
+ HRCWL_VCO_1X2 |\
+ HRCWL_CE_PLL_VCO_DIV_4 |\
+ HRCWL_CE_PLL_DIV_1X1 |\
+ HRCWL_CE_TO_PLL_1X15 |\
+ HRCWL_CORE_TO_CSB_2X1)
+#elif defined(CONFIG_CLKIN_66MHZ)
#define CONFIG_SYS_HRCW_LOW (\
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
HRCWL_DDR_TO_SCB_CLK_1X1 |\
@@ -61,6 +87,7 @@
HRCWL_CE_PLL_DIV_1X1 |\
HRCWL_CE_TO_PLL_1X6 |\
HRCWL_CORE_TO_CSB_2X1)
+#endif
#ifdef CONFIG_PCISLAVE
#define CONFIG_SYS_HRCW_HIGH (\