Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> Signed-off by: John Rigby <jrigby@freescale.com>master
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Freescale MCF5475EVB ColdFire Development Board |
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================================================ |
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TsiChung Liew(Tsi-Chung.Liew@freescale.com) |
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Created Jan 08, 2008 |
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=========================================== |
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Changed files: |
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============== |
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- board/freescale/m547xevb/m547xevb.c Dram setup, IDE pre init, and PCI init |
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- board/freescale/m547xevb/mii.c MII init |
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- board/freescale/m547xevb/Makefile Makefile |
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- board/freescale/m547xevb/config.mk config make |
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- board/freescale/m547xevb/u-boot.lds Linker description |
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- cpu/mcf547x_8x/cpu.c cpu specific code |
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- cpu/mcf547x_8x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs |
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- cpu/mcf547x_8x/interrupts.c cpu specific interrupt support |
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- cpu/mcf547x_8x/slicetimer.c Timer support |
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- cpu/mcf547x_8x/speed.c system, pci, flexbus, and cpu clock |
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- cpu/mcf547x_8x/Makefile Makefile |
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- cpu/mcf547x_8x/config.mk config make |
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- cpu/mcf547x_8x/start.S start up assembly code |
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- doc/README.m5475evb This readme file |
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- drivers/dma/MCD_dmaApi.c DMA API functions |
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- drivers/dma/MCD_tasks.c DMA Tasks |
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- drivers/dma/MCD_tasksInit.c DMA Tasks Init |
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- drivers/net/fsl_mcdmafec.c ColdFire common DMA FEC driver |
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- drivers/serial/mcfuart.c ColdFire common UART driver |
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- include/MCD_dma.h DMA header file |
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- include/MCD_progCheck.h DMA header file |
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- include/MCD_tasksInit.h DMA header file |
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- include/asm-m68k/bitops.h Bit operation function export |
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- include/asm-m68k/byteorder.h Byte order functions |
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- include/asm-m68k/errno.h Error Number definition |
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- include/asm-m68k/fec.h FEC structure and definition |
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- include/asm-m68k/fsl_i2c.h I2C structure and definition |
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- include/asm-m68k/fsl_mcddmafec.h DMA FEC structure and definition |
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- include/asm-m68k/global_data.h Global data structure |
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- include/asm-m68k/immap.h ColdFire specific header file and driver macros |
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- include/asm-m68k/immap_547x_8x.h mcf547x_8x specific header file |
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- include/asm-m68k/io.h io functions |
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- include/asm-m68k/m547x_8x.h mcf547x_8x specific header file |
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- include/asm-m68k/posix_types.h Posix |
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- include/asm-m68k/processor.h header file |
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- include/asm-m68k/ptrace.h Exception structure |
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- include/asm-m68k/rtc.h Realtime clock header file |
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- include/asm-m68k/string.h String function export |
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- include/asm-m68k/timer.h Timer structure and definition |
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- include/asm-m68k/types.h Data types definition |
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- include/asm-m68k/uart.h Uart structure and definition |
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- include/asm-m68k/u-boot.h u-boot structure |
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- include/configs/M5475EVB.h Board specific configuration file |
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- lib_m68k/board.c board init function |
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- lib_m68k/cache.c |
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- lib_m68k/interrupts Coldfire common interrupt functions |
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- lib_m68k/m68k_linux.c |
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- lib_m68k/traps.c Exception init code |
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1 MCF547x specific Options/Settings |
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==================================== |
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1.1 pre-loader is no longer suppoer in thie coldfire family |
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1.2 Configuration settings for M5475EVB Development Board |
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CONFIG_MCF547x_8x -- define for all MCF547x_8x CPUs |
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CONFIG_M547x -- define for all Freescale MCF547x CPUs |
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CONFIG_M5475 -- define for M5475EVB board |
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CONFIG_MCFUART -- define to use common CF Uart driver |
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CFG_UART_PORT -- define UART port number, start with 0, 1 and 2 |
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CONFIG_BAUDRATE -- define UART baudrate |
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CONFIG_FSLDMAFEC -- define to use common dma FEC driver |
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CONFIG_NET_MULTI -- define to use multi FEC in u-boot |
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CONFIG_MII -- enable to use MII driver |
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CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c |
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CFG_DISCOVER_PHY -- enable PHY discovery |
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CFG_RX_ETH_BUFFER -- Set FEC Receive buffer |
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CFG_FAULT_ECHO_LINK_DOWN-- |
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CFG_FEC0_PINMUX -- Set FEC0 Pin configuration |
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CFG_FEC1_PINMUX -- Set FEC1 Pin configuration |
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CFG_FEC0_MIIBASE -- Set FEC0 MII base register |
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CFG_FEC1_MIIBASE -- Set FEC0 MII base register |
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MCFFEC_TOUT_LOOP -- set FEC timeout loop |
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CONFIG_HAS_ETH1 -- define to enable second FEC in u-boot |
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CONFIG_CMD_USB -- enable USB commands |
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CONFIG_USB_OHCI_NEW -- enable USB OHCI driver |
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CONFIG_USB_STORAGE -- enable USB Storage device |
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CONFIG_DOS_PARTITION -- enable DOS read/write |
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CONFIG_SLTTMR -- define to use SLT timer |
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CONFIG_FSL_I2C -- define to use FSL common I2C driver |
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CONFIG_HARD_I2C -- define for I2C hardware support |
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CONFIG_SOFT_I2C -- define for I2C bit-banged |
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CFG_I2C_SPEED -- define for I2C speed |
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CFG_I2C_SLAVE -- define for I2C slave address |
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CFG_I2C_OFFSET -- define for I2C base address offset |
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CFG_IMMR -- define for MBAR offset |
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CONFIG_PCI -- define for PCI support |
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CONFIG_PCI_PNP -- define for Plug n play support |
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CONFIG_SKIPPCI_HOSTBRIDGE -- SKIP PCI Host bridge |
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CFG_PCI_MEM_BUS -- PCI memory logical offset |
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CFG_PCI_MEM_PHYS -- PCI memory physical offset |
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CFG_PCI_MEM_SIZE -- PCI memory size |
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CFG_PCI_IO_BUS -- PCI IO logical offset |
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CFG_PCI_IO_PHYS -- PCI IO physical offset |
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CFG_PCI_IO_SIZE -- PCI IO size |
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CFG_PCI_CFG_BUS -- PCI Configuration logical offset |
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CFG_PCI_CFG_PHYS -- PCI Configuration physical offset |
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CFG_PCI_CFG_SIZE -- PCI Configuration size |
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CFG_MBAR -- define MBAR offset |
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CONFIG_MONITOR_IS_IN_RAM -- Not support |
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CFG_INIT_RAM_ADDR -- defines the base address of the MCF547x internal SRAM |
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CFG_CSn_BASE -- defines the Chip Select Base register |
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CFG_CSn_MASK -- defines the Chip Select Mask register |
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CFG_CSn_CTRL -- defines the Chip Select Control register |
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CFG_SDRAM_BASE -- defines the DRAM Base |
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2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL |
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=========================================== |
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2.1. System memory map: |
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Flash: 0xFF800000-0xFFFFFFFF (8MB) |
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DDR: 0x00000000-0x3FFFFFFF (1024MB) |
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SRAM: 0xF2000000-0xF2000FFF (4KB) |
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PCI: 0x70000000-0x8FFFFFFF (512MB) |
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IP: 0xF0000000-0xFFFFFFFF (256MB) |
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3. COMPILATION |
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============== |
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3.1 To create U-Boot the gcc-4.x compiler set (ColdFire ELF or uclinux |
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version) from codesourcery.com was used. Download it from: |
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http://www.codesourcery.com/gnu_toolchains/coldfire/download.html |
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3.2 Compilation |
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export CROSS_COMPILE=cross-compile-prefix |
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cd u-boot-1.x.x |
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make distclean |
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make M5475AFE_config, or - boot 2MB, RAM 64MB |
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make M5475BFE_config, or - boot 2MB, code 16MB, RAM 64MB |
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make M5475CFE_config, or - boot 2MB, code 16MB, Video, USB, RAM 64MB |
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make M5475DFE_config, or - boot 2MB, USB, RAM 64MB |
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make M5475EFE_config, or - boot 2MB, Video, USB, RAM 64MB |
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make M5475FFE_config, or - boot 2MB, code 32MB, Video, USB, RAM 128MB |
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make M5475GFE_config, or - boot 2MB, RAM 64MB |
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make |
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5. SCREEN DUMP |
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============== |
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5.1 |
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U-Boot 1.3.1 (Jan 8 2008 - 12:47:44) |
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CPU: Freescale MCF5475 |
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CPU CLK 266 Mhz BUS CLK 133 Mhz |
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Board: Freescale FireEngine 5475 EVB |
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I2C: ready |
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DRAM: 64 MB |
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FLASH: 18 MB |
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In: serial |
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Out: serial |
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Err: serial |
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Net: FEC0, FEC1 |
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-> pri |
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bootdelay=1 |
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baudrate=115200 |
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ethaddr=00:e0:0c:bc:e5:60 |
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eth1addr=00:e0:0c:bc:e5:61 |
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ipaddr=192.162.1.2 |
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serverip=192.162.1.1 |
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gatewayip=192.162.1.1 |
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netmask=255.255.255.0 |
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hostname=M547xEVB |
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netdev=eth0 |
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loadaddr=10000 |
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u-boot=u-boot.bin |
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load=tftp ${loadaddr) ${u-boot} |
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upd=run load; run prog |
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prog=prot off bank 1;era ff800000 ff82ffff;cp.b ${loadaddr} ff800000 ${filesize};save |
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stdin=serial |
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stdout=serial |
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stderr=serial |
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ethact=FEC0 |
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mem=65024k |
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Environment size: 433/8188 bytes |
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-> bdin |
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memstart = 0x00000000 |
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memsize = 0x04000000 |
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flashstart = 0xFF800000 |
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flashsize = 0x01200000 |
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flashoffset = 0x00000000 |
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sramstart = 0xF2000000 |
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sramsize = 0x00001000 |
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mbar = 0xF0000000 |
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busfreq = 133.333 MHz |
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pcifreq = 0 MHz |
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ethaddr = 00:E0:0C:BC:E5:60 |
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eth1addr = 00:E0:0C:BC:E5:61 |
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ip_addr = 192.162.1.2 |
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baudrate = 115200 bps |
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-> ? |
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? - alias for 'help' |
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autoscr - run script from memory |
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base - print or set address offset |
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bdinfo - print Board Info structure |
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boot - boot default, i.e., run 'bootcmd' |
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bootd - boot default, i.e., run 'bootcmd' |
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bootelf - Boot from an ELF image in memory |
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bootm - boot application image from memory |
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bootp - boot image via network using BootP/TFTP protocol |
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bootvx - Boot vxWorks from an ELF image |
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cmp - memory compare |
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coninfo - print console devices and information |
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cp - memory copy |
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crc32 - checksum calculation |
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dcache - enable or disable data cache |
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echo - echo args to console |
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erase - erase FLASH memory |
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flinfo - print FLASH memory information |
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go - start application at address 'addr' |
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help - print online help |
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icache - enable or disable instruction cache |
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icrc32 - checksum calculation |
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iloop - infinite loop on address range |
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imd - i2c memory display |
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iminfo - print header information for application image |
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imls - list all images found in flash |
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imm - i2c memory modify (auto-incrementing) |
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imw - memory write (fill) |
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inm - memory modify (constant address) |
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iprobe - probe to discover valid I2C chip addresses |
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itest - return true/false on integer compare |
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loadb - load binary file over serial line (kermit mode) |
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loads - load S-Record file over serial line |
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loady - load binary file over serial line (ymodem mode) |
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loop - infinite loop on address range |
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md - memory display |
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mii - MII utility commands |
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mm - memory modify (auto-incrementing) |
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mtest - simple RAM test |
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mw - memory write (fill) |
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nfs - boot image via network using NFS protocol |
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nm - memory modify (constant address) |
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pci - list and access PCI Configuration Space |
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ping - send ICMP ECHO_REQUEST to network host |
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printenv- print environment variables |
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protect - enable or disable FLASH write protection |
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rarpboot- boot image via network using RARP/TFTP protocol |
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reset - Perform RESET of the CPU |
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run - run commands in an environment variable |
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saveenv - save environment variables to persistent storage |
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setenv - set environment variables |
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sleep - delay execution for some time |
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tftpboot- boot image via network using TFTP protocol |
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usb - USB sub-system |
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usbboot - boot from USB device |
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version - print monitor version |
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-> usb start |
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(Re)start USB... |
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USB: OHCI pci controller (1131, 1561) found @(0:17:0) |
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OHCI regs address 0x80000000 |
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scanning bus for devices... 2 USB Device(s) found |
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scanning bus for storage devices... 1 Storage Device(s) found |
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-> |
@ -0,0 +1,311 @@ |
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/*
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* Configuation settings for the Freescale MCF5475 board. |
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* |
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* Copyright (C) 2004-2008 Freescale Semiconductor, Inc. |
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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/*
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* board/config.h - configuration options, board specific |
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*/ |
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#ifndef _M5475EVB_H |
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#define _M5475EVB_H |
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/*
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* High Level Configuration Options |
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* (easy to change) |
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*/ |
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#define CONFIG_MCF547x_8x /* define processor family */ |
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#define CONFIG_M547x /* define processor type */ |
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#define CONFIG_M5475 /* define processor type */ |
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#undef DEBUG |
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#define CONFIG_MCFUART |
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#define CFG_UART_PORT (0) |
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#define CONFIG_BAUDRATE 115200 |
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#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } |
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#define CONFIG_HW_WATCHDOG |
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#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ |
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/* Command line configuration */ |
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#include <config_cmd_default.h> |
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#define CONFIG_CMD_CACHE |
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#undef CONFIG_CMD_DATE |
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#define CONFIG_CMD_ELF |
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#define CONFIG_CMD_FLASH |
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#define CONFIG_CMD_I2C |
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#define CONFIG_CMD_MEMORY |
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#define CONFIG_CMD_MISC |
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#define CONFIG_CMD_MII |
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#define CONFIG_CMD_NET |
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#define CONFIG_CMD_PCI |
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#define CONFIG_CMD_PING |
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#define CONFIG_CMD_REGINFO |
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#define CONFIG_CMD_USB |
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#define CONFIG_SLTTMR |
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#define CONFIG_FSLDMAFEC |
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#ifdef CONFIG_FSLDMAFEC |
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# define CONFIG_NET_MULTI 1 |
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# define CONFIG_MII 1 |
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# define CONFIG_HAS_ETH1 |
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# define CFG_DISCOVER_PHY |
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# define CFG_RX_ETH_BUFFER 32 |
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# define CFG_TX_ETH_BUFFER 48 |
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# define CFG_FAULT_ECHO_LINK_DOWN |
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# define CFG_FEC0_PINMUX 0 |
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# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE |
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# define CFG_FEC1_PINMUX 0 |
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# define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE |
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# define MCFFEC_TOUT_LOOP 50000 |
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/* If CFG_DISCOVER_PHY is not defined - hardcoded */ |
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# ifndef CFG_DISCOVER_PHY |
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# define FECDUPLEX FULL |
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# define FECSPEED _100BASET |
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# else |
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# ifndef CFG_FAULT_ECHO_LINK_DOWN |
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# define CFG_FAULT_ECHO_LINK_DOWN |
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# endif |
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# endif /* CFG_DISCOVER_PHY */ |
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# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 |
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# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 |
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# define CONFIG_IPADDR 192.162.1.2 |
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# define CONFIG_NETMASK 255.255.255.0 |
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# define CONFIG_SERVERIP 192.162.1.1 |
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# define CONFIG_GATEWAYIP 192.162.1.1 |
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# define CONFIG_OVERWRITE_ETHADDR_ONCE |
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#endif |
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#ifdef CONFIG_CMD_USB |
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# define CONFIG_USB_OHCI_NEW |
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# define CONFIG_USB_STORAGE |
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# ifndef CONFIG_CMD_PCI |
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# define CONFIG_CMD_PCI |
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# endif |
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# define CONFIG_PCI_OHCI |
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# define CONFIG_DOS_PARTITION |
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# undef CFG_USB_OHCI_BOARD_INIT |
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# undef CFG_USB_OHCI_CPU_INIT |
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# define CFG_USB_OHCI_MAX_ROOT_PORTS 15 |
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# define CFG_USB_OHCI_SLOT_NAME "isp1561" |
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# define CFG_OHCI_SWAP_REG_ACCESS |
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#endif |
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/* I2C */ |
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#define CONFIG_FSL_I2C |
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#define CONFIG_HARD_I2C /* I2C with hw support */ |
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
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#define CFG_I2C_SPEED 80000 |
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#define CFG_I2C_SLAVE 0x7F |
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#define CFG_I2C_OFFSET 0x00008F00 |
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#define CFG_IMMR CFG_MBAR |
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/* PCI */ |
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#ifdef CONFIG_CMD_PCI |
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#define CONFIG_PCI 1 |
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#define CONFIG_PCI_PNP 1 |
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#define CONFIG_SKIPPCI_HOSTBRIDGE |
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#define CFG_PCI_CACHE_LINE_SIZE 8 |
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#define CFG_PCI_MEM_BUS 0x80000000 |
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#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS |
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#define CFG_PCI_MEM_SIZE 0x10000000 |
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#define CFG_PCI_IO_BUS 0x71000000 |
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#define CFG_PCI_IO_PHYS CFG_PCI_IO_BUS |
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#define CFG_PCI_IO_SIZE 0x01000000 |
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#define CFG_PCI_CFG_BUS 0x70000000 |
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#define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS |
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#define CFG_PCI_CFG_SIZE 0x01000000 |
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#endif |
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#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ |
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#define CONFIG_UDP_CHECKSUM |
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#ifdef CONFIG_MCFFEC |
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# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 |
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# define CONFIG_IPADDR 192.162.1.2 |
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# define CONFIG_NETMASK 255.255.255.0 |
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# define CONFIG_SERVERIP 192.162.1.1 |
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# define CONFIG_GATEWAYIP 192.162.1.1 |
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# define CONFIG_OVERWRITE_ETHADDR_ONCE |
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#endif /* FEC_ENET */ |
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#define CONFIG_HOSTNAME M547xEVB |
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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"netdev=eth0\0" \
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"loadaddr=10000\0" \
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"u-boot=u-boot.bin\0" \
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"load=tftp ${loadaddr) ${u-boot}\0" \
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"upd=run load; run prog\0" \
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"prog=prot off bank 1;" \
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"era ff800000 ff82ffff;" \
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"cp.b ${loadaddr} ff800000 ${filesize};"\
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"save\0" \
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"" |
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#define CONFIG_PRAM 512 /* 512 KB */ |
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#define CFG_PROMPT "-> " |
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#define CFG_LONGHELP /* undef to save memory */ |
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#ifdef CONFIG_CMD_KGDB |
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# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
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#else |
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# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
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#endif |
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
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#define CFG_MAXARGS 16 /* max number of command args */ |
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
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#define CFG_LOAD_ADDR 0x00010000 |
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#define CFG_HZ 1000 |
||||
#define CFG_CLK CFG_BUSCLK |
||||
#define CFG_CPU_CLK CFG_CLK * 2 |
||||
|
||||
#define CFG_MBAR 0xF0000000 |
||||
#define CFG_INTSRAM (CFG_MBAR + 0x10000) |
||||
#define CFG_INTSRAMSZ 0x8000 |
||||
|
||||
/*#define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000)*/ |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR 0xF2000000 |
||||
#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ |
||||
#define CFG_INIT_RAM_CTRL 0x21 |
||||
#define CFG_INIT_RAM1_ADDR (CFG_INIT_RAM_ADDR + CFG_INIT_RAM_END) |
||||
#define CFG_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ |
||||
#define CFG_INIT_RAM1_CTRL 0x21 |
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_SDRAM_CFG1 0x73711630 |
||||
#define CFG_SDRAM_CFG2 0x46370000 |
||||
#define CFG_SDRAM_CTRL 0xE10B0000 |
||||
#define CFG_SDRAM_EMOD 0x40010000 |
||||
#define CFG_SDRAM_MODE 0x018D0000 |
||||
#define CFG_SDRAM_DRVSTRENGTH 0x000002AA |
||||
#ifdef CFG_DRAMSZ1 |
||||
# define CFG_SDRAM_SIZE (CFG_DRAMSZ + CFG_DRAMSZ1) |
||||
#else |
||||
# define CFG_SDRAM_SIZE CFG_DRAMSZ |
||||
#endif |
||||
|
||||
#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 |
||||
#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) |
||||
|
||||
#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) |
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
|
||||
#define CFG_BOOTPARAMS_LEN 64*1024 |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization ?? |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_FLASH_CFI |
||||
#ifdef CFG_FLASH_CFI |
||||
# define CFG_FLASH_BASE (CFG_CS0_BASE) |
||||
# define CFG_FLASH_CFI_DRIVER 1 |
||||
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
||||
# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ |
||||
# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ |
||||
# define CFG_FLASH_USE_BUFFER_WRITE |
||||
#ifdef CFG_NOR1SZ |
||||
# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
||||
# define CFG_FLASH_SIZE ((CFG_NOR1SZ + CFG_BOOTSZ) << 20) |
||||
# define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE, CFG_CS1_BASE } |
||||
#else |
||||
# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
# define CFG_FLASH_SIZE (CFG_BOOTSZ << 20) |
||||
#endif |
||||
#endif |
||||
|
||||
/* Configuration for environment
|
||||
* Environment is embedded in u-boot in the second sector of the flash |
||||
*/ |
||||
#define CFG_ENV_OFFSET 0x2000 |
||||
#define CFG_ENV_SECT_SIZE 0x2000 |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_IS_EMBEDDED 1 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 16 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Chipselect bank definitions |
||||
*/ |
||||
/*
|
||||
* CS0 - NOR Flash 1, 2, 4, or 8MB |
||||
* CS1 - NOR Flash |
||||
* CS2 - Available |
||||
* CS3 - Available |
||||
* CS4 - Available |
||||
* CS5 - Available |
||||
*/ |
||||
#define CFG_CS0_BASE 0xFF800000 |
||||
#define CFG_CS0_MASK (((CFG_BOOTSZ << 20) - 1) & 0xFFFF0001) |
||||
#define CFG_CS0_CTRL 0x00101980 |
||||
|
||||
#ifdef CFG_NOR1SZ |
||||
#define CFG_CS1_BASE 0xF8000000 |
||||
#define CFG_CS1_MASK (((CFG_NOR1SZ << 20) - 1) & 0xFFFF0001) |
||||
#define CFG_CS1_CTRL 0x00000D80 |
||||
#endif |
||||
|
||||
#endif /* _M5475EVB_H */ |
@ -0,0 +1,296 @@ |
||||
/*
|
||||
* Configuation settings for the Freescale MCF5485 FireEngine board. |
||||
* |
||||
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc. |
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef _M5485EVB_H |
||||
#define _M5485EVB_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#define CONFIG_MCF547x_8x /* define processor family */ |
||||
#define CONFIG_M548x /* define processor type */ |
||||
#define CONFIG_M5485 /* define processor type */ |
||||
|
||||
#undef DEBUG |
||||
|
||||
#define CONFIG_MCFUART |
||||
#define CFG_UART_PORT (0) |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } |
||||
|
||||
#define CONFIG_HW_WATCHDOG |
||||
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ |
||||
|
||||
/* Command line configuration */ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_CACHE |
||||
#undef CONFIG_CMD_DATE |
||||
#define CONFIG_CMD_ELF |
||||
#define CONFIG_CMD_FLASH |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_MEMORY |
||||
#define CONFIG_CMD_MISC |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_CMD_PCI |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_REGINFO |
||||
#define CONFIG_CMD_USB |
||||
|
||||
#define CONFIG_SLTTMR |
||||
|
||||
#define CONFIG_FSLDMAFEC |
||||
#ifdef CONFIG_FSLDMAFEC |
||||
# define CONFIG_NET_MULTI 1 |
||||
# define CONFIG_MII 1 |
||||
# define CONFIG_HAS_ETH1 |
||||
|
||||
# define CFG_DISCOVER_PHY |
||||
# define CFG_RX_ETH_BUFFER 32 |
||||
# define CFG_TX_ETH_BUFFER 48 |
||||
# define CFG_FAULT_ECHO_LINK_DOWN |
||||
|
||||
# define CFG_FEC0_PINMUX 0 |
||||
# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE |
||||
# define CFG_FEC1_PINMUX 0 |
||||
# define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE |
||||
|
||||
# define MCFFEC_TOUT_LOOP 50000 |
||||
/* If CFG_DISCOVER_PHY is not defined - hardcoded */ |
||||
# ifndef CFG_DISCOVER_PHY |
||||
# define FECDUPLEX FULL |
||||
# define FECSPEED _100BASET |
||||
# else |
||||
# ifndef CFG_FAULT_ECHO_LINK_DOWN |
||||
# define CFG_FAULT_ECHO_LINK_DOWN |
||||
# endif |
||||
# endif /* CFG_DISCOVER_PHY */ |
||||
|
||||
# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 |
||||
# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 |
||||
# define CONFIG_IPADDR 192.162.1.2 |
||||
# define CONFIG_NETMASK 255.255.255.0 |
||||
# define CONFIG_SERVERIP 192.162.1.1 |
||||
# define CONFIG_GATEWAYIP 192.162.1.1 |
||||
# define CONFIG_OVERWRITE_ETHADDR_ONCE |
||||
|
||||
#endif |
||||
|
||||
#ifdef CONFIG_CMD_USB |
||||
# define CONFIG_USB_STORAGE |
||||
# define CONFIG_DOS_PARTITION |
||||
# define CONFIG_USB_OHCI_NEW |
||||
# ifndef CONFIG_CMD_PCI |
||||
# define CONFIG_CMD_PCI |
||||
# endif |
||||
/*# define CONFIG_PCI_OHCI*/ |
||||
# define CFG_USB_OHCI_REGS_BASE 0x80041000 |
||||
# define CFG_USB_OHCI_MAX_ROOT_PORTS 15 |
||||
# define CFG_USB_OHCI_SLOT_NAME "isp1561" |
||||
# define CFG_OHCI_SWAP_REG_ACCESS |
||||
#endif |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_FSL_I2C |
||||
#define CONFIG_HARD_I2C /* I2C with hw support */ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 80000 |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
#define CFG_I2C_OFFSET 0x00008F00 |
||||
#define CFG_IMMR CFG_MBAR |
||||
|
||||
/* PCI */ |
||||
#ifdef CONFIG_CMD_PCI |
||||
#define CONFIG_PCI 1 |
||||
#define CONFIG_PCI_PNP 1 |
||||
|
||||
#define CFG_PCI_MEM_BUS 0x80000000 |
||||
#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS |
||||
#define CFG_PCI_MEM_SIZE 0x10000000 |
||||
|
||||
#define CFG_PCI_IO_BUS 0x71000000 |
||||
#define CFG_PCI_IO_PHYS CFG_PCI_IO_BUS |
||||
#define CFG_PCI_IO_SIZE 0x01000000 |
||||
|
||||
#define CFG_PCI_CFG_BUS 0x70000000 |
||||
#define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS |
||||
#define CFG_PCI_CFG_SIZE 0x01000000 |
||||
#endif |
||||
|
||||
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ |
||||
#define CONFIG_UDP_CHECKSUM |
||||
|
||||
#define CONFIG_HOSTNAME M548xEVB |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"loadaddr=10000\0" \
|
||||
"u-boot=u-boot.bin\0" \
|
||||
"load=tftp ${loadaddr) ${u-boot}\0" \
|
||||
"upd=run load; run prog\0" \
|
||||
"prog=prot off bank 1;" \
|
||||
"era ff800000 ff82ffff;" \
|
||||
"cp.b ${loadaddr} ff800000 ${filesize};"\
|
||||
"save\0" \
|
||||
"" |
||||
|
||||
#define CONFIG_PRAM 512 /* 512 KB */ |
||||
#define CFG_PROMPT "-> " |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
|
||||
#ifdef CONFIG_CMD_KGDB |
||||
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CFG_LOAD_ADDR 0x00010000 |
||||
|
||||
#define CFG_HZ 1000 |
||||
#define CFG_CLK CFG_BUSCLK |
||||
#define CFG_CPU_CLK CFG_CLK * 2 |
||||
|
||||
#define CFG_MBAR 0xF0000000 |
||||
#define CFG_INTSRAM (CFG_MBAR + 0x10000) |
||||
#define CFG_INTSRAMSZ 0x8000 |
||||
|
||||
/*#define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000)*/ |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR 0xF2000000 |
||||
#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ |
||||
#define CFG_INIT_RAM_CTRL 0x21 |
||||
#define CFG_INIT_RAM1_ADDR (CFG_INIT_RAM_ADDR + CFG_INIT_RAM_END) |
||||
#define CFG_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ |
||||
#define CFG_INIT_RAM1_CTRL 0x21 |
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_SDRAM_CFG1 0x73711630 |
||||
#define CFG_SDRAM_CFG2 0x46370000 |
||||
#define CFG_SDRAM_CTRL 0xE10B0000 |
||||
#define CFG_SDRAM_EMOD 0x40010000 |
||||
#define CFG_SDRAM_MODE 0x018D0000 |
||||
#define CFG_SDRAM_DRVSTRENGTH 0x000002AA |
||||
#ifdef CFG_DRAMSZ1 |
||||
# define CFG_SDRAM_SIZE (CFG_DRAMSZ + CFG_DRAMSZ1) |
||||
#else |
||||
# define CFG_SDRAM_SIZE CFG_DRAMSZ |
||||
#endif |
||||
|
||||
#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 |
||||
#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) |
||||
|
||||
#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) |
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
|
||||
#define CFG_BOOTPARAMS_LEN 64*1024 |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization ?? |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_FLASH_CFI |
||||
#ifdef CFG_FLASH_CFI |
||||
# define CFG_FLASH_BASE (CFG_CS0_BASE) |
||||
# define CFG_FLASH_CFI_DRIVER 1 |
||||
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
||||
# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ |
||||
# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ |
||||
# define CFG_FLASH_USE_BUFFER_WRITE |
||||
#ifdef CFG_NOR1SZ |
||||
# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
||||
# define CFG_FLASH_SIZE ((CFG_NOR1SZ + CFG_BOOTSZ) << 20) |
||||
# define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE, CFG_CS1_BASE } |
||||
#else |
||||
# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
# define CFG_FLASH_SIZE (CFG_BOOTSZ << 20) |
||||
#endif |
||||
#endif |
||||
|
||||
/* Configuration for environment
|
||||
* Environment is embedded in u-boot in the second sector of the flash |
||||
*/ |
||||
#define CFG_ENV_OFFSET 0x2000 |
||||
#define CFG_ENV_SECT_SIZE 0x2000 |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_IS_EMBEDDED 1 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 16 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Chipselect bank definitions |
||||
*/ |
||||
/*
|
||||
* CS0 - NOR Flash 1, 2, 4, or 8MB |
||||
* CS1 - NOR Flash |
||||
* CS2 - Available |
||||
* CS3 - Available |
||||
* CS4 - Available |
||||
* CS5 - Available |
||||
*/ |
||||
#define CFG_CS0_BASE 0xFF800000 |
||||
#define CFG_CS0_MASK (((CFG_BOOTSZ << 20) - 1) & 0xFFFF0001) |
||||
#define CFG_CS0_CTRL 0x00101980 |
||||
|
||||
#ifdef CFG_NOR1SZ |
||||
#define CFG_CS1_BASE 0xF8000000 |
||||
#define CFG_CS1_MASK (((CFG_NOR1SZ << 20) - 1) & 0xFFFF0001) |
||||
#define CFG_CS1_CTRL 0x00000D80 |
||||
#endif |
||||
|
||||
#endif /* _M5485EVB_H */ |
Loading…
Reference in new issue