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@ -21,32 +21,51 @@ |
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DECLARE_GLOBAL_DATA_PTR; |
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int get_memory_base_size(fdt_addr_t *mr_base, fdt_addr_t *mr_size) |
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{ |
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int mr_node; |
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mr_node = fdt_path_offset(gd->fdt_blob, "/memory"); |
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if (mr_node < 0) |
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return mr_node; |
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*mr_base = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, mr_node, |
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"reg", 0, mr_size, false); |
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debug("mr_base = %lx, mr_size= %lx\n", *mr_base, *mr_size); |
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return 0; |
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} |
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int dram_init(void) |
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{ |
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struct udevice *dev; |
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struct ram_info ram; |
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int rv; |
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fdt_addr_t mr_base, mr_size; |
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rv = uclass_get_device(UCLASS_RAM, 0, &dev); |
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if (rv) { |
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debug("DRAM init failed: %d\n", rv); |
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return rv; |
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} |
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rv = ram_get_info(dev, &ram); |
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if (rv) { |
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debug("Cannot get DRAM size: %d\n", rv); |
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rv = get_memory_base_size(&mr_base, &mr_size); |
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if (rv) |
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return rv; |
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} |
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debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size); |
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gd->ram_size = ram.size; |
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gd->ram_size = mr_size; |
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gd->ram_top = mr_base; |
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return rv; |
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} |
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int dram_init_banksize(void) |
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{ |
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fdt_addr_t mr_base, mr_size; |
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get_memory_base_size(&mr_base, &mr_size); |
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/*
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* Fill in global info with description of SRAM configuration |
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*/ |
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gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE; |
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gd->bd->bi_dram[0].size = ram.size; |
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gd->bd->bi_dram[0].start = mr_base; |
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gd->bd->bi_dram[0].size = mr_size; |
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return rv; |
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return 0; |
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} |
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#ifdef CONFIG_ETH_DESIGNWARE |
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@ -111,7 +130,6 @@ int board_late_init(void) |
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int board_init(void) |
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{ |
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
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gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; |
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return 0; |
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} |
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