Wolfgang Denk
16 years ago
commit
57bf140ac6
@ -0,0 +1,51 @@ |
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#
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# (C) Copyright 2000, 2001, 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS := da830evm.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak *~ .depend
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#########################################################################
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# This is for $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,43 @@ |
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#
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# (C) Copyright 2008, Texas Instruments, Inc. http://www.ti.com/
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#
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# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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#
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# (C) Copyright 2002
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# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
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# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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# Texas Instruments DA8xx EVM board (ARM925EJS) cpu
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# see http://www.ti.com/ for more information on Texas Instruments
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#
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# DA8xx EVM has 1 bank of 64 MB SDRAM (2 16Meg x16 chips).
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# Physical Address:
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# C000'0000 to C400'0000
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#
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# Linux-Kernel is expected to be at C000'8000, entry C000'8000
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# (mem base + reserved)
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#
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# we load ourself to C108 '0000
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#Provide at least 16MB spacing between us and the Linux Kernel image
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TEXT_BASE = 0xC1080000
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@ -0,0 +1,127 @@ |
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/*
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* Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com> |
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* |
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* Base on code from TI. Original Notices follow: |
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* |
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* (C) Copyright 2008, Texas Instruments, Inc. http://www.ti.com/
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* |
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* Modified for DA8xx EVM. |
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* |
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
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* |
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* Parts are shamelessly stolen from various TI sources, original copyright |
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* follows: |
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* ----------------------------------------------------------------- |
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* |
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* Copyright (C) 2004 Texas Instruments. |
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* |
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* ---------------------------------------------------------------------------- |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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* ---------------------------------------------------------------------------- |
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*/ |
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#include <common.h> |
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#include <i2c.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/io.h> |
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#include "../common/misc.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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#define pinmux &davinci_syscfg_regs->pinmux |
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#ifdef CONFIG_SPI_FLASH |
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/* SPI0 pin muxer settings */ |
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const struct pinmux_config spi0_pins[] = { |
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{ pinmux[7], 1, 3 }, |
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{ pinmux[7], 1, 4 }, |
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{ pinmux[7], 1, 5 }, |
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{ pinmux[7], 1, 6 }, |
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{ pinmux[7], 1, 7 } |
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}; |
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#endif |
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/* UART pin muxer settings */ |
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const struct pinmux_config uart_pins[] = { |
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{ pinmux[8], 2, 7 }, |
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{ pinmux[9], 2, 0 } |
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}; |
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/* I2C pin muxer settings */ |
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const struct pinmux_config i2c_pins[] = { |
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{ pinmux[9], 2, 3 }, |
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{ pinmux[9], 2, 4 } |
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}; |
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int board_init(void) |
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{ |
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#ifndef CONFIG_USE_IRQ |
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/*
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* Mask all IRQs by clearing the global enable and setting |
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* the enable clear for all the 90 interrupts. |
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*/ |
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writel(0, &davinci_aintc_regs->ger); |
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writel(0, &davinci_aintc_regs->hier); |
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writel(0xffffffff, &davinci_aintc_regs->ecr1); |
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writel(0xffffffff, &davinci_aintc_regs->ecr2); |
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writel(0xffffffff, &davinci_aintc_regs->ecr3); |
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#endif |
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/* arch number of the board */ |
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gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA830_EVM; |
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/* address of boot parameters */ |
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gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; |
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/*
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* Power on required peripherals |
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* ARM does not have access by default to PSC0 and PSC1 |
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* assuming here that the DSP bootloader has set the IOPU |
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* such that PSC access is available to ARM |
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*/ |
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lpsc_on(DAVINCI_LPSC_AEMIF); /* NAND, NOR */ |
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lpsc_on(DAVINCI_LPSC_SPI0); /* Serial Flash */ |
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lpsc_on(DAVINCI_LPSC_EMAC); /* image download */ |
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lpsc_on(DAVINCI_LPSC_UART2); /* console */ |
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lpsc_on(DAVINCI_LPSC_GPIO); |
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/* setup the SUSPSRC for ARM to control emulation suspend */ |
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writel(readl(&davinci_syscfg_regs->suspsrc) & |
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~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | |
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DAVINCI_SYSCFG_SUSPSRC_SPI0 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | |
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DAVINCI_SYSCFG_SUSPSRC_UART2), |
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&davinci_syscfg_regs->suspsrc); |
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#ifdef CONFIG_SPI_FLASH |
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if (davinci_configure_pin_mux(spi0_pins, ARRAY_SIZE(spi0_pins)) != 0) |
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return 1; |
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#endif |
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if (davinci_configure_pin_mux(uart_pins, ARRAY_SIZE(uart_pins)) != 0) |
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return 1; |
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if (davinci_configure_pin_mux(i2c_pins, ARRAY_SIZE(i2c_pins)) != 0) |
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return 1; |
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/* enable the console UART */ |
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writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | |
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DAVINCI_UART_PWREMU_MGMT_UTRST), |
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&davinci_uart2_ctrl_regs->pwremu_mgmt); |
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return(0); |
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} |
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@ -0,0 +1,51 @@ |
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS := a320evb.o
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SOBJS := lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,73 @@ |
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/*
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* (C) Copyright 2009 Faraday Technology |
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* Po-Yu Chuang <ratbert@faraday-tech.com> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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*/ |
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#include <common.h> |
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#include <netdev.h> |
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#include <asm/io.h> |
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#include <asm/arch/ftsmc020.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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/*
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* Miscellaneous platform dependent initialisations |
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*/ |
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int board_init(void) |
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{ |
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gd->bd->bi_arch_number = MACH_TYPE_FARADAY; |
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; |
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ftsmc020_init(); /* initialize Flash */ |
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return 0; |
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} |
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int dram_init(void) |
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{ |
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unsigned long sdram_base = PHYS_SDRAM_1; |
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unsigned long expected_size = PHYS_SDRAM_1_SIZE; |
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unsigned long actual_size; |
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actual_size = get_ram_size((void *)sdram_base, expected_size); |
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gd->bd->bi_dram[0].start = sdram_base; |
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gd->bd->bi_dram[0].size = actual_size; |
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if (expected_size != actual_size) |
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printf("Warning: Only %lu of %lu MiB SDRAM is working\n", |
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actual_size >> 20, expected_size >> 20); |
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return 0; |
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} |
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int board_eth_init(bd_t *bd) |
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{ |
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return ftmac100_initialize(bd); |
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} |
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ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) |
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{ |
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if (banknum == 0) { /* non-CFI boot flash */ |
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info->portwidth = FLASH_CFI_8BIT; |
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info->chipwidth = FLASH_CFI_BY8; |
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info->interface = FLASH_CFI_X8; |
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return 1; |
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} else |
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return 0; |
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} |
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@ -0,0 +1,35 @@ |
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#
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# (C) Copyright 2009 Faraday Technology
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# Po-Yu Chuang <ratbert@faraday-tech.com>
|
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#
|
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# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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# MA 02111-1307 USA
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#
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|
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# Faraday A320 board with FA526/FA626TE/ARM926EJ-S cpus
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#
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# see http://www.faraday-tech.com/ for more information
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# A320 has 1 bank of 64 MB DRAM
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#
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# 1000'0000 to 1400'0000
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#
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# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
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#
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# we load ourself to 13f8'0000
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#
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# download area is 1200'0000
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TEXT_BASE = 0x13f80000
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@ -0,0 +1,118 @@ |
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/* |
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* (C) Copyright 2009 Faraday Technology |
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* Po-Yu Chuang <ratbert@faraday-tech.com>
|
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* |
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or
|
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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*/ |
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|
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#include <config.h> |
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#include <version.h> |
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|
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#include <asm/macro.h> |
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#include <asm/arch/ftsdmc020.h> |
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|
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/* |
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* parameters for the SDRAM controller |
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*/ |
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#define TP0_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP0) |
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#define TP1_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP1) |
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#define CR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_CR) |
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#define B0_BSR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_BANK0_BSR) |
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#define ACR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_ACR) |
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|
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#define TP0_D CONFIG_SYS_FTSDMC020_TP0 |
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#define TP1_D CONFIG_SYS_FTSDMC020_TP1 |
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#define CR_D1 FTSDMC020_CR_IPREC |
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#define CR_D2 FTSDMC020_CR_ISMR |
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#define CR_D3 FTSDMC020_CR_IREF |
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|
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#define B0_BSR_D (CONFIG_SYS_FTSDMC020_BANK0_BSR | \ |
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FTSDMC020_BANK_BASE(PHYS_SDRAM_1)) |
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#define ACR_D FTSDMC020_ACR_TOC(0x18) |
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|
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/* |
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* numeric 7 segment display |
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*/ |
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.macro led, num |
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write32 CONFIG_DEBUG_LED, \num |
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.endm |
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|
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/* |
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* Waiting for SDRAM to set up |
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*/ |
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.macro wait_sdram
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ldr r0, =CONFIG_FTSDMC020_BASE |
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1: |
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ldr r1, [r0, #FTSDMC020_OFFSET_CR] |
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cmp r1, #0 |
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bne 1b |
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.endm |
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|
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.globl lowlevel_init
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lowlevel_init: |
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mov r11, lr |
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|
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led 0x0 |
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|
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bl init_sdmc |
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|
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led 0x1 |
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|
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/* everything is fine now */ |
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mov lr, r11 |
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mov pc, lr |
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|
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/* |
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* memory initialization |
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*/ |
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init_sdmc: |
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led 0x10 |
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|
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/* set SDRAM register */ |
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|
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write32 TP0_A, TP0_D |
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led 0x11 |
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|
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write32 TP1_A, TP1_D |
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led 0x12 |
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|
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/* set to precharge */ |
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write32 CR_A, CR_D1 |
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led 0x13 |
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|
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wait_sdram |
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led 0x14 |
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|
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/* set mode register */ |
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write32 CR_A, CR_D2 |
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led 0x15 |
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|
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wait_sdram |
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led 0x16 |
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|
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/* set to refresh */ |
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write32 CR_A, CR_D3 |
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led 0x17 |
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|
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wait_sdram |
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led 0x18 |
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|
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write32 B0_BSR_A, B0_BSR_D |
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led 0x19 |
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|
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write32 ACR_A, ACR_D |
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led 0x1a |
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|
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mov pc, lr |
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@ -0,0 +1,47 @@ |
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#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(SOC).a
|
||||
|
||||
SOBJS += reset.o
|
||||
COBJS += timer.o
|
||||
COBJS += ftsmc020.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
|
||||
all: $(obj).depend $(LIB) |
||||
|
||||
$(LIB): $(OBJS) |
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,51 @@ |
||||
/*
|
||||
* (C) Copyright 2009 Faraday Technology |
||||
* Po-Yu Chuang <ratbert@faraday-tech.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/ftsmc020.h> |
||||
|
||||
struct ftsmc020_config { |
||||
unsigned int config; |
||||
unsigned int timing; |
||||
}; |
||||
|
||||
static struct ftsmc020_config config[] = CONFIG_SYS_FTSMC020_CONFIGS; |
||||
|
||||
static struct ftsmc020 *smc = (struct ftsmc020 *)CONFIG_FTSMC020_BASE; |
||||
|
||||
static void ftsmc020_setup_bank(unsigned int bank, struct ftsmc020_config *cfg) |
||||
{ |
||||
if (bank > 3) { |
||||
printf("bank # %u invalid\n", bank); |
||||
return; |
||||
} |
||||
|
||||
writel(cfg->config, &smc->bank[bank].cr); |
||||
writel(cfg->timing, &smc->bank[bank].tpr); |
||||
} |
||||
|
||||
void ftsmc020_init(void) |
||||
{ |
||||
int i; |
||||
|
||||
for (i = 0; i < ARRAY_SIZE(config); i++) |
||||
ftsmc020_setup_bank(i, &config[i]); |
||||
} |
||||
@ -0,0 +1,22 @@ |
||||
/* |
||||
* (C) Copyright 2009 Faraday Technology |
||||
* Po-Yu Chuang <ratbert@faraday-tech.com>
|
||||
* |
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
*/ |
||||
|
||||
.global reset_cpu
|
||||
reset_cpu: |
||||
b reset_cpu |
||||
@ -0,0 +1,193 @@ |
||||
/*
|
||||
* (C) Copyright 2009 Faraday Technology |
||||
* Po-Yu Chuang <ratbert@faraday-tech.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/ftpmu010.h> |
||||
#include <asm/arch/fttmr010.h> |
||||
|
||||
static ulong timestamp; |
||||
static ulong lastdec; |
||||
|
||||
static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; |
||||
static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; |
||||
|
||||
#define TIMER_CLOCK 32768 |
||||
#define TIMER_LOAD_VAL 0xffffffff |
||||
|
||||
int timer_init(void) |
||||
{ |
||||
unsigned int oscc; |
||||
unsigned int cr; |
||||
|
||||
debug("%s()\n", __func__); |
||||
|
||||
/* disable timers */ |
||||
writel(0, &tmr->cr); |
||||
|
||||
/*
|
||||
* use 32768Hz oscillator for RTC, WDT, TIMER |
||||
*/ |
||||
|
||||
/* enable the 32768Hz oscillator */ |
||||
oscc = readl(&pmu->OSCC); |
||||
oscc &= ~(FTPMU010_OSCC_OSCL_OFF | FTPMU010_OSCC_OSCL_TRI); |
||||
writel(oscc, &pmu->OSCC); |
||||
|
||||
/* wait until ready */ |
||||
while (!(readl(&pmu->OSCC) & FTPMU010_OSCC_OSCL_STABLE)) |
||||
; |
||||
|
||||
/* select 32768Hz oscillator */ |
||||
oscc = readl(&pmu->OSCC); |
||||
oscc |= FTPMU010_OSCC_OSCL_RTCLSEL; |
||||
writel(oscc, &pmu->OSCC); |
||||
|
||||
/* setup timer */ |
||||
writel(TIMER_LOAD_VAL, &tmr->timer3_load); |
||||
writel(TIMER_LOAD_VAL, &tmr->timer3_counter); |
||||
writel(0, &tmr->timer3_match1); |
||||
writel(0, &tmr->timer3_match2); |
||||
|
||||
/* we don't want timer to issue interrupts */ |
||||
writel(FTTMR010_TM3_MATCH1 | |
||||
FTTMR010_TM3_MATCH2 | |
||||
FTTMR010_TM3_OVERFLOW, |
||||
&tmr->interrupt_mask); |
||||
|
||||
cr = readl(&tmr->cr); |
||||
cr |= FTTMR010_TM3_CLOCK; /* use external clock */ |
||||
cr |= FTTMR010_TM3_ENABLE; |
||||
writel(cr, &tmr->cr); |
||||
|
||||
/* init the timestamp and lastdec value */ |
||||
reset_timer_masked(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* timer without interrupts |
||||
*/ |
||||
|
||||
/*
|
||||
* reset time |
||||
*/ |
||||
void reset_timer_masked(void) |
||||
{ |
||||
/* capure current decrementer value time */ |
||||
lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ); |
||||
timestamp = 0; /* start "advancing" time stamp from 0 */ |
||||
|
||||
debug("%s(): lastdec = %lx\n", __func__, lastdec); |
||||
} |
||||
|
||||
void reset_timer(void) |
||||
{ |
||||
debug("%s()\n", __func__); |
||||
reset_timer_masked(); |
||||
} |
||||
|
||||
/*
|
||||
* return timer ticks |
||||
*/ |
||||
ulong get_timer_masked(void) |
||||
{ |
||||
/* current tick value */ |
||||
ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ); |
||||
|
||||
debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec); |
||||
|
||||
if (lastdec >= now) { |
||||
/*
|
||||
* normal mode (non roll) |
||||
* move stamp fordward with absoulte diff ticks |
||||
*/ |
||||
timestamp += lastdec - now; |
||||
} else { |
||||
/*
|
||||
* we have overflow of the count down timer |
||||
* |
||||
* nts = ts + ld + (TLV - now) |
||||
* ts=old stamp, ld=time that passed before passing through -1 |
||||
* (TLV-now) amount of time after passing though -1 |
||||
* nts = new "advancing time stamp"...it could also roll and |
||||
* cause problems. |
||||
*/ |
||||
timestamp += lastdec + TIMER_LOAD_VAL - now; |
||||
} |
||||
|
||||
lastdec = now; |
||||
|
||||
debug("%s() returns %lx\n", __func__, timestamp); |
||||
|
||||
return timestamp; |
||||
} |
||||
|
||||
/*
|
||||
* return difference between timer ticks and base |
||||
*/ |
||||
ulong get_timer(ulong base) |
||||
{ |
||||
debug("%s(%lx)\n", __func__, base); |
||||
return get_timer_masked() - base; |
||||
} |
||||
|
||||
void set_timer(ulong t) |
||||
{ |
||||
debug("%s(%lx)\n", __func__, t); |
||||
timestamp = t; |
||||
} |
||||
|
||||
/* delay x useconds AND perserve advance timstamp value */ |
||||
void udelay(unsigned long usec) |
||||
{ |
||||
long tmo = usec * (TIMER_CLOCK / 1000) / 1000; |
||||
unsigned long now, last = readl(&tmr->timer3_counter); |
||||
|
||||
debug("%s(%lu)\n", __func__, usec); |
||||
while (tmo > 0) { |
||||
now = readl(&tmr->timer3_counter); |
||||
if (now > last) /* count down timer overflow */ |
||||
tmo -= TIMER_LOAD_VAL + last - now; |
||||
else |
||||
tmo -= last - now; |
||||
last = now; |
||||
} |
||||
} |
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (read timebase as long long). |
||||
* On ARM it just returns the timer value. |
||||
*/ |
||||
unsigned long long get_ticks(void) |
||||
{ |
||||
debug("%s()\n", __func__); |
||||
return get_timer(0); |
||||
} |
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (timebase clock frequency). |
||||
* On ARM it returns the number of timer ticks per second. |
||||
*/ |
||||
ulong get_tbclk(void) |
||||
{ |
||||
debug("%s()\n", __func__); |
||||
return CONFIG_SYS_HZ; |
||||
} |
||||
@ -0,0 +1,116 @@ |
||||
Summary |
||||
======= |
||||
|
||||
This README is about U-Boot support for TI's ARM 926EJS based family of SoCs. |
||||
These SOCs are used for cameras, video security and surveillance, DVR's, etc. |
||||
DaVinci SOC's comprise of DM644x, DM646x, DM35x and DM36x series of SOC's |
||||
Additionally there are some SOCs meant for the audio market which though have |
||||
an OMAP part number are very similar to the DaVinci series of SOC's |
||||
Additionally, some family members contain a TI DSP and/or graphics |
||||
co processors along with a host of other peripherals. |
||||
|
||||
Currently the following boards are supported: |
||||
|
||||
* TI DaVinci DM644x EVM |
||||
|
||||
* TI DaVinci DM646x EVM |
||||
|
||||
* TI DaVinci DM355 EVM |
||||
|
||||
* TI DaVinci DM365 EVM |
||||
|
||||
* TI DA830 EVM |
||||
|
||||
* DM355 based Leopard board |
||||
|
||||
* DM644x based schmoogie board |
||||
|
||||
* DM644x based sffsdr board |
||||
|
||||
* DM644x based sonata board |
||||
|
||||
Build |
||||
===== |
||||
|
||||
* TI DaVinci DM644x EVM: |
||||
|
||||
make davinci_dvevm_config |
||||
make |
||||
|
||||
* TI DaVinci DM646x EVM: |
||||
|
||||
make davinci_dm6467evm_config |
||||
make |
||||
|
||||
* TI DaVinci DM355 EVM: |
||||
|
||||
make davinci_dm355evm_config |
||||
make |
||||
|
||||
* TI DaVinci DM365 EVM: |
||||
|
||||
make davinci_dm365evm_config |
||||
make |
||||
|
||||
* TI DA830 EVM: |
||||
|
||||
make da830evm_config |
||||
make |
||||
|
||||
* DM355 based Leopard board: |
||||
|
||||
make davinci_dm355leopard_config |
||||
make |
||||
|
||||
* DM644x based schmoogie board: |
||||
|
||||
make davinci_schmoogie_config |
||||
make |
||||
|
||||
* DM644x based sffsdr board: |
||||
|
||||
make davinci_sffsdr_config |
||||
make |
||||
|
||||
* DM644x based sonata board: |
||||
|
||||
make davinci_sonata_config |
||||
make |
||||
|
||||
Bootloaders |
||||
=============== |
||||
|
||||
The DaVinci SOC's use 2 bootloaders. The low level initialization |
||||
is done by a UBL(user boot loader). The UBL is written to a NAND/NOR/SPI flash |
||||
by a programmer. During initial bootup, the ROM Bootloader reads the UBL |
||||
from a storage device and loads it into the IRAM. The UBL then loads the U-Boot |
||||
into the RAM. |
||||
The programmers and UBL are always released as part of any standard TI |
||||
software release associated with an SOC. |
||||
|
||||
Links |
||||
===== |
||||
|
||||
1) TI DaVinci DM355 EVM: |
||||
http://focus.ti.com/docs/prod/folders/print/tms320dm355.html |
||||
http://www.spectrumdigital.com/product_info.php?cPath=103&products_id=203&osCsid=c499af6087317f11b3da19b4e8f1af32 |
||||
|
||||
2) TI DaVinci DM365 EVM: |
||||
http://focus.ti.com/docs/prod/folders/print/tms320dm365.html?247SEM= |
||||
http://support.spectrumdigital.com/boards/evmdm365/revc/ |
||||
|
||||
3) DaVinci DM355 based leopard board |
||||
http://designsomething.org/leopardboard/default.aspx |
||||
http://www.spectrumdigital.com/product_info.php?cPath=103&products_id=192&osCsid=67c20335668ffc57cb35727106eb24b1 |
||||
|
||||
4) TI DaVinci DM6467 EVM: |
||||
http://focus.ti.com/docs/prod/folders/print/tms320dm6467.html |
||||
http://support.spectrumdigital.com/boards/evmdm6467/revf/ |
||||
|
||||
5) TI DaVinci DM6446 EVM: |
||||
http://focus.ti.com/docs/prod/folders/print/tms320dm6446.html |
||||
http://www.spectrumdigital.com/product_info.php?cPath=103&products_id=222 |
||||
|
||||
6) TI DA830 EVM |
||||
http://focus.ti.com/apps/docs/gencontent.tsp?appId=1&contentId=52385 |
||||
http://www.spectrumdigital.com/product_info.php?cPath=37&products_id=214 |
||||
@ -0,0 +1,124 @@ |
||||
/*
|
||||
* Faraday FTRTC010 Real Time Clock |
||||
* |
||||
* (C) Copyright 2009 Faraday Technology |
||||
* Po-Yu Chuang <ratbert@faraday-tech.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <common.h> |
||||
#include <rtc.h> |
||||
#include <asm/io.h> |
||||
|
||||
struct ftrtc010 { |
||||
unsigned int sec; /* 0x00 */ |
||||
unsigned int min; /* 0x04 */ |
||||
unsigned int hour; /* 0x08 */ |
||||
unsigned int day; /* 0x0c */ |
||||
unsigned int alarm_sec; /* 0x10 */ |
||||
unsigned int alarm_min; /* 0x14 */ |
||||
unsigned int alarm_hour; /* 0x18 */ |
||||
unsigned int record; /* 0x1c */ |
||||
unsigned int cr; /* 0x20 */ |
||||
}; |
||||
|
||||
/*
|
||||
* RTC Control Register |
||||
*/ |
||||
#define FTRTC010_CR_ENABLE (1 << 0) |
||||
#define FTRTC010_CR_INTERRUPT_SEC (1 << 1) /* per second irq */ |
||||
#define FTRTC010_CR_INTERRUPT_MIN (1 << 2) /* per minute irq */ |
||||
#define FTRTC010_CR_INTERRUPT_HR (1 << 3) /* per hour irq */ |
||||
#define FTRTC010_CR_INTERRUPT_DAY (1 << 4) /* per day irq */ |
||||
|
||||
static struct ftrtc010 *rtc = (struct ftrtc010 *)CONFIG_FTRTC010_BASE; |
||||
|
||||
static void ftrtc010_enable(void) |
||||
{ |
||||
writel(FTRTC010_CR_ENABLE, &rtc->cr); |
||||
} |
||||
|
||||
/*
|
||||
* return current time in seconds |
||||
*/ |
||||
static unsigned long ftrtc010_time(void) |
||||
{ |
||||
unsigned long day; |
||||
unsigned long hour; |
||||
unsigned long minute; |
||||
unsigned long second; |
||||
unsigned long second2; |
||||
|
||||
do { |
||||
second = readl(&rtc->sec); |
||||
day = readl(&rtc->day); |
||||
hour = readl(&rtc->hour); |
||||
minute = readl(&rtc->min); |
||||
second2 = readl(&rtc->sec); |
||||
} while (second != second2); |
||||
|
||||
return day * 24 * 60 * 60 + hour * 60 * 60 + minute * 60 + second; |
||||
} |
||||
|
||||
/*
|
||||
* Get the current time from the RTC |
||||
*/ |
||||
|
||||
int rtc_get(struct rtc_time *tmp) |
||||
{ |
||||
unsigned long now; |
||||
|
||||
debug("%s(): record register: %x\n", |
||||
__func__, readl(&rtc->record)); |
||||
|
||||
now = ftrtc010_time() + readl(&rtc->record); |
||||
|
||||
to_tm(now, tmp); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Set the RTC |
||||
*/ |
||||
int rtc_set(struct rtc_time *tmp) |
||||
{ |
||||
unsigned long new; |
||||
unsigned long now; |
||||
|
||||
debug("%s(): DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", |
||||
__func__, |
||||
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, |
||||
tmp->tm_hour, tmp->tm_min, tmp->tm_sec); |
||||
|
||||
new = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_hour, |
||||
tmp->tm_min, tmp->tm_sec); |
||||
|
||||
now = ftrtc010_time(); |
||||
|
||||
debug("%s(): write %lx to record register\n", __func__, new - now); |
||||
|
||||
writel(new - now, &rtc->record); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void rtc_reset(void) |
||||
{ |
||||
debug("%s()\n", __func__); |
||||
ftrtc010_enable(); |
||||
} |
||||
@ -0,0 +1,35 @@ |
||||
/*
|
||||
* (C) Copyright 2009 Faraday Technology |
||||
* Po-Yu Chuang <ratbert@faraday-tech.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
*/ |
||||
|
||||
#ifndef __A320_H |
||||
#define __A320_H |
||||
|
||||
/*
|
||||
* Hardware register bases |
||||
*/ |
||||
#define CONFIG_FTSMC020_BASE 0x90200000 /* Static Memory Controller */ |
||||
#define CONFIG_DEBUG_LED 0x902ffffc /* Debug LED */ |
||||
#define CONFIG_FTSDMC020_BASE 0x90300000 /* SDRAM Controller */ |
||||
#define CONFIG_FTMAC100_BASE 0x90900000 /* Ethernet */ |
||||
#define CONFIG_FTPMU010_BASE 0x98100000 /* Power Management Unit */ |
||||
#define CONFIG_FTTMR010_BASE 0x98400000 /* Timer */ |
||||
#define CONFIG_FTRTC010_BASE 0x98600000 /* Real Time Clock*/ |
||||
|
||||
#endif /* __A320_H */ |
||||
|
||||
@ -0,0 +1,146 @@ |
||||
/*
|
||||
* (C) Copyright 2009 Faraday Technology |
||||
* Po-Yu Chuang <ratbert@faraday-tech.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
*/ |
||||
|
||||
/*
|
||||
* Power Management Unit |
||||
*/ |
||||
#ifndef __FTPMU010_H |
||||
#define __FTPMU010_H |
||||
|
||||
struct ftpmu010 { |
||||
unsigned int IDNMBR0; /* 0x00 */ |
||||
unsigned int reserved0; /* 0x04 */ |
||||
unsigned int OSCC; /* 0x08 */ |
||||
unsigned int PMODE; /* 0x0C */ |
||||
unsigned int PMCR; /* 0x10 */ |
||||
unsigned int PED; /* 0x14 */ |
||||
unsigned int PEDSR; /* 0x18 */ |
||||
unsigned int reserved1; /* 0x1C */ |
||||
unsigned int PMSR; /* 0x20 */ |
||||
unsigned int PGSR; /* 0x24 */ |
||||
unsigned int MFPSR; /* 0x28 */ |
||||
unsigned int MISC; /* 0x2C */ |
||||
unsigned int PDLLCR0; /* 0x30 */ |
||||
unsigned int PDLLCR1; /* 0x34 */ |
||||
unsigned int AHBMCLKOFF; /* 0x38 */ |
||||
unsigned int APBMCLKOFF; /* 0x3C */ |
||||
unsigned int DCSRCR0; /* 0x40 */ |
||||
unsigned int DCSRCR1; /* 0x44 */ |
||||
unsigned int DCSRCR2; /* 0x48 */ |
||||
unsigned int SDRAMHTC; /* 0x4C */ |
||||
unsigned int PSPR0; /* 0x50 */ |
||||
unsigned int PSPR1; /* 0x54 */ |
||||
unsigned int PSPR2; /* 0x58 */ |
||||
unsigned int PSPR3; /* 0x5C */ |
||||
unsigned int PSPR4; /* 0x60 */ |
||||
unsigned int PSPR5; /* 0x64 */ |
||||
unsigned int PSPR6; /* 0x68 */ |
||||
unsigned int PSPR7; /* 0x6C */ |
||||
unsigned int PSPR8; /* 0x70 */ |
||||
unsigned int PSPR9; /* 0x74 */ |
||||
unsigned int PSPR10; /* 0x78 */ |
||||
unsigned int PSPR11; /* 0x7C */ |
||||
unsigned int PSPR12; /* 0x80 */ |
||||
unsigned int PSPR13; /* 0x84 */ |
||||
unsigned int PSPR14; /* 0x88 */ |
||||
unsigned int PSPR15; /* 0x8C */ |
||||
unsigned int AHBDMA_RACCS; /* 0x90 */ |
||||
unsigned int reserved2; /* 0x94 */ |
||||
unsigned int reserved3; /* 0x98 */ |
||||
unsigned int JSS; /* 0x9C */ |
||||
unsigned int CFC_RACC; /* 0xA0 */ |
||||
unsigned int SSP1_RACC; /* 0xA4 */ |
||||
unsigned int UART1TX_RACC; /* 0xA8 */ |
||||
unsigned int UART1RX_RACC; /* 0xAC */ |
||||
unsigned int UART2TX_RACC; /* 0xB0 */ |
||||
unsigned int UART2RX_RACC; /* 0xB4 */ |
||||
unsigned int SDC_RACC; /* 0xB8 */ |
||||
unsigned int I2SAC97_RACC; /* 0xBC */ |
||||
unsigned int IRDATX_RACC; /* 0xC0 */ |
||||
unsigned int reserved4; /* 0xC4 */ |
||||
unsigned int USBD_RACC; /* 0xC8 */ |
||||
unsigned int IRDARX_RACC; /* 0xCC */ |
||||
unsigned int IRDA_RACC; /* 0xD0 */ |
||||
unsigned int ED0_RACC; /* 0xD4 */ |
||||
unsigned int ED1_RACC; /* 0xD8 */ |
||||
}; |
||||
|
||||
/*
|
||||
* ID Number 0 Register |
||||
*/ |
||||
#define FTPMU010_ID_A320A 0x03200000 |
||||
#define FTPMU010_ID_A320C 0x03200010 |
||||
#define FTPMU010_ID_A320D 0x03200030 |
||||
|
||||
/*
|
||||
* OSC Control Register |
||||
*/ |
||||
#define FTPMU010_OSCC_OSCH_TRI (1 << 11) |
||||
#define FTPMU010_OSCC_OSCH_STABLE (1 << 9) |
||||
#define FTPMU010_OSCC_OSCH_OFF (1 << 8) |
||||
|
||||
#define FTPMU010_OSCC_OSCL_TRI (1 << 3) |
||||
#define FTPMU010_OSCC_OSCL_RTCLSEL (1 << 2) |
||||
#define FTPMU010_OSCC_OSCL_STABLE (1 << 1) |
||||
#define FTPMU010_OSCC_OSCL_OFF (1 << 0) |
||||
|
||||
/*
|
||||
* Power Mode Register |
||||
*/ |
||||
#define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4) |
||||
#define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4) |
||||
#define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4) |
||||
#define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4) |
||||
#define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4) |
||||
#define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4) |
||||
#define FTPMU010_PMODE_DIVAHBCLK(pmode) (((pmode) >> 4) & 0x7) |
||||
#define FTPMU010_PMODE_FCS (1 << 2) |
||||
#define FTPMU010_PMODE_TURBO (1 << 1) |
||||
#define FTPMU010_PMODE_SLEEP (1 << 0) |
||||
|
||||
/*
|
||||
* Power Manager Status Register |
||||
*/ |
||||
#define FTPMU010_PMSR_SMR (1 << 10) |
||||
|
||||
#define FTPMU010_PMSR_RDH (1 << 2) |
||||
#define FTPMU010_PMSR_PH (1 << 1) |
||||
#define FTPMU010_PMSR_CKEHLOW (1 << 0) |
||||
|
||||
/*
|
||||
* Multi-Function Port Setting Register |
||||
*/ |
||||
#define FTPMU010_MFPSR_MODEMPINSEL (1 << 14) |
||||
#define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13) |
||||
#define FTPMU010_MFPSR_AC97PINSEL (1 << 3) |
||||
|
||||
/*
|
||||
* PLL/DLL Control Register 0 |
||||
*/ |
||||
#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) >> 20) & 0xf) |
||||
#define FTPMU010_PDLLCR0_DLLFRAG (1 << 19) |
||||
#define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18) |
||||
#define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17) |
||||
#define FTPMU010_PDLLCR0_DLLDIS (1 << 16) |
||||
#define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) >> 3) & 0x1ff) |
||||
#define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2) |
||||
#define FTPMU010_PDLLCR0_PLL1STABLE (1 << 1) |
||||
#define FTPMU010_PDLLCR0_PLL1DIS (1 << 0) |
||||
|
||||
#endif /* __FTPMU010_H */ |
||||
@ -0,0 +1,103 @@ |
||||
/*
|
||||
* (C) Copyright 2009 Faraday Technology |
||||
* Po-Yu Chuang <ratbert@faraday-tech.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
*/ |
||||
|
||||
/*
|
||||
* SDRAM Controller |
||||
*/ |
||||
#ifndef __FTSDMC020_H |
||||
#define __FTSDMC020_H |
||||
|
||||
#define FTSDMC020_OFFSET_TP0 0x00 |
||||
#define FTSDMC020_OFFSET_TP1 0x04 |
||||
#define FTSDMC020_OFFSET_CR 0x08 |
||||
#define FTSDMC020_OFFSET_BANK0_BSR 0x0C |
||||
#define FTSDMC020_OFFSET_BANK1_BSR 0x10 |
||||
#define FTSDMC020_OFFSET_BANK2_BSR 0x14 |
||||
#define FTSDMC020_OFFSET_BANK3_BSR 0x18 |
||||
#define FTSDMC020_OFFSET_BANK4_BSR 0x1C |
||||
#define FTSDMC020_OFFSET_BANK5_BSR 0x20 |
||||
#define FTSDMC020_OFFSET_BANK6_BSR 0x24 |
||||
#define FTSDMC020_OFFSET_BANK7_BSR 0x28 |
||||
#define FTSDMC020_OFFSET_ACR 0x34 |
||||
|
||||
/*
|
||||
* Timing Parametet 0 Register |
||||
*/ |
||||
#define FTSDMC020_TP0_TCL(x) ((x) & 0x3) |
||||
#define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4) |
||||
#define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8) |
||||
#define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12) |
||||
#define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16) |
||||
#define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20) |
||||
|
||||
/*
|
||||
* Timing Parametet 1 Register |
||||
*/ |
||||
#define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff) |
||||
#define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16) |
||||
#define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20) |
||||
|
||||
/*
|
||||
* Configuration Register |
||||
*/ |
||||
#define FTSDMC020_CR_SREF (1 << 0) |
||||
#define FTSDMC020_CR_PWDN (1 << 1) |
||||
#define FTSDMC020_CR_ISMR (1 << 2) |
||||
#define FTSDMC020_CR_IREF (1 << 3) |
||||
#define FTSDMC020_CR_IPREC (1 << 4) |
||||
#define FTSDMC020_CR_REFTYPE (1 << 5) |
||||
|
||||
/*
|
||||
* SDRAM External Bank Base/Size Register |
||||
*/ |
||||
#define FTSDMC020_BANK_ENABLE (1 << 28) |
||||
|
||||
#define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16) |
||||
|
||||
#define FTSDMC020_BANK_DDW_X4 (0 << 12) |
||||
#define FTSDMC020_BANK_DDW_X8 (1 << 12) |
||||
#define FTSDMC020_BANK_DDW_X16 (2 << 12) |
||||
#define FTSDMC020_BANK_DDW_X32 (3 << 12) |
||||
|
||||
#define FTSDMC020_BANK_DSZ_16M (0 << 8) |
||||
#define FTSDMC020_BANK_DSZ_64M (1 << 8) |
||||
#define FTSDMC020_BANK_DSZ_128M (2 << 8) |
||||
#define FTSDMC020_BANK_DSZ_256M (3 << 8) |
||||
|
||||
#define FTSDMC020_BANK_MBW_8 (0 << 4) |
||||
#define FTSDMC020_BANK_MBW_16 (1 << 4) |
||||
#define FTSDMC020_BANK_MBW_32 (2 << 4) |
||||
|
||||
#define FTSDMC020_BANK_SIZE_1M 0x0 |
||||
#define FTSDMC020_BANK_SIZE_2M 0x1 |
||||
#define FTSDMC020_BANK_SIZE_4M 0x2 |
||||
#define FTSDMC020_BANK_SIZE_8M 0x3 |
||||
#define FTSDMC020_BANK_SIZE_16M 0x4 |
||||
#define FTSDMC020_BANK_SIZE_32M 0x5 |
||||
#define FTSDMC020_BANK_SIZE_64M 0x6 |
||||
#define FTSDMC020_BANK_SIZE_128M 0x7 |
||||
#define FTSDMC020_BANK_SIZE_256M 0x8 |
||||
|
||||
/*
|
||||
* Arbiter Control Register |
||||
*/ |
||||
#define FTSDMC020_ACR_TOC(x) ((x) & 0x1f) |
||||
#define FTSDMC020_ACR_TOE (1 << 8) |
||||
|
||||
#endif /* __FTSDMC020_H */ |
||||
@ -0,0 +1,79 @@ |
||||
/*
|
||||
* (C) Copyright 2009 Faraday Technology |
||||
* Po-Yu Chuang <ratbert@faraday-tech.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
*/ |
||||
|
||||
/*
|
||||
* Static Memory Controller |
||||
*/ |
||||
#ifndef __FTSMC020_H |
||||
#define __FTSMC020_H |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
|
||||
struct ftsmc020 { |
||||
struct { |
||||
unsigned int cr; /* 0x00, 0x08, 0x10, 0x18 */ |
||||
unsigned int tpr; /* 0x04, 0x0c, 0x14, 0x1c */ |
||||
} bank[4]; |
||||
unsigned int pad[8]; /* 0x20 - 0x3c */ |
||||
unsigned int ssr; /* 0x40 */ |
||||
}; |
||||
|
||||
void ftsmc020_init(void); |
||||
|
||||
#endif /* __ASSEMBLY__ */ |
||||
|
||||
/*
|
||||
* Memory Bank Configuration Register |
||||
*/ |
||||
#define FTSMC020_BANK_ENABLE (1 << 28) |
||||
#define FTSMC020_BANK_BASE(x) ((x) & 0x0fff1000) |
||||
|
||||
#define FTSMC020_BANK_WPROT (1 << 11) |
||||
|
||||
#define FTSMC020_BANK_SIZE_32K (0xb << 4) |
||||
#define FTSMC020_BANK_SIZE_64K (0xc << 4) |
||||
#define FTSMC020_BANK_SIZE_128K (0xd << 4) |
||||
#define FTSMC020_BANK_SIZE_256K (0xe << 4) |
||||
#define FTSMC020_BANK_SIZE_512K (0xf << 4) |
||||
#define FTSMC020_BANK_SIZE_1M (0x0 << 4) |
||||
#define FTSMC020_BANK_SIZE_2M (0x1 << 4) |
||||
#define FTSMC020_BANK_SIZE_4M (0x2 << 4) |
||||
#define FTSMC020_BANK_SIZE_8M (0x3 << 4) |
||||
#define FTSMC020_BANK_SIZE_16M (0x4 << 4) |
||||
#define FTSMC020_BANK_SIZE_32M (0x5 << 4) |
||||
|
||||
#define FTSMC020_BANK_MBW_8 (0x0 << 0) |
||||
#define FTSMC020_BANK_MBW_16 (0x1 << 0) |
||||
#define FTSMC020_BANK_MBW_32 (0x2 << 0) |
||||
|
||||
/*
|
||||
* Memory Bank Timing Parameter Register |
||||
*/ |
||||
#define FTSMC020_TPR_ETRNA(x) (((x) & 0xf) << 28) |
||||
#define FTSMC020_TPR_EATI(x) (((x) & 0xf) << 24) |
||||
#define FTSMC020_TPR_RBE (1 << 20) |
||||
#define FTSMC020_TPR_AST(x) (((x) & 0x3) << 18) |
||||
#define FTSMC020_TPR_CTW(x) (((x) & 0x3) << 16) |
||||
#define FTSMC020_TPR_ATI(x) (((x) & 0xf) << 12) |
||||
#define FTSMC020_TPR_AT2(x) (((x) & 0x3) << 8) |
||||
#define FTSMC020_TPR_WTC(x) (((x) & 0x3) << 6) |
||||
#define FTSMC020_TPR_AHT(x) (((x) & 0x3) << 4) |
||||
#define FTSMC020_TPR_TRNA(x) (((x) & 0xf) << 0) |
||||
|
||||
#endif /* __FTSMC020_H */ |
||||
@ -0,0 +1,73 @@ |
||||
/*
|
||||
* (C) Copyright 2009 Faraday Technology |
||||
* Po-Yu Chuang <ratbert@faraday-tech.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
*/ |
||||
|
||||
/*
|
||||
* Timer |
||||
*/ |
||||
#ifndef __FTTMR010_H |
||||
#define __FTTMR010_H |
||||
|
||||
struct fttmr010 { |
||||
unsigned int timer1_counter; /* 0x00 */ |
||||
unsigned int timer1_load; /* 0x04 */ |
||||
unsigned int timer1_match1; /* 0x08 */ |
||||
unsigned int timer1_match2; /* 0x0c */ |
||||
unsigned int timer2_counter; /* 0x10 */ |
||||
unsigned int timer2_load; /* 0x14 */ |
||||
unsigned int timer2_match1; /* 0x18 */ |
||||
unsigned int timer2_match2; /* 0x1c */ |
||||
unsigned int timer3_counter; /* 0x20 */ |
||||
unsigned int timer3_load; /* 0x24 */ |
||||
unsigned int timer3_match1; /* 0x28 */ |
||||
unsigned int timer3_match2; /* 0x2c */ |
||||
unsigned int cr; /* 0x30 */ |
||||
unsigned int interrupt_state; /* 0x34 */ |
||||
unsigned int interrupt_mask; /* 0x38 */ |
||||
}; |
||||
|
||||
/*
|
||||
* Timer Control Register |
||||
*/ |
||||
#define FTTMR010_TM3_UPDOWN (1 << 11) |
||||
#define FTTMR010_TM2_UPDOWN (1 << 10) |
||||
#define FTTMR010_TM1_UPDOWN (1 << 9) |
||||
#define FTTMR010_TM3_OFENABLE (1 << 8) |
||||
#define FTTMR010_TM3_CLOCK (1 << 7) |
||||
#define FTTMR010_TM3_ENABLE (1 << 6) |
||||
#define FTTMR010_TM2_OFENABLE (1 << 5) |
||||
#define FTTMR010_TM2_CLOCK (1 << 4) |
||||
#define FTTMR010_TM2_ENABLE (1 << 3) |
||||
#define FTTMR010_TM1_OFENABLE (1 << 2) |
||||
#define FTTMR010_TM1_CLOCK (1 << 1) |
||||
#define FTTMR010_TM1_ENABLE (1 << 0) |
||||
|
||||
/*
|
||||
* Timer Interrupt State & Mask Registers |
||||
*/ |
||||
#define FTTMR010_TM3_OVERFLOW (1 << 8) |
||||
#define FTTMR010_TM3_MATCH2 (1 << 7) |
||||
#define FTTMR010_TM3_MATCH1 (1 << 6) |
||||
#define FTTMR010_TM2_OVERFLOW (1 << 5) |
||||
#define FTTMR010_TM2_MATCH2 (1 << 4) |
||||
#define FTTMR010_TM2_MATCH1 (1 << 3) |
||||
#define FTTMR010_TM1_OVERFLOW (1 << 2) |
||||
#define FTTMR010_TM1_MATCH2 (1 << 1) |
||||
#define FTTMR010_TM1_MATCH1 (1 << 0) |
||||
|
||||
#endif /* __FTTMR010_H */ |
||||
@ -0,0 +1,652 @@ |
||||
/*
|
||||
* (C) Copyright 2003 |
||||
* David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/************************************************
|
||||
* NAME : s3c24x0.h |
||||
* Version : 31.3.2003 |
||||
* |
||||
* common stuff for SAMSUNG S3C24X0 SoC |
||||
************************************************/ |
||||
|
||||
#ifndef __S3C24X0_H__ |
||||
#define __S3C24X0_H__ |
||||
|
||||
/* Memory controller (see manual chapter 5) */ |
||||
struct s3c24x0_memctl { |
||||
u32 BWSCON; |
||||
u32 BANKCON[8]; |
||||
u32 REFRESH; |
||||
u32 BANKSIZE; |
||||
u32 MRSRB6; |
||||
u32 MRSRB7; |
||||
}; |
||||
|
||||
|
||||
/* USB HOST (see manual chapter 12) */ |
||||
struct s3c24x0_usb_host { |
||||
u32 HcRevision; |
||||
u32 HcControl; |
||||
u32 HcCommonStatus; |
||||
u32 HcInterruptStatus; |
||||
u32 HcInterruptEnable; |
||||
u32 HcInterruptDisable; |
||||
u32 HcHCCA; |
||||
u32 HcPeriodCuttendED; |
||||
u32 HcControlHeadED; |
||||
u32 HcControlCurrentED; |
||||
u32 HcBulkHeadED; |
||||
u32 HcBuldCurrentED; |
||||
u32 HcDoneHead; |
||||
u32 HcRmInterval; |
||||
u32 HcFmRemaining; |
||||
u32 HcFmNumber; |
||||
u32 HcPeriodicStart; |
||||
u32 HcLSThreshold; |
||||
u32 HcRhDescriptorA; |
||||
u32 HcRhDescriptorB; |
||||
u32 HcRhStatus; |
||||
u32 HcRhPortStatus1; |
||||
u32 HcRhPortStatus2; |
||||
}; |
||||
|
||||
|
||||
/* INTERRUPT (see manual chapter 14) */ |
||||
struct s3c24x0_interrupt { |
||||
u32 SRCPND; |
||||
u32 INTMOD; |
||||
u32 INTMSK; |
||||
u32 PRIORITY; |
||||
u32 INTPND; |
||||
u32 INTOFFSET; |
||||
#ifdef CONFIG_S3C2410 |
||||
u32 SUBSRCPND; |
||||
u32 INTSUBMSK; |
||||
#endif |
||||
}; |
||||
|
||||
|
||||
/* DMAS (see manual chapter 8) */ |
||||
struct s3c24x0_dma { |
||||
u32 DISRC; |
||||
#ifdef CONFIG_S3C2410 |
||||
u32 DISRCC; |
||||
#endif |
||||
u32 DIDST; |
||||
#ifdef CONFIG_S3C2410 |
||||
u32 DIDSTC; |
||||
#endif |
||||
u32 DCON; |
||||
u32 DSTAT; |
||||
u32 DCSRC; |
||||
u32 DCDST; |
||||
u32 DMASKTRIG; |
||||
#ifdef CONFIG_S3C2400 |
||||
u32 res[1]; |
||||
#endif |
||||
#ifdef CONFIG_S3C2410 |
||||
u32 res[7]; |
||||
#endif |
||||
}; |
||||
|
||||
struct s3c24x0_dmas { |
||||
struct s3c24x0_dma dma[4]; |
||||
}; |
||||
|
||||
|
||||
/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */ |
||||
/* (see S3C2410 manual chapter 7) */ |
||||
struct s3c24x0_clock_power { |
||||
u32 LOCKTIME; |
||||
u32 MPLLCON; |
||||
u32 UPLLCON; |
||||
u32 CLKCON; |
||||
u32 CLKSLOW; |
||||
u32 CLKDIVN; |
||||
}; |
||||
|
||||
|
||||
/* LCD CONTROLLER (see manual chapter 15) */ |
||||
struct s3c24x0_lcd { |
||||
u32 LCDCON1; |
||||
u32 LCDCON2; |
||||
u32 LCDCON3; |
||||
u32 LCDCON4; |
||||
u32 LCDCON5; |
||||
u32 LCDSADDR1; |
||||
u32 LCDSADDR2; |
||||
u32 LCDSADDR3; |
||||
u32 REDLUT; |
||||
u32 GREENLUT; |
||||
u32 BLUELUT; |
||||
u32 res[8]; |
||||
u32 DITHMODE; |
||||
u32 TPAL; |
||||
#ifdef CONFIG_S3C2410 |
||||
u32 LCDINTPND; |
||||
u32 LCDSRCPND; |
||||
u32 LCDINTMSK; |
||||
u32 LPCSEL; |
||||
#endif |
||||
}; |
||||
|
||||
|
||||
/* NAND FLASH (see S3C2410 manual chapter 6) */ |
||||
struct s3c2410_nand { |
||||
u32 NFCONF; |
||||
u32 NFCMD; |
||||
u32 NFADDR; |
||||
u32 NFDATA; |
||||
u32 NFSTAT; |
||||
u32 NFECC; |
||||
}; |
||||
|
||||
|
||||
/* UART (see manual chapter 11) */ |
||||
struct s3c24x0_uart { |
||||
u32 ULCON; |
||||
u32 UCON; |
||||
u32 UFCON; |
||||
u32 UMCON; |
||||
u32 UTRSTAT; |
||||
u32 UERSTAT; |
||||
u32 UFSTAT; |
||||
u32 UMSTAT; |
||||
#ifdef __BIG_ENDIAN |
||||
u8 res1[3]; |
||||
u8 UTXH; |
||||
u8 res2[3]; |
||||
u8 URXH; |
||||
#else /* Little Endian */ |
||||
u8 UTXH; |
||||
u8 res1[3]; |
||||
u8 URXH; |
||||
u8 res2[3]; |
||||
#endif |
||||
u32 UBRDIV; |
||||
}; |
||||
|
||||
|
||||
/* PWM TIMER (see manual chapter 10) */ |
||||
struct s3c24x0_timer { |
||||
u32 TCNTB; |
||||
u32 TCMPB; |
||||
u32 TCNTO; |
||||
}; |
||||
|
||||
struct s3c24x0_timers { |
||||
u32 TCFG0; |
||||
u32 TCFG1; |
||||
u32 TCON; |
||||
struct s3c24x0_timer ch[4]; |
||||
u32 TCNTB4; |
||||
u32 TCNTO4; |
||||
}; |
||||
|
||||
|
||||
/* USB DEVICE (see manual chapter 13) */ |
||||
struct s3c24x0_usb_dev_fifos { |
||||
#ifdef __BIG_ENDIAN |
||||
u8 res[3]; |
||||
u8 EP_FIFO_REG; |
||||
#else /* little endian */ |
||||
u8 EP_FIFO_REG; |
||||
u8 res[3]; |
||||
#endif |
||||
}; |
||||
|
||||
struct s3c24x0_usb_dev_dmas { |
||||
#ifdef __BIG_ENDIAN |
||||
u8 res1[3]; |
||||
u8 EP_DMA_CON; |
||||
u8 res2[3]; |
||||
u8 EP_DMA_UNIT; |
||||
u8 res3[3]; |
||||
u8 EP_DMA_FIFO; |
||||
u8 res4[3]; |
||||
u8 EP_DMA_TTC_L; |
||||
u8 res5[3]; |
||||
u8 EP_DMA_TTC_M; |
||||
u8 res6[3]; |
||||
u8 EP_DMA_TTC_H; |
||||
#else /* little endian */ |
||||
u8 EP_DMA_CON; |
||||
u8 res1[3]; |
||||
u8 EP_DMA_UNIT; |
||||
u8 res2[3]; |
||||
u8 EP_DMA_FIFO; |
||||
u8 res3[3]; |
||||
u8 EP_DMA_TTC_L; |
||||
u8 res4[3]; |
||||
u8 EP_DMA_TTC_M; |
||||
u8 res5[3]; |
||||
u8 EP_DMA_TTC_H; |
||||
u8 res6[3]; |
||||
#endif |
||||
}; |
||||
|
||||
struct s3c24x0_usb_device { |
||||
#ifdef __BIG_ENDIAN |
||||
u8 res1[3]; |
||||
u8 FUNC_ADDR_REG; |
||||
u8 res2[3]; |
||||
u8 PWR_REG; |
||||
u8 res3[3]; |
||||
u8 EP_INT_REG; |
||||
u8 res4[15]; |
||||
u8 USB_INT_REG; |
||||
u8 res5[3]; |
||||
u8 EP_INT_EN_REG; |
||||
u8 res6[15]; |
||||
u8 USB_INT_EN_REG; |
||||
u8 res7[3]; |
||||
u8 FRAME_NUM1_REG; |
||||
u8 res8[3]; |
||||
u8 FRAME_NUM2_REG; |
||||
u8 res9[3]; |
||||
u8 INDEX_REG; |
||||
u8 res10[7]; |
||||
u8 MAXP_REG; |
||||
u8 res11[3]; |
||||
u8 EP0_CSR_IN_CSR1_REG; |
||||
u8 res12[3]; |
||||
u8 IN_CSR2_REG; |
||||
u8 res13[7]; |
||||
u8 OUT_CSR1_REG; |
||||
u8 res14[3]; |
||||
u8 OUT_CSR2_REG; |
||||
u8 res15[3]; |
||||
u8 OUT_FIFO_CNT1_REG; |
||||
u8 res16[3]; |
||||
u8 OUT_FIFO_CNT2_REG; |
||||
#else /* little endian */ |
||||
u8 FUNC_ADDR_REG; |
||||
u8 res1[3]; |
||||
u8 PWR_REG; |
||||
u8 res2[3]; |
||||
u8 EP_INT_REG; |
||||
u8 res3[15]; |
||||
u8 USB_INT_REG; |
||||
u8 res4[3]; |
||||
u8 EP_INT_EN_REG; |
||||
u8 res5[15]; |
||||
u8 USB_INT_EN_REG; |
||||
u8 res6[3]; |
||||
u8 FRAME_NUM1_REG; |
||||
u8 res7[3]; |
||||
u8 FRAME_NUM2_REG; |
||||
u8 res8[3]; |
||||
u8 INDEX_REG; |
||||
u8 res9[7]; |
||||
u8 MAXP_REG; |
||||
u8 res10[7]; |
||||
u8 EP0_CSR_IN_CSR1_REG; |
||||
u8 res11[3]; |
||||
u8 IN_CSR2_REG; |
||||
u8 res12[3]; |
||||
u8 OUT_CSR1_REG; |
||||
u8 res13[7]; |
||||
u8 OUT_CSR2_REG; |
||||
u8 res14[3]; |
||||
u8 OUT_FIFO_CNT1_REG; |
||||
u8 res15[3]; |
||||
u8 OUT_FIFO_CNT2_REG; |
||||
u8 res16[3]; |
||||
#endif /* __BIG_ENDIAN */ |
||||
struct s3c24x0_usb_dev_fifos fifo[5]; |
||||
struct s3c24x0_usb_dev_dmas dma[5]; |
||||
}; |
||||
|
||||
|
||||
/* WATCH DOG TIMER (see manual chapter 18) */ |
||||
struct s3c24x0_watchdog { |
||||
u32 WTCON; |
||||
u32 WTDAT; |
||||
u32 WTCNT; |
||||
}; |
||||
|
||||
|
||||
/* IIC (see manual chapter 20) */ |
||||
struct s3c24x0_i2c { |
||||
u32 IICCON; |
||||
u32 IICSTAT; |
||||
u32 IICADD; |
||||
u32 IICDS; |
||||
}; |
||||
|
||||
|
||||
/* IIS (see manual chapter 21) */ |
||||
struct s3c24x0_i2s { |
||||
#ifdef __BIG_ENDIAN |
||||
u16 res1; |
||||
u16 IISCON; |
||||
u16 res2; |
||||
u16 IISMOD; |
||||
u16 res3; |
||||
u16 IISPSR; |
||||
u16 res4; |
||||
u16 IISFCON; |
||||
u16 res5; |
||||
u16 IISFIFO; |
||||
#else /* little endian */ |
||||
u16 IISCON; |
||||
u16 res1; |
||||
u16 IISMOD; |
||||
u16 res2; |
||||
u16 IISPSR; |
||||
u16 res3; |
||||
u16 IISFCON; |
||||
u16 res4; |
||||
u16 IISFIFO; |
||||
u16 res5; |
||||
#endif |
||||
}; |
||||
|
||||
|
||||
/* I/O PORT (see manual chapter 9) */ |
||||
struct s3c24x0_gpio { |
||||
#ifdef CONFIG_S3C2400 |
||||
u32 PACON; |
||||
u32 PADAT; |
||||
|
||||
u32 PBCON; |
||||
u32 PBDAT; |
||||
u32 PBUP; |
||||
|
||||
u32 PCCON; |
||||
u32 PCDAT; |
||||
u32 PCUP; |
||||
|
||||
u32 PDCON; |
||||
u32 PDDAT; |
||||
u32 PDUP; |
||||
|
||||
u32 PECON; |
||||
u32 PEDAT; |
||||
u32 PEUP; |
||||
|
||||
u32 PFCON; |
||||
u32 PFDAT; |
||||
u32 PFUP; |
||||
|
||||
u32 PGCON; |
||||
u32 PGDAT; |
||||
u32 PGUP; |
||||
|
||||
u32 OPENCR; |
||||
|
||||
u32 MISCCR; |
||||
u32 EXTINT; |
||||
#endif |
||||
#ifdef CONFIG_S3C2410 |
||||
u32 GPACON; |
||||
u32 GPADAT; |
||||
u32 res1[2]; |
||||
u32 GPBCON; |
||||
u32 GPBDAT; |
||||
u32 GPBUP; |
||||
u32 res2; |
||||
u32 GPCCON; |
||||
u32 GPCDAT; |
||||
u32 GPCUP; |
||||
u32 res3; |
||||
u32 GPDCON; |
||||
u32 GPDDAT; |
||||
u32 GPDUP; |
||||
u32 res4; |
||||
u32 GPECON; |
||||
u32 GPEDAT; |
||||
u32 GPEUP; |
||||
u32 res5; |
||||
u32 GPFCON; |
||||
u32 GPFDAT; |
||||
u32 GPFUP; |
||||
u32 res6; |
||||
u32 GPGCON; |
||||
u32 GPGDAT; |
||||
u32 GPGUP; |
||||
u32 res7; |
||||
u32 GPHCON; |
||||
u32 GPHDAT; |
||||
u32 GPHUP; |
||||
u32 res8; |
||||
|
||||
u32 MISCCR; |
||||
u32 DCLKCON; |
||||
u32 EXTINT0; |
||||
u32 EXTINT1; |
||||
u32 EXTINT2; |
||||
u32 EINTFLT0; |
||||
u32 EINTFLT1; |
||||
u32 EINTFLT2; |
||||
u32 EINTFLT3; |
||||
u32 EINTMASK; |
||||
u32 EINTPEND; |
||||
u32 GSTATUS0; |
||||
u32 GSTATUS1; |
||||
u32 GSTATUS2; |
||||
u32 GSTATUS3; |
||||
u32 GSTATUS4; |
||||
#endif |
||||
}; |
||||
|
||||
|
||||
/* RTC (see manual chapter 17) */ |
||||
struct s3c24x0_rtc { |
||||
#ifdef __BIG_ENDIAN |
||||
u8 res1[67]; |
||||
u8 RTCCON; |
||||
u8 res2[3]; |
||||
u8 TICNT; |
||||
u8 res3[11]; |
||||
u8 RTCALM; |
||||
u8 res4[3]; |
||||
u8 ALMSEC; |
||||
u8 res5[3]; |
||||
u8 ALMMIN; |
||||
u8 res6[3]; |
||||
u8 ALMHOUR; |
||||
u8 res7[3]; |
||||
u8 ALMDATE; |
||||
u8 res8[3]; |
||||
u8 ALMMON; |
||||
u8 res9[3]; |
||||
u8 ALMYEAR; |
||||
u8 res10[3]; |
||||
u8 RTCRST; |
||||
u8 res11[3]; |
||||
u8 BCDSEC; |
||||
u8 res12[3]; |
||||
u8 BCDMIN; |
||||
u8 res13[3]; |
||||
u8 BCDHOUR; |
||||
u8 res14[3]; |
||||
u8 BCDDATE; |
||||
u8 res15[3]; |
||||
u8 BCDDAY; |
||||
u8 res16[3]; |
||||
u8 BCDMON; |
||||
u8 res17[3]; |
||||
u8 BCDYEAR; |
||||
#else /* little endian */ |
||||
u8 res0[64]; |
||||
u8 RTCCON; |
||||
u8 res1[3]; |
||||
u8 TICNT; |
||||
u8 res2[11]; |
||||
u8 RTCALM; |
||||
u8 res3[3]; |
||||
u8 ALMSEC; |
||||
u8 res4[3]; |
||||
u8 ALMMIN; |
||||
u8 res5[3]; |
||||
u8 ALMHOUR; |
||||
u8 res6[3]; |
||||
u8 ALMDATE; |
||||
u8 res7[3]; |
||||
u8 ALMMON; |
||||
u8 res8[3]; |
||||
u8 ALMYEAR; |
||||
u8 res9[3]; |
||||
u8 RTCRST; |
||||
u8 res10[3]; |
||||
u8 BCDSEC; |
||||
u8 res11[3]; |
||||
u8 BCDMIN; |
||||
u8 res12[3]; |
||||
u8 BCDHOUR; |
||||
u8 res13[3]; |
||||
u8 BCDDATE; |
||||
u8 res14[3]; |
||||
u8 BCDDAY; |
||||
u8 res15[3]; |
||||
u8 BCDMON; |
||||
u8 res16[3]; |
||||
u8 BCDYEAR; |
||||
u8 res17[3]; |
||||
#endif |
||||
}; |
||||
|
||||
|
||||
/* ADC (see manual chapter 16) */ |
||||
struct s3c2400_adc { |
||||
u32 ADCCON; |
||||
u32 ADCDAT; |
||||
}; |
||||
|
||||
|
||||
/* ADC (see manual chapter 16) */ |
||||
struct s3c2410_adc { |
||||
u32 ADCCON; |
||||
u32 ADCTSC; |
||||
u32 ADCDLY; |
||||
u32 ADCDAT0; |
||||
u32 ADCDAT1; |
||||
}; |
||||
|
||||
|
||||
/* SPI (see manual chapter 22) */ |
||||
struct s3c24x0_spi_channel { |
||||
u8 SPCON; |
||||
u8 res1[3]; |
||||
u8 SPSTA; |
||||
u8 res2[3]; |
||||
u8 SPPIN; |
||||
u8 res3[3]; |
||||
u8 SPPRE; |
||||
u8 res4[3]; |
||||
u8 SPTDAT; |
||||
u8 res5[3]; |
||||
u8 SPRDAT; |
||||
u8 res6[3]; |
||||
u8 res7[16]; |
||||
}; |
||||
|
||||
struct s3c24x0_spi { |
||||
struct s3c24x0_spi_channel ch[S3C24X0_SPI_CHANNELS]; |
||||
}; |
||||
|
||||
|
||||
/* MMC INTERFACE (see S3C2400 manual chapter 19) */ |
||||
struct s3c2400_mmc { |
||||
#ifdef __BIG_ENDIAN |
||||
u8 res1[3]; |
||||
u8 MMCON; |
||||
u8 res2[3]; |
||||
u8 MMCRR; |
||||
u8 res3[3]; |
||||
u8 MMFCON; |
||||
u8 res4[3]; |
||||
u8 MMSTA; |
||||
u16 res5; |
||||
u16 MMFSTA; |
||||
u8 res6[3]; |
||||
u8 MMPRE; |
||||
u16 res7; |
||||
u16 MMLEN; |
||||
u8 res8[3]; |
||||
u8 MMCR7; |
||||
u32 MMRSP[4]; |
||||
u8 res9[3]; |
||||
u8 MMCMD0; |
||||
u32 MMCMD1; |
||||
u16 res10; |
||||
u16 MMCR16; |
||||
u8 res11[3]; |
||||
u8 MMDAT; |
||||
#else |
||||
u8 MMCON; |
||||
u8 res1[3]; |
||||
u8 MMCRR; |
||||
u8 res2[3]; |
||||
u8 MMFCON; |
||||
u8 res3[3]; |
||||
u8 MMSTA; |
||||
u8 res4[3]; |
||||
u16 MMFSTA; |
||||
u16 res5; |
||||
u8 MMPRE; |
||||
u8 res6[3]; |
||||
u16 MMLEN; |
||||
u16 res7; |
||||
u8 MMCR7; |
||||
u8 res8[3]; |
||||
u32 MMRSP[4]; |
||||
u8 MMCMD0; |
||||
u8 res9[3]; |
||||
u32 MMCMD1; |
||||
u16 MMCR16; |
||||
u16 res10; |
||||
u8 MMDAT; |
||||
u8 res11[3]; |
||||
#endif |
||||
}; |
||||
|
||||
|
||||
/* SD INTERFACE (see S3C2410 manual chapter 19) */ |
||||
struct s3c2410_sdi { |
||||
u32 SDICON; |
||||
u32 SDIPRE; |
||||
u32 SDICARG; |
||||
u32 SDICCON; |
||||
u32 SDICSTA; |
||||
u32 SDIRSP0; |
||||
u32 SDIRSP1; |
||||
u32 SDIRSP2; |
||||
u32 SDIRSP3; |
||||
u32 SDIDTIMER; |
||||
u32 SDIBSIZE; |
||||
u32 SDIDCON; |
||||
u32 SDIDCNT; |
||||
u32 SDIDSTA; |
||||
u32 SDIFSTA; |
||||
#ifdef __BIG_ENDIAN |
||||
u8 res[3]; |
||||
u8 SDIDAT; |
||||
#else |
||||
u8 SDIDAT; |
||||
u8 res[3]; |
||||
#endif |
||||
u32 SDIIMSK; |
||||
}; |
||||
|
||||
#endif /*__S3C24X0_H__*/ |
||||
@ -0,0 +1,27 @@ |
||||
/*
|
||||
* (C) Copyright 2009 |
||||
* Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt@fearnside-systems.co.uk> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifdef CONFIG_S3C2400 |
||||
#include <asm/arch/s3c2400.h> |
||||
#elif defined CONFIG_S3C2410 |
||||
#include <asm/arch/s3c2410.h> |
||||
#else |
||||
#error Please define the s3c24x0 cpu type |
||||
#endif |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,222 @@ |
||||
/*
|
||||
* (C) Copyright 2009 Faraday Technology |
||||
* Po-Yu Chuang <ratbert@faraday-tech.com> |
||||
* |
||||
* Configuation settings for the Faraday A320 board. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#include <asm/arch/a320.h> |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* CPU and Board Configuration Options |
||||
*/ |
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
||||
|
||||
#undef CONFIG_SKIP_LOWLEVEL_INIT |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Timer |
||||
*/ |
||||
#define CONFIG_SYS_HZ 1000 /* timer ticks per second */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Real Time Clock |
||||
*/ |
||||
#define CONFIG_RTC_FTRTC010 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial console configuration |
||||
*/ |
||||
|
||||
/* FTUART is a high speed NS 16C550A compatible UART */ |
||||
#define CONFIG_BAUDRATE 38400 |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_COM1 0x98200000 |
||||
#define CONFIG_SYS_NS16550_REG_SIZE -4 |
||||
#define CONFIG_SYS_NS16550_CLK 18432000 |
||||
|
||||
/* valid baudrates */ |
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Ethernet |
||||
*/ |
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_FTMAC100 |
||||
|
||||
#define CONFIG_BOOTDELAY 3 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_CACHE |
||||
#define CONFIG_CMD_DATE |
||||
#define CONFIG_CMD_PING |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_PROMPT "A320 # " /* Monitor Command Prompt */ |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
|
||||
/* Print Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE \ |
||||
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
|
||||
/* max number of command args */ |
||||
#define CONFIG_SYS_MAXARGS 16 |
||||
|
||||
/* Boot Argument Buffer Size */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Stack sizes |
||||
* |
||||
* The stack sizes are set up in start.S using the settings below |
||||
*/ |
||||
#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ |
||||
#ifdef CONFIG_USE_IRQ |
||||
#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */ |
||||
#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* size in bytes reserved for initial data |
||||
*/ |
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SDRAM controller configuration |
||||
*/ |
||||
#define CONFIG_SYS_FTSDMC020_TP0 (FTSDMC020_TP0_TRAS(2) | \ |
||||
FTSDMC020_TP0_TRP(1) | \
|
||||
FTSDMC020_TP0_TRCD(1) | \
|
||||
FTSDMC020_TP0_TRF(3) | \
|
||||
FTSDMC020_TP0_TWR(1) | \
|
||||
FTSDMC020_TP0_TCL(2)) |
||||
|
||||
#define CONFIG_SYS_FTSDMC020_TP1 (FTSDMC020_TP1_INI_PREC(4) | \ |
||||
FTSDMC020_TP1_INI_REFT(8) | \
|
||||
FTSDMC020_TP1_REF_INTV(0x180)) |
||||
|
||||
#define CONFIG_SYS_FTSDMC020_BANK0_BSR (FTSDMC020_BANK_ENABLE | \ |
||||
FTSDMC020_BANK_DDW_X16 | \
|
||||
FTSDMC020_BANK_DSZ_256M | \
|
||||
FTSDMC020_BANK_MBW_32 | \
|
||||
FTSDMC020_BANK_SIZE_64M) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
||||
#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ |
||||
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ |
||||
|
||||
/*
|
||||
* Load address and memory test area should agree with |
||||
* board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself. |
||||
*/ |
||||
#define CONFIG_SYS_LOAD_ADDR 0x12000000 |
||||
|
||||
/* memtest works on 63 MB in DRAM */ |
||||
#define CONFIG_SYS_MEMTEST_START 0x10000000 |
||||
#define CONFIG_SYS_MEMTEST_END 0x13F00000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Static memory controller configuration |
||||
*/ |
||||
|
||||
#include <asm/arch/ftsmc020.h> |
||||
|
||||
#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ |
||||
FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
|
||||
FTSMC020_BANK_SIZE_1M | \
|
||||
FTSMC020_BANK_MBW_8) |
||||
|
||||
#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE | \ |
||||
FTSMC020_TPR_AST(3) | \
|
||||
FTSMC020_TPR_CTW(3) | \
|
||||
FTSMC020_TPR_ATI(0xf) | \
|
||||
FTSMC020_TPR_AT2(3) | \
|
||||
FTSMC020_TPR_WTC(3) | \
|
||||
FTSMC020_TPR_AHT(3) | \
|
||||
FTSMC020_TPR_TRNA(0xf)) |
||||
|
||||
#define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \ |
||||
FTSMC020_BANK_BASE(PHYS_FLASH_2) | \
|
||||
FTSMC020_BANK_SIZE_32M | \
|
||||
FTSMC020_BANK_MBW_32) |
||||
|
||||
#define FTSMC020_BANK1_TIMING (FTSMC020_TPR_AST(3) | \ |
||||
FTSMC020_TPR_CTW(3) | \
|
||||
FTSMC020_TPR_ATI(0xf) | \
|
||||
FTSMC020_TPR_AT2(3) | \
|
||||
FTSMC020_TPR_WTC(3) | \
|
||||
FTSMC020_TPR_AHT(3) | \
|
||||
FTSMC020_TPR_TRNA(0xf)) |
||||
|
||||
#define CONFIG_SYS_FTSMC020_CONFIGS { \ |
||||
{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
|
||||
{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
|
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization |
||||
*/ |
||||
|
||||
/* use CFI framework */ |
||||
#define CONFIG_SYS_FLASH_CFI |
||||
#define CONFIG_FLASH_CFI_DRIVER |
||||
|
||||
/* support JEDEC */ |
||||
#define CONFIG_FLASH_CFI_LEGACY |
||||
#define CONFIG_SYS_FLASH_LEGACY_512Kx8 |
||||
|
||||
#define PHYS_FLASH_1 0x00000000 |
||||
#define PHYS_FLASH_2 0x00400000 |
||||
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2, } |
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 |
||||
|
||||
/* max number of memory banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 |
||||
|
||||
/* max number of sectors on one chip */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 |
||||
|
||||
#undef CONFIG_SYS_FLASH_EMPTY_INFO |
||||
|
||||
/* environments */ |
||||
#define CONFIG_ENV_IS_IN_FLASH |
||||
#define CONFIG_ENV_ADDR 0x00060000 |
||||
#define CONFIG_ENV_SIZE 0x20000 |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -0,0 +1,243 @@ |
||||
/*
|
||||
* Copyright (C) 2008 Texas Instruments, Inc <www.ti.com> |
||||
* |
||||
* Based on davinci_dvevm.h. Original Copyrights follow: |
||||
* |
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* Board |
||||
*/ |
||||
|
||||
/*
|
||||
* SoC Configuration |
||||
*/ |
||||
#define CONFIG_MACH_DAVINCI_DA830_EVM |
||||
#define CONFIG_ARM926EJS /* arm926ejs CPU core */ |
||||
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ |
||||
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) |
||||
#define CONFIG_SYS_OSCIN_FREQ 24000000 |
||||
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE |
||||
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) |
||||
#define CONFIG_SYS_HZ 1000 |
||||
#define CONFIG_SKIP_LOWLEVEL_INIT |
||||
#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ |
||||
|
||||
/*
|
||||
* Memory Info |
||||
*/ |
||||
#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ |
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */ |
||||
#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ |
||||
#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ |
||||
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* memtest start addr */ |
||||
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 16*1024*1024) /* 16MB test */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
||||
#define CONFIG_STACKSIZE (256*1024) /* regular stack */ |
||||
|
||||
/*
|
||||
* Serial Driver info |
||||
*/ |
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ |
||||
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ |
||||
#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) |
||||
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ |
||||
#define CONFIG_BAUDRATE 115200 /* Default baud rate */ |
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*
|
||||
* I2C Configuration |
||||
*/ |
||||
#define CONFIG_HARD_I2C |
||||
#define CONFIG_DRIVER_DAVINCI_I2C |
||||
#define CONFIG_SYS_I2C_SPEED 25000 /* 100Kbps won't work, H/W bug */ |
||||
#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ |
||||
|
||||
/*
|
||||
* I2C EEPROM definitions for catalyst 24W256 EEPROM chip |
||||
*/ |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 |
||||
|
||||
/*
|
||||
* Network & Ethernet Configuration |
||||
*/ |
||||
#ifdef CONFIG_DRIVER_TI_EMAC |
||||
#define CONFIG_MII |
||||
#define CONFIG_BOOTP_DEFAULT |
||||
#define CONFIG_BOOTP_DNS |
||||
#define CONFIG_BOOTP_DNS2 |
||||
#define CONFIG_BOOTP_SEND_HOSTNAME |
||||
#define CONFIG_NET_RETRY_COUNT 10 |
||||
#define CONFIG_NET_MULTI |
||||
#endif |
||||
|
||||
/*
|
||||
* Flash & Environment |
||||
*/ |
||||
#ifdef CONFIG_USE_NAND |
||||
#undef CONFIG_ENV_IS_IN_FLASH |
||||
#define CONFIG_NAND_DAVINCI |
||||
#define CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ |
||||
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ |
||||
#define CONFIG_ENV_SIZE (128 << 10) |
||||
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST |
||||
#define CONFIG_SYS_NAND_CS 3 |
||||
#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE |
||||
#define CONFIG_SYS_CLE_MASK 0x10 |
||||
#define CONFIG_SYS_ALE_MASK 0x8 |
||||
#define CONFIG_SYS_NAND_HW_ECC |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ |
||||
#define NAND_MAX_CHIPS 1 |
||||
#define DEF_BOOTM "" |
||||
#endif |
||||
|
||||
#ifdef CONFIG_USE_NOR |
||||
#define CONFIG_ENV_IS_IN_FLASH |
||||
#undef CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_SYS_FLASH_CFI_DRIVER |
||||
#define CONFIG_SYS_FLASH_CFI |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ |
||||
#define CONFIG_SYS_FLASH_SECT_SZ (64 << 10) /* 64KB */ |
||||
#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ*3) |
||||
#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE |
||||
#define PHYS_FLASH_SIZE (32 << 20) /* Flash size 32MB */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) |
||||
#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ |
||||
#define CONFIG_SYS_FLASH_SPL_ACCESS |
||||
#endif |
||||
|
||||
#ifdef CONFIG_USE_SPIFLASH |
||||
#undef CONFIG_ENV_IS_IN_FLASH |
||||
#undef CONFIG_ENV_IS_IN_NAND |
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH |
||||
#define CONFIG_ENV_SIZE (16 << 10) |
||||
#define CONFIG_ENV_OFFSET (256 << 10) |
||||
#define CONFIG_ENV_SECT_SIZE 4096 |
||||
#define CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_SPI |
||||
#define CONFIG_SPI_FLASH |
||||
#define CONFIG_SPI_FLASH_WINBOND |
||||
#define CONFIG_DAVINCI_SPI |
||||
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI0_BASE |
||||
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID) |
||||
#define CONFIG_SF_DEFAULT_SPEED 50000000 |
||||
#define CONFIG_SYS_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* U-Boot general configuration |
||||
*/ |
||||
#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ |
||||
#undef CONFIG_MISC_INIT_R |
||||
#undef CONFIG_BOOTDELAY |
||||
#define CONFIG_BOOTFILE "uImage" /* Boot file name */ |
||||
#define CONFIG_SYS_PROMPT "DA830-evm > " /* Command Prompt */ |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ |
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_MEMTEST_START + 0x700000) |
||||
#define CONFIG_VERSION_VARIABLE |
||||
#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */ |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
#define CONFIG_CMDLINE_EDITING |
||||
#define CONFIG_SYS_LONGHELP |
||||
#define CONFIG_CRC32_VERIFY |
||||
#define CONFIG_MX_CYCLIC |
||||
|
||||
/*
|
||||
* Linux Information |
||||
*/ |
||||
#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100) |
||||
#define CONFIG_CMDLINE_TAG |
||||
#define CONFIG_SETUP_MEMORY_TAGS |
||||
#define CONFIG_BOOTARGS "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock/2 rw noinitrd ip=dhcp" |
||||
#define CONFIG_BOOTCOMMAND "" |
||||
#define CONFIG_BOOTDELAY 3 |
||||
|
||||
/*
|
||||
* U-Boot commands |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
#define CONFIG_CMD_ENV |
||||
#define CONFIG_CMD_ASKENV |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_DIAG |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_SAVES |
||||
#define CONFIG_CMD_MEMORY |
||||
#undef CONFIG_CMD_FPGA |
||||
#undef CONFIG_CMD_SETGETDCR |
||||
#define CONFIG_CMD_EEPROM |
||||
|
||||
#ifndef CONFIG_DRIVER_TI_EMAC |
||||
#undef CONFIG_CMD_NET |
||||
#undef CONFIG_CMD_DHCP |
||||
#undef CONFIG_CMD_MII |
||||
#undef CONFIG_CMD_PING |
||||
#endif |
||||
|
||||
#ifdef CONFIG_USE_NAND |
||||
#undef CONFIG_CMD_FLASH |
||||
#undef CONFIG_CMD_IMLS |
||||
#define CONFIG_CMD_NAND |
||||
#define CONFIG_CMD_MTDPARTS |
||||
#define CONFIG_MTD_PARTITIONS |
||||
#define CONFIG_CMD_UBI |
||||
#define CONFIG_RBTREE |
||||
#endif |
||||
|
||||
#ifdef CONFIG_USE_SPIFLASH |
||||
#undef CONFIG_CMD_IMLS |
||||
#undef CONFIG_CMD_FLASH |
||||
#define CONFIG_CMD_SPI |
||||
#define CONFIG_CMD_SAVEENV |
||||
#endif |
||||
|
||||
#if !defined(CONFIG_USE_NAND) && \ |
||||
!defined(CONFIG_USE_NOR) && \
|
||||
!defined(CONFIG_USE_SPIFLASH) |
||||
#define CONFIG_ENV_IS_NOWHERE |
||||
#define CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_ENV_SIZE (16 << 10) |
||||
#undef CONFIG_CMD_IMLS |
||||
#undef CONFIG_CMD_FLASH |
||||
#undef CONFIG_CMD_ENV |
||||
#endif |
||||
|
||||
#ifdef CONFIG_USB_DA8XX |
||||
#define CONFIG_CMD_USB /* include support for usb */ |
||||
#define CONFIG_CMD_STORAGE /* include support for usb */ |
||||
#define CONFIG_CMD_FAT /* include support for FAT/storage*/ |
||||
#define CONFIG_DOS_PARTITION /* include support for FAT/storage*/ |
||||
#endif |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
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