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@ -33,12 +33,21 @@ typedef void (*ExcpHndlr) (void) ; |
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/*
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* PXA Chip selects |
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*/ |
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#ifdef CONFIG_CPU_MONAHANS |
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#define PXA_CS0_PHYS 0x00000000 /* for both small and large same start */ |
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#define PXA_CS1_PHYS 0x04000000 /* Small partition start address (64MB) */ |
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#define PXA_CS1_LPHYS 0x30000000 /* Large partition start address (256MB) */ |
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#define PXA_CS2_PHYS 0x10000000 /* (64MB) */ |
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#define PXA_CS3_PHYS 0x14000000 /* (64MB) */ |
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#define PXA_PCMCIA_PHYS 0x20000000 /* (256MB) */ |
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#else |
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#define PXA_CS0_PHYS 0x00000000 |
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#define PXA_CS1_PHYS 0x04000000 |
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#define PXA_CS2_PHYS 0x08000000 |
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#define PXA_CS3_PHYS 0x0C000000 |
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#define PXA_CS4_PHYS 0x10000000 |
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#define PXA_CS5_PHYS 0x14000000 |
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#endif /* CONFIG_CPU_MONAHANS */ |
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/*
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* Personal Computer Memory Card International Association (PCMCIA) sockets |
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@ -49,10 +58,12 @@ typedef void (*ExcpHndlr) (void) ; |
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#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ |
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#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ |
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#ifndef CONFIG_CPU_MONAHANS /* Monahans supports only one slot */ |
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#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ |
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#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ |
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#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ |
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#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ |
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#endif |
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#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ |
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#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ |
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@ -72,10 +83,12 @@ typedef void (*ExcpHndlr) (void) ; |
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#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ |
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#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ |
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#ifndef CONFIG_CPU_MONAHANS /* Monahans supports only one slot */ |
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#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ |
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#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ |
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#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ |
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#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ |
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#endif |
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/*
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* DMA Controller |
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@ -96,6 +109,24 @@ typedef void (*ExcpHndlr) (void) ; |
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#define DCSR13 __REG(0x40000034) /* DMA Control / Status Register for Channel 13 */ |
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#define DCSR14 __REG(0x40000038) /* DMA Control / Status Register for Channel 14 */ |
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#define DCSR15 __REG(0x4000003c) /* DMA Control / Status Register for Channel 15 */ |
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#ifdef CONFIG_CPU_MONAHANS |
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#define DCSR16 __REG(0x40000040) /* DMA Control / Status Register for Channel 16 */ |
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#define DCSR17 __REG(0x40000044) /* DMA Control / Status Register for Channel 17 */ |
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#define DCSR18 __REG(0x40000048) /* DMA Control / Status Register for Channel 18 */ |
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#define DCSR19 __REG(0x4000004c) /* DMA Control / Status Register for Channel 19 */ |
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#define DCSR20 __REG(0x40000050) /* DMA Control / Status Register for Channel 20 */ |
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#define DCSR21 __REG(0x40000054) /* DMA Control / Status Register for Channel 21 */ |
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#define DCSR22 __REG(0x40000058) /* DMA Control / Status Register for Channel 22 */ |
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#define DCSR23 __REG(0x4000005c) /* DMA Control / Status Register for Channel 23 */ |
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#define DCSR24 __REG(0x40000060) /* DMA Control / Status Register for Channel 24 */ |
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#define DCSR25 __REG(0x40000064) /* DMA Control / Status Register for Channel 25 */ |
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#define DCSR26 __REG(0x40000068) /* DMA Control / Status Register for Channel 26 */ |
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#define DCSR27 __REG(0x4000006c) /* DMA Control / Status Register for Channel 27 */ |
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#define DCSR28 __REG(0x40000070) /* DMA Control / Status Register for Channel 28 */ |
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#define DCSR29 __REG(0x40000074) /* DMA Control / Status Register for Channel 29 */ |
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#define DCSR30 __REG(0x40000078) /* DMA Control / Status Register for Channel 30 */ |
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#define DCSR31 __REG(0x4000007c) /* DMA Control / Status Register for Channel 31 */ |
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#endif /* CONFIG_CPU_MONAHANS */ |
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#define DCSR(x) __REG2(0x40000000, (x) << 2) |
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@ -103,7 +134,7 @@ typedef void (*ExcpHndlr) (void) ; |
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#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ |
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#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ |
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#if defined(CONFIG_PXA27X) |
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#if defined(CONFIG_PXA27X) || defined (CONFIG_CPU_MONAHANS) |
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#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ |
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#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ |
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#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ |
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@ -813,15 +844,45 @@ typedef void (*ExcpHndlr) (void) ; |
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/*
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* OS Timer & Match Registers |
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*/ |
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#define OSMR0 __REG(0x40A00000) /* */ |
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#define OSMR1 __REG(0x40A00004) /* */ |
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#define OSMR2 __REG(0x40A00008) /* */ |
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#define OSMR3 __REG(0x40A0000C) /* */ |
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#define OSMR0 __REG(0x40A00000) /* OS Timer Match Register 0 */ |
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#define OSMR1 __REG(0x40A00004) /* OS Timer Match Register 1 */ |
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#define OSMR2 __REG(0x40A00008) /* OS Timer Match Register 2 */ |
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#define OSMR3 __REG(0x40A0000C) /* OS Timer Match Register 3 */ |
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#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */ |
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#define OSSR __REG(0x40A00014) /* OS Timer Status Register */ |
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#define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */ |
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#define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */ |
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#ifdef CONFIG_CPU_MONAHANS |
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#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register 4 */ |
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#define OSCR5 __REG(0x40A00044) /* OS Timer Counter Register 5 */ |
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#define OSCR6 __REG(0x40A00048) /* OS Timer Counter Register 6 */ |
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#define OSCR7 __REG(0x40A0004C) /* OS Timer Counter Register 7 */ |
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#define OSCR8 __REG(0x40A00050) /* OS Timer Counter Register 8 */ |
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#define OSCR9 __REG(0x40A00054) /* OS Timer Counter Register 9 */ |
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#define OSCR10 __REG(0x40A00058) /* OS Timer Counter Register 10 */ |
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#define OSCR11 __REG(0x40A0005C) /* OS Timer Counter Register 11 */ |
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#define OSMR4 __REG(0x40A00080) /* OS Timer Match Register 4 */ |
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#define OSMR5 __REG(0x40A00084) /* OS Timer Match Register 5 */ |
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#define OSMR6 __REG(0x40A00088) /* OS Timer Match Register 6 */ |
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#define OSMR7 __REG(0x40A0008C) /* OS Timer Match Register 7 */ |
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#define OSMR8 __REG(0x40A00090) /* OS Timer Match Register 8 */ |
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#define OSMR9 __REG(0x40A00094) /* OS Timer Match Register 9 */ |
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#define OSMR10 __REG(0x40A00098) /* OS Timer Match Register 10 */ |
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#define OSMR11 __REG(0x40A0009C) /* OS Timer Match Register 11 */ |
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#define OMCR4 __REG(0x40A000C0) /* OS Match Control Register 4 */ |
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#define OMCR5 __REG(0x40A000C4) /* OS Match Control Register 5 */ |
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#define OMCR6 __REG(0x40A000C8) /* OS Match Control Register 6 */ |
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#define OMCR7 __REG(0x40A000CC) /* OS Match Control Register 7 */ |
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#define OMCR8 __REG(0x40A000D0) /* OS Match Control Register 8 */ |
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#define OMCR9 __REG(0x40A000D4) /* OS Match Control Register 9 */ |
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#define OMCR10 __REG(0x40A000D8) /* OS Match Control Register 10 */ |
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#define OMCR11 __REG(0x40A000DC) /* OS Match Control Register 11 */ |
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#endif /* CONFIG_CPU_MONAHANS */ |
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#define OSSR_M4 (1 << 4) /* Match status channel 4 */ |
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#define OSSR_M3 (1 << 3) /* Match status channel 3 */ |
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#define OSSR_M2 (1 << 2) /* Match status channel 2 */ |
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#define OSSR_M1 (1 << 1) /* Match status channel 1 */ |
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@ -829,6 +890,7 @@ typedef void (*ExcpHndlr) (void) ; |
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#define OWER_WME (1 << 0) /* Watchdog Match Enable */ |
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#define OIER_E4 (1 << 4) /* Interrupt enable channel 4 */ |
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#define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */ |
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#define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */ |
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#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ |
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@ -855,6 +917,19 @@ typedef void (*ExcpHndlr) (void) ; |
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#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */ |
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#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */ |
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#ifdef CONFIG_CPU_MONAHANS |
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#define ICHP __REG(0x40D00018) /* Interrupt Controller Highest Priority Register */ |
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/* Missing: 32 Interrupt priority registers */ |
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/* mk@tbd: These are the same as beneath for PXA27x: maybe can be
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* merged if GPIO Stuff is same too. */ |
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#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ |
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#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ |
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#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ |
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#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ |
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#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ |
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/* Missing: 2 Interrupt priority registers */ |
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#endif /* CONFIG_CPU_MONAHANS */ |
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/*
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* General Purpose I/O |
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*/ |
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@ -1142,6 +1217,79 @@ typedef void (*ExcpHndlr) (void) ; |
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/*
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* Power Manager |
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*/ |
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#ifdef CONFIG_CPU_MONAHANS |
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#define ASCR __REG(0x40F40000) /* Application Subsystem Power Status/Control Register */ |
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#define ARSR __REG(0x40F40004) /* Application Subsystem Reset Status Register */ |
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#define AD3ER __REG(0x40F40008) /* Application Subsystem D3 state Wakeup Enable Register */ |
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#define AD3SR __REG(0x40F4000C) /* Application Subsystem D3 state Wakeup Status Register */ |
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#define AD2D0ER __REG(0x40F40010) /* Application Subsystem D2 to D0 state Wakeup Enable Register */ |
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#define AD2D0SR __REG(0x40F40014) /* Application Subsystem D2 to D0 state Wakeup Status Register */ |
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#define AD2D1ER __REG(0x40F40018) /* Application Subsystem D2 to D1 state Wakeup Enable Register */ |
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#define AD2D1SR __REG(0x40F4001C) /* Application Subsystem D2 to D1 state Wakeup Status Register */ |
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#define AD1D0ER __REG(0x40F40020) /* Application Subsystem D1 to D0 state Wakeup Enable Register */ |
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#define AD1D0SR __REG(0x40F40024) /* Application Subsystem D1 to D0 state Wakeup Status Register */ |
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#define ASDCNT __REG(0x40F40028) /* Application Subsystem SRAM Drowsy Count Register */ |
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#define AD3R __REG(0x40F40030) /* Application Subsystem D3 State Configuration Register */ |
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#define AD2R __REG(0x40F40034) /* Application Subsystem D2 State Configuration Register */ |
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#define AD1R __REG(0x40F40038) /* Application Subsystem D1 State Configuration Register */ |
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#define PMCR __REG(0x40F50000) /* Power Manager Control Register */ |
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#define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */ |
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#define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */ |
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#define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */ |
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#define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */ |
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#define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */ |
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#define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */ |
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#define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */ |
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#define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */ |
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#define PCMD(x) __REG(0x40F50110 + x*4) |
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#define PCMD0 __REG(0x40F50110 + 0 * 4) |
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#define PCMD1 __REG(0x40F50110 + 1 * 4) |
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#define PCMD2 __REG(0x40F50110 + 2 * 4) |
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#define PCMD3 __REG(0x40F50110 + 3 * 4) |
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#define PCMD4 __REG(0x40F50110 + 4 * 4) |
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#define PCMD5 __REG(0x40F50110 + 5 * 4) |
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#define PCMD6 __REG(0x40F50110 + 6 * 4) |
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#define PCMD7 __REG(0x40F50110 + 7 * 4) |
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#define PCMD8 __REG(0x40F50110 + 8 * 4) |
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#define PCMD9 __REG(0x40F50110 + 9 * 4) |
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#define PCMD10 __REG(0x40F50110 + 10 * 4) |
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#define PCMD11 __REG(0x40F50110 + 11 * 4) |
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#define PCMD12 __REG(0x40F50110 + 12 * 4) |
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#define PCMD13 __REG(0x40F50110 + 13 * 4) |
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#define PCMD14 __REG(0x40F50110 + 14 * 4) |
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#define PCMD15 __REG(0x40F50110 + 15 * 4) |
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#define PCMD16 __REG(0x40F50110 + 16 * 4) |
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#define PCMD17 __REG(0x40F50110 + 17 * 4) |
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#define PCMD18 __REG(0x40F50110 + 18 * 4) |
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#define PCMD19 __REG(0x40F50110 + 19 * 4) |
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#define PCMD20 __REG(0x40F50110 + 20 * 4) |
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#define PCMD21 __REG(0x40F50110 + 21 * 4) |
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#define PCMD22 __REG(0x40F50110 + 22 * 4) |
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#define PCMD23 __REG(0x40F50110 + 23 * 4) |
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#define PCMD24 __REG(0x40F50110 + 24 * 4) |
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#define PCMD25 __REG(0x40F50110 + 25 * 4) |
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#define PCMD26 __REG(0x40F50110 + 26 * 4) |
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#define PCMD27 __REG(0x40F50110 + 27 * 4) |
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#define PCMD28 __REG(0x40F50110 + 28 * 4) |
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#define PCMD29 __REG(0x40F50110 + 29 * 4) |
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#define PCMD30 __REG(0x40F50110 + 30 * 4) |
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#define PCMD31 __REG(0x40F50110 + 31 * 4) |
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#define PCMD_MBC (1<<12) |
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#define PCMD_DCE (1<<11) |
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#define PCMD_LC (1<<10) |
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#define PCMD_SQC (3<<8) /* only 00 and 01 are valid */ |
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#define PVCR_FVC (0x1 << 28) |
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#define PVCR_VCSA (0x1<<14) |
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#define PVCR_CommandDelay (0xf80) |
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#define PVCR_ReadPointer (0x01f00000) |
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#define PVCR_SlaveAddress (0x7f) |
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#else /* ifdef CONFIG_CPU_MONAHANS */ |
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#define PMCR __REG(0x40F00000) /* Power Manager Control Register */ |
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#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */ |
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#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */ |
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@ -1225,6 +1373,8 @@ typedef void (*ExcpHndlr) (void) ; |
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#define RCSR_WDR (1 << 1) /* Watchdog Reset */ |
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#define RCSR_HWR (1 << 0) /* Hardware Reset */ |
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#endif /* CONFIG_CPU_MONAHANS */ |
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/*
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* SSP Serial Port Registers |
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*/ |
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@ -1259,6 +1409,67 @@ typedef void (*ExcpHndlr) (void) ; |
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/*
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* Core Clock |
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*/ |
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#if defined(CONFIG_CPU_MONAHANS) |
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#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */ |
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#define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */ |
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#define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */ |
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#define CKENA __REG(0x4134000C) /* A Clock Enable Register */ |
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#define CKENB __REG(0x41340010) /* B Clock Enable Register */ |
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#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ |
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#define ACCR_SMC_MASK 0x03800000 /* Static Memory Controller Frequency Select */ |
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#define ACCR_SRAM_MASK 0x000c0000 /* SRAM Controller Frequency Select */ |
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#define ACCR_FC_MASK 0x00030000 /* Frequency Change Frequency Select */ |
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#define ACCR_HSIO_MASK 0x0000c000 /* High Speed IO Frequency Select */ |
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#define ACCR_DDR_MASK 0x00003000 /* DDR Memory Controller Frequency Select */ |
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#define ACCR_XN_MASK 0x00000700 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ |
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#define ACCR_XL_MASK 0x0000001f /* Crystal Frequency to Memory Frequency Multiplier */ |
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#define ACCR_XPDIS (1 << 31) |
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#define ACCR_SPDIS (1 << 30) |
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#define ACCR_13MEND1 (1 << 27) |
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#define ACCR_D0CS (1 << 26) |
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#define ACCR_13MEND2 (1 << 21) |
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#define ACCR_PCCE (1 << 11) |
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#define CKENA_30_MSL0 (1 << 30) /* MSL0 Interface Unit Clock Enable */ |
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#define CKENA_29_SSP4 (1 << 29) /* SSP3 Unit Clock Enable */ |
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#define CKENA_28_SSP3 (1 << 28) /* SSP2 Unit Clock Enable */ |
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#define CKENA_27_SSP2 (1 << 27) /* SSP1 Unit Clock Enable */ |
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#define CKENA_26_SSP1 (1 << 26) /* SSP0 Unit Clock Enable */ |
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#define CKENA_25_TSI (1 << 25) /* TSI Clock Enable */ |
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#define CKENA_24_AC97 (1 << 24) /* AC97 Unit Clock Enable */ |
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#define CKENA_23_STUART (1 << 23) /* STUART Unit Clock Enable */ |
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#define CKENA_22_FFUART (1 << 22) /* FFUART Unit Clock Enable */ |
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#define CKENA_21_BTUART (1 << 21) /* BTUART Unit Clock Enable */ |
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#define CKENA_20_UDC (1 << 20) /* UDC Clock Enable */ |
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#define CKENA_19_TPM (1 << 19) /* TPM Unit Clock Enable */ |
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#define CKENA_18_USIM1 (1 << 18) /* USIM1 Unit Clock Enable */ |
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#define CKENA_17_USIM0 (1 << 17) /* USIM0 Unit Clock Enable */ |
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#define CKENA_15_CIR (1 << 15) /* Consumer IR Clock Enable */ |
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#define CKENA_14_KEY (1 << 14) /* Keypad Controller Clock Enable */ |
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#define CKENA_13_MMC1 (1 << 13) /* MMC1 Clock Enable */ |
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#define CKENA_12_MMC0 (1 << 12) /* MMC0 Clock Enable */ |
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#define CKENA_11_FLASH (1 << 11) /* Boot ROM Clock Enable */ |
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#define CKENA_10_SRAM (1 << 10) /* SRAM Controller Clock Enable */ |
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#define CKENA_9_SMC (1 << 9) /* Static Memory Controller */ |
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#define CKENA_8_DMC (1 << 8) /* Dynamic Memory Controller */ |
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#define CKENA_7_GRAPHICS (1 << 7) /* 2D Graphics Clock Enable */ |
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#define CKENA_6_USBCLI (1 << 6) /* USB Client Unit Clock Enable */ |
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#define CKENA_4_NAND (1 << 4) /* NAND Flash Controller Clock Enable */ |
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#define CKENA_3_CAMERA (1 << 3) /* Camera Interface Clock Enable */ |
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#define CKENA_2_USBHOST (1 << 2) /* USB Host Unit Clock Enable */ |
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#define CKENA_1_LCD (1 << 1) /* LCD Unit Clock Enable */ |
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#define CKENB_8_1WIRE ((1 << 8) + 32) /* One Wire Interface Unit Clock Enable */ |
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#define CKENB_7_GPIO ((1 << 7) + 32) /* GPIO Clock Enable */ |
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#define CKENB_6_IRQ ((1 << 6) + 32) /* Interrupt Controller Clock Enable */ |
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#define CKENB_4_I2C ((1 << 4) + 32) /* I2C Unit Clock Enable */ |
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#define CKENB_1_PWM1 ((1 << 1) + 32) /* PWM2 & PWM3 Clock Enable */ |
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#define CKENB_0_PWM0 ((1 << 0) + 32) /* PWM0 & PWM1 Clock Enable */ |
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#else /* if defined CONFIG_CPU_MONAHANS */ |
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#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */ |
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#define CKEN __REG(0x41300004) /* Clock Enable Register */ |
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#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */ |
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@ -1318,6 +1529,8 @@ typedef void (*ExcpHndlr) (void) ; |
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#define CCCR_N30 (0x6 << 7) |
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#endif |
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#endif /* CONFIG_CPU_MONAHANS */ |
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/*
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* LCD |
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*/ |
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@ -1502,6 +1715,111 @@ typedef void (*ExcpHndlr) (void) ; |
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/*
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* Memory controller |
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*/ |
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#ifdef CONFIG_CPU_MONAHANS |
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/* Static Memory Controller Registers */ |
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#define MSC0 __REG_2(0x4A000008) /* Static Memory Control Register 0 */ |
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#define MSC1 __REG_2(0x4A00000C) /* Static Memory Control Register 1 */ |
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#define MECR __REG_2(0x4A000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ |
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#define SXCNFG __REG_2(0x4A00001C) /* Synchronous Static Memory Control Register */ |
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#define MCMEM0 __REG_2(0x4A000028) /* Card interface Common Memory Space Socket 0 Timing */ |
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#define MCATT0 __REG_2(0x4A000030) /* Card interface Attribute Space Socket 0 Timing Configuration */ |
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#define MCIO0 __REG_2(0x4A000038) /* Card interface I/O Space Socket 0 Timing Configuration */ |
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#define MEMCLKCFG __REG_2(0x4A000068) /* SCLK speed configuration */ |
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#define CSADRCFG0 __REG_2(0x4A000080) /* Address Configuration for chip select 0 */ |
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#define CSADRCFG1 __REG_2(0x4A000084) /* Address Configuration for chip select 1 */ |
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#define CSADRCFG2 __REG_2(0x4A000088) /* Address Configuration for chip select 2 */ |
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#define CSADRCFG3 __REG_2(0x4A00008C) /* Address Configuration for chip select 3 */ |
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#define CSADRCFG_P __REG_2(0x4A000090) /* Address Configuration for pcmcia card interface */ |
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#define CSMSADRCFG __REG_2(0x4A0000A0) /* Master Address Configuration Register */ |
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#define CLK_RET_DEL __REG_2(0x4A0000B0) /* Delay line and mux selects for return data latching for sync. flash */ |
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#define ADV_RET_DEL __REG_2(0x4A0000B4) /* Delay line and mux selects for return data latching for sync. flash */ |
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/* Dynamic Memory Controller Registers */ |
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#define MDCNFG __REG_2(0x48100000) /* SDRAM Configuration Register 0 */ |
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#define MDREFR __REG_2(0x48100004) /* SDRAM Refresh Control Register */ |
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#define FLYCNFG __REG_2(0x48100020) /* Fly-by DMA DVAL[1:0] polarities */ |
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#define MDMRS __REG_2(0x48100040) /* MRS value to be written to SDRAM */ |
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#define DDR_SCAL __REG_2(0x48100050) /* Software Delay Line Calibration/Configuration for external DDR memory. */ |
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#define DDR_HCAL __REG_2(0x48100060) /* Hardware Delay Line Calibration/Configuration for external DDR memory. */ |
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#define DDR_WCAL __REG_2(0x48100068) /* DDR Write Strobe Calibration Register */ |
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#define DMCIER __REG_2(0x48100070) /* Dynamic MC Interrupt Enable Register. */ |
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#define DMCISR __REG_2(0x48100078) /* Dynamic MC Interrupt Status Register. */ |
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#define DDR_DLS __REG_2(0x48100080) /* DDR Delay Line Value Status register for external DDR memory. */ |
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#define EMPI __REG_2(0x48100090) /* EMPI Control Register */ |
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#define RCOMP __REG_2(0x48100100) |
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#define PAD_MA __REG_2(0x48100110) |
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#define PAD_MDMSB __REG_2(0x48100114) |
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#define PAD_MDLSB __REG_2(0x48100118) |
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#define PAD_DMEM __REG_2(0x4810011c) |
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#define PAD_SDCLK __REG_2(0x48100120) |
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#define PAD_SDCS __REG_2(0x48100124) |
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#define PAD_SMEM __REG_2(0x48100128) |
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#define PAD_SCLK __REG_2(0x4810012C) |
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#define TAI __REG_2(0x48100F00) /* TAI Tavor Address Isolation Register */ |
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/* Data Flash Controller Registers */ |
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#define NDCR __REG_2(0x43100000) /* Data Flash Control register */ |
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#define NDTR0CS0 __REG_2(0x43100004) /* Data Controller Timing Parameter 0 Register for ND_nCS0 */ |
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#define NDTR0CS1 __REG_2(0x43100008) /* Data Controller Timing Parameter 0 Register for ND_nCS1 */ |
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#define NDTR1CS0 __REG_2(0x4310000C) /* Data Controller Timing Parameter 1 Register for ND_nCS0 */ |
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#define NDTR1CS1 __REG_2(0x43100010) /* Data Controller Timing Parameter 1 Register for ND_nCS1 */ |
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#define NDSR __REG_2(0x43100014) /* Data Controller Status Register */ |
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#define NDPCR __REG_2(0x43100018) /* Data Controller Page Count Register */ |
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#define NDBDR0 __REG_2(0x4310001C) /* Data Controller Bad Block Register 0 */ |
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#define NDBDR1 __REG_2(0x43100020) /* Data Controller Bad Block Register 1 */ |
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#define NDDB __REG_2(0x43100040) /* Data Controller Data Buffer */ |
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#define NDCB0 __REG_2(0x43100048) /* Data Controller Command Buffer0 */ |
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#define NDCB1 __REG_2(0x4310004C) /* Data Controller Command Buffer1 */ |
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#define NDCB2 __REG_2(0x43100050) /* Data Controller Command Buffer2 */ |
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#define NDCR_SPARE_EN (0x1<<31) |
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#define NDCR_ECC_EN (0x1<<30) |
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#define NDCR_DMA_EN (0x1<<29) |
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#define NDCR_ND_RUN (0x1<<28) |
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#define NDCR_DWIDTH_C (0x1<<27) |
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#define NDCR_DWIDTH_M (0x1<<26) |
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#define NDCR_PAGE_SZ (0x3<<24) |
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#define NDCR_NCSX (0x1<<23) |
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#define NDCR_ND_MODE (0x3<<21) |
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#define NDCR_NAND_MODE 0x0 |
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#define NDCR_CLR_PG_CNT (0x1<<20) |
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#define NDCR_CLR_ECC (0x1<<19) |
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#define NDCR_RD_ID_CNT (0x7<<16) |
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#define NDCR_RA_START (0x1<<15) |
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#define NDCR_PG_PER_BLK (0x1<<14) |
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#define NDCR_ND_ARB_EN (0x1<<12) |
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#define NDSR_RDY (0x1<<11) |
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#define NDSR_CS0_PAGED (0x1<<10) |
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#define NDSR_CS1_PAGED (0x1<<9) |
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#define NDSR_CS0_CMDD (0x1<<8) |
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#define NDSR_CS1_CMDD (0x1<<7) |
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#define NDSR_CS0_BBD (0x1<<6) |
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#define NDSR_CS1_BBD (0x1<<5) |
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#define NDSR_BDERR (0x1<<4) |
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#define NDSR_SBERR (0x1<<3) |
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#define NDSR_WRDREQ (0x1<<2) |
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#define NDSR_RDDREQ (0x1<<1) |
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#define NDSR_WRCMDREQ (0x1) |
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#define NDCB0_AUTO_RS (0x1<<25) |
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#define NDCB0_CSEL (0x1<<24) |
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#define NDCB0_CMD_TYPE (0x7<<21) |
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#define NDCB0_NC (0x1<<20) |
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#define NDCB0_DBC (0x1<<19) |
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#define NDCB0_ADDR_CYC (0x7<<16) |
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#define NDCB0_CMD2 (0xff<<8) |
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#define NDCB0_CMD1 (0xff) |
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#define MCMEM(s) MCMEM0 |
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#define MCATT(s) MCATT0 |
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#define MCIO(s) MCIO0 |
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#define MECR_CIT (1 << 1)/* Card Is There: 0 -> no card, 1 -> card inserted */ |
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#else /* CONFIG_CPU_MONAHANS */ |
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#define MEMC_BASE __REG(0x48000000) /* Base of Memory Controller */ |
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#define MDCNFG_OFFSET 0x0 |
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#define MDREFR_OFFSET 0x4 |
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@ -1573,6 +1891,8 @@ typedef void (*ExcpHndlr) (void) ; |
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#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ |
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#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ |
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#endif /* CONFIG_CPU_MONAHANS */ |
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/* Interrupt Controller */ |
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#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ |
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Markus Klotzbcher
19 years ago
committed by
Markus Klotzbcher