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@ -1069,10 +1069,22 @@ int update_flash_size (int flash_size) |
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static u8 hwctl = 0; |
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static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
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static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte) |
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{ |
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struct nand_chip *this = mtd->priv; |
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struct nand_chip *this = mtdinfo->priv; |
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ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); |
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if (hwctl & 0x1) { |
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WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS); |
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} else if (hwctl & 0x2) { |
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WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS); |
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} else { |
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WRITE_NAND(byte, base); |
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} |
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} |
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static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
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{ |
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if (ctrl & NAND_CTRL_CHANGE) { |
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if ( ctrl & NAND_CLE ) |
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hwctl |= 0x1; |
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@ -1084,21 +1096,7 @@ static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
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hwctl &= ~0x2; |
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} |
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if (cmd != NAND_CMD_NONE) |
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writeb(cmd, this->IO_ADDR_W); |
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} |
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static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte) |
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{ |
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struct nand_chip *this = mtdinfo->priv; |
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ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); |
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if (hwctl & 0x1) { |
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WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS); |
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} else if (hwctl & 0x2) { |
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WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS); |
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} else { |
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WRITE_NAND(byte, base); |
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} |
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upmnand_write_byte (mtd, cmd); |
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} |
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static u_char upmnand_read_byte(struct mtd_info *mtdinfo) |
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@ -1191,7 +1189,6 @@ int board_nand_init(struct nand_chip *nand) |
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nand->cmd_ctrl = upmnand_hwcontrol; |
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nand->read_byte = upmnand_read_byte; |
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nand->write_byte = upmnand_write_byte; |
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nand->dev_ready = tqm8272_dev_ready; |
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#ifndef CONFIG_NAND_SPL |
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