@ -56,60 +56,53 @@ struct fsl_e_tlb_entry tlb_table[] = {
0 , 0 , BOOKE_PAGESZ_64M , 1 ) ,
/*
* TLB 1 : 256 M Non - cacheable , guarded
* 0x80000000 256 M PCI1 MEM First half
* TLB 1 : 1 G Non - cacheable , guarded
* 0x80000000 512 M PCI1 MEM
* 0xa0000000 512 M PCIe MEM
*/
SET_TLB_ENTRY ( 1 , CONFIG_SYS_PCI1_MEM_PHYS , CONFIG_SYS_PCI1_MEM_PHYS ,
SET_TLB_ENTRY ( 1 , CONFIG_SYS_PCI1_MEM_VIRT , CONFIG_SYS_PCI1_MEM_PHYS ,
MAS3_SX | MAS3_SW | MAS3_SR , MAS2_I | MAS2_G ,
0 , 1 , BOOKE_PAGESZ_256M , 1 ) ,
0 , 1 , BOOKE_PAGESZ_1G , 1 ) ,
/*
* TLB 2 : 256 M Non - cacheable , guarded
* 0x90000000 256 M PCI1 MEM Second half
*/
SET_TLB_ENTRY ( 1 , CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000 ,
CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000 ,
MAS3_SX | MAS3_SW | MAS3_SR , MAS2_I | MAS2_G ,
0 , 2 , BOOKE_PAGESZ_256M , 1 ) ,
/*
* TLB 3 : 256 M Cacheable , non - guarded
* TLB 2 : 256 M Cacheable , non - guarded
* 0x0 256 M DDR SDRAM
*/
# if !defined(CONFIG_SPD_EEPROM)
# if !defined(CONFIG_SPD_EEPROM)
SET_TLB_ENTRY ( 1 , CONFIG_SYS_DDR_SDRAM_BASE , CONFIG_SYS_DDR_SDRAM_BASE ,
MAS3_SX | MAS3_SW | MAS3_SR , 0 ,
0 , 3 , BOOKE_PAGESZ_256M , 1 ) ,
# endif
0 , 2 , BOOKE_PAGESZ_256M , 1 ) ,
# endif
/*
* TLB 4 : 64 M Non - cacheable , guarded
* TLB 3 : 64 M Non - cacheable , guarded
* 0xe0000000 1 M CCSRBAR
* 0xe2000000 16 M PCI1 IO
* 0xe2000000 8 M PCI1 IO
* 0xe2800000 8 M PCIe IO
*/
SET_TLB_ENTRY ( 1 , CONFIG_SYS_CCSRBAR , CONFIG_SYS_CCSRBAR_PHYS ,
MAS3_SX | MAS3_SW | MAS3_SR , MAS2_I | MAS2_G ,
0 , 4 , BOOKE_PAGESZ_64M , 1 ) ,
0 , 3 , BOOKE_PAGESZ_64M , 1 ) ,
/*
* TLB 5 : 64 M Cacheable , non - guarded
* TLB 4 : 64 M Cacheable , non - guarded
* 0xf0000000 64 M LBC SDRAM First half
*/
SET_TLB_ENTRY ( 1 , CONFIG_SYS_LBC_SDRAM_BASE , CONFIG_SYS_LBC_SDRAM_BASE ,
MAS3_SX | MAS3_SW | MAS3_SR , 0 ,
0 , 5 , BOOKE_PAGESZ_64M , 1 ) ,
0 , 4 , BOOKE_PAGESZ_64M , 1 ) ,
/*
* TLB 6 : 64 M Cacheable , non - guarded
* TLB 5 : 64 M Cacheable , non - guarded
* 0xf4000000 64 M LBC SDRAM Second half
*/
SET_TLB_ENTRY ( 1 , CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000 ,
CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000 ,
MAS3_SX | MAS3_SW | MAS3_SR , 0 ,
0 , 6 , BOOKE_PAGESZ_64M , 1 ) ,
0 , 5 , BOOKE_PAGESZ_64M , 1 ) ,
/*
* TLB 7 : 16 M Cacheable , non - guarded
* TLB 6 : 16 M Cacheable , non - guarded
* 0xf8000000 1 M 7 - segment LED display
* 0xf8100000 1 M User switches
* 0xf8300000 1 M Board revision
@ -117,24 +110,24 @@ struct fsl_e_tlb_entry tlb_table[] = {
*/
SET_TLB_ENTRY ( 1 , CONFIG_SYS_EPLD_BASE , CONFIG_SYS_EPLD_BASE ,
MAS3_SX | MAS3_SW | MAS3_SR , MAS2_I | MAS2_G ,
0 , 7 , BOOKE_PAGESZ_16M , 1 ) ,
0 , 6 , BOOKE_PAGESZ_16M , 1 ) ,
/*
* TLB 8 : 4 M Non - cacheable , guarded
* TLB 7 : 4 M Non - cacheable , guarded
* 0xfb800000 4 M 1 st 4 MB block of 64 MB user FLASH
*/
SET_TLB_ENTRY ( 1 , CONFIG_SYS_ALT_FLASH , CONFIG_SYS_ALT_FLASH ,
MAS3_SX | MAS3_SW | MAS3_SR , MAS2_I | MAS2_G ,
0 , 8 , BOOKE_PAGESZ_4M , 1 ) ,
0 , 7 , BOOKE_PAGESZ_4M , 1 ) ,
/*
* TLB 9 : 4 M Non - cacheable , guarded
* TLB 8 : 4 M Non - cacheable , guarded
* 0xfbc00000 4 M 2 nd 4 MB block of 64 MB user FLASH
*/
SET_TLB_ENTRY ( 1 , CONFIG_SYS_ALT_FLASH + 0x400000 ,
CONFIG_SYS_ALT_FLASH + 0x400000 ,
MAS3_SX | MAS3_SW | MAS3_SR , MAS2_I | MAS2_G ,
0 , 9 , BOOKE_PAGESZ_4M , 1 ) ,
0 , 8 , BOOKE_PAGESZ_4M , 1 ) ,
} ;