clk: zynq: Show watchdog clock rate properly

watchdog clock is also connected to cpu 1X clocksource.

Zynq> clk dump
...

Before:
      swdt          4294967290
After:
      swdt           111111110

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

drivers/clk/clk_zynq.c

@@ -394,7 +394,7 @@ static ulong zynq_clk_get_rate(struct clk *clk)
 		return zynq_clk_get_peripheral_rate(priv, id, two_divs);
 	case dma_clk:
 		return zynq_clk_get_cpu_rate(priv, cpu_2x_clk);
-	case usb0_aper_clk ... smc_aper_clk:
+	case usb0_aper_clk ... swdt_clk:
 		return zynq_clk_get_cpu_rate(priv, cpu_1x_clk);
 	default:
 		return -ENXIO;