Gateworks Ventana is a product family based on the i.MX6. This patch adds support for all boards in the Ventana family. Where possible, data from the boards EEPROM is used to determine various details about the board at runtime. Signed-off-by: Tim Harvey <tharvey@gateworks.com>master
Tim Harvey
10 years ago
committed by
Stefano Babic
parent
1ad6364eeb
commit
59189a8b26
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#
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# Copyright (C) 2012-2013, Guennadi Liakhovetski <lg@denx.de>
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# (C) Copyright 2012-2013 Freescale Semiconductor, Inc.
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# Copyright (C) 2013, Gateworks Corporation
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := gw_ventana.o gsc.o
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U-Boot for the Gateworks Ventana Product Family boards |
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This file contains information for the port of U-Boot to the Gateworks |
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Ventana Product family boards. |
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1. Boot source, boot from NAND |
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------------------------------ |
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The i.MX6 BOOT ROM expects some structures that provide details of NAND layout |
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and bad block information (referred to as 'bootstreams') which are replicated |
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multiple times in NAND. The number of replications is configurable through |
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board strapping options and eFUSE settings. The Freescale 'kobs-ng' |
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application from the Freescale LTIB BSP, which runs under Linux, must be used |
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to program the bootstream in order to setup the replicated headers correctly. |
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The Gateworks Ventana boards with NAND flash have been factory programmed |
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such that their eFUSE settings expect 2 copies of the boostream (this is |
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specified by providing kobs-ng with the --search_exponent=1 argument). Once in |
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Linux with MTD support for the NAND on /dev/mtd0 you can program the boostream |
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with: |
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kobs-ng init -v -x --search_exponent=1 u-boot.imx |
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The kobs-ng application uses an imximage (u-boot.imx) which contains the |
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Image Vector Table (IVT) and Device Configuration Data (DCD) structures that |
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the i.MX6 BOOT ROM requires to boot. The kobs-ng adds the Firmware |
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Configuration Block (FCB) and Discovered Bad Block Table (DBBT). |
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This information is taken from: |
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http://trac.gateworks.com/wiki/ventana/bootloader#NANDFLASH |
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More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manual. |
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2. Build |
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-------- |
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There are several Gateworks Ventana boards that share a simliar design but |
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vary based on CPU, Memory configuration, and subloaded devices. Although |
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the subloaded devices are handled dynamically in the bootloader using |
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factory configured EEPROM data to modify the device-tree, the CPU choice |
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(IMX6Q vs IMX6DL) and memory configurations are currently compile-time |
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options. |
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The following Gateworks Ventana configurations exist: |
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gwventanaq1gspi: MX6Q,1GB,SPI FLASH |
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gwventanaq : MX6Q,512MB,NAND FLASH |
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gwventanaq1g : MX6Q,1GB,NAND FLASH |
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gwventanadl : MX6DL,512MB,NAND FLASH |
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gwventanadl1g : MX6DL,1GB,NAND FLASH |
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To build U-Boot for the MX6Q,1GB,NAND FLASH for example: |
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make gwventanaq1g_config |
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make |
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@ -0,0 +1,42 @@ |
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/* |
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* Copyright (C) 2013 Boundary Devices |
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* Copyright (C) 2013 Gateworks Corporation |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* Device Configuration Data (DCD) |
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* |
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* Each entry must have the format: |
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* Addr-type Address Value |
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* |
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* where: |
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* Addr-type register length (1,2 or 4 bytes) |
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* Address absolute address of the register |
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* value value to be stored in the register |
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*/ |
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/* set the default clock gate to save power */ |
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DATA 4, CCM_CCGR0, 0x00C03F3F |
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DATA 4, CCM_CCGR1, 0x0030FC03 |
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DATA 4, CCM_CCGR2, 0x0FFFC000 |
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DATA 4, CCM_CCGR3, 0x3FF00000 |
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DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */ |
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DATA 4, CCM_CCGR5, 0x0F0000C3 |
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DATA 4, CCM_CCGR6, 0x000003FF |
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/* enable AXI cache for VDOA/VPU/IPU */ |
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DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF |
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/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ |
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DATA 4, MX6_IOMUXC_GPR6, 0x007F007F |
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DATA 4, MX6_IOMUXC_GPR7, 0x007F007F |
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/* |
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* Setup CCM_CCOSR register as follows: |
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* |
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* cko1_en = 1 --> CKO1 enabled |
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* cko1_div = 111 --> divide by 8 |
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* cko1_sel = 1011 --> ahb_clk_root |
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* |
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* This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz |
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*/ |
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DATA 4, CCM_CCOSR, 0x000000fb |
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@ -0,0 +1,129 @@ |
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/*
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* Copyright (C) 2013 Gateworks Corporation |
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* |
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* Author: Tim Harvey <tharvey@gateworks.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <asm/errno.h> |
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#include <common.h> |
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#include <i2c.h> |
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#include <linux/ctype.h> |
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#include "gsc.h" |
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#define MINMAX(n, percent) ((n)*(100-percent)/100), ((n)*(100+percent)/100) |
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/*
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* The Gateworks System Controller will fail to ACK a master transaction if |
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* it is busy, which can occur during its 1HZ timer tick while reading ADC's. |
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* When this does occur, it will never be busy long enough to fail more than |
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* 2 back-to-back transfers. Thus we wrap i2c_read and i2c_write with |
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* 3 retries. |
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*/ |
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int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) |
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{ |
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int retry = 3; |
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int n = 0; |
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int ret; |
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while (n++ < retry) { |
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ret = i2c_read(chip, addr, alen, buf, len); |
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if (!ret) |
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break; |
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debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr, |
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n, ret); |
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if (ret != -ENODEV) |
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break; |
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mdelay(10); |
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} |
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return ret; |
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} |
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int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) |
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{ |
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int retry = 3; |
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int n = 0; |
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int ret; |
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while (n++ < retry) { |
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ret = i2c_write(chip, addr, alen, buf, len); |
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if (!ret) |
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break; |
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debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr, |
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n, ret); |
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if (ret != -ENODEV) |
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break; |
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mdelay(10); |
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} |
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mdelay(1); |
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return ret; |
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} |
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#ifdef CONFIG_CMD_GSC |
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static void read_hwmon(const char *name, uint reg, uint size, uint low, |
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uint high) |
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{ |
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unsigned char buf[3]; |
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uint ui; |
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printf("%-8s:", name); |
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memset(buf, 0, sizeof(buf)); |
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if (gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, size)) { |
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puts("fRD\n"); |
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} else { |
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ui = buf[0] | (buf[1]<<8) | (buf[2]<<16); |
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if (ui == 0xffffff) |
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printf("invalid"); |
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else if (ui < low) |
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printf("%d Failed - Low", ui); |
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else if (ui > high) |
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printf("%d Failed - High", ui); |
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else |
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printf("%d", ui); |
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} |
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puts("\n"); |
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} |
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int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
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{ |
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const char *model = getenv("model"); |
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i2c_set_bus_num(0); |
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read_hwmon("Temp", GSC_HWMON_TEMP, 2, 0, 9000); |
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read_hwmon("VIN", GSC_HWMON_VIN, 3, 8000, 60000); |
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read_hwmon("VBATT", GSC_HWMON_VBATT, 3, 1800, 3500); |
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read_hwmon("VDD_3P3", GSC_HWMON_VDD_3P3, 3, MINMAX(3300, 10)); |
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read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3, MINMAX(3000, 10)); |
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read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR, 3, MINMAX(1500, 10)); |
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read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0, 3, MINMAX(5000, 10)); |
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read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3, MINMAX(2500, 10)); |
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read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8, 3, MINMAX(1800, 10)); |
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switch (model[3]) { |
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case '1': /* GW51xx */ |
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read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10)); |
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read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10)); |
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break; |
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case '2': /* GW52xx */ |
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case '3': /* GW53xx */ |
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read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10)); |
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read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10)); |
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read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3, MINMAX(1000, 10)); |
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break; |
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case '4': /* GW54xx */ |
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read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1375, 10)); |
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read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1375, 10)); |
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read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3, MINMAX(1000, 10)); |
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break; |
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} |
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return 0; |
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} |
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U_BOOT_CMD(gsc, 1, 1, do_gsc, |
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"GSC test", |
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"" |
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); |
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#endif /* CONFIG_CMD_GSC */ |
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@ -0,0 +1,64 @@ |
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/*
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* Copyright (C) 2013 Gateworks Corporation |
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* |
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* Author: Tim Harvey <tharvey@gateworks.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __ASSEMBLY__ |
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/* i2c slave addresses */ |
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#define GSC_SC_ADDR 0x20 |
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#define GSC_RTC_ADDR 0x68 |
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#define GSC_HWMON_ADDR 0x29 |
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#define GSC_EEPROM_ADDR 0x51 |
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/* System Controller registers */ |
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enum { |
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GSC_SC_CTRL0 = 0x00, |
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GSC_SC_CTRL1 = 0x01, |
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GSC_SC_STATUS = 0x0a, |
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GSC_SC_FWVER = 0x0e, |
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}; |
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/* System Controller Control1 bits */ |
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enum { |
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GSC_SC_CTRL1_WDDIS = 7, /* 1 = disable watchdog */ |
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}; |
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/* System Controller Interrupt bits */ |
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enum { |
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GSC_SC_IRQ_PB = 0, /* Pushbutton switch */ |
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GSC_SC_IRQ_SECURE = 1, /* Secure Key erase operation complete */ |
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GSC_SC_IRQ_EEPROM_WP = 2, /* EEPROM write violation */ |
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GSC_SC_IRQ_GPIO = 4, /* GPIO change */ |
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GSC_SC_IRQ_TAMPER = 5, /* Tamper detect */ |
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GSC_SC_IRQ_WATCHDOG = 6, /* Watchdog trip */ |
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GSC_SC_IRQ_PBLONG = 7, /* Pushbutton long hold */ |
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}; |
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/* Hardware Monitor registers */ |
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enum { |
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GSC_HWMON_TEMP = 0x00, |
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GSC_HWMON_VIN = 0x02, |
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GSC_HWMON_VDD_3P3 = 0x05, |
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GSC_HWMON_VBATT = 0x08, |
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GSC_HWMON_VDD_5P0 = 0x0b, |
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GSC_HWMON_VDD_CORE = 0x0e, |
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GSC_HWMON_VDD_HIGH = 0x14, |
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GSC_HWMON_VDD_DDR = 0x17, |
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GSC_HWMON_VDD_SOC = 0x11, |
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GSC_HWMON_VDD_1P8 = 0x1d, |
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GSC_HWMON_VDD_2P5 = 0x23, |
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GSC_HWMON_VDD_1P0 = 0x20, |
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}; |
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/*
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* I2C transactions to the GSC are done via these functions which |
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* perform retries in the case of a busy GSC NAK'ing the transaction |
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*/ |
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int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len); |
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int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len); |
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#endif |
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,44 @@ |
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/* |
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* Copyright (C) 2013 Gateworks Corporation |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* Refer doc/README.imximage for more details about how-to configure |
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* and create imximage boot image |
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* |
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* The syntax is taken as close as possible with the kwbimage |
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*/ |
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/* image version */ |
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IMAGE_VERSION 2 |
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/* |
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* Boot Device : one of |
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* spi, sd, nand, sata |
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*/ |
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#ifdef CONFIG_SPI_FLASH |
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BOOT_FROM spi |
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#else |
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BOOT_FROM nand |
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#endif |
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#define __ASSEMBLY__ |
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#include <config.h> |
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#include "asm/arch/mx6-ddr.h" |
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#include "asm/arch/iomux.h" |
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#include "asm/arch/crm_regs.h" |
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/* Memory configuration (size is overridden via eeprom config) */ |
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#include "../../boundary/nitrogen6x/ddr-setup.cfg" |
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#if defined(CONFIG_MX6Q) && CONFIG_DDR_MB == 1024 |
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#include "../../boundary/nitrogen6x/1066mhz_4x128mx16.cfg" |
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#elif defined(CONFIG_MX6DL) && CONFIG_DDR_MB == 1024 |
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#include "../../boundary/nitrogen6x/800mhz_4x128mx16.cfg" |
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#elif defined(CONFIG_MX6DL) && CONFIG_DDR_MB == 512 |
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#include "../../boundary/nitrogen6x/800mhz_2x128mx16.cfg" |
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#elif defined(CONFIG_MX6Q) && CONFIG_DDR_MB == 512 |
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#include "../../boundary/nitrogen6x/800mhz_2x128mx16.cfg" |
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#else |
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#error "Unsupported CPU/Memory configuration" |
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#endif |
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#include "clocks.cfg" |
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@ -0,0 +1,106 @@ |
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/*
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* Copyright (C) 2013 Gateworks Corporation |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _VENTANA_EEPROM_ |
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#define _VENTANA_EEPROM_ |
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struct ventana_board_info { |
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u8 mac0[6]; /* 0x00: MAC1 */ |
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u8 mac1[6]; /* 0x06: MAC2 */ |
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u8 res0[12]; /* 0x0C: reserved */ |
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u32 serial; /* 0x18: Serial Number (read only) */ |
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u8 res1[4]; /* 0x1C: reserved */ |
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u8 mfgdate[4]; /* 0x20: MFG date (read only) */ |
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u8 res2[7]; /* 0x24 */ |
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/* sdram config */ |
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u8 sdram_size; /* 0x2B: enum (512,1024,2048) MB */ |
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u8 sdram_speed; /* 0x2C: enum (100,133,166,200,267,333,400) MHz */ |
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u8 sdram_width; /* 0x2D: enum (32,64) bit */ |
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/* cpu config */ |
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u8 cpu_speed; /* 0x2E: enum (800,1000,1200) MHz */ |
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u8 cpu_type; /* 0x2F: enum (imx6q,imx6d,imx6dl,imx6s) */ |
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u8 model[16]; /* 0x30: model string */ |
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/* FLASH config */ |
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u8 nand_flash_size; /* 0x40: enum (4,8,16,32,64,128) MB */ |
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u8 spi_flash_size; /* 0x41: enum (4,8,16,32,64,128) MB */ |
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/* Config1: SoC Peripherals */ |
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u8 config[8]; /* 0x42: loading options */ |
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u8 res3[4]; /* 0x4A */ |
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u8 chksum[2]; /* 0x4E */ |
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}; |
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/* config bits */ |
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enum { |
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EECONFIG_ETH0, |
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EECONFIG_ETH1, |
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EECONFIG_HDMI_OUT, |
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EECONFIG_SATA, |
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EECONFIG_PCIE, |
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EECONFIG_SSI0, |
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EECONFIG_SSI1, |
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EECONFIG_LCD, |
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EECONFIG_LVDS0, |
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EECONFIG_LVDS1, |
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EECONFIG_USB0, |
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EECONFIG_USB1, |
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EECONFIG_SD0, |
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EECONFIG_SD1, |
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EECONFIG_SD2, |
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EECONFIG_SD3, |
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EECONFIG_UART0, |
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EECONFIG_UART1, |
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EECONFIG_UART2, |
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EECONFIG_UART3, |
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EECONFIG_UART4, |
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EECONFIG_IPU0, |
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EECONFIG_IPU1, |
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EECONFIG_FLEXCAN, |
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EECONFIG_MIPI_DSI, |
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EECONFIG_MIPI_CSI, |
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EECONFIG_TZASC0, |
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EECONFIG_TZASC1, |
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EECONFIG_I2C0, |
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EECONFIG_I2C1, |
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EECONFIG_I2C2, |
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EECONFIG_VPU, |
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EECONFIG_CSI0, |
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EECONFIG_CSI1, |
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EECONFIG_CAAM, |
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EECONFIG_MEZZ, |
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EECONFIG_RES1, |
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EECONFIG_RES2, |
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EECONFIG_RES3, |
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EECONFIG_RES4, |
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EECONFIG_ESPCI0, |
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EECONFIG_ESPCI1, |
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EECONFIG_ESPCI2, |
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EECONFIG_ESPCI3, |
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EECONFIG_ESPCI4, |
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EECONFIG_ESPCI5, |
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EECONFIG_RES5, |
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EECONFIG_RES6, |
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EECONFIG_GPS, |
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EECONFIG_SPIFL0, |
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EECONFIG_SPIFL1, |
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EECONFIG_GSPBATT, |
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EECONFIG_HDMI_IN, |
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EECONFIG_VID_OUT, |
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EECONFIG_VID_IN, |
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EECONFIG_NAND, |
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EECONFIG_RES8, |
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EECONFIG_RES9, |
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EECONFIG_RES10, |
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EECONFIG_RES11, |
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EECONFIG_RES12, |
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EECONFIG_RES13, |
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EECONFIG_RES14, |
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EECONFIG_RES15, |
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}; |
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#endif |
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@ -0,0 +1,425 @@ |
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/*
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* Copyright (C) 2013 Gateworks Corporation |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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#include "mx6_common.h" |
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#define CONFIG_MX6 |
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#define CONFIG_DISPLAY_CPUINFO /* display cpu info */ |
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#define CONFIG_DISPLAY_BOARDINFO_LATE /* display board info (after reloc) */ |
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#define CONFIG_MACH_TYPE 4520 /* Gateworks Ventana Platform */ |
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#include <asm/arch/imx-regs.h> |
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#include <asm/imx-common/gpio.h> |
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/* ATAGs */ |
||||
#define CONFIG_CMDLINE_TAG |
||||
#define CONFIG_SETUP_MEMORY_TAGS |
||||
#define CONFIG_INITRD_TAG |
||||
#define CONFIG_SERIAL_TAG |
||||
#define CONFIG_REVISION_TAG |
||||
|
||||
/* Size of malloc() pool */ |
||||
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) |
||||
|
||||
/* Init Functions */ |
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
/* GPIO */ |
||||
#define CONFIG_MXC_GPIO |
||||
|
||||
/* Serial */ |
||||
#define CONFIG_MXC_UART |
||||
#define CONFIG_MXC_UART_BASE UART2_BASE |
||||
|
||||
#ifdef CONFIG_SPI_FLASH |
||||
|
||||
/* SPI */ |
||||
#define CONFIG_CMD_SF |
||||
#ifdef CONFIG_CMD_SF |
||||
#define CONFIG_MXC_SPI |
||||
#define CONFIG_SPI_FLASH_MTD |
||||
#define CONFIG_SPI_FLASH_BAR |
||||
#define CONFIG_SPI_FLASH_WINBOND |
||||
#define CONFIG_SF_DEFAULT_BUS 0 |
||||
#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 19)<<8)) |
||||
/* GPIO 3-19 (21248) */ |
||||
#define CONFIG_SF_DEFAULT_SPEED 30000000 |
||||
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) |
||||
#endif |
||||
|
||||
#else |
||||
/* Enable NAND support */ |
||||
#define CONFIG_CMD_TIME |
||||
#define CONFIG_CMD_NAND |
||||
#define CONFIG_CMD_NAND_TRIMFFS |
||||
#ifdef CONFIG_CMD_NAND |
||||
#define CONFIG_NAND_MXS |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||
#define CONFIG_SYS_NAND_BASE 0x40000000 |
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE |
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION |
||||
|
||||
/* DMA stuff, needed for GPMI/MXS NAND support */ |
||||
#define CONFIG_APBH_DMA |
||||
#define CONFIG_APBH_DMA_BURST |
||||
#define CONFIG_APBH_DMA_BURST8 |
||||
#endif |
||||
|
||||
#endif /* CONFIG_SPI_FLASH */ |
||||
|
||||
/* Flattened Image Tree Suport */ |
||||
#define CONFIG_FIT |
||||
#define CONFIG_FIT_VERBOSE |
||||
|
||||
/* I2C Configs */ |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_MXC |
||||
#define CONFIG_SYS_I2C_SPEED 100000 |
||||
|
||||
/* MMC Configs */ |
||||
#define CONFIG_FSL_ESDHC |
||||
#define CONFIG_FSL_USDHC |
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
||||
#define CONFIG_SYS_FSL_USDHC_NUM 1 |
||||
#define CONFIG_MMC |
||||
#define CONFIG_CMD_MMC |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_BOUNCE_BUFFER |
||||
|
||||
/* Filesystem support */ |
||||
#define CONFIG_CMD_EXT2 |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_CMD_UBIFS |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
/* Network config - Allow larger/faster download for TFTP/NFS */ |
||||
#define CONFIG_IP_DEFRAG |
||||
#define CONFIG_TFTP_BLOCKSIZE 4096 |
||||
#define CONFIG_NFS_READ_SIZE 4096 |
||||
|
||||
/*
|
||||
* SATA Configs |
||||
*/ |
||||
#define CONFIG_CMD_SATA |
||||
#ifdef CONFIG_CMD_SATA |
||||
#define CONFIG_DWC_AHSATA |
||||
#define CONFIG_SYS_SATA_MAX_DEVICE 1 |
||||
#define CONFIG_DWC_AHSATA_PORT_ID 0 |
||||
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR |
||||
#define CONFIG_LBA48 |
||||
#define CONFIG_LIBATA |
||||
#endif |
||||
|
||||
/*
|
||||
* PCI express |
||||
*/ |
||||
#define CONFIG_CMD_PCI |
||||
#ifdef CONFIG_CMD_PCI |
||||
#define CONFIG_PCI |
||||
#define CONFIG_PCI_PNP |
||||
#define CONFIG_PCI_SCAN_SHOW |
||||
#define CONFIG_PCIE_IMX |
||||
#endif |
||||
|
||||
/*
|
||||
* PMIC |
||||
*/ |
||||
#define CONFIG_POWER |
||||
#define CONFIG_POWER_I2C |
||||
#define CONFIG_POWER_PFUZE100 |
||||
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 |
||||
|
||||
/* Various command support */ |
||||
#include <config_cmd_default.h> |
||||
#undef CONFIG_CMD_IMLS |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_CMD_BMODE /* set eFUSE shadow for a boot dev and reset */ |
||||
#define CONFIG_CMD_HDMIDETECT /* detect HDMI output device */ |
||||
#define CONFIG_CMD_SETEXPR |
||||
#define CONFIG_CMD_BOOTZ |
||||
#define CONFIG_CMD_GSC |
||||
#define CONFIG_CMD_UBI |
||||
#define CONFIG_RBTREE |
||||
#define CONFIG_LZO |
||||
#define CONFIG_CMD_FUSE /* eFUSE read/write support */ |
||||
#ifdef CONFIG_CMD_FUSE |
||||
#define CONFIG_MXC_OCOTP |
||||
#endif |
||||
|
||||
|
||||
/* Ethernet support */ |
||||
#define CONFIG_FEC_MXC |
||||
#define CONFIG_MII |
||||
#define IMX_FEC_BASE ENET_BASE_ADDR |
||||
#define CONFIG_FEC_XCV_TYPE RGMII |
||||
#define CONFIG_ETHPRIME "FEC" |
||||
#define CONFIG_FEC_MXC_PHYADDR 0 |
||||
#define CONFIG_PHYLIB |
||||
#define CONFIG_ARP_TIMEOUT 200UL |
||||
|
||||
/* USB Configs */ |
||||
#define CONFIG_CMD_USB |
||||
#define CONFIG_USB_EHCI |
||||
#define CONFIG_USB_EHCI_MX6 |
||||
#define CONFIG_USB_STORAGE |
||||
#define CONFIG_USB_HOST_ETHER |
||||
#define CONFIG_USB_ETHER_ASIX |
||||
#define CONFIG_USB_ETHER_SMSC95XX |
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ |
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
||||
#define CONFIG_MXC_USB_FLAGS 0 |
||||
#define CONFIG_USB_KEYBOARD |
||||
#define CONFIG_CI_UDC |
||||
#define CONFIG_USBD_HS |
||||
#define CONFIG_USB_GADGET_DUALSPEED |
||||
#define CONFIG_USB_ETHER |
||||
#define CONFIG_USB_ETH_CDC |
||||
#define CONFIG_NETCONSOLE |
||||
#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP |
||||
#define CONFIG_USB_HUB_MIN_POWER_ON_DELAY 1200 |
||||
|
||||
/* serial console (ttymxc1,115200) */ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
/* Miscellaneous configurable options */ |
||||
#define CONFIG_SYS_LONGHELP |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_SYS_PROMPT "Ventana > " |
||||
#define CONFIG_SYS_CBSIZE 1024 |
||||
#define CONFIG_AUTO_COMPLETE |
||||
#define CONFIG_CMDLINE_EDITING |
||||
#define CONFIG_HWCONFIG |
||||
|
||||
/* Print Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
#define CONFIG_SYS_MAXARGS 16 |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
|
||||
/* Memory configuration */ |
||||
#define CONFIG_SYS_MEMTEST_START 0x10000000 |
||||
#define CONFIG_SYS_MEMTEST_END 0x10010000 |
||||
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 |
||||
#define CONFIG_SYS_TEXT_BASE 0x17800000 |
||||
#define CONFIG_SYS_LOAD_ADDR 0x12000000 |
||||
|
||||
/* Physical Memory Map */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR |
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR \ |
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
||||
|
||||
/* FLASH and environment organization */ |
||||
#define CONFIG_SYS_NO_FLASH /* no NOR flash */ |
||||
|
||||
/*
|
||||
* MTD Command for mtdparts |
||||
*/ |
||||
#define CONFIG_CMD_MTDPARTS |
||||
#define CONFIG_MTD_DEVICE |
||||
#define CONFIG_MTD_PARTITIONS |
||||
#ifdef CONFIG_SPI_FLASH |
||||
#define MTDIDS_DEFAULT "nor0=nor" |
||||
#define MTDPARTS_DEFAULT \ |
||||
"mtdparts=nor:512k(uboot),64k(env),2m(kernel),-(rootfs)" |
||||
#else |
||||
#define MTDIDS_DEFAULT "nand0=nand" |
||||
#define MTDPARTS_DEFAULT "mtdparts=nand:16m(uboot),1m(env),-(rootfs)" |
||||
#endif |
||||
|
||||
/* Persistent Environment Config */ |
||||
#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ |
||||
#ifdef CONFIG_SPI_FLASH |
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH |
||||
#else |
||||
#define CONFIG_ENV_IS_IN_NAND |
||||
#endif |
||||
#if defined(CONFIG_ENV_IS_IN_MMC) |
||||
#define CONFIG_ENV_OFFSET (6 * 64 * 1024) |
||||
#define CONFIG_ENV_SIZE (8 * 1024) |
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 |
||||
#elif defined(CONFIG_ENV_IS_IN_NAND) |
||||
#define CONFIG_ENV_OFFSET (16 << 20) |
||||
#define CONFIG_ENV_SECT_SIZE (128 << 10) |
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + (512 << 10)) |
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
||||
#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) |
||||
#define CONFIG_ENV_OFFSET (512 * 1024) |
||||
#define CONFIG_ENV_SECT_SIZE (64 * 1024) |
||||
#define CONFIG_ENV_SIZE (8 * 1024) |
||||
#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS |
||||
#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS |
||||
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE |
||||
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED |
||||
#endif |
||||
|
||||
/* Environment */ |
||||
#define CONFIG_BOOTDELAY 3 |
||||
#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR |
||||
#define CONFIG_IPADDR 192.168.1.1 |
||||
#define CONFIG_SERVERIP 192.168.1.146 |
||||
#define HWCONFIG_DEFAULT \ |
||||
"hwconfig=rs232;" \
|
||||
"dio0:mode=gpio;dio1:mode=gpio;dio2:mode=gpio;dio3:mode=gpio\0" \
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \ |
||||
"console=ttymxc1\0" \
|
||||
"bootdevs=usb mmc sata flash\0" \
|
||||
HWCONFIG_DEFAULT \
|
||||
"video=\0" \
|
||||
\
|
||||
"mtdparts=" MTDPARTS_DEFAULT "\0" \
|
||||
"mtdids=" MTDIDS_DEFAULT "\0" \
|
||||
\
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"fdt_addr=0x18000000\0" \
|
||||
"loadfdt=" \
|
||||
"if ${fsload} ${fdt_addr} boot/${fdt_file}; then " \
|
||||
"echo Loaded DTB from boot/${fdt_file}; " \
|
||||
"elif ${fsload} ${fdt_addr} boot/${fdt_file1}; then " \
|
||||
"echo Loaded DTB from boot/${fdt_file1}; " \
|
||||
"elif ${fsload} ${fdt_addr} boot/${fdt_file2}; then " \
|
||||
"echo Loaded DTB from boot/${fdt_file2}; " \
|
||||
"fi\0" \
|
||||
\
|
||||
"script=boot/6x_bootscript-ventana\0" \
|
||||
"loadscript=" \
|
||||
"if ${fsload} ${loadaddr} ${script}; then " \
|
||||
"source; " \
|
||||
"fi\0" \
|
||||
\
|
||||
"uimage=boot/uImage\0" \
|
||||
"mmc_root=/dev/mmcblk0p1 rootfstype=ext4 rootwait rw\0" \
|
||||
"mmc_boot=" \
|
||||
"setenv fsload 'ext2load mmc 0:1'; " \
|
||||
"mmc dev 0 && mmc rescan && " \
|
||||
"run loadscript; " \
|
||||
"if ${fsload} ${loadaddr} ${uimage}; then " \
|
||||
"setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/mmcblk0p1 rootfstype=ext4 " \
|
||||
"rootwait rw ${video} ${extra}; " \
|
||||
"if run loadfdt && fdt addr ${fdt_addr}; then " \
|
||||
"bootm ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"bootm; " \
|
||||
"fi; " \
|
||||
"fi\0" \
|
||||
\
|
||||
"sata_boot=" \
|
||||
"setenv fsload 'ext2load sata 0:1'; sata init && " \
|
||||
"run loadscript; " \
|
||||
"if ${fsload} ${loadaddr} ${uimage}; then " \
|
||||
"setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/sda1 rootfstype=ext4 " \
|
||||
"rootwait rw ${video} ${extra}; " \
|
||||
"if run loadfdt && fdt addr ${fdt_addr}; then " \
|
||||
"bootm ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"bootm; " \
|
||||
"fi; " \
|
||||
"fi\0" \
|
||||
"usb_boot=" \
|
||||
"setenv fsload 'ext2load usb 0:1'; usb start && usb dev 0 && " \
|
||||
"run loadscript; " \
|
||||
"if ${fsload} ${loadaddr} ${uimage}; then " \
|
||||
"setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/sda1 rootfstype=ext4 " \
|
||||
"rootwait rw ${video} ${extra}; " \
|
||||
"if run loadfdt && fdt addr ${fdt_addr}; then " \
|
||||
"bootm ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"bootm; " \
|
||||
"fi; " \
|
||||
"fi\0" |
||||
|
||||
#ifdef CONFIG_SPI_FLASH |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
CONFIG_EXTRA_ENV_SETTINGS_COMMON \
|
||||
"image_os=ventana/openwrt-imx6-imx6q-gw5400-a-squashfs.bin\0" \
|
||||
"image_uboot=ventana/u-boot_spi.imx\0" \
|
||||
\
|
||||
"spi_koffset=0x90000\0" \
|
||||
"spi_klen=0x200000\0" \
|
||||
\
|
||||
"spi_updateuboot=echo Updating uboot from " \
|
||||
"${serverip}:${image_uboot}...; " \
|
||||
"tftpboot ${loadaddr} ${image_uboot} && " \
|
||||
"sf probe && sf erase 0 80000 && " \
|
||||
"sf write ${loadaddr} 400 ${filesize}\0" \
|
||||
"spi_update=echo Updating OS from ${serverip}:${image_os} " \
|
||||
"to ${spi_koffset} ...; " \
|
||||
"tftp ${loadaddr} ${image_os} && " \
|
||||
"sf probe && " \
|
||||
"sf update ${loadaddr} ${spi_koffset} ${filesize}\0" \
|
||||
\
|
||||
"flash_boot=" \
|
||||
"if sf probe && " \
|
||||
"sf read ${loadaddr} ${spi_koffset} ${spi_klen}; then " \
|
||||
"setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/mtdblock3 " \
|
||||
"rootfstype=squashfs,jffs2 " \
|
||||
"${video} ${extra}; " \
|
||||
"bootm; " \
|
||||
"fi\0" |
||||
#else |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
CONFIG_EXTRA_ENV_SETTINGS_COMMON \
|
||||
"image_rootfs=openwrt-imx6-ventana-rootfs.ubi\0" \
|
||||
\
|
||||
"nand_update=echo Updating NAND from ${serverip}:${image_rootfs}...; " \
|
||||
"tftp ${loadaddr} ${image_rootfs} && " \
|
||||
"nand erase.part rootfs && " \
|
||||
"nand write ${loadaddr} rootfs ${filesize}\0" \
|
||||
\
|
||||
"flash_boot=" \
|
||||
"setenv fsload 'ubifsload'; " \
|
||||
"ubi part rootfs && ubifsmount ubi0:rootfs; " \
|
||||
"run loadscript; " \
|
||||
"if ${fsload} ${loadaddr} ${uimage}; then " \
|
||||
"setenv bootargs console=${console},${baudrate} " \
|
||||
"root=ubi0:rootfs ubi.mtd=2 " \
|
||||
"rootfstype=ubifs ${video} ${extra}; " \
|
||||
"if run loadfdt && fdt addr ${fdt_addr}; then " \
|
||||
"ubifsumount; " \
|
||||
"bootm ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"ubifsumount; bootm; " \
|
||||
"fi; " \
|
||||
"fi\0" |
||||
#endif |
||||
|
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"for btype in ${bootdevs}; do " \
|
||||
"echo; echo Attempting ${btype} boot...; " \
|
||||
"if run ${btype}_boot; then; fi; " \
|
||||
"done" |
||||
|
||||
/* Device Tree Support */ |
||||
#define CONFIG_OF_BOARD_SETUP |
||||
#define CONFIG_OF_LIBFDT |
||||
#define CONFIG_FDT_FIXUP_PARTITIONS |
||||
|
||||
#ifndef CONFIG_SYS_DCACHE_OFF |
||||
#define CONFIG_CMD_CACHE |
||||
#endif |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue