|
|
|
@ -50,43 +50,6 @@ copyex: |
|
|
|
|
bne copyex |
|
|
|
|
#endif |
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_S3C24X0 |
|
|
|
|
/* turn off the watchdog */ |
|
|
|
|
|
|
|
|
|
# if defined(CONFIG_S3C2400) |
|
|
|
|
# define pWTCON 0x15300000 |
|
|
|
|
# define INTMSK 0x14400008 /* Interrupt-Controller base addresses */ |
|
|
|
|
# define CLKDIVN 0x14800014 /* clock divisor register */ |
|
|
|
|
#else |
|
|
|
|
# define pWTCON 0x53000000 |
|
|
|
|
# define INTMSK 0x4A000008 /* Interrupt-Controller base addresses */ |
|
|
|
|
# define INTSUBMSK 0x4A00001C |
|
|
|
|
# define CLKDIVN 0x4C000014 /* clock divisor register */ |
|
|
|
|
# endif |
|
|
|
|
|
|
|
|
|
ldr r0, =pWTCON |
|
|
|
|
mov r1, #0x0 |
|
|
|
|
str r1, [r0] |
|
|
|
|
|
|
|
|
|
/* |
|
|
|
|
* mask all IRQs by setting all bits in the INTMR - default |
|
|
|
|
*/ |
|
|
|
|
mov r1, #0xffffffff |
|
|
|
|
ldr r0, =INTMSK |
|
|
|
|
str r1, [r0] |
|
|
|
|
# if defined(CONFIG_S3C2410) |
|
|
|
|
ldr r1, =0x3ff |
|
|
|
|
ldr r0, =INTSUBMSK |
|
|
|
|
str r1, [r0] |
|
|
|
|
# endif |
|
|
|
|
|
|
|
|
|
/* FCLK:HCLK:PCLK = 1:2:4 */ |
|
|
|
|
/* default FCLK is 120 MHz ! */ |
|
|
|
|
ldr r0, =CLKDIVN |
|
|
|
|
mov r1, #3 |
|
|
|
|
str r1, [r0] |
|
|
|
|
#endif /* CONFIG_S3C24X0 */ |
|
|
|
|
|
|
|
|
|
/* |
|
|
|
|
* we do sys-critical inits only at reboot, |
|
|
|
|
* not when booting from ram! |
|
|
|
|