add support for using spl code on at91sam9260 and at91sam9g45 based boards. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bo Shen <voice.shen@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> [adopt Bo's change in spl.c] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>master
Heiko Schocher
10 years ago
committed by
Tom Rini
parent
667af36905
commit
5abc00d020
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/*
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* (C) Copyright 2014 |
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* Heiko Schocher, DENX Software Engineering, hs@denx.de. |
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* |
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* Based on: |
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* (C) Copyright 2007-2008 |
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* Stelian Pop <stelian@popies.net> |
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* Lead Tech Design <www.leadtechdesign.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/at91_common.h> |
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#include <asm/arch/at91_pmc.h> |
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#include <asm/arch/at91sam9_sdramc.h> |
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#include <asm/arch/gpio.h> |
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int sdramc_initialize(unsigned int sdram_address, const struct sdramc_reg *p) |
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{ |
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struct sdramc_reg *reg = (struct sdramc_reg *)ATMEL_BASE_SDRAMC; |
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unsigned int i; |
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/* SDRAM feature must be in the configuration register */ |
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writel(p->cr, ®->cr); |
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/* The SDRAM memory type must be set in the Memory Device Register */ |
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writel(p->mdr, ®->mdr); |
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/*
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* The minimum pause of 200 us is provided to precede any single |
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* toggle |
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*/ |
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for (i = 0; i < 1000; i++) |
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; |
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/* A NOP command is issued to the SDRAM devices */ |
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writel(AT91_SDRAMC_MODE_NOP, ®->mr); |
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writel(0x00000000, sdram_address); |
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/* An All Banks Precharge command is issued to the SDRAM devices */ |
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writel(AT91_SDRAMC_MODE_PRECHARGE, ®->mr); |
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writel(0x00000000, sdram_address); |
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for (i = 0; i < 10000; i++) |
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; |
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/* Eight auto-refresh cycles are provided */ |
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for (i = 0; i < 8; i++) { |
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writel(AT91_SDRAMC_MODE_REFRESH, ®->mr); |
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writel(0x00000001 + i, sdram_address + 4 + 4 * i); |
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} |
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/*
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* A Mode Register set (MRS) cyscle is issued to program the |
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* SDRAM parameters(TCSR, PASR, DS) |
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*/ |
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writel(AT91_SDRAMC_MODE_LMR, ®->mr); |
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writel(0xcafedede, sdram_address + 0x24); |
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/*
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* The application must go into Normal Mode, setting Mode |
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* to 0 in the Mode Register and perform a write access at |
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* any location in the SDRAM. |
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*/ |
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writel(AT91_SDRAMC_MODE_NORMAL, ®->mr); |
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writel(0x00000000, sdram_address); /* Perform Normal mode */ |
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/*
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* Write the refresh rate into the count field in the SDRAMC |
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* Refresh Timer Rgister. |
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*/ |
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writel(p->tr, ®->tr); |
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return 0; |
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} |
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@ -0,0 +1,124 @@ |
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/*
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* (C) Copyright 2014 DENX Software Engineering |
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* Heiko Schocher <hs@denx.de> |
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* |
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* Based on: |
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* Copyright (C) 2013 Atmel Corporation |
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* Bo Shen <voice.shen@atmel.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/at91_common.h> |
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#include <asm/arch/at91sam9_matrix.h> |
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#include <asm/arch/at91_pit.h> |
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#include <asm/arch/at91_pmc.h> |
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#include <asm/arch/at91_rstc.h> |
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#include <asm/arch/at91_wdt.h> |
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#include <asm/arch/clk.h> |
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#include <spl.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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static void enable_ext_reset(void) |
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{ |
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struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; |
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writel(AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN, &rstc->mr); |
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} |
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void lowlevel_clock_init(void) |
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{ |
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; |
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if (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) { |
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/* Enable Main Oscillator */ |
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writel(AT91_PMC_MOSCS | (0x40 << 8), &pmc->mor); |
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/* Wait until Main Oscillator is stable */ |
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while (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) |
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; |
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} |
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/* After stabilization, switch to Main Oscillator */ |
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if ((readl(&pmc->mckr) & AT91_PMC_CSS) == AT91_PMC_CSS_SLOW) { |
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unsigned long tmp; |
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tmp = readl(&pmc->mckr); |
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tmp &= ~AT91_PMC_CSS; |
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tmp |= AT91_PMC_CSS_MAIN; |
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writel(tmp, &pmc->mckr); |
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while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) |
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; |
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tmp &= ~AT91_PMC_PRES; |
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tmp |= AT91_PMC_PRES_1; |
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writel(tmp, &pmc->mckr); |
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while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) |
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; |
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} |
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return; |
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} |
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void __weak matrix_init(void) |
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{ |
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} |
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void __weak at91_spl_board_init(void) |
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{ |
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} |
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void spl_board_init(void) |
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{ |
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; |
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lowlevel_clock_init(); |
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at91_disable_wdt(); |
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/*
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* At this stage the main oscillator is supposed to be enabled |
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* PCK = MCK = MOSC |
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*/ |
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writel(0x00, &pmc->pllicpr); |
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/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ |
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at91_plla_init(CONFIG_SYS_AT91_PLLA); |
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/* PCK = PLLA = 2 * MCK */ |
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at91_mck_init(CONFIG_SYS_MCKR); |
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/* Switch MCK on PLLA output */ |
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at91_mck_init(CONFIG_SYS_MCKR_CSS); |
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#if defined(CONFIG_SYS_AT91_PLLB) |
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/* Configure PLLB */ |
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at91_pllb_init(CONFIG_SYS_AT91_PLLB); |
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#endif |
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/* Enable External Reset */ |
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enable_ext_reset(); |
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/* Initialize matrix */ |
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matrix_init(); |
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gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK; |
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/*
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* init timer long enough for using in spl. |
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*/ |
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timer_init(); |
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/* enable clocks for all PIOs */ |
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at91_periph_clk_enable(ATMEL_ID_PIOA); |
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at91_periph_clk_enable(ATMEL_ID_PIOB); |
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at91_periph_clk_enable(ATMEL_ID_PIOC); |
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/* init console */ |
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at91_seriald_hw_init(); |
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preloader_console_init(); |
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mem_init(); |
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at91_spl_board_init(); |
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} |
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@ -0,0 +1,80 @@ |
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/*
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* Copyright (C) 2013 Atmel Corporation |
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* Bo Shen <voice.shen@atmel.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/at91_common.h> |
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#include <asm/arch/at91_pit.h> |
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#include <asm/arch/at91_pmc.h> |
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#include <asm/arch/at91_rstc.h> |
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#include <asm/arch/at91_wdt.h> |
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#include <asm/arch/clk.h> |
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#include <spl.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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static void switch_to_main_crystal_osc(void) |
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{ |
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; |
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u32 tmp; |
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tmp = readl(&pmc->mor); |
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tmp &= ~AT91_PMC_MOR_OSCOUNT(0xff); |
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tmp &= ~AT91_PMC_MOR_KEY(0xff); |
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tmp |= AT91_PMC_MOR_MOSCEN; |
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tmp |= AT91_PMC_MOR_OSCOUNT(8); |
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tmp |= AT91_PMC_MOR_KEY(0x37); |
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writel(tmp, &pmc->mor); |
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while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCS)) |
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; |
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tmp = readl(&pmc->mor); |
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tmp &= ~AT91_PMC_MOR_OSCBYPASS; |
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tmp &= ~AT91_PMC_MOR_KEY(0xff); |
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tmp |= AT91_PMC_MOR_KEY(0x37); |
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writel(tmp, &pmc->mor); |
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tmp = readl(&pmc->mor); |
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tmp |= AT91_PMC_MOR_MOSCSEL; |
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tmp &= ~AT91_PMC_MOR_KEY(0xff); |
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tmp |= AT91_PMC_MOR_KEY(0x37); |
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writel(tmp, &pmc->mor); |
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while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCSELS)) |
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; |
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/* Wait until MAINRDY field is set to make sure main clock is stable */ |
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while (!(readl(&pmc->mcfr) & AT91_PMC_MAINRDY)) |
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; |
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tmp = readl(&pmc->mor); |
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tmp &= ~AT91_PMC_MOR_MOSCRCEN; |
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tmp &= ~AT91_PMC_MOR_KEY(0xff); |
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tmp |= AT91_PMC_MOR_KEY(0x37); |
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writel(tmp, &pmc->mor); |
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} |
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void s_init(void) |
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{ |
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switch_to_main_crystal_osc(); |
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/* disable watchdog */ |
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at91_disable_wdt(); |
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/* PMC configuration */ |
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at91_pmc_init(); |
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at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); |
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timer_init(); |
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board_early_init_f(); |
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preloader_console_init(); |
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mem_init(); |
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} |
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