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wdenk 23 years ago
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  1. 290
      board/RPXClassic/RPXClassic.c
  2. 29
      board/RPXClassic/config.mk
  3. 447
      board/RPXClassic/flash.c
  4. 195
      board/RPXlite/RPXlite.c
  5. 490
      board/iphase4539/flash.c
  6. 563
      board/sixnet/sixnet.c
  7. 1096
      cpu/mpc8xx/lcd.c
  8. 782
      cpu/mpc8xx/start.S
  9. 1265
      cpu/mpc8xx/video.c
  10. 358
      doc/README.IPHASE4539
  11. 21
      doc/README.RPXClassic
  12. 90
      doc/README.fads
  13. 30
      doc/README.video
  14. 85
      include/asm-ppc/u-boot.h
  15. 470
      include/configs/FADS823.h
  16. 717
      include/configs/GEN860T.h
  17. 348
      include/configs/NETVIA.h
  18. 439
      include/configs/RPXClassic.h
  19. 392
      include/configs/RPXlite.h
  20. 505
      include/configs/RPXsuper.h
  21. 689
      include/configs/ep8260.h
  22. 35
      include/hush.h
  23. 147
      include/image.h
  24. 949
      include/malloc.h
  25. 29
      include/version.h
  26. 202
      rtc/ds174x.c
  27. 4
      tools/easylogo/runme.sh
  28. 722
      tools/mkimage.c
  29. 68
      tools/scripts/README

290
board/RPXClassic/RPXClassic.c
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/*
* (C) Copyright 2001
* Stäubli Faverges - <www.staubli.com>
* Pierre AUBERT p.aubert@staubli.com
* U-Boot port on RPXClassic LF (CLLF_BW31) board
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <i2c.h>
#include <config.h>
#include <mpc8xx.h>
/* ------------------------------------------------------------------------- */
static long int dram_size (long int, long int *, long int);
static unsigned char aschex_to_byte (unsigned char *cp);
/* ------------------------------------------------------------------------- */
#define _NOT_USED_ 0xFFFFCC25
const uint sdram_table[] =
{
/*
* Single Read. (Offset 00h in UPMA RAM)
*/
0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08,
0x3FBFCC27, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Read. (Offset 08h in UPMA RAM)
*/
0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88,
0x3FBFCC27, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18h in UPMA RAM)
*/
0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00,
0x3FFFCC27, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20h in UPMA RAM)
*/
0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C,
0x0CFFCC00, 0x33FFCC27, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_,
/*
* Refresh. (Offset 30h in UPMA RAM)
*/
0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24,
0x3FFFCC27, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Exception. (Offset 3Ch in UPMA RAM)
*/
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
};
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity:
*/
int checkboard (void)
{
puts ("Board: RPXClassic\n");
return (0);
}
/*-----------------------------------------------------------------------------
* board_get_enetaddr -- Read the MAC Address in the I2C EEPROM
*-----------------------------------------------------------------------------
*/
void board_get_enetaddr (uchar * enet)
{
int i;
char buff[256], *cp;
/* Initialize I2C */
i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
/* Read 256 bytes in EEPROM */
i2c_read (0x54, 0, 1, buff, 128);
i2c_read (0x54, 128, 1, buff + 128, 128);
/* Retrieve MAC address in buffer (key EA) */
for (cp = buff;;) {
if (cp[0] == 'E' && cp[1] == 'A') {
cp += 3;
/* Read MAC address */
for (i = 0; i < 6; i++, cp += 2) {
enet[i] = aschex_to_byte (cp);
}
}
/* Scan to the end of the record */
while ((*cp != '\n') && (*cp != 0xff)) {
cp++;
}
/* If the next character is a \n, 0 or ff, we are done. */
cp++;
if ((*cp == '\n') || (*cp == 0) || (*cp == 0xff))
break;
}
#ifdef CONFIG_FEC_ENET
/* The MAC address is the same as normal ethernet except the 3rd byte */
/* (See the E.P. Planet Core Overview manual */
enet[3] |= 0x80;
/* Validate the fast ethernet tranceiver */
*((volatile uchar *) BCSR2) &= ~BCSR2_MIICTL;
*((volatile uchar *) BCSR2) &= ~BCSR2_MIIPWRDWN;
*((volatile uchar *) BCSR2) |= BCSR2_MIIRST;
*((volatile uchar *) BCSR2) |= BCSR2_MIIPWRDWN;
#endif
printf ("MAC address = %02x:%02x:%02x:%02x:%02x:%02x\n",
enet[0], enet[1], enet[2], enet[3], enet[4], enet[5]);
}
void rpxclassic_init (void)
{
/* Enable NVRAM */
*((uchar *) BCSR0) |= BCSR0_ENNVRAM;
}
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size10;
upmconfig (UPMA, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
/* Refresh clock prescalar */
memctl->memc_mptpr = CFG_MPTPR;
memctl->memc_mar = 0x00000000;
/* Map controller banks 1 to the SDRAM bank */
memctl->memc_or1 = CFG_OR1_PRELIM;
memctl->memc_br1 = CFG_BR1_PRELIM;
memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
udelay (200);
/* perform SDRAM initializsation sequence */
memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */
udelay (1);
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
udelay (1000);
/* Check Bank 0 Memory Size
* try 10 column mode
*/
size10 = dram_size (CFG_MAMR_10COL, (ulong *) SDRAM_BASE_PRELIM,
SDRAM_MAX_SIZE);
return (size10);
}
/* ------------------------------------------------------------------------- */
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof (long));
}
}
return (maxsize);
}
static unsigned char aschex_to_byte (unsigned char *cp)
{
u_char byte, c;
c = *cp++;
if ((c >= 'A') && (c <= 'F')) {
c -= 'A';
c += 10;
} else if ((c >= 'a') && (c <= 'f')) {
c -= 'a';
c += 10;
} else {
c -= '0';
}
byte = c * 16;
c = *cp;
if ((c >= 'A') && (c <= 'F')) {
c -= 'A';
c += 10;
} else if ((c >= 'a') && (c <= 'f')) {
c -= 'a';
c += 10;
} else {
c -= '0';
}
byte += c;
return (byte);
}

29
board/RPXClassic/config.mk
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#
# (C) Copyright 2001
# Stäubli Faverges - <www.staubli.com>
# Pierre AUBERT p.aubert@staubli.com
# U-Boot port on RPXClassic LF (CLLF_BW31) board
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
TEXT_BASE = 0xff000000

447
board/RPXClassic/flash.c
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/*
* (C) Copyright 2001
* Stäubli Faverges - <www.staubli.com>
* Pierre AUBERT p.aubert@staubli.com
* U-Boot port on RPXClassic LF (CLLF_BW31) board
*
* RPXClassic uses Am29DL323B flash memory with 2 banks
*
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc8xx.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
static void flash_get_offsets (ulong base, flash_info_t *info);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
unsigned long size_b0 ;
int i;
/* Init: no FLASHes known */
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
&flash_info[0]);
#endif
flash_info[0].size = size_b0;
return (size_b0);
}
/*-----------------------------------------------------------------------
*/
static void flash_get_offsets (ulong base, flash_info_t *info)
{
int i;
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00008000;
info->start[2] = base + 0x00010000;
info->start[3] = base + 0x00018000;
info->start[4] = base + 0x00020000;
info->start[5] = base + 0x00028000;
info->start[6] = base + 0x00030000;
info->start[7] = base + 0x00038000;
for (i = 8; i < info->sector_count; i++) {
info->start[i] = base + ((i-7) * 0x00040000) ;
}
}
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD: printf ("AMD "); break;
default: printf ("Unknown Vendor "); break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AMDL323B:
printf ("AMDL323DB (16 Mbytes, bottom boot sect)\n");
break;
default:
printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " "
);
}
printf ("\n");
}
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
{
short i;
ulong value;
ulong base = (ulong)addr;
/* Reset flash componeny */
addr [0] = 0xf0f0f0f0;
/* Write auto select command: read Manufacturer ID */
addr[0xAAA] = 0xAAAAAAAA ;
addr[0x555] = 0x55555555 ;
addr[0xAAA] = 0x90909090 ;
value = addr[0] ;
switch (value & 0x00FF00FF) {
case AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* no or unknown flash */
}
value = addr[2] ; /* device ID */
switch (value & 0x00FF00FF) {
case (AMD_ID_DL323B & 0x00FF00FF):
info->flash_id += FLASH_AMDL323B;
info->sector_count = 71;
info->size = 0x01000000; /* 16 Mb */
break;
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
}
/* set up sector start address table */
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00008000;
info->start[2] = base + 0x00010000;
info->start[3] = base + 0x00018000;
info->start[4] = base + 0x00020000;
info->start[5] = base + 0x00028000;
info->start[6] = base + 0x00030000;
info->start[7] = base + 0x00038000;
for (i = 8; i < info->sector_count; i++) {
info->start[i] = base + ((i-7) * 0x00040000) ;
}
/* check for protected sectors */
for (i = 0; i < 23; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
addr = (volatile unsigned long *)(info->start[i]);
info->protect[i] = addr[4] & 1 ;
}
/* Check for protected sectors in the 2nd bank */
addr[0x100AAA] = 0xAAAAAAAA ;
addr[0x100555] = 0x55555555 ;
addr[0x100AAA] = 0x90909090 ;
for (i = 23; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
addr = (volatile unsigned long *)(info->start[i]);
info->protect[i] = addr[4] & 1 ;
}
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
addr = (volatile unsigned long *)info->start[0];
*addr = 0xF0F0F0F0; /* reset bank 1 */
addr = (volatile unsigned long *)info->start[23];
*addr = 0xF0F0F0F0; /* reset bank 2 */
}
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
vu_long *addr = (vu_long*)(info->start[0]);
int flag, prot, sect, l_sect;
ulong start, now, last;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
if ((info->flash_id == FLASH_UNKNOWN) ||
(info->flash_id > FLASH_AMD_COMP)) {
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0xAAA] = 0xAAAAAAAA;
addr[0x555] = 0x55555555;
addr[0xAAA] = 0x80808080;
addr[0xAAA] = 0xAAAAAAAA;
addr[0x555] = 0x55555555;
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = (vu_long *)(info->start[sect]) ;
addr[0] = 0x30303030 ;
l_sect = sect;
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
start = get_timer (0);
last = start;
addr = (vu_long *)(info->start[l_sect]);
while ((addr[0] & 0x80808080) != 0x80808080) {
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
DONE:
/* reset to read mode */
addr = (vu_long *)info->start[0];
addr[0] = 0xF0F0F0F0; /* reset bank */
printf (" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
for (; i<4 && cnt>0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt==0 && i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
data = 0;
for (i=0; i<4; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
cnt -= 4;
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
return (write_word(info, wp, data));
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word (flash_info_t *info, ulong dest, ulong data)
{
vu_long *addr = (vu_long *)(info->start[0]);
ulong start;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*((vu_long *)dest) & data) != data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0xAAA] = 0xAAAAAAAA;
addr[0x555] = 0x55555555;
addr[0xAAA] = 0xA0A0A0A0;
*((vu_long *)dest) = data;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer (0);
while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
}
return (0);
}
/*-----------------------------------------------------------------------
*/

195
board/RPXlite/RPXlite.c
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/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
* U-Boot port on RPXlite board
*
* DRAM related UPMA register values are modified.
* See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS
*/
#include <common.h>
#include <mpc8xx.h>
/* ------------------------------------------------------------------------- */
static long int dram_size (long int, long int *, long int);
/* ------------------------------------------------------------------------- */
#define _NOT_USED_ 0xFFFFCC25
const uint sdram_table[] =
{
/*
* Single Read. (Offset 00h in UPMA RAM)
*/
0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08,
0x3FBFCC27, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Read. (Offset 08h in UPMA RAM)
*/
0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88,
0x3FBFCC27, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18h in UPMA RAM)
*/
0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00,
0x3FFFCC27, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20h in UPMA RAM)
*/
0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C,
0x0CFFCC00, 0x33FFCC27, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_,
/*
* Refresh. (Offset 30h in UPMA RAM)
*/
0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24,
0x3FFFCC27, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Exception. (Offset 3Ch in UPMA RAM)
*/
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
};
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity:
*/
int checkboard (void)
{
puts ("Board: RPXlite\n") ;
return (0) ;
}
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size10 ;
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
/* Refresh clock prescalar */
memctl->memc_mptpr = CFG_MPTPR ;
memctl->memc_mar = 0x00000000;
/* Map controller banks 1 to the SDRAM bank */
memctl->memc_or1 = CFG_OR1_PRELIM;
memctl->memc_br1 = CFG_BR1_PRELIM;
memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
udelay(200);
/* perform SDRAM initializsation sequence */
memctl->memc_mcr = 0x80002230 ; /* SDRAM bank 0 - refresh twice */
udelay(1);
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
udelay (1000);
/* Check Bank 0 Memory Size
* try 10 column mode
*/
size10 = dram_size (CFG_MAMR_10COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE) ;
return (size10);
}
/* ------------------------------------------------------------------------- */
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof(long));
}
}
return (maxsize);
}

490
board/iphase4539/flash.c
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/*
* (C) Copyright 2001
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Adapted for Interphase 4539 by Wolfgang Grandegger <wg@denx.de>.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <flash.h>
#include <asm/io.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
extern int hwc_flash_size(void);
static ulong flash_get_size (u32 addr, flash_info_t *info);
static int flash_get_offsets (u32 base, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
static void flash_reset (u32 addr);
#define out8(a,v) *(volatile unsigned char*)(a) = v
#define in8(a) *(volatile unsigned char*)(a)
#define in32(a) *(volatile unsigned long*)(a)
#define iobarrier_rw() eieio()
unsigned long flash_init (void)
{
unsigned int i;
unsigned long flash_size = 0;
unsigned long bank_size;
unsigned int bank = 0;
/* Init: no FLASHes known */
for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
flash_info[i].sector_count = 0;
flash_info[i].size = 0;
}
/* Initialise the BOOT Flash */
if (bank == CFG_MAX_FLASH_BANKS) {
puts ("Warning: not all Flashes are initialised !");
return flash_size;
}
bank_size = flash_get_size (CFG_FLASH_BASE, flash_info + bank);
if (bank_size) {
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE && \
CFG_MONITOR_BASE < CFG_FLASH_BASE + CFG_MAX_FLASH_SIZE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
flash_info + bank);
#endif
#ifdef CFG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
flash_info + bank);
#endif
/* HWC protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_FLASH_BASE,
CFG_FLASH_BASE + 0x10000 - 1,
flash_info + bank);
flash_size += bank_size;
bank++;
} else {
puts ("Warning: the BOOT Flash is not initialised !");
}
return flash_size;
}
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (u32 addr, flash_info_t *info)
{
volatile uchar value;
#if 0
int i;
#endif
/* Write auto select command: read Manufacturer ID */
out8(addr + 0x0555, 0xAA);
iobarrier_rw();
udelay(10);
out8(addr + 0x02AA, 0x55);
iobarrier_rw();
udelay(10);
out8(addr + 0x0555, 0x90);
iobarrier_rw();
udelay(10);
value = in8(addr);
iobarrier_rw();
udelay(10);
switch (value | (value << 16)) {
case AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
case FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;
break;
default:
info->flash_id = FLASH_UNKNOWN;
flash_reset (addr);
return 0;
}
value = in8(addr + 1); /* device ID */
iobarrier_rw();
switch (value) {
case AMD_ID_LV033C:
info->flash_id += FLASH_AM033C;
info->size = hwc_flash_size();
if (info->size > CFG_MAX_FLASH_SIZE) {
printf("U-Boot supports only %d MB\n",
CFG_MAX_FLASH_SIZE);
info->size = CFG_MAX_FLASH_SIZE;
}
info->sector_count = info->size / 0x10000;
break; /* => 4 MB */
default:
info->flash_id = FLASH_UNKNOWN;
flash_reset (addr);
return (0); /* => no or unknown flash */
}
if (!flash_get_offsets (addr, info)) {
flash_reset (addr);
return 0;
}
#if 0
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
value = in8(info->start[i] + 2);
iobarrier_rw();
info->protect[i] = (value & 1) != 0;
}
#endif
/*
* Reset bank to read mode
*/
flash_reset (addr);
return (info->size);
}
static int flash_get_offsets (u32 base, flash_info_t *info)
{
unsigned int i, size;
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM033C:
/* set sector offsets for uniform sector type */
size = info->size / info->sector_count;
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base + i * size;
}
break;
default:
return 0;
}
return 1;
}
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
volatile u32 addr = info->start[0];
int flag, prot, sect, l_sect;
ulong start, now, last;
if (s_first < 0 || s_first > s_last) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
if (info->flash_id == FLASH_UNKNOWN ||
info->flash_id > FLASH_AMD_COMP) {
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
out8(addr + 0x555, 0xAA);
iobarrier_rw();
out8(addr + 0x2AA, 0x55);
iobarrier_rw();
out8(addr + 0x555, 0x80);
iobarrier_rw();
out8(addr + 0x555, 0xAA);
iobarrier_rw();
out8(addr + 0x2AA, 0x55);
iobarrier_rw();
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = info->start[sect];
out8(addr, 0x30);
iobarrier_rw();
l_sect = sect;
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
start = get_timer (0);
last = start;
addr = info->start[l_sect];
while ((in8(addr) & 0x80) != 0x80) {
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
iobarrier_rw();
}
DONE:
/* reset to read mode */
flash_reset (info->start[0]);
printf (" done\n");
return 0;
}
/*
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
for (; i<4 && cnt>0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt==0 && i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
data = 0;
for (i=0; i<4; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
cnt -= 4;
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
return (write_word(info, wp, data));
}
/*
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word (flash_info_t *info, ulong dest, ulong data)
{
volatile u32 addr = info->start[0];
ulong start;
int flag, i;
/* Check if Flash is (sufficiently) erased */
if ((in32(dest) & data) != data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
/* first, perform an unlock bypass command to speed up flash writes */
out8(addr + 0x555, 0xAA);
iobarrier_rw();
out8(addr + 0x2AA, 0x55);
iobarrier_rw();
out8(addr + 0x555, 0x20);
iobarrier_rw();
/* write each byte out */
for (i = 0; i < 4; i++) {
char *data_ch = (char *)&data;
out8(addr, 0xA0);
iobarrier_rw();
out8(dest+i, data_ch[i]);
iobarrier_rw();
udelay(10); /* XXX */
}
/* we're done, now do an unlock bypass reset */
out8(addr, 0x90);
iobarrier_rw();
out8(addr, 0x00);
iobarrier_rw();
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer (0);
while ((in32(dest) & 0x80808080) != (data & 0x80808080)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
iobarrier_rw();
}
flash_reset (addr);
return (0);
}
/*
* Reset bank to read mode
*/
static void flash_reset (u32 addr)
{
out8(addr, 0xF0); /* reset bank */
iobarrier_rw();
}
void flash_print_info (flash_info_t *info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD: printf ("AMD "); break;
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
default: printf ("Unknown Vendor "); break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM033C: printf ("AM29LV033C (32 Mbit, uniform sectors)\n");
break;
default: printf ("Unknown Chip Type\n");
break;
}
if (info->size % 0x100000 == 0) {
printf (" Size: %ld MB in %d Sectors\n",
info->size / 0x100000, info->sector_count);
}
else if (info->size % 0x400 == 0) {
printf (" Size: %ld KB in %d Sectors\n",
info->size / 0x400, info->sector_count);
}
else {
printf (" Size: %ld B in %d Sectors\n",
info->size, info->sector_count);
}
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " "
);
}
printf ("\n");
}

563
board/sixnet/sixnet.c
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/*
* (C) Copyright 2001, 2002
* Dave Ellis, SIXNET, dge@sixnetio.com.
* Based on code by:
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* and other contributors to U-Boot. See file CREDITS for list
* of people who contributed to this project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <config.h>
#include <mpc8xx.h>
#include <net.h> /* for eth_init() */
#include <rtc.h>
#include "sixnet.h"
#define ORMASK(size) ((-size) & OR_AM_MSK)
static long ram_size(ulong *, long);
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity:
* returns 0 if recognized, -1 if unknown
*/
int checkboard (void)
{
puts ("Board: SIXNET SXNI855T\n");
return 0;
}
/* ------------------------------------------------------------------------- */
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
#error "SXNI855T has no PCMCIA port"
#endif /* CFG_CMD_PCMCIA */
/* ------------------------------------------------------------------------- */
#define _not_used_ 0xffffffff
/* UPMB table for dual UART. */
/* this table is for 50MHz operation, it should work at all lower speeds */
const uint duart_table[] =
{
/* single read. (offset 0 in upm RAM) */
0xfffffc04, 0x0ffffc04, 0x0ff3fc04, 0x0ff3fc04,
0x0ff3fc00, 0x0ff3fc04, 0xfffffc04, 0xfffffc05,
/* burst read. (offset 8 in upm RAM) */
_not_used_, _not_used_, _not_used_, _not_used_,
_not_used_, _not_used_, _not_used_, _not_used_,
_not_used_, _not_used_, _not_used_, _not_used_,
_not_used_, _not_used_, _not_used_, _not_used_,
/* single write. (offset 18 in upm RAM) */
0xfffffc04, 0x0ffffc04, 0x00fffc04, 0x00fffc04,
0x00fffc04, 0x00fffc00, 0xfffffc04, 0xfffffc05,
/* burst write. (offset 20 in upm RAM) */
_not_used_, _not_used_, _not_used_, _not_used_,
_not_used_, _not_used_, _not_used_, _not_used_,
_not_used_, _not_used_, _not_used_, _not_used_,
_not_used_, _not_used_, _not_used_, _not_used_,
/* refresh. (offset 30 in upm RAM) */
_not_used_, _not_used_, _not_used_, _not_used_,
_not_used_, _not_used_, _not_used_, _not_used_,
_not_used_, _not_used_, _not_used_, _not_used_,
/* exception. (offset 3c in upm RAM) */
_not_used_, _not_used_, _not_used_, _not_used_,
};
/* Load FPGA very early in boot sequence, since it must be
* loaded before the 16C2550 serial channels can be used as
* console channels.
*
* Note: Much of the configuration is not complete. The
* stack is in DPRAM since SDRAM has not been initialized,
* so the stack must be kept small. Global variables
* are still in FLASH, so they cannot be written.
* Only the FLASH, DPRAM, immap and FPGA can be addressed,
* the other chip selects may not have been initialized.
* The clocks have been initialized, so udelay() can be
* used.
*/
#define FPGA_DONE 0x0080 /* PA8, input, high when FPGA load complete */
#define FPGA_PROGRAM_L 0x0040 /* PA9, output, low to reset, high to start */
#define FPGA_INIT_L 0x0020 /* PA10, input, low indicates not ready */
#define fpga (*(volatile unsigned char *)(CFG_FPGA_PROG)) /* FPGA port */
int board_postclk_init (void)
{
/* the data to load to the XCSxxXL FPGA */
static const unsigned char fpgadata[] = {
# include "fpgadata.c"
};
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
#define porta (immap->im_ioport.iop_padat)
const unsigned char* pdata;
/* /INITFPGA and DONEFPGA signals are inputs */
immap->im_ioport.iop_padir &= ~(FPGA_INIT_L | FPGA_DONE);
/* Force output pin to begin at 0, /PROGRAM asserted (0) resets FPGA */
porta &= ~FPGA_PROGRAM_L;
/* Set FPGA as an output */
immap->im_ioport.iop_padir |= FPGA_PROGRAM_L;
/* delay a little to make sure FPGA sees it, really
* only need less than a microsecond.
*/
udelay(10);
/* unassert /PROGRAM */
porta |= FPGA_PROGRAM_L;
/* delay while FPGA does last erase, indicated by
* /INITFPGA going high. This should happen within a
* few milliseconds.
*/
/* ### FIXME - a timeout check would be good, maybe flash
* the status LED to indicate the error?
*/
while ((porta & FPGA_INIT_L) == 0)
; /* waiting */
/* write program data to FPGA at the programming address
* so extra /CS1 strobes at end of configuration don't actually
* write to any registers.
*/
fpga = 0xff; /* first write is ignored */
fpga = 0xff; /* fill byte */
fpga = 0xff; /* fill byte */
fpga = 0x4f; /* preamble code */
fpga = 0x80; fpga = 0xaf; fpga = 0x9b; /* length (ignored) */
fpga = 0x4b; /* field check code */
pdata = fpgadata;
/* while no error write out each of the 28 byte frames */
while ((porta & (FPGA_INIT_L | FPGA_DONE)) == FPGA_INIT_L
&& pdata < fpgadata + sizeof(fpgadata)) {
fpga = 0x4f; /* preamble code */
/* 21 bytes of data in a frame */
fpga = *(pdata++); fpga = *(pdata++);
fpga = *(pdata++); fpga = *(pdata++);
fpga = *(pdata++); fpga = *(pdata++);
fpga = *(pdata++); fpga = *(pdata++);
fpga = *(pdata++); fpga = *(pdata++);
fpga = *(pdata++); fpga = *(pdata++);
fpga = *(pdata++); fpga = *(pdata++);
fpga = *(pdata++); fpga = *(pdata++);
fpga = *(pdata++); fpga = *(pdata++);
fpga = *(pdata++); fpga = *(pdata++);
fpga = *(pdata++);
fpga = 0x4b; /* field check code */
fpga = 0xff; /* extended write cycle */
fpga = 0x4b; /* extended write cycle
* (actually 0x4b from bitgen.exe)
*/
fpga = 0xff; /* extended write cycle */
fpga = 0xff; /* extended write cycle */
fpga = 0xff; /* extended write cycle */
}
fpga = 0xff; /* startup byte */
fpga = 0xff; /* startup byte */
fpga = 0xff; /* startup byte */
fpga = 0xff; /* startup byte */
#if 0 /* ### FIXME */
/* If didn't load all the data or FPGA_DONE is low the load failed.
* Maybe someday stop here and flash the status LED? The console
* is not configured, so can't print an error message. Can't write
* global variables to set a flag (except gd?).
* For now it must work.
*/
#endif
/* Now that the FPGA is loaded, set up the Dual UART chip
* selects. Must be done here since it may be used as the console.
*/
upmconfig(UPMB, (uint *)duart_table, sizeof(duart_table)/sizeof(uint));
memctl->memc_mbmr = DUART_MBMR;
memctl->memc_or5 = DUART_OR_VALUE;
memctl->memc_br5 = DUART_BR5_VALUE;
memctl->memc_or6 = DUART_OR_VALUE;
memctl->memc_br6 = DUART_BR6_VALUE;
return (0);
}
/* ------------------------------------------------------------------------- */
/* base address for SRAM, assume 32-bit port, valid */
#define NVRAM_BR_VALUE (CFG_SRAM_BASE | BR_PS_32 | BR_V)
/* up to 64MB - will be adjusted for actual size */
#define NVRAM_OR_PRELIM (ORMASK(CFG_SRAM_SIZE) \
| OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR)
/*
* Miscellaneous platform dependent initializations after running in RAM.
*/
int misc_init_r (void)
{
DECLARE_GLOBAL_DATA_PTR;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
bd_t *bd = gd->bd;
memctl->memc_or2 = NVRAM_OR_PRELIM;
memctl->memc_br2 = NVRAM_BR_VALUE;
/* Is there any SRAM? Is it 16 or 32 bits wide? */
/* First look for 32-bit SRAM */
bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE);
if (bd->bi_sramsize == 0) {
/* no 32-bit SRAM, but there could be 16-bit SRAM since
* it would report size 0 when configured for 32-bit bus.
* Try again with a 16-bit bus.
*/
memctl->memc_br2 |= BR_PS_16;
bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE);
}
if (bd->bi_sramsize == 0) {
memctl->memc_br2 = 0; /* disable select since nothing there */
}
else {
/* adjust or2 for actual size of SRAM */
memctl->memc_or2 |= ORMASK(bd->bi_sramsize);
bd->bi_sramstart = CFG_SRAM_BASE;
printf("SRAM: %lu KB\n", bd->bi_sramsize >> 10);
}
/* set standard MPC8xx clock so kernel will see the time
* even if it doesn't have a DS1306 clock driver.
* This helps with experimenting with standard kernels.
*/
{
ulong tim;
struct rtc_time tmp;
rtc_get(&tmp); /* get time from DS1306 RTC */
/* convert to seconds since 1970 */
tim = mktime(tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
immap->im_sitk.sitk_rtck = KAPWR_KEY;
immap->im_sit.sit_rtc = tim;
}
#if 0
/* The code below is no longer valid since the prototype of
* eth_init() and eth_halt() have been changed to support
* multi-ethernet feature in U-Boot; the eth_initialize()
* routine should be called before any access to the ethernet
* callbacks.
*/
/* FIXME - for now init ethernet to force PHY special mode */
eth_init(bd);
eth_halt();
#endif
return (0);
}
/* ------------------------------------------------------------------------- */
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'.
*
* The memory size MUST be a power of 2 for this to work.
*
* The only memory modified is 4 bytes at offset 0. This is important
* since for the SRAM this location is reserved for autosizing, so if
* it is modified and the board is reset before ram_size() completes
* no damage is done. Normally even the memory at 0 is preserved. The
* higher SRAM addresses may contain battery backed RAM disk data which
* must never be corrupted.
*/
static long ram_size(ulong *base, long maxsize)
{
volatile long *test_addr;
volatile long *base_addr = base;
volatile long *flash = (volatile long*)CFG_FLASH_BASE;
ulong ofs; /* byte offset from base_addr */
ulong save; /* to make test non-destructive */
ulong junk;
long ramsize = -1; /* size not determined yet */
save = *base_addr; /* save value at 0 so can restore */
/* is any SRAM present? */
*base_addr = 0x5555aaaa;
/* use flash read to modify data bus, since with no SRAM present
* the data bus may retain the value if our code is running
* completely in the cache.
*/
junk = *flash;
if (*base_addr != 0x5555aaaa)
ramsize = 0; /* no RAM present, or defective */
else {
*base_addr = 0xaaaa5555;
junk = *flash; /* use flash read to modify data bus */
if (*base_addr != 0xaaaa5555)
ramsize = 0; /* no RAM present, or defective */
}
/* now size it if any is present */
for (ofs = 4; ofs < maxsize && ramsize < 0; ofs <<= 1) {
test_addr = (long*)((long)base_addr + ofs); /* location to test */
*base_addr = ~*test_addr;
if (*base_addr == *test_addr)
ramsize = ofs; /* wrapped back to 0, so this is the size */
}
*base_addr = save; /* restore value at 0 */
return (ramsize);
}
/* ------------------------------------------------------------------------- */
/* sdram table based on the FADS manual */
/* for chip MB811171622A-100 */
/* this table is for 50MHz operation, it should work at all lower speeds */
const uint sdram_table[] =
{
/* single read. (offset 0 in upm RAM) */
0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
0x1ff77c47,
/* precharge and Mode Register Set initialization (offset 5).
* This is also entered at offset 6 to do Mode Register Set
* without the precharge.
*/
0x1ff77c34, 0xefeabc34, 0x1fb57c35,
/* burst read. (offset 8 in upm RAM) */
0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
_not_used_, _not_used_, _not_used_, _not_used_,
_not_used_, _not_used_, _not_used_, _not_used_,
/* single write. (offset 18 in upm RAM) */
/* FADS had 0x1f27fc04, ...
* but most other boards have 0x1f07fc04, which
* sets GPL0 from A11MPC to 0 1/4 clock earlier,
* like the single read.
* This seems better so I am going with the change.
*/
0x1f07fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
_not_used_, _not_used_, _not_used_, _not_used_,
/* burst write. (offset 20 in upm RAM) */
0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
_not_used_, _not_used_, _not_used_, _not_used_,
_not_used_, _not_used_, _not_used_, _not_used_,
/* refresh. (offset 30 in upm RAM) */
0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
_not_used_, _not_used_, _not_used_, _not_used_,
/* exception. (offset 3c in upm RAM) */
0x7ffffc07, _not_used_, _not_used_, _not_used_ };
/* ------------------------------------------------------------------------- */
#define SDRAM_MAX_SIZE 0x10000000 /* max 256 MB SDRAM */
/* precharge and set Mode Register */
#define SDRAM_MCR_PRE (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \
MCR_MB_CS3 | /* chip select */ \
MCR_MLCF(1) | MCR_MAD(5)) /* 1 time at 0x05 */
/* set Mode Register, no precharge */
#define SDRAM_MCR_MRS (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \
MCR_MB_CS3 | /* chip select */ \
MCR_MLCF(1) | MCR_MAD(6)) /* 1 time at 0x06 */
/* runs refresh loop twice so get 8 refresh cycles */
#define SDRAM_MCR_REFR (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \
MCR_MB_CS3 | /* chip select */ \
MCR_MLCF(2) | MCR_MAD(0x30)) /* twice at 0x30 */
/* MAMR values work in either mamr or mbmr */
/* 8 column SDRAM */
#define SDRAM_MAMR_8COL /* refresh at 50MHz */ \
((195 << MAMR_PTA_SHIFT) | MAMR_PTAE \
| MAMR_AMA_TYPE_0 /* Address MUX 0 */ \
| MAMR_DSA_1_CYCL /* 1 cycle disable */ \
| MAMR_G0CLA_A11 /* GPL0 A11[MPC] */ \
| MAMR_RLFA_1X /* Read loop 1 time */ \
| MAMR_WLFA_1X /* Write loop 1 time */ \
| MAMR_TLFA_4X) /* Timer loop 4 times */
/* 9 column SDRAM */
#define SDRAM_MAMR_9COL ((SDRAM_MAMR_8COL & (~MAMR_G0CLA_A11)) | MAMR_G0CLA_A10)
/* base address 0, 32-bit port, SDRAM UPM, valid */
#define SDRAM_BR_VALUE (BR_PS_32 | BR_MS_UPMA | BR_V)
/* up to 256MB, SAM, G5LS - will be adjusted for actual size */
#define SDRAM_OR_PRELIM (ORMASK(SDRAM_MAX_SIZE) | OR_CSNT_SAM | OR_G5LS)
/* This is the Mode Select Register value for the SDRAM.
* Burst length: 4
* Burst Type: sequential
* CAS Latency: 2
* Write Burst Length: burst
*/
#define SDRAM_MODE 0x22 /* CAS latency 2, burst length 4 */
/* ------------------------------------------------------------------------- */
long int initdram(int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
uint size_sdram = 0;
uint size_sdram9 = 0;
uint base = 0; /* SDRAM must start at 0 */
int i;
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
/* Configure the refresh (mostly). This needs to be
* based upon processor clock speed and optimized to provide
* the highest level of performance.
*
* Preliminary prescaler for refresh.
* This value is selected for four cycles in 31.2 us,
* which gives 8192 cycles in 64 milliseconds.
* This may be too fast, but works for any memory.
* It is adjusted to 4096 cycles in 64 milliseconds if
* possible once we know what memory we have.
*
* We have to be careful changing UPM registers after we
* ask it to run these commands.
*
* PTA - periodic timer period for our design is
* 50 MHz x 31.2us
* --------------- = 195
* 1 x 8 x 1
*
* 50MHz clock
* 31.2us refresh interval
* SCCR[DFBRG] 0
* PTP divide by 8
* 1 chip select
*/
memctl->memc_mptpr = MPTPR_PTP_DIV8; /* 0x0800 */
memctl->memc_mamr = SDRAM_MAMR_8COL & (~MAMR_PTAE); /* no refresh yet */
/* The SDRAM Mode Register value is shifted left 2 bits since
* A30 and A31 don't connect to the SDRAM for 32-bit wide memory.
*/
memctl->memc_mar = SDRAM_MODE << 2; /* MRS code */
udelay(200); /* SDRAM needs 200uS before set it up */
/* Now run the precharge/nop/mrs commands. */
memctl->memc_mcr = SDRAM_MCR_PRE;
udelay(2);
/* Run 8 refresh cycles (2 sets of 4) */
memctl->memc_mcr = SDRAM_MCR_REFR; /* run refresh twice */
udelay(2);
/* some brands want Mode Register set after the refresh
* cycles. This shouldn't hurt anything for the brands
* that were happy with the first time we set it.
*/
memctl->memc_mcr = SDRAM_MCR_MRS;
udelay(2);
memctl->memc_mamr = SDRAM_MAMR_8COL; /* enable refresh */
memctl->memc_or3 = SDRAM_OR_PRELIM;
memctl->memc_br3 = SDRAM_BR_VALUE + base;
/* Some brands need at least 10 DRAM accesses to stabilize.
* It wont hurt the brands that don't.
*/
for (i=0; i<10; ++i) {
volatile ulong *addr = (volatile ulong *)base;
ulong val;
val = *(addr + i);
*(addr + i) = val;
}
/* Check SDRAM memory Size in 8 column mode.
* For a 9 column memory we will get half the actual size.
*/
size_sdram = ram_size((ulong *)0, SDRAM_MAX_SIZE);
/* Check SDRAM memory Size in 9 column mode.
* For an 8 column memory we will see at most 4 megabytes.
*/
memctl->memc_mamr = SDRAM_MAMR_9COL;
size_sdram9 = ram_size((ulong *)0, SDRAM_MAX_SIZE);
if (size_sdram < size_sdram9) /* leave configuration at 9 columns */
size_sdram = size_sdram9;
else /* go back to 8 columns */
memctl->memc_mamr = SDRAM_MAMR_8COL;
/* adjust or3 for actual size of SDRAM
*/
memctl->memc_or3 |= ORMASK(size_sdram);
/* Adjust refresh rate depending on SDRAM type.
* For types > 128 MBit (32 Mbyte for 2 x16 devices) leave
* it at the current (fast) rate.
* For 16, 64 and 128 MBit half the rate will do.
*/
if (size_sdram <= 32 * 1024 * 1024)
memctl->memc_mptpr = MPTPR_PTP_DIV16; /* 0x0400 */
return (size_sdram);
}

1096
cpu/mpc8xx/lcd.c
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782
cpu/mpc8xx/start.S
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/*
* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* U-Boot - Startup Code for PowerPC based Embedded Boards
*
*
* The processor starts at 0x00000100 and the code is executed
* from flash. The code is organized to be at an other address
* in memory, but as long we don't jump around before relocating.
* board_init lies at a quite high address and when the cpu has
* jumped there, everything is ok.
* This works because the cpu gives the FLASH (CS0) the whole
* address space at startup, and board_init lies as a echo of
* the flash somewhere up there in the memorymap.
*
* board_init will change CS0 to be positioned at the correct
* address and (s)dram will be positioned at address 0
*/
#include <config.h>
#include <mpc8xx.h>
#include <version.h>
#define CONFIG_8xx 1 /* needed for Linux kernel header files */
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#ifndef CONFIG_IDENT_STRING
#define CONFIG_IDENT_STRING ""
#endif
/* We don't want the MMU yet.
*/
#undef MSR_KERNEL
#define MSR_KERNEL ( MSR_ME | MSR_RI ) /* Machine Check and Recoverable Interr. */
/*
* Set up GOT: Global Offset Table
*
* Use r14 to access the GOT
*/
START_GOT
GOT_ENTRY(_GOT2_TABLE_)
GOT_ENTRY(_FIXUP_TABLE_)
GOT_ENTRY(_start)
GOT_ENTRY(_start_of_vectors)
GOT_ENTRY(_end_of_vectors)
GOT_ENTRY(transfer_to_handler)
GOT_ENTRY(_end)
GOT_ENTRY(.bss)
#if defined(CONFIG_FADS) || defined(CONFIG_ICU862)
GOT_ENTRY(environment)
#endif
END_GOT
/*
* r3 - 1st arg to board_init(): IMMP pointer
* r4 - 2nd arg to board_init(): boot flag
*/
.text
.long 0x27051956 /* U-Boot Magic Number */
.globl version_string
version_string:
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"
. = EXC_OFF_SYS_RESET
.globl _start
_start:
lis r3, CFG_IMMR@h /* position IMMR */
mtspr 638, r3
li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
b boot_cold
. = EXC_OFF_SYS_RESET + 0x10
.globl _start_warm
_start_warm:
li r21, BOOTFLAG_WARM /* Software reboot */
b boot_warm
boot_cold:
boot_warm:
/* Initialize machine status; enable machine check interrupt */
/*----------------------------------------------------------------------*/
li r3, MSR_KERNEL /* Set ME, RI flags */
mtmsr r3
mtspr SRR1, r3 /* Make SRR1 match MSR */
mfspr r3, ICR /* clear Interrupt Cause Register */
/* Initialize debug port registers */
/*----------------------------------------------------------------------*/
xor r0, r0, r0 /* Clear R0 */
mtspr LCTRL1, r0 /* Initialize debug port regs */
mtspr LCTRL2, r0
mtspr COUNTA, r0
mtspr COUNTB, r0
/* Reset the caches */
/*----------------------------------------------------------------------*/
mfspr r3, IC_CST /* Clear error bits */
mfspr r3, DC_CST
lis r3, IDC_UNALL@h /* Unlock all */
mtspr IC_CST, r3
mtspr DC_CST, r3
lis r3, IDC_INVALL@h /* Invalidate all */
mtspr IC_CST, r3
mtspr DC_CST, r3
lis r3, IDC_DISABLE@h /* Disable data cache */
mtspr DC_CST, r3
#if !(defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || defined (CONFIG_FLAGADM))
/* On IP860 and PCU E,
* we cannot enable IC yet
*/
lis r3, IDC_ENABLE@h /* Enable instruction cache */
#endif
mtspr IC_CST, r3
/* invalidate all tlb's */
/*----------------------------------------------------------------------*/
tlbia
isync
/*
* Calculate absolute address in FLASH and jump there
*----------------------------------------------------------------------*/
lis r3, CFG_MONITOR_BASE@h
ori r3, r3, CFG_MONITOR_BASE@l
addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
mtlr r3
blr
in_flash:
/* initialize some SPRs that are hard to access from C */
/*----------------------------------------------------------------------*/
lis r3, CFG_IMMR@h /* pass IMMR as arg1 to C routine */
ori r1, r3, CFG_INIT_SP_OFFSET /* set up the stack in internal DPRAM */
/* Note: R0 is still 0 here */
stwu r0, -4(r1) /* clear final stack frame so that */
stwu r0, -4(r1) /* stack backtraces terminate cleanly */
/*
* Disable serialized ifetch and show cycles
* (i.e. set processor to normal mode).
* This is also a silicon bug workaround, see errata
*/
li r2, 0x0007
mtspr ICTRL, r2
/* Set up debug mode entry */
lis r2, CFG_DER@h
ori r2, r2, CFG_DER@l
mtspr DER, r2
/* let the C-code set up the rest */
/* */
/* Be careful to keep code relocatable ! */
/*----------------------------------------------------------------------*/
GET_GOT /* initialize GOT access */
/* r3: IMMR */
bl cpu_init_f /* run low-level CPU init code (from Flash) */
mr r3, r21
/* r3: BOOTFLAG */
bl board_init_f /* run 1st part of board init code (from Flash) */
.globl _start_of_vectors
_start_of_vectors:
/* Machine check */
STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
/* Data Storage exception. "Never" generated on the 860. */
STD_EXCEPTION(0x300, DataStorage, UnknownException)
/* Instruction Storage exception. "Never" generated on the 860. */
STD_EXCEPTION(0x400, InstStorage, UnknownException)
/* External Interrupt exception. */
STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
stw r5,_DSISR(r21)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
lwz r6,GOT(transfer_to_handler)
mtlr r6
blrl
.L_Alignment:
.long AlignmentException - _start + EXC_OFF_SYS_RESET
.long int_return - _start + EXC_OFF_SYS_RESET
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
lwz r6,GOT(transfer_to_handler)
mtlr r6
blrl
.L_ProgramCheck:
.long ProgramCheckException - _start + EXC_OFF_SYS_RESET
.long int_return - _start + EXC_OFF_SYS_RESET
/* No FPU on MPC8xx. This exception is not supposed to happen.
*/
STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
/* I guess we could implement decrementer, and may have
* to someday for timekeeping.
*/
STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
. = 0xc00
/*
* r0 - SYSCALL number
* r3-... arguments
*/
SystemCall:
addis r11,r0,0 /* get functions table addr */
ori r11,r11,0 /* Note: this code is patched in trap_init */
addis r12,r0,0 /* get number of functions */
ori r12,r12,0
cmplw 0, r0, r12
bge 1f
rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
add r11,r11,r0
lwz r11,0(r11)
li r12,0xd00-4*3 /* save LR & SRRx */
mflr r0
stw r0,0(r12)
mfspr r0,SRR0
stw r0,4(r12)
mfspr r0,SRR1
stw r0,8(r12)
li r12,0xc00+_back-SystemCall
mtlr r12
mtspr SRR0,r11
1: SYNC
rfi
_back:
mfmsr r11 /* Disable interrupts */
li r12,0
ori r12,r12,MSR_EE
andc r11,r11,r12
SYNC /* Some chip revs need this... */
mtmsr r11
SYNC
li r12,0xd00-4*3 /* restore regs */
lwz r11,0(r12)
mtlr r11
lwz r11,4(r12)
mtspr SRR0,r11
lwz r11,8(r12)
mtspr SRR1,r11
SYNC
rfi
STD_EXCEPTION(0xd00, SingleStep, UnknownException)
STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
/* On the MPC8xx, this is a software emulation interrupt. It occurs
* for all unimplemented and illegal instructions.
*/
STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
STD_EXCEPTION(0x1500, Reserved5, UnknownException)
STD_EXCEPTION(0x1600, Reserved6, UnknownException)
STD_EXCEPTION(0x1700, Reserved7, UnknownException)
STD_EXCEPTION(0x1800, Reserved8, UnknownException)
STD_EXCEPTION(0x1900, Reserved9, UnknownException)
STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
.globl _end_of_vectors
_end_of_vectors:
. = 0x2000
/*
* This code finishes saving the registers to the exception frame
* and jumps to the appropriate handler for the exception.
* Register r21 is pointer into trap frame, r1 has new stack pointer.
*/
.globl transfer_to_handler
transfer_to_handler:
stw r22,_NIP(r21)
lis r22,MSR_POW@h
andc r23,r23,r22
stw r23,_MSR(r21)
SAVE_GPR(7, r21)
SAVE_4GPRS(8, r21)
SAVE_8GPRS(12, r21)
SAVE_8GPRS(24, r21)
mflr r23
andi. r24,r23,0x3f00 /* get vector offset */
stw r24,TRAP(r21)
li r22,0
stw r22,RESULT(r21)
mtspr SPRG2,r22 /* r1 is now kernel sp */
lwz r24,0(r23) /* virtual address of handler */
lwz r23,4(r23) /* where to go when done */
mtspr SRR0,r24
mtspr SRR1,r20
mtlr r23
SYNC
rfi /* jump to handler, enable MMU */
int_return:
mfmsr r28 /* Disable interrupts */
li r4,0
ori r4,r4,MSR_EE
andc r28,r28,r4
SYNC /* Some chip revs need this... */
mtmsr r28
SYNC
lwz r2,_CTR(r1)
lwz r0,_LINK(r1)
mtctr r2
mtlr r0
lwz r2,_XER(r1)
lwz r0,_CCR(r1)
mtspr XER,r2
mtcrf 0xFF,r0
REST_10GPRS(3, r1)
REST_10GPRS(13, r1)
REST_8GPRS(23, r1)
REST_GPR(31, r1)
lwz r2,_NIP(r1) /* Restore environment */
lwz r0,_MSR(r1)
mtspr SRR0,r2
mtspr SRR1,r0
lwz r0,GPR0(r1)
lwz r2,GPR2(r1)
lwz r1,GPR1(r1)
SYNC
rfi
/* Cache functions.
*/
.globl icache_enable
icache_enable:
SYNC
lis r3, IDC_INVALL@h
mtspr IC_CST, r3
lis r3, IDC_ENABLE@h
mtspr IC_CST, r3
blr
.globl icache_disable
icache_disable:
SYNC
lis r3, IDC_DISABLE@h
mtspr IC_CST, r3
blr
.globl icache_status
icache_status:
mfspr r3, IC_CST
srwi r3, r3, 31 /* >>31 => select bit 0 */
blr
.globl dcache_enable
dcache_enable:
#if 0
SYNC
#endif
#if 1
lis r3, 0x0400 /* Set cache mode with MMU off */
mtspr MD_CTR, r3
#endif
lis r3, IDC_INVALL@h
mtspr DC_CST, r3
#if 0
lis r3, DC_SFWT@h
mtspr DC_CST, r3
#endif
lis r3, IDC_ENABLE@h
mtspr DC_CST, r3
blr
.globl dcache_disable
dcache_disable:
SYNC
lis r3, IDC_DISABLE@h
mtspr DC_CST, r3
lis r3, IDC_INVALL@h
mtspr DC_CST, r3
blr
.globl dcache_status
dcache_status:
mfspr r3, DC_CST
srwi r3, r3, 31 /* >>31 => select bit 0 */
blr
.globl dc_read
dc_read:
mtspr DC_ADR, r3
mfspr r3, DC_DAT
blr
/*
* unsigned int get_immr (unsigned int mask)
*
* return (mask ? (IMMR & mask) : IMMR);
*/
.globl get_immr
get_immr:
mr r4,r3 /* save mask */
mfspr r3, IMMR /* IMMR */
cmpwi 0,r4,0 /* mask != 0 ? */
beq 4f
and r3,r3,r4 /* IMMR & mask */
4:
blr
.globl get_pvr
get_pvr:
mfspr r3, PVR
blr
.globl wr_ic_cst
wr_ic_cst:
mtspr IC_CST, r3
blr
.globl rd_ic_cst
rd_ic_cst:
mfspr r3, IC_CST
blr
.globl wr_ic_adr
wr_ic_adr:
mtspr IC_ADR, r3
blr
.globl wr_dc_cst
wr_dc_cst:
mtspr DC_CST, r3
blr
.globl rd_dc_cst
rd_dc_cst:
mfspr r3, DC_CST
blr
.globl wr_dc_adr
wr_dc_adr:
mtspr DC_ADR, r3
blr
/*------------------------------------------------------------------------------*/
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* r3 = dest
* r4 = src
* r5 = length in bytes
* r6 = cachelinesize
*/
.globl relocate_code
relocate_code:
mr r1, r3 /* Set new stack pointer */
mr r9, r4 /* Save copy of Global Data pointer */
mr r10, r5 /* Save copy of Destination Address */
mr r3, r5 /* Destination Address */
lis r4, CFG_MONITOR_BASE@h /* Source Address */
ori r4, r4, CFG_MONITOR_BASE@l
lis r5, CFG_MONITOR_LEN@h /* Length in Bytes */
ori r5, r5, CFG_MONITOR_LEN@l
li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
/*
* Fix GOT pointer:
*
* New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
*
* Offset:
*/
sub r15, r10, r4
/* First our own GOT */
add r14, r14, r15
/* the the one used by the C code */
add r30, r30, r15
/*
* Now relocate code
*/
cmplw cr1,r3,r4
addi r0,r5,3
srwi. r0,r0,2
beq cr1,4f /* In place copy is not necessary */
beq 7f /* Protect against 0 count */
mtctr r0
bge cr1,2f
la r8,-4(r4)
la r7,-4(r3)
1: lwzu r0,4(r8)
stwu r0,4(r7)
bdnz 1b
b 4f
2: slwi r0,r0,2
add r8,r4,r0
add r7,r3,r0
3: lwzu r0,-4(r8)
stwu r0,-4(r7)
bdnz 3b
/*
* Now flush the cache: note that we must start from a cache aligned
* address. Otherwise we might miss one cache line.
*/
4: cmpwi r6,0
add r5,r3,r5
beq 7f /* Always flush prefetch queue in any case */
subi r0,r6,1
andc r3,r3,r0
mr r4,r3
5: dcbst 0,r4
add r4,r4,r6
cmplw r4,r5
blt 5b
sync /* Wait for all dcbst to complete on bus */
mr r4,r3
6: icbi 0,r4
add r4,r4,r6
cmplw r4,r5
blt 6b
7: sync /* Wait for all icbi to complete on bus */
isync
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
mtlr r0
blr
in_ram:
/*
* Relocation Function, r14 point to got2+0x8000
*
* Adjust got2 pointers, no need to check for 0, this code
* already puts a few entries in the table.
*/
li r0,__got2_entries@sectoff@l
la r3,GOT(_GOT2_TABLE_)
lwz r11,GOT(_GOT2_TABLE_)
mtctr r0
sub r11,r3,r11
addi r3,r3,-4
1: lwzu r0,4(r3)
add r0,r0,r11
stw r0,0(r3)
bdnz 1b
/*
* Now adjust the fixups and the pointers to the fixups
* in case we need to move ourselves again.
*/
2: li r0,__fixup_entries@sectoff@l
lwz r3,GOT(_FIXUP_TABLE_)
cmpwi r0,0
mtctr r0
addi r3,r3,-4
beq 4f
3: lwzu r4,4(r3)
lwzux r0,r4,r11
add r0,r0,r11
stw r10,0(r3)
stw r0,0(r4)
bdnz 3b
4:
clear_bss:
/*
* Now clear BSS segment
*/
lwz r3,GOT(.bss)
#if defined(CONFIG_FADS) || defined(CONFIG_ICU862)
/*
* For the FADS - the environment is the very last item in flash.
* The real .bss stops just before environment starts, so only
* clear up to that point.
*/
lwz r4,GOT(environment)
#else
lwz r4,GOT(_end)
#endif
cmplw 0, r3, r4
beq 6f
li r0, 0
5:
stw r0, 0(r3)
addi r3, r3, 4
cmplw 0, r3, r4
bne 5b
6:
mr r3, r9 /* Global Data pointer */
mr r4, r10 /* Destination Address */
bl board_init_r
/* Problems accessing "end" in C, so do it here */
.globl get_endaddr
get_endaddr:
lwz r3,GOT(_end)
blr
/*
* Copy exception vector code to low memory
*
* r3: dest_addr
* r7: source address, r8: end address, r9: target address
*/
.globl trap_init
trap_init:
lwz r7, GOT(_start)
lwz r8, GOT(_end_of_vectors)
rlwinm r9, r7, 0, 22, 31 /* _start & 0x3FF */
cmplw 0, r7, r8
bgelr /* return if r7>=r8 - just in case */
mflr r4 /* save link register */
1:
lwz r0, 0(r7)
stw r0, 0(r9)
addi r7, r7, 4
addi r9, r9, 4
cmplw 0, r7, r8
bne 1b
/*
* relocate `hdlr' and `int_return' entries
*/
li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
li r8, Alignment - _start + EXC_OFF_SYS_RESET
2:
bl trap_reloc
addi r7, r7, 0x100 /* next exception vector */
cmplw 0, r7, r8
blt 2b
li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
bl trap_reloc
li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
bl trap_reloc
li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
li r8, SystemCall - _start + EXC_OFF_SYS_RESET
3:
bl trap_reloc
addi r7, r7, 0x100 /* next exception vector */
cmplw 0, r7, r8
blt 3b
li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
4:
bl trap_reloc
addi r7, r7, 0x100 /* next exception vector */
cmplw 0, r7, r8
blt 4b
mtlr r4 /* restore link register */
blr
/*
* Function: relocate entries for one exception vector
*/
trap_reloc:
lwz r0, 0(r7) /* hdlr ... */
add r0, r0, r3 /* ... += dest_addr */
stw r0, 0(r7)
lwz r0, 4(r7) /* int_return ... */
add r0, r0, r3 /* ... += dest_addr */
stw r0, 4(r7)
sync
isync
blr

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This file contains basic information on the port of U-Boot to IPHASE4539
(Interphase 4539 T1/E1/J1 PMC Communications Controller).
All the changes fit in the common U-Boot infrastructure, providing a new
IPHASE4539-specific entry in makefiles. To build U-Boot for IPHASE4539,
type "make IPHASE4539_config", edit the "include/config_IPHASE4539.h"
file if necessary, then type "make".
Common file modifications:
--------------------------
The following common files have been modified by this project:
(starting from the ppcboot-1.1.5/ directory)
MAKEALL - IPHASE4539 entry added
Makefile - IPHASE4539_config entry added
New files:
----------
The following new files have been added by this project:
(starting from the ppcboot-1.1.5/ directory)
board/iphase4539/ - board-specific directory
board/iphase4539/Makefile - board-specific makefile
board/iphase4539/config.mk - config file
board/iphase4539/flash.c - flash driver (for AM29LV033C)
board/iphase4539/ppcboot.lds - linker script
board/iphase4539/iphase4539.c - ioport and memory initialization
include/config_IPHASE4539.h - main configuration file
New configuration options:
--------------------------
CONFIG_IPHASE4539
Main board-specific option (should be defined for IPHASE4539).
Acceptance criteria tests:
--------------------------
The following tests have been conducted to validate the port of U-Boot
to IPHASE4539:
1. Operation on serial console:
With SMC1 defined as console in the main configuration file, the U-Boot
output appeared on the serial terminal connected to the 2.5mm stereo jack
connector as follows:
------------------------------------------------------------------------------
=> help
autoscr - run script from memory
base - print or set address offset
bdinfo - print Board Info structure
bootm - boot application image from memory
bootp - boot image via network using BootP/TFTP protocol
bootd - boot default, i.e., run 'bootcmd'
cmp - memory compare
coninfo - print console devices and informations
cp - memory copy
crc32 - checksum calculation
dcache - enable or disable data cache
echo - echo args to console
erase - erase FLASH memory
flinfo - print FLASH memory information
go - start application at address 'addr'
help - print online help
icache - enable or disable instruction cache
iminfo - print header information for application image
loadb - load binary file over serial line (kermit mode)
loads - load S-Record file over serial line
loop - infinite loop on address range
md - memory display
mm - memory modify (auto-incrementing)
mtest - simple RAM test
mw - memory write (fill)
nm - memory modify (constant address)
printenv- print environment variables
protect - enable or disable FLASH write protection
rarpboot- boot image via network using RARP/TFTP protocol
reset - Perform RESET of the CPU
run - run commands in an environment variable
saveenv - save environment variables to persistent storage
setenv - set environment variables
sleep - delay execution for some time
tftpboot- boot image via network using TFTP protocol
and env variables ipaddr and serverip
version - print monitor version
? - alias for 'help'
=>
------------------------------------------------------------------------------
2. Flash driver operation
The following sequence was performed to test the "flinfo" command:
------------------------------------------------------------------------------
=> flinfo
Bank # 1: AMD AM29LV033C (32 Mbit, uniform sectors)
Size: 4 MB in 64 Sectors
Sector Start Addresses:
FF800000 (RO) FF810000 (RO) FF820000 FF830000 FF840000
FF850000 FF860000 FF870000 FF880000 FF890000
FF8A0000 FF8B0000 FF8C0000 FF8D0000 FF8E0000
FF8F0000 FF900000 FF910000 FF920000 FF930000
FF940000 FF950000 FF960000 FF970000 FF980000
FF990000 FF9A0000 FF9B0000 FF9C0000 FF9D0000
FF9E0000 FF9F0000 FFA00000 FFA10000 FFA20000
FFA30000 FFA40000 FFA50000 FFA60000 FFA70000
FFA80000 FFA90000 FFAA0000 FFAB0000 FFAC0000
FFAD0000 FFAE0000 FFAF0000 FFB00000 (RO) FFB10000 (RO)
FFB20000 (RO) FFB30000 (RO) FFB40000 FFB50000 FFB60000
FFB70000 FFB80000 FFB90000 FFBA0000 FFBB0000
FFBC0000 FFBD0000 FFBE0000 FFBF0000
------------------------------------------------------------------------------
Note: the Hardware Configuration Word (HWC) of the 8260 is on the
first sector of the flash and should not be touched. The U-Boot
environment variables are stored on second sector and U-Boot
starts at the address 0xFFB00000.
The following sequence was performed to test the erase command:
------------------------------------------------------------------------------
=> cp 0 ff880000 10
Copy to Flash... done
=> md ff880000 20
ff880000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x
ff880010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x
ff880020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6.
ff880030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x
ff880040: ffffffff ffffffff ffffffff ffffffff ................
ff880050: ffffffff ffffffff ffffffff ffffffff ................
ff880060: ffffffff ffffffff ffffffff ffffffff ................
ff880070: ffffffff ffffffff ffffffff ffffffff ................
=> erase ff880000 ff88ffff
Erase Flash from 0xff880000 to 0xff88ffff
.. done
Erased 1 sectors
=> md ff880000
ff880000: ffffffff ffffffff ffffffff ffffffff ................
ff880010: ffffffff ffffffff ffffffff ffffffff ................
ff880020: ffffffff ffffffff ffffffff ffffffff ................
ff880030: ffffffff ffffffff ffffffff ffffffff ................
ff880040: ffffffff ffffffff ffffffff ffffffff ................
ff880050: ffffffff ffffffff ffffffff ffffffff ................
ff880060: ffffffff ffffffff ffffffff ffffffff ................
ff880070: ffffffff ffffffff ffffffff ffffffff ................
=> cp 0 ff880000 10
Copy to Flash... done
=> md ff880000 20
ff880000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x
ff880010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x
ff880020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6.
ff880030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x
ff880040: ffffffff ffffffff ffffffff ffffffff ................
ff880050: ffffffff ffffffff ffffffff ffffffff ................
ff880060: ffffffff ffffffff ffffffff ffffffff ................
ff880070: ffffffff ffffffff ffffffff ffffffff ................
=> erase 1:8
Erase Flash Sectors 8-8 in Bank # 1
.. done
=> md ff880000 20
ff880000: ffffffff ffffffff ffffffff ffffffff ................
ff880010: ffffffff ffffffff ffffffff ffffffff ................
ff880020: ffffffff ffffffff ffffffff ffffffff ................
ff880030: ffffffff ffffffff ffffffff ffffffff ................
ff880040: ffffffff ffffffff ffffffff ffffffff ................
ff880050: ffffffff ffffffff ffffffff ffffffff ................
ff880060: ffffffff ffffffff ffffffff ffffffff ................
ff880070: ffffffff ffffffff ffffffff ffffffff ................
=> cp 0 ff880000 10
Copy to Flash... done
=> cp 0 ff890000 10
=> md ff880000 20
ff880000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x
ff880010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x
ff880020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6.
ff880030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x
ff880040: ffffffff ffffffff ffffffff ffffffff ................
ff880050: ffffffff ffffffff ffffffff ffffffff ................
ff880060: ffffffff ffffffff ffffffff ffffffff ................
ff880070: ffffffff ffffffff ffffffff ffffffff ................
=> md ff890000
ff890000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x
ff890010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x
ff890020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6.
ff890030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x
ff890040: ffffffff ffffffff ffffffff ffffffff ................
ff890050: ffffffff ffffffff ffffffff ffffffff ................
ff890060: ffffffff ffffffff ffffffff ffffffff ................
ff890070: ffffffff ffffffff ffffffff ffffffff ................
=> erase 1:8-9
Erase Flash Sectors 8-9 in Bank # 1
.... done
=> md ff880000 20
ff880000: ffffffff ffffffff ffffffff ffffffff ................
ff880010: ffffffff ffffffff ffffffff ffffffff ................
ff880020: ffffffff ffffffff ffffffff ffffffff ................
ff880030: ffffffff ffffffff ffffffff ffffffff ................
ff880040: ffffffff ffffffff ffffffff ffffffff ................
ff880050: ffffffff ffffffff ffffffff ffffffff ................
ff880060: ffffffff ffffffff ffffffff ffffffff ................
ff880070: ffffffff ffffffff ffffffff ffffffff ................
=> md ff890000
ff890000: ffffffff ffffffff ffffffff ffffffff ................
ff890010: ffffffff ffffffff ffffffff ffffffff ................
ff890020: ffffffff ffffffff ffffffff ffffffff ................
ff890030: ffffffff ffffffff ffffffff ffffffff ................
ff890040: ffffffff ffffffff ffffffff ffffffff ................
ff890050: ffffffff ffffffff ffffffff ffffffff ................
ff890060: ffffffff ffffffff ffffffff ffffffff ................
ff890070: ffffffff ffffffff ffffffff ffffffff ................
=>
------------------------------------------------------------------------------
The following sequence was performed to test the Flash programming commands:
------------------------------------------------------------------------------
=> erase ff880000 ff88ffff
Erase Flash from 0xff880000 to 0xff88ffff
.. done
Erased 1 sectors
=> cp 0 ff880000 10
Copy to Flash... done
=> md 0 20
00000000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x
00000010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x
00000020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6.
00000030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x
00000040: 3c83c000 2c040000 40823378 7c0000a6 <...,...@.3x|...
00000050: 60000030 7c1b03a6 3c00c000 600035ec `..0|...<...`.5.
00000060: 7c1a03a6 4c000064 00000000 00000000 |...L..d........
00000070: 00000000 00000000 00000000 00000000 ................
=> md ff880000 20
ff880000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x
ff880010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x
ff880020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6.
ff880030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x
ff880040: ffffffff ffffffff ffffffff ffffffff ................
ff880050: ffffffff ffffffff ffffffff ffffffff ................
ff880060: ffffffff ffffffff ffffffff ffffffff ................
ff880070: ffffffff ffffffff ffffffff ffffffff ................
=>
------------------------------------------------------------------------------
The following sequence was performed to test storage of the environment
variables in Flash:
------------------------------------------------------------------------------
=> setenv foo bar
=> saveenv
Un-Protected 1 sectors
Erasing Flash...
.. done
Erased 1 sectors
Saving Environment to Flash...
Protected 1 sectors
=> reset
...
=> printenv
...
foo=bar
...
Environment size: 339/65532 bytes
=>
------------------------------------------------------------------------------
The following sequence was performed to test image download and run over
Ethernet interface (both interfaces were tested):
------------------------------------------------------------------------------
=> tftpboot 40000 hello_world.bin
ARP broadcast 1
TFTP from server 10.0.0.1; our IP address is 10.0.0.8
Filename 'hello_world.bin'.
Load address: 0x40000
Loading: #############
done
Bytes transferred = 65932 (1018c hex)
=> go 40004
## Starting application at 0x00040004 ...
Hello World
argc = 1
argv[0] = "40004"
argv[1] = "<NULL>"
Hit any key to exit ...
## Application terminated, rc = 0x0
=>
------------------------------------------------------------------------------
3. Known Problems
None for the moment.
----------------------------------------------------------------------------
U-Boot and Linux for Interphase 4539 T1/E1/J1 PMC Communications Controller
----------------------------------------------------------------------------
U-Boot:
Configure and make U-Boot:
$ cd <path>/u-boot
$ make IPHASE4539_config
$ make dep
$ make
$ cp -p u-boot.bin /tftpboot
Load u-boot.bin into the Flash memory at 0xffb00000.
Linux:
Configure and make Linux:
$ cd <patch>/linux-2.4
$ make IPHASE4539_config
$ make oldconfig
$ make dep
$ make pImage
$ cp -p arch/ppc/mbxboot/pImage /tftpboot
Load pImage via tftp and boot it.
Flash organisation:
The following preliminary layout of the Flash memory
is defined:
0xff800000 ( 0 - 64 kB): Hardware Configuration Word.
0xff810000 ( 64 kB - 128 kB): U-Boot Environment.
0xff820000 ( 128 kB - 3 MB): RAMdisk.
0xffb00000 ( 3 MB - 3328 kB): U-Boot.
0xffb40000 (3328 KB - 4 MB): Linux Kernel.
For further information concerning U-Boot and Linux please consult
the "DENX U-Boot and Linux Guide".
(C) 2002 Wolfgang Grandegger, DENX Software Engineering, wg@denx.de
===================================================================

21
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# Porting U-Boot onto RPXClassic LF_BW31 board
# Written by Pierre AUBERT
# E-Mail p.aubert@staubli.com
# Stäubli Faverges - <www.staubli.com>
#
# Sept. 20 2001
#
# Cross compile: Montavista Hardhat ported on HP-UX 10.20
#
Flash memories : AM29DL323B (2 banks flash memories) 16 Mb from 0xff000000
DRAM : 16 Mb from 0
NVRAM : 512 kb from 0xfa000000
- environment is stored in NVRAM
- Mac address is read from EEPROM
- ethernet on SCC1 or fast ethernet on FEC are running (depending on the
configuration flag CONFIG_FEC_ENET)

90
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/*
* (C) Copyright 2000
* Dave Ellis, SIXNET, dge@sixnetio.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
Using the Motorola MPC8XXFADS development board
===============================================
CONFIGURATIONS
--------------
There are ready-to-use default configurations available for the
FADS823, FADS850SAR and FADS860T. The FADS860T configuration also
works for the 855T processor.
LOADING U-Boot INTO FADS FLASH MEMORY
--------------------------------------
MPC8BUG can load U-Boot into the FLASH memory using LOADF.
loadf u-boot.srec 100000
STARTING U-Boot FROM MPC8BUG
-----------------------------
To start U-Boot from MPC8BUG:
1. Reset the board:
reset :h
2. Change BR0 and OR0 back to their values at reset:
rms memc br0 00000001
rms memc or0 00000d34
3. Modify DER so MPC8BUG gets control only when it should:
rms der 2002000f
4. Start as if from reset:
go 100
This is NOT exactly the same as starting U-Boot without
MPC8BUG. MPC8BUG turns off the watchdog as part of the hard reset.
After it does the reset it writes SYPCR (to disable the watchdog)
and sets BR0 and OR0 to map the FLASH at 0x02800000 (and does lots
of other initialization). That is why it is necessary to set BR0
and OR0 to map the FLASH everywhere. U-Boot can't turn on the
watchdog after that, since MPC8BUG has used the only chance to write
to SYPCR.
Here is a bizarre sequence of MPC8BUG and U-Boot commands that lets
U-Boot write to SYPCR. It works with MPC8BUG 1.5 and an 855T
processor (your mileage may vary). It is probably better (and a lot
easier) just to accept having the watchdog disabled when the debug
cable is connected.
in MPC8BUG:
reset :h
rms memc br0 00000001
rms memc or0 00000d34
rms der 2000f
go 100
Now U-Boot is running with the MPC8BUG value for SYPCR. Use the
U-Boot 'reset' command to reset the board.
=>reset
Next, in MPC8BUG:
rms der 2000f
go
Now U-Boot is running with the U-Boot value for SYPCR.

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doc/README.video
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/*
* (C) Copyright 2000
* Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
U-Boot MPC8xx video controller driver
======================================
The driver has been tested with the following configurations:
- MPC823FADS with AD7176 on a PAL TV (YCbYCr) - arsenio@tin.it
- GENIETV with AD7177 on a PAL TV (YCbYCr) - arsenio@tin.it

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include/asm-ppc/u-boot.h
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/*
* (C) Copyright 2000 - 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __U_BOOT_H__
#define __U_BOOT_H__
/*
* Board information passed to Linux kernel from U-Boot
*
* include/asm-ppc/u-boot.h
*/
#ifndef __ASSEMBLY__
#include <linux/types.h>
typedef struct bd_info {
unsigned long bi_memstart; /* start of DRAM memory */
unsigned long bi_memsize; /* size of DRAM memory in bytes */
unsigned long bi_flashstart; /* start of FLASH memory */
unsigned long bi_flashsize; /* size of FLASH memory */
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
#if defined(CONFIG_8xx) || defined(CONFIG_8260)
unsigned long bi_immr_base; /* base of IMMR register */
#endif
unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */
unsigned long bi_ip_addr; /* IP Address */
unsigned char bi_enetaddr[6]; /* Ethernet adress */
unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
unsigned long bi_intfreq; /* Internal Freq, in MHz */
unsigned long bi_busfreq; /* Bus Freq, in MHz */
#if defined(CONFIG_8260)
unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */
unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */
unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */
unsigned long bi_vco; /* VCO Out from PLL, in MHz */
#endif
unsigned long bi_baudrate; /* Console Baudrate */
#if defined(CONFIG_405GP) || \
defined(CONFIG_405CR) || \
defined(CONFIG_440) || \
defined(CONFIG_405)
unsigned char bi_s_version[4]; /* Version of this structure */
unsigned char bi_r_version[32]; /* Version of the ROM (IBM) */
unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */
unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */
unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */
#endif
#if defined(CONFIG_HYMOD)
hymod_conf_t bi_hymod_conf; /* hymod configuration information */
#endif
#if defined(CONFIG_EVB64260) || defined(CONFIG_PN62)
/* second onboard ethernet port */
unsigned char bi_enet1addr[6];
#endif
#if defined(CONFIG_EVB64260)
/* third onboard ethernet port */
unsigned char bi_enet2addr[6];
#endif
#if defined(CONFIG_NX823)
unsigned char bi_sernum[8];
#endif
} bd_t;
#endif /* __ASSEMBLY__ */
#endif /* __U_BOOT_H__ */

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/*
* A collection of structures, addresses, and values associated with
* the Motorola 860T FADS board. Copied from the MBX stuff.
* Magnus Damm added defines for 8xxrom and extended bd_info.
* Helmut Buchsbaum added bitvalues for BCSRx
*
* Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
*/
/*
* 1999-nov-26: The FADS is using the following physical memorymap:
*
* ff020000 -> ff02ffff : pcmcia io remapping
* ff010000 -> ff01ffff : BCSR connected to CS1, setup by U-Boot
* ff000000 -> ff00ffff : IMAP internal in the cpu
* e0000000 -> f3ffffff : pcmcia memory remapping by m8xx_pcmcia
* fe000000 -> fe1fffff : flash connected to CS0, setup by U-Boot
* 00000000 -> nnnnnnnn : sdram/dram setup by U-Boot
*/
#define CFG_PCMCIA_IO_ADDR 0xff020000
#define CFG_PCMCIA_IO_SIZE 0x10000
#define CFG_PCMCIA_MEM_ADDR 0xe0000000
#define CFG_PCMCIA_MEM_SIZE 0x10000
#define CFG_IMMR 0xFF000000
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0x02800000
#define BCSR_ADDR ((uint) 0xff010000)
#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */
/* ------------------------------------------------------------------------- */
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_ETHADDR 08:00:22:50:70:63 /* Ethernet address */
#define CONFIG_ENV_OVERWRITE 1 /* Overwrite the environment */
#define CONFIG_VIDEO 1 /* To enable video controller support */
#define CONFIG_HARD_I2C 1 /* To I2C with hardware support */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
/*Now included by CFG_CMD_PCMCIA */
/*#define CONFIG_PCMCIA 1 / * To enable PCMCIA support */
/* Video related */
#define CONFIG_VIDEO_LOGO 1 /* Show the logo */
#define CONFIG_VIDEO_ENCODER_AD7176 1 /* Enable this encoder */
#define CONFIG_VIDEO_ENCODER_AD7176_ADDR 0x54 /* Default on fads */
#define CONFIG_VIDEO_SIZE (2*1024*1024)
/* #define CONFIG_VIDEO_ADDR (gd->bd->bi_memsize - CONFIG_VIDEO_SIZE) Frame buffer address */
/* Wireless 56Khz 4PPM keyboard on SMCx */
/*#define CONFIG_WL_4PPM_KEYBOARD 1 */
#define CONFIG_WL_4PPM_KEYBOARD_SMC 0 /* SMC to use (0 indexed) */
/*
* High Level Configuration Options
* (easy to change)
*/
#include <mpc8xx_irq.h>
#define CONFIG_MPC823 1
#define CONFIG_MPC823FADS 1
#define CONFIG_FADS 1
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 115200
/* Set the CPU speed to 50Mhz on the FADS */
#if 0
#define MPC8XX_FACT 10 /* Multiply by 10 */
#define MPC8XX_XIN 5000000 /* 5 MHz in */
#else
#define MPC8XX_FACT 10 /* Multiply by 10 */
#define MPC8XX_XIN 5000000 /* 5 MHz in */
#define CFG_PLPRCR_MF (MPC8XX_FACT-1) << 20 /* From 0 to 4095 */
#endif
#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
#if 1
#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
#define CONFIG_LOADS_ECHO 0 /* Dont echoes received characters */
#define CONFIG_BOOTARGS ""
#define CONFIG_BOOTCOMMAND \
"bootp ;" \
"setenv bootargs console=tty0 console=ttyS0 " \
"root=/dev/nfs nfsroot=$(serverip):$(rootpath) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):eth0:off ;" \
"bootm"
#else
#define CONFIG_BOOTDELAY 0 /* autoboot disabled */
#endif
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT ":>" /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
#define CFG_MEMTEST_END 0x01000000 /* 0 ... 16 MB in DRAM */
#define CFG_LOAD_ADDR 0x00100000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Internal Memory Mapped Register
*/
#define CFG_IMMR_SIZE ((uint)(64 * 1024))
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR CFG_IMMR
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
* Also NOTE that it doesn't mean SDRAM - it means MEMORY.
*/
#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
#if 0
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#else
#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
#endif
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9
* SYPCR can only be written once after reset!
*-----------------------------------------------------------------------
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
*/
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
*-----------------------------------------------------------------------
* Clear Reference Interrupt Status, Timebase freezing enabled
*/
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 11-31
*-----------------------------------------------------------------------
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
*/
#define CFG_PISCR (PISCR_PS | PISCR_PITF)
/*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
*-----------------------------------------------------------------------
* Reset PLL lock status sticky bit, timer expired status bit and timer *
* interrupt status bit - leave PLL multiplication factor unchanged !
*/
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CFG_PLPRCR_MF)
/*-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register 15-27
*-----------------------------------------------------------------------
* Set clock output, timebase and RTC source and divider,
* power management and some other internal clocks
*/
#define SCCR_MASK SCCR_EBDF11
#define CFG_SCCR (SCCR_TBS | \
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00)
/*-----------------------------------------------------------------------
*
*-----------------------------------------------------------------------
*
*/
#define CFG_DER 0
/* Because of the way the 860 starts up and assigns CS0 the
* entire address space, we have to set the memory controller
* differently. Normally, you write the option register
* first, and then enable the chip select by writing the
* base register. For CS0, you must write the base register
* first, followed by the option register.
*/
/*
* Init Memory Controller:
*
* BR0/1 and OR0/1 (FLASH)
*/
/* the other CS:s are determined by looking at parameters in BCSRx */
#define BCSR_SIZE ((uint)(64 * 1024))
#define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
#define CFG_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */
/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
/* BCSRx - Board Control and Status Registers */
#define CFG_OR1_REMAP CFG_OR0_REMAP
#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */
#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V )
/*
* Memory Periodic Timer Prescaler
*/
/* periodic timer for refresh */
#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
/*
* MAMR settings for SDRAM
*/
/* 8 column SDRAM */
#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
#define CFG_MAMR 0x13a01114
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/* values according to the manual */
#define BCSR0 ((uint) (BCSR_ADDR + 00))
#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
#define BCSR4 ((uint) (BCSR_ADDR + 0x10))
/* FADS bitvalues by Helmut Buchsbaum
* see MPC8xxADS User's Manual for a proper description
* of the following structures
*/
#define BCSR0_ERB ((uint)0x80000000)
#define BCSR0_IP ((uint)0x40000000)
#define BCSR0_BDIS ((uint)0x10000000)
#define BCSR0_BPS_MASK ((uint)0x0C000000)
#define BCSR0_ISB_MASK ((uint)0x01800000)
#define BCSR0_DBGC_MASK ((uint)0x00600000)
#define BCSR0_DBPC_MASK ((uint)0x00180000)
#define BCSR0_EBDF_MASK ((uint)0x00060000)
#define BCSR1_FLASH_EN ((uint)0x80000000)
#define BCSR1_DRAM_EN ((uint)0x40000000)
#define BCSR1_ETHEN ((uint)0x20000000)
#define BCSR1_IRDEN ((uint)0x10000000)
#define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
#define BCSR1_BCSR_EN ((uint)0x02000000)
#define BCSR1_RS232EN_1 ((uint)0x01000000)
#define BCSR1_PCCEN ((uint)0x00800000)
#define BCSR1_PCCVCC0 ((uint)0x00400000)
#define BCSR1_PCCVPP_MASK ((uint)0x00300000)
#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
#define BCSR1_RS232EN_2 ((uint)0x00040000)
#define BCSR1_SDRAM_EN ((uint)0x00020000)
#define BCSR1_PCCVCC1 ((uint)0x00010000)
#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
#define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
#define BCSR2_DRAM_PD_SHIFT (23)
#define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
#define BCSR2_DBREVNR_MASK ((uint)0x00030000)
#define BCSR3_DBID_MASK ((ushort)0x3800)
#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
#define BCSR3_BREVNR0 ((ushort)0x0080)
#define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
#define BCSR3_BREVN1 ((ushort)0x0008)
#define BCSR3_BREVN2_MASK ((ushort)0x0003)
#define BCSR4_ETHLOOP ((uint)0x80000000)
#define BCSR4_TFPLDL ((uint)0x40000000)
#define BCSR4_TPSQEL ((uint)0x20000000)
#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
#ifdef CONFIG_MPC823
#define BCSR4_USB_EN ((uint)0x08000000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860SAR
#define BCSR4_UTOPIA_EN ((uint)0x08000000)
#endif /* CONFIG_MPC860SAR */
#ifdef CONFIG_MPC860T
#define BCSR4_FETH_EN ((uint)0x08000000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_USB_SPEED ((uint)0x04000000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHCFG0 ((uint)0x04000000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_VCCO ((uint)0x02000000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHFDE ((uint)0x02000000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_VIDEO_ON ((uint)0x00800000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC823
#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHCFG1 ((uint)0x00400000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_VIDEO_RST ((uint)0x00200000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHRST ((uint)0x00200000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_MODEM_EN ((uint)0x00100000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC823
#define BCSR4_DATA_VOICE ((uint)0x00080000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC850
#define BCSR4_DATA_VOICE ((uint)0x00080000)
#endif /* CONFIG_MPC850 */
#define CONFIG_DRAM_50MHZ 1
#define CONFIG_SDRAM_50MHZ
#ifdef CONFIG_MPC860T
/* Interrupt level assignments.
*/
#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
#endif /* CONFIG_MPC860T */
/* We don't use the 8259.
*/
#define NR_8259_INTS 0
/* Machine type
*/
#define _MACH_8xx (_MACH_fads)
/*
* MPC8xx CPM Options
*/
#define CONFIG_SCC_ENET 1
#define CONFIG_SCC2_ENET 1
#undef CONFIG_FEC_ENET
#undef CONFIG_CPM_IIC
#undef CONFIG_UCODE_PATCH
#define CONFIG_DISK_SPINUP_TIME 1000000
/* PCMCIA configuration */
#define PCMCIA_MAX_SLOTS 1
#ifdef CONFIG_MPC860
#define PCMCIA_SLOT_A 1
#endif
#endif /* __CONFIG_H */

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/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* Keith Outwater, keith_outwater@mvis.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config_GEN860T.h - board specific configuration options
*/
#ifndef __CONFIG_GEN860T_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_MPC860
#define CONFIG_GEN860T
/*
* Identify the board
*/
#define CONFIG_IDENT_STRING " GEN860T"
/*
* Don't depend on the RTC clock to determine clock frequency -
* the 860's internal rtc uses a 32.768 KHz clock which is
* generated by the DS1337 - and the DS1337 clock can be turned off.
*/
#define CONFIG_8xx_GCLK_FREQ 66600000
/*
* The RS-232 console port is on SMC1
*/
#define CONFIG_8xx_CONS_SMC1
#define CONFIG_BAUDRATE 38400
/*
* Set allowable console baud rates
*/
#define CFG_BAUDRATE_TABLE { 9600, \
19200, \
38400, \
57600, \
115200, \
}
/*
* Print console information
*/
#undef CFG_CONSOLE_INFO_QUIET
/*
* Set the autoboot delay in seconds. A delay of -1 disables autoboot
*/
#define CONFIG_BOOTDELAY 5
/*
* Pass the clock frequency to the Linux kernel in units of MHz
*/
#define CONFIG_CLOCKS_IN_MHZ
#define CONFIG_PREBOOT \
"echo;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp;" \
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
"bootm"
/*
* Turn off echo for serial download by default. Allow baud rate to be changed
* for downloads
*/
#undef CONFIG_LOADS_ECHO
#define CFG_LOADS_BAUD_CHANGE
/*
* Set default load address for tftp network downloads
*/
#define CFG_TFTP_LOADADDR 0x01000000
/*
* Turn off the watchdog timer
*/
#undef CONFIG_WATCHDOG
/*
* Do not reboot if a panic occurs
*/
#define CONFIG_PANIC_HANG
/*
* Enable the status LED
*/
#define CONFIG_STATUS_LED
/*
* Reset address. We pick an address such that when an instruction
* is executed at that address, a machine check exception occurs
*/
#define CFG_RESET_ADDRESS ((ulong) -1)
/*
* BOOTP options
*/
#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \
CONFIG_BOOTP_BOOTFILESIZE \
)
/*
* The GEN860T network interface uses the on-chip 10/100 FEC with
* an Intel LXT971A PHY connected to the 860T's MII. The PHY's
* MII address is hardwired on the board to zero.
*/
#define CONFIG_FEC_ENET
#define CFG_DISCOVER_PHY
#define CONFIG_MII
#define CONFIG_PHY_ADDR 0
/*
* Set default IP stuff just to get bootstrap entries into the
* environment so that we can autoscript the full default environment.
*/
#define CONFIG_ETHADDR 9a:52:63:15:85:25
#define CONFIG_SERVERIP 10.0.4.200
#define CONFIG_IPADDR 10.0.4.111
/*
* This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to
* the MPC860T I2C interface.
*/
#define CFG_I2C_EEPROM_ADDR 0x50
#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10 mS w/ 20% margin */
#define CFG_I2C_EEPROM_ADDR_LEN 2 /* need 16 bit address */
#define CFG_ENV_EEPROM_SIZE (32 * 1024)
#undef CONFIG_HARD_I2C
#define CONFIG_SOFT_I2C
/*
* Configure software I2C support (taken from IP860 BSP).
* The I2C bus is connected to the GEN860T's 'dedicated' I2C
* pins, i.e. PB26 and PB27
*/
#define PB_SCL 0x00000020 /* PB 26 */
#define PB_SDA 0x00000010 /* PB 27 */
#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
else immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
else immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
#define CFG_I2C_SPEED 100000 /* clock speed in Hz */
#define CFG_I2C_SLAVE 0xFE /* I2C slave address */
/*
* Allow environment overwrites by anyone
*/
#define CONFIG_ENV_OVERWRITE
/*
* The MPC860's internal RTC is horribly broken in rev D masks. Three
* internal MPC860T circuit nodes were inadvertently left floating; this
* causes KAPWR current in power down mode to be three orders of magnitude
* higher than specified in the datasheet (from 10 uA to 10 mA). No
* reasonable battery can keep that kind RTC running during powerdown for any
* length of time, so we use an external RTC on the I2C bus instead.
*/
#undef CONFIG_RTC_MPC8xx
#define CONFIG_RTC_DS1337
#define CFG_I2C_RTC_ADDR 0x68
/*
* Allow partial commands to be matched to uniqueness.
*/
#define CFG_MATCH_PARTIAL_CMD
/*
* List of available monitor commands. Use the system default list
* plus add some of the "non-standard" commands back in.
* See ./cmd_confdefs.h
*/
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
CFG_CMD_DHCP | \
CFG_CMD_I2C | \
CFG_CMD_DOC | \
CFG_CMD_EEPROM | \
CFG_CMD_REGINFO | \
CFG_CMD_IMMAP | \
CFG_CMD_ELF | \
CFG_CMD_DATE | \
CFG_CMD_DATE | \
CFG_CMD_FPGA | \
CFG_CMD_MII | \
CFG_CMD_BEDBUG \
)
/*
* There is no IDE/PCMCIA hardware support on the board.
*/
#undef CONFIG_IDE_PCMCIA
#undef CONFIG_IDE_LED
#undef CONFIG_IDE_RESET
/*
* Enable the call to misc_init_r() for miscellaneous platform
* dependent initialization.
*/
#define CONFIG_MISC_INIT_R
/*
* Enable call to last_stage_init() so we can twiddle some LEDS :)
*/
#define CONFIG_LAST_STAGE_INIT
/*
* Virtex2 FPGA configuration support
*/
#define CONFIG_FPGA_COUNT 1
#define CONFIG_FPGA CFG_XILINX_VIRTEX2
#define CFG_FPGA_PROG_FEEDBACK
/************************************************************************
* This must be included AFTER the definition of any CONFIG_COMMANDS
*/
#include <cmd_confdefs.h>
/*
* Verbose help from command monitor.
*/
#define CFG_LONGHELP
#define CFG_PROMPT "gen860t> "
/*
* Use the "hush" command parser
*/
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
/*
* Set buffer size for console I/O
*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024
#else
#define CFG_CBSIZE 256
#endif
/*
* Print buffer size
*/
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
/*
* Maximum number of arguments that a command can accept
*/
#define CFG_MAXARGS 16
/*
* Boot argument buffer size
*/
#define CFG_BARGSIZE CFG_CBSIZE
/*
* Default memory test range
*/
#define CFG_MEMTEST_START 0x0100000
#define CFG_MEMTEST_END (CFG_MEMTEST_START + (128 * 1024))
/*
* Select the more full-featured memory test
*/
#define CFG_ALT_MEMTEST
/*
* Default load address
*/
#define CFG_LOAD_ADDR 0x01000000
/*
* Set decrementer frequency (1 ms ticks)
*/
#define CFG_HZ 1000
/*
* Device memory map (after SDRAM remap to 0x0):
*
* CS Device Base Addr Size
* ----------------------------------------------------
* CS0* Flash 0x40000000 64 M
* CS1* SDRAM 0x00000000 16 M
* CS2* Disk-On-Chip 0x50000000 32 K
* CS3* FPGA 0x60000000 64 M
* CS4* SelectMap 0x70000000 32 K
* CS5* Mil-Std 1553 I/F 0x80000000 32 K
* CS6* Unused
* CS7* Unused
* IMMR 860T Registers 0xfff00000
*/
/*
* Base addresses and block sizes
*/
#define CFG_IMMR 0xFF000000
#define SDRAM_BASE 0x00000000
#define SDRAM_SIZE (64 * 1024 * 1024)
#define FLASH_BASE 0x40000000
#define FLASH_SIZE (16 * 1024 * 1024)
#define DOC_BASE 0x50000000
#define DOC_SIZE (32 * 1024)
#define FPGA_BASE 0x60000000
#define FPGA_SIZE (64 * 1024 * 1024)
#define SELECTMAP_BASE 0x70000000
#define SELECTMAP_SIZE (32 * 1024)
#define M1553_BASE 0x80000000
#define M1553_SIZE (64 * 1024)
/*
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR CFG_IMMR
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
#define CFG_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE SDRAM_BASE
/*
* FLASH organization
*/
#define CFG_FLASH_BASE FLASH_BASE
#define CFG_FLASH_SIZE FLASH_SIZE
#define CFG_FLASH_SECT_SIZE (128 * 1024)
#define CFG_MAX_FLASH_BANKS 1
#define CFG_MAX_FLASH_SECT 128
/*
* The timeout values are for an entire chip and are in milliseconds.
* Yes I know that the write timeout is huge. Accroding to the
* datasheet a single byte takes 630 uS (round to 1 ms) max at worst
* case VCC and temp after 100K programming cycles. It works out
* to 280 minutes (might as well be forever).
*/
#define CFG_FLASH_ERASE_TOUT (CFG_MAX_FLASH_SECT * 5000)
#define CFG_FLASH_WRITE_TOUT (CFG_MAX_FLASH_SECT * 128 * 1024 * 1)
/*
* Allow direct writes to FLASH from tftp transfers (** dangerous **)
*/
#define CFG_DIRECT_FLASH_TFTP
/*
* Reserve memory for U-Boot.
*/
#define CFG_MAX_U_BOOT_SECT 3
#if defined(DEBUG)
#define CFG_MONITOR_LEN (512 * 1024)
#else
#define CFG_MONITOR_LEN (256 * 1024)
#endif
#define CFG_MONITOR_BASE CFG_FLASH_BASE
/*
* Select environment placement. NOTE that u-boot.lds must
* be edited if this is changed!
*/
#undef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_IS_IN_EEPROM
#if defined(CFG_ENV_IS_IN_EEPROM)
#define CFG_ENV_SIZE (2 * 1024)
#define CFG_ENV_OFFSET (CFG_ENV_EEPROM_SIZE - (8 * 1024))
#else
#define CFG_ENV_SIZE (4 * 1024)
#define CFG_ENV_OFFSET (CFG_MAX_U_BOOT_SECT * CFG_FLASH_SECT_SIZE)
#endif
/*
* Reserve memory for malloc()
*/
#define CFG_MALLOC_LEN (128 * 1024)
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
/*
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of above value */
#endif
/*------------------------------------------------------------------------
* SYPCR - System Protection Control UM 11-9
* -----------------------------------------------------------------------
* SYPCR can only be written once after reset!
*
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
*/
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR ( SYPCR_SWTC | \
SYPCR_BMT | \
SYPCR_BME | \
SYPCR_SWF | \
SYPCR_SWE | \
SYPCR_SWRI | \
SYPCR_SWP \
)
#else
#define CFG_SYPCR ( SYPCR_SWTC | \
SYPCR_BMT | \
SYPCR_BME | \
SYPCR_SWF | \
SYPCR_SWP \
)
#endif
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration UM 11-6
*-----------------------------------------------------------------------
* Set debug pin mux, enable SPKROUT and GPLB5*.
*/
#define CFG_SIUMCR ( SIUMCR_DBGC11 | \
SIUMCR_DBPC11 | \
SIUMCR_MLRC11 | \
SIUMCR_GB5E \
)
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control UM 11-26
*-----------------------------------------------------------------------
* Clear Reference Interrupt Status, Timebase freeze enabled
*/
#define CFG_TBSCR ( TBSCR_REFA | \
TBSCR_REFB | \
TBSCR_TBF \
)
/*-----------------------------------------------------------------------
* RTCSC - Real-Time Clock Status and Control Register UM 11-27
*-----------------------------------------------------------------------
*/
#define CFG_RTCSC ( RTCSC_SEC | \
RTCSC_ALR | \
RTCSC_RTF | \
RTCSC_RTE \
)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control UM 11-31
*-----------------------------------------------------------------------
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
*/
#define CFG_PISCR ( PISCR_PS | \
PISCR_PITF \
)
/*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register UM 15-30
*-----------------------------------------------------------------------
* Reset PLL lock status sticky bit, timer expired status bit and timer
* interrupt status bit. Set MF for 1:2:1 mode.
*/
#define CFG_PLPRCR ( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK) | \
PLPRCR_SPLSS | \
PLPRCR_TEXPS | \
PLPRCR_TMIST \
)
/*-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register UM 15-27
*-----------------------------------------------------------------------
* Set clock output, timebase and RTC source and divider,
* power management and some other internal clocks
*/
#define SCCR_MASK SCCR_EBDF11
#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \
SCCR_COM00 | /* full strength CLKOUT */ \
SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \
SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \
SCCR_DFNL000 | \
SCCR_DFNH000 \
)
/*-----------------------------------------------------------------------
* DER - Debug Enable Register UM 37-46
*-----------------------------------------------------------------------
* Mask all events that can cause entry into debug mode
*/
#define CFG_DER 0
/*
* Initialize Memory Controller:
*
* BR0 and OR0 (FLASH memory)
*/
#define FLASH_BASE0_PRELIM FLASH_BASE
/*
* Flash address mask
*/
#define CFG_PRELIM_OR_AM 0xfe000000
/*
* FLASH timing:
* 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1
*/
#define CFG_OR_TIMING_FLASH ( OR_CSNT_SAM | \
OR_ACS_DIV2 | \
OR_BI | \
OR_SCY_2_CLK | \
OR_TRLX | \
OR_EHTR \
)
#define CFG_OR0_PRELIM ( CFG_PRELIM_OR_AM | \
CFG_OR_TIMING_FLASH \
)
#define CFG_BR0_PRELIM ( (FLASH_BASE0_PRELIM & BR_BA_MSK) | \
BR_MS_GPCM | \
BR_PS_8 | \
BR_V \
)
/*
* SDRAM configuration
*/
#define CFG_OR1_AM 0xfc000000
#define CFG_OR1 ( (CFG_OR1_AM & OR_AM_MSK) | \
OR_CSNT_SAM \
)
#define CFG_BR1 ( (SDRAM_BASE & BR_BA_MSK) | \
BR_MS_UPMA | \
BR_PS_32 | \
BR_V \
)
/*
* Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank
* of 256 MBit SDRAM
*/
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16
/*
* Periodic timer for refresh @ 33 MHz system clock
*/
#define CFG_MAMR_PTA 64
/*
* MAMR settings for SDRAM
*/
#define CFG_MAMR_8COL ( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \
MAMR_PTAE | \
MAMR_AMA_TYPE_1 | \
MAMR_DSA_1_CYCL | \
MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | \
MAMR_WLFA_1X | \
MAMR_TLFA_4X \
)
/*
* CS2* configuration for Disk On Chip:
* 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1,
* no burst.
*/
#define CFG_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
OR_CSNT_SAM | \
OR_ACS_DIV2 | \
OR_BI | \
OR_SCY_2_CLK | \
OR_TRLX | \
OR_EHTR \
)
#define CFG_BR2_PRELIM ( (DOC_BASE & BR_BA_MSK) | \
BR_PS_8 | \
BR_MS_GPCM | \
BR_V \
)
/*
* CS3* configuration for FPGA:
* 33 MHz bus with SCY=15, no burst.
* The FPGA uses TA and TEA to terminate bus cycles, but we
* clear SETA and set the cycle length to a large number so that
* the cycle will still complete even if there is a configuration
* error that prevents TA from asserting on FPGA accesss.
*/
#define CFG_OR3_PRELIM ( (0xfc000000 & OR_AM_MSK) | \
OR_SCY_15_CLK | \
OR_BI \
)
#define CFG_BR3_PRELIM ( (FPGA_BASE & BR_BA_MSK) | \
BR_PS_32 | \
BR_MS_GPCM | \
BR_V \
)
/*
* CS4* configuration for FPGA SelectMap configuration interface.
* 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge
* of GCLK1_50
*/
#define CFG_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
OR_G5LS | \
OR_BI \
)
#define CFG_BR4_PRELIM ( (SELECTMAP_BASE & BR_BA_MSK) | \
BR_PS_8 | \
BR_MS_UPMB | \
BR_V \
)
/*
* CS5* configuration for Mil-Std 1553 databus interface.
* 33 MHz bus, GPCM, no burst.
* The 1553 interface uses TA and TEA to terminate bus cycles,
* but we clear SETA and set the cycle length to a large number so that
* the cycle will still complete even if there is a configuration
* error that prevents TA from asserting on FPGA accesss.
*/
#define CFG_OR5_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
OR_SCY_15_CLK | \
OR_EHTR | \
OR_TRLX | \
OR_CSNT_SAM | \
OR_BI \
)
#define CFG_BR5_PRELIM ( (M1553_BASE & BR_BA_MSK) | \
BR_PS_16 | \
BR_MS_GPCM | \
BR_V \
)
/*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/*
* Disk On Chip (millenium) configuration
*/
#define CFG_MAX_DOC_DEVICE 1
#undef CFG_DOC_SUPPORT_2000
#define CFG_DOC_SUPPORT_MILLENNIUM
#undef CFG_DOC_PASSIVE_PROBE
/*
* FEC interrupt assignment
*/
#define FEC_INTERRUPT SIU_LEVEL1
/*
* Sanity checks
*/
#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
#endif
#endif /* __CONFIG_GEN860T_H */
/* vim: set ts=4 tw=78 ai shiftwidth=4: */

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include/configs/NETVIA.h
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/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Pantelis Antoniou, Intracom S.A., panto@intracom.gr
* U-Boot port on NetVia board
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
#define CONFIG_NETVIA 1 /* ...on a NetVia board */
#undef CONFIG_NETVIA_PLL_CLOCK /* PLL or fixed crystal clock */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#ifdef CONFIG_NETVIA_PLL_CLOCK
/* XXX make sure that you calculate these two correctly */
#define CFG_GCLK_MF 1350
#define CONFIG_8xx_GCLK_FREQ 44236800
#else
#define CFG_GCLK_MF 1
#define CONFIG_8xx_GCLK_FREQ 50000000
#endif
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"tftpboot; " \
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
"bootm"
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_DHCP )
#define CONFIG_BOARD_PRE_INIT
#define CONFIG_MISC_INIT_R
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0300000 /* memtest works on */
#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Internal Memory Mapped Register
*/
#define CFG_IMMR 0xFF000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR CFG_IMMR
#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0x40000000
#if defined(DEBUG)
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#else
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
#endif
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE 0x10000
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9
* SYPCR can only be written once after reset!
*-----------------------------------------------------------------------
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
*/
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
#ifndef CONFIG_CAN_DRIVER
#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
#else /* we must activate GPL5 in the SIUMCR for CAN */
#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
#endif /* CONFIG_CAN_DRIVER */
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
*-----------------------------------------------------------------------
* Clear Reference Interrupt Status, Timebase freezing enabled
*/
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
/*-----------------------------------------------------------------------
* RTCSC - Real-Time Clock Status and Control Register 11-27
*-----------------------------------------------------------------------
*/
#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 11-31
*-----------------------------------------------------------------------
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
*/
#define CFG_PISCR (PISCR_PS | PISCR_PITF)
/*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
*-----------------------------------------------------------------------
* Reset PLL lock status sticky bit, timer expired status bit and timer
* interrupt status bit
*
*/
#define CFG_PLPRCR ( ((CFG_GCLK_MF-1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
/*-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register 15-27
*-----------------------------------------------------------------------
* Set clock output, timebase and RTC source and divider,
* power management and some other internal clocks
*/
#define SCCR_MASK SCCR_EBDF11
#define CFG_SCCR (SCCR_TBS | \
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00)
/*-----------------------------------------------------------------------
*
*-----------------------------------------------------------------------
*
*/
/*#define CFG_DER 0x2002000F*/
#define CFG_DER 0
/*
* Init Memory Controller:
*
* BR0/1 and OR0/1 (FLASH)
*/
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
/* used to re-map FLASH both when starting from SRAM or FLASH:
* restrict access enough to keep SRAM working (if any)
* but not too much to meddle with FLASH accesses
*/
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
/*
* BR1/2 and OR1/2 (4MByte Flash Bank x 2)
*
*/
#define FLASH0_SIZE 0x00400000 /* 4MByte */
#define FLASH0_BASE 0xF0000000
#define CFG_OR1_PRELIM ((0xFFFFFFFFLU & ~(FLASH0_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
#define CFG_BR1_PRELIM ((FLASH0_BASE & BR_BA_MSK) | BR_PS_32 | BR_V)
#define FLASH1_SIZE 0x00400000
#define FLASH1_BASE 0xF0400000
#define CFG_OR2_PRELIM ((0xFFFFFFFFLU & ~(FLASH1_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
#define CFG_BR2_PRELIM ((FLASH1_BASE & BR_BA_MSK) | BR_PS_32 | BR_V)
/*
* BR3 and OR3 (SDRAM)
*
*/
#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
#define CFG_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
/*
* BR6 (External register)
* 16 bit port size - leds are at high 8 bits
*/
#define EXTREG_BASE 0x30000000 /* external register */
#define EXTREG_SIZE 0x00010000 /* max 64K */
#define CFG_OR6_PRELIM ((0xFFFFFFFFLU & ~(EXTREG_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_15_CLK | OR_TRLX)
#define CFG_BR6_PRELIM ((EXTREG_BASE & BR_BA_MSK) | BR_PS_32 | BR_V)
/*
* Memory Periodic Timer Prescaler
*/
/* periodic timer for refresh */
#define CFG_MAMR_PTA 208
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
/*
* MAMR settings for SDRAM
*/
/* 9 column SDRAM */
#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/* Ethernet at SCC2 */
#define CONFIG_SCC2_ENET
#endif /* __CONFIG_H */

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/*
* (C) Copyright 2000, 2001, 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
* U-Boot port on RPXlite board
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define RPXClassic_50MHz
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC860 1
#define CONFIG_RPXCLASSIC 1
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
/* Define CONFIG_FEC_ENET to use Fast ethernet instead of ethernet on SCC1 */
#undef CONFIG_FEC_ENET
#ifdef CONFIG_FEC_ENET
#define CFG_DISCOVER_PHY 1
#endif /* CONFIG_FEC_ENET */
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
#define CONFIG_ZERO_BOOTDELAY_CHECK 1
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"tftpboot; " \
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
"bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
#define CONFIG_COMMANDS (CFG_CMD_ALL & ~CFG_CMD_NONSTD | CFG_CMD_ELF)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_RESET_ADDRESS 0x80000000
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0040000 /* memtest works on */
#define CFG_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Internal Memory Mapped Register
*/
#define CFG_IMMR 0xFA200000
/*-----------------------------------------------------------------------------
* I2C Configuration
*-----------------------------------------------------------------------------
*/
#define CONFIG_I2C 1
#define CFG_I2C_SPEED 50000
#define CFG_I2C_SLAVE 0x34
/* enable I2C and select the hardware/software driver */
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
/*
* Software (bit-bang) I2C driver configuration
*/
#define I2C_PORT 1 /* Port A=0, B=1, C=2, D=3 */
#define I2C_ACTIVE (iop->pdir |= 0x00000010)
#define I2C_TRISTATE (iop->pdir &= ~0x00000010)
#define I2C_READ ((iop->pdat & 0x00000010) != 0)
#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000010; \
else iop->pdat &= ~0x00000010
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000020; \
else iop->pdat &= ~0x00000020
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
# define CFG_I2C_SPEED 50000
# define CFG_I2C_SLAVE 0x34
# define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */
# define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR CFG_IMMR
#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xFF000000
#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#else
#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
#endif
#define CFG_MONITOR_BASE 0xFF000000
/*%%% #define CFG_MONITOR_BASE CFG_FLASH_BASE */
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#if 0
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
#else
#define CFG_ENV_IS_IN_NVRAM 1
#define CFG_ENV_ADDR 0xfa000100
#define CFG_ENV_SIZE 0x1000
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9
* SYPCR can only be written once after reset!
*-----------------------------------------------------------------------
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
*/
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
SYPCR_SWP)
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
#define CFG_SIUMCR (SIUMCR_MLRC10)
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
*-----------------------------------------------------------------------
* Clear Reference Interrupt Status, Timebase freezing enabled
*/
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
/*-----------------------------------------------------------------------
* RTCSC - Real-Time Clock Status and Control Register 11-27
*-----------------------------------------------------------------------
*/
/*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 11-31
*-----------------------------------------------------------------------
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
*/
#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
/*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
*-----------------------------------------------------------------------
* Reset PLL lock status sticky bit, timer expired status bit and timer
* interrupt status bit
*
* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
*/
/* up to 50 MHz we use a 1:1 clock */
#define CFG_PLPRCR ( (4 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS | PLPRCR_SPLSS | PLPRCR_TMIST)
/*-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register 15-27
*-----------------------------------------------------------------------
* Set clock output, timebase and RTC source and divider,
* power management and some other internal clocks
*/
#define SCCR_MASK SCCR_EBDF00
/* up to 50 MHz we use a 1:1 clock */
#define CFG_SCCR (SCCR_COM00 | SCCR_TBS)
/*-----------------------------------------------------------------------
* PCMCIA stuff
*-----------------------------------------------------------------------
*
*/
#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
#define CFG_PCMCIA_IO_ADDR (0xEC000000)
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
/*-----------------------------------------------------------------------
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
*-----------------------------------------------------------------------
*/
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
#define CFG_ATA_IDE0_OFFSET 0x0000
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
/* Offset for data I/O */
#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
/* Offset for normal register accesses */
#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
/* Offset for alternate registers */
#define CFG_ATA_ALT_OFFSET 0x0100
/*-----------------------------------------------------------------------
*
*-----------------------------------------------------------------------
*
*/
/* #define CFG_DER 0x2002000F */
/* #define CFG_DER 0 */
#define CFG_DER 0x0082000F
/*
* Init Memory Controller:
*
* BR0 and OR0 (FLASH)
*/
#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */
#define CFG_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
/*
* BR1 and OR1 (SDRAM)
*
*/
#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
#define CFG_OR_TIMING_SDRAM 0x00000E00
#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
/* RPXLITE mem setting */
#define CFG_BR3_PRELIM 0xFA400001 /* BCSR */
#define CFG_OR3_PRELIM 0xff7f8970
#define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
#define CFG_OR4_PRELIM 0xFFF80970
/*
* Memory Periodic Timer Prescaler
*/
/* periodic timer for refresh */
#define CFG_MAMR_PTA 58
/*
* Refresh clock Prescalar
*/
#define CFG_MPTPR MPTPR_PTP_DIV8
/*
* MAMR settings for SDRAM
*/
/* 10 column SDRAM */
#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \
MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
/* Configuration variable added by yooth. */
/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
/*
* BCSRx
*
* Board Status and Control Registers
*
*/
#define BCSR0 0xFA400000
#define BCSR1 0xFA400001
#define BCSR2 0xFA400002
#define BCSR3 0xFA400003
#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
#define BCSR0_COLTEST 0x20
#define BCSR0_ETHLPBK 0x40
#define BCSR0_ETHEN 0x80
#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
#define BCSR1_PCVCTL6 0x02
#define BCSR1_PCVCTL5 0x04
#define BCSR1_PCVCTL4 0x08
#define BCSR1_IPB5SEL 0x10
#define BCSR2_MIIRST 0x80
#define BCSR2_MIIPWRDWN 0x40
#define BCSR2_MIICTL 0x08
#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
#define BCSR3_BWNVR 0x02 /* NVRAM Battery */
#define BCSR3_RDY_BSY 0x04 /* Flash Operation */
#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
#define BCSR3_D27 0x10 /* Dip Switch settings */
#define BCSR3_D26 0x20
#define BCSR3_D25 0x40
#define BCSR3_D24 0x80
/*
* Environment setting
*/
/* #define CONFIG_ETHADDR 00:10:EC:00:2C:A2 */
/* #define CONFIG_IPADDR 10.10.106.1 */
/* #define CONFIG_SERVERIP 10.10.104.11 */
#endif /* __CONFIG_H */

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/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
* U-Boot port on RPXlite board
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define RPXLite_50MHz
/*
* High Level Configuration Options
* (easy to change)
*/
#undef CONFIG_MPC860
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
#define CONFIG_RPXLITE 1
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp; " \
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
"bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0040000 /* memtest works on */
#define CFG_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Internal Memory Mapped Register
*/
#define CFG_IMMR 0xFA200000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR CFG_IMMR
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xFFC00000
/*%%% #define CFG_FLASH_BASE 0xFFF00000 */
#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#else
#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
#endif
#define CFG_MONITOR_BASE 0xFFF00000
/*%%% #define CFG_MONITOR_BASE CFG_FLASH_BASE */
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 19 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9
* SYPCR can only be written once after reset!
*-----------------------------------------------------------------------
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
*/
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
#define CFG_SIUMCR (SIUMCR_MLRC10)
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
*-----------------------------------------------------------------------
* Clear Reference Interrupt Status, Timebase freezing enabled
*/
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
/*-----------------------------------------------------------------------
* RTCSC - Real-Time Clock Status and Control Register 11-27
*-----------------------------------------------------------------------
*/
/*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
#define CFG_RTCSC (RTCSC_SEC | RTCSC_RTE)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 11-31
*-----------------------------------------------------------------------
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
*/
#define CFG_PISCR (PISCR_PS | PISCR_PITF)
/*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
*-----------------------------------------------------------------------
* Reset PLL lock status sticky bit, timer expired status bit and timer
* interrupt status bit
*
* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
*/
/* up to 50 MHz we use a 1:1 clock */
#define CFG_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
/*-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register 15-27
*-----------------------------------------------------------------------
* Set clock output, timebase and RTC source and divider,
* power management and some other internal clocks
*/
#define SCCR_MASK SCCR_EBDF00
/* up to 50 MHz we use a 1:1 clock */
#define CFG_SCCR (SCCR_COM11 | SCCR_TBS)
/*-----------------------------------------------------------------------
* PCMCIA stuff
*-----------------------------------------------------------------------
*
*/
#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
#define CFG_PCMCIA_IO_ADDR (0xEC000000)
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
/*-----------------------------------------------------------------------
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
*-----------------------------------------------------------------------
*/
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
#define CFG_ATA_IDE0_OFFSET 0x0000
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
/* Offset for data I/O */
#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
/* Offset for normal register accesses */
#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
/* Offset for alternate registers */
#define CFG_ATA_ALT_OFFSET 0x0100
/*-----------------------------------------------------------------------
*
*-----------------------------------------------------------------------
*
*/
/*#define CFG_DER 0x2002000F*/
#define CFG_DER 0
/*
* Init Memory Controller:
*
* BR0 and OR0 (FLASH)
*/
#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */
#define CFG_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
/*
* BR1 and OR1 (SDRAM)
*
*/
#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
#define CFG_OR_TIMING_SDRAM 0x00000E00
#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
/* RPXLITE mem setting */
#define CFG_BR3_PRELIM 0xFA400001 /* BCSR */
#define CFG_OR3_PRELIM 0xFFFF8910
#define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
#define CFG_OR4_PRELIM 0xFFFE0970
/*
* Memory Periodic Timer Prescaler
*/
/* periodic timer for refresh */
#define CFG_MAMR_PTA 58
/*
* Refresh clock Prescalar
*/
#define CFG_MPTPR MPTPR_PTP_DIV8
/*
* MAMR settings for SDRAM
*/
/* 10 column SDRAM */
#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \
MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
/* Configuration variable added by yooth. */
/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
/*
* BCSRx
*
* Board Status and Control Registers
*
*/
#define BCSR0 0xFA400000
#define BCSR1 0xFA400001
#define BCSR2 0xFA400002
#define BCSR3 0xFA400003
#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
#define BCSR0_COLTEST 0x20
#define BCSR0_ETHLPBK 0x40
#define BCSR0_ETHEN 0x80
#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
#define BCSR1_PCVCTL6 0x02
#define BCSR1_PCVCTL5 0x04
#define BCSR1_PCVCTL4 0x08
#define BCSR1_IPB5SEL 0x10
#define BCSR2_ENPA5HDR 0x08 /* USB Control */
#define BCSR2_ENUSBCLK 0x10
#define BCSR2_USBPWREN 0x20
#define BCSR2_USBSPD 0x40
#define BCSR2_USBSUSP 0x80
#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
#define BCSR3_BWNVR 0x02 /* NVRAM Battery */
#define BCSR3_RDY_BSY 0x04 /* Flash Operation */
#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
#define BCSR3_D27 0x10 /* Dip Switch settings */
#define BCSR3_D26 0x20
#define BCSR3_D25 0x40
#define BCSR3_D24 0x80
/*
* Environment setting
*/
#define CONFIG_ETHADDR 00:10:EC:00:1D:0B
#define CONFIG_IPADDR 192.168.1.65
#define CONFIG_SERVERIP 192.168.1.27
#endif /* __CONFIG_H */

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include/configs/RPXsuper.h
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#ifndef __CONFIG_H
#define __CONFIG_H
/*****************************************************************************
*
* These settings must match the way _your_ board is set up
*
*****************************************************************************/
/* for the AY-Revision which does not use the HRCW */
#define CFG_DEFAULT_IMMR 0x00010000
/* What is the oscillator's (UX2) frequency in Hz? */
#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
/* How is switch S2 set? We really only want the MODCK[1-3] bits, so
* only the 3 least significant bits are important.
*/
#define CFG_SBC_S2 0x04
/* What should MODCK_H be? It is dependent on the oscillator
* frequency, MODCK[1-3], and desired CPM and core frequencies.
* Some example values (all frequencies are in MHz):
*
* MODCK_H MODCK[1-3] Osc CPM Core
* 0x2 0x2 33 133 133
* 0x2 0x4 33 133 200
* 0x5 0x5 66 133 133
* 0x5 0x7 66 133 200
*/
#define CFG_SBC_MODCK_H 0x06
#define CFG_SBC_BOOT_LOW 1 /* only for HRCW */
#undef CFG_SBC_BOOT_LOW
/* What should the base address of the main FLASH be and how big is
* it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk
* The main FLASH is whichever is connected to *CS0. U-Boot expects
* this to be the SIMM.
*/
#define CFG_FLASH0_BASE 0x80000000
#define CFG_FLASH0_SIZE 16
/* What should the base address of the secondary FLASH be and how big
* is it (in Mbytes)? The secondary FLASH is whichever is connected
* to *CS6. U-Boot expects this to be the on board FLASH. If you don't
* want it enabled, don't define these constants.
*/
#define CFG_FLASH1_BASE 0
#define CFG_FLASH1_SIZE 0
#undef CFG_FLASH1_BASE
#undef CFG_FLASH1_SIZE
/* What should be the base address of SDRAM DIMM and how big is
* it (in Mbytes)?
*/
#define CFG_SDRAM0_BASE 0x00000000
#define CFG_SDRAM0_SIZE 64
/* What should be the base address of SDRAM DIMM and how big is
* it (in Mbytes)?
*/
#define CFG_SDRAM1_BASE 0x04000000
#define CFG_SDRAM1_SIZE 32
/* What should be the base address of the LEDs and switch S0?
* If you don't want them enabled, don't define this.
*/
#define CFG_LED_BASE 0x00000000
/*
* select serial console configuration
*
* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
* for SCC).
*
* if CONFIG_CONS_NONE is defined, then the serial console routines must
* defined elsewhere.
*/
#define CONFIG_CONS_ON_SMC /* define if console on SMC */
#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
#undef CONFIG_CONS_NONE /* define if console on neither */
#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
/*
* select ethernet configuration
*
* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
* defined elsewhere (as for the console), or CFG_CMD_NET must be removed
* from CONFIG_COMMANDS to remove support for networking.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
#define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */
#if ( CONFIG_ETHER_INDEX == 3 )
/*
* - Rx-CLK is CLK15
* - Tx-CLK is CLK16
* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
* - Enable Half Duplex in FSMR
*/
# define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
# define CFG_CPMFCR_RAMTYPE 0
/*#define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */
# define CFG_FCC_PSMR 0
#else /* CONFIG_ETHER_INDEX */
# error "on RPX Super ethernet must be FCC3"
#endif /* CONFIG_ETHER_INDEX */
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
/* Define this to reserve an entire FLASH sector (256 KB) for
* environment variables. Otherwise, the environment will be
* put in the same sector as U-Boot, and changing variables
* will erase U-Boot temporarily
*/
#define CFG_ENV_IN_OWN_SECT
/* Define to allow the user to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
/* What should the console's baud rate be? */
#define CONFIG_BAUDRATE 115200
/* Ethernet MAC address */
#define CONFIG_ETHADDR 08:00:22:50:70:63
#define CONFIG_IPADDR 192.168.1.99
#define CONFIG_SERVERIP 192.168.1.3
/* Set to a positive value to delay for running BOOTCOMMAND */
#define CONFIG_BOOTDELAY -1
/* undef this to save memory */
#define CFG_LONGHELP
/* Monitor Command Prompt */
#define CFG_PROMPT "=> "
/* What U-Boot subsytems do you want enabled? */
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_IMMAP | \
CFG_CMD_ASKENV | \
CFG_CMD_ECHO | \
CFG_CMD_I2C | \
CFG_CMD_REGINFO & \
~CFG_CMD_KGDB )
/* Where do the internal registers live? */
#define CFG_IMMR 0xF0000000
/* Where do the on board registers (CS4) live? */
#define CFG_REGS_BASE 0xFA000000
/*****************************************************************************
*
* You should not have to modify any of the following settings
*
*****************************************************************************/
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_RPXSUPER 1 /* on an Embedded Planet RPX Super Board */
#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
/* Print Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
#define CFG_MAXARGS 8 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x04000000 /* memtest works on */
#define CFG_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/* valid baudrates */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
#define CFG_FLASH_BASE CFG_FLASH0_BASE
#define CFG_SDRAM_BASE CFG_SDRAM0_BASE
/*-----------------------------------------------------------------------
* Hard Reset Configuration Words
*/
#if defined(CFG_SBC_BOOT_LOW)
# define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
#else
# define CFG_SBC_HRCW_BOOT_FLAGS (0)
#endif /* defined(CFG_SBC_BOOT_LOW) */
/* get the HRCW ISB field from CFG_IMMR */
#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\
((CFG_IMMR & 0x01000000) >> 7) |\
((CFG_IMMR & 0x00100000) >> 4) )
#define CFG_HRCW_MASTER (HRCW_BPS11 |\
HRCW_DPPC11 |\
CFG_SBC_HRCW_IMMR |\
HRCW_MMR00 |\
HRCW_LBPC11 |\
HRCW_APPC10 |\
HRCW_CS10PC00 |\
(CFG_SBC_MODCK_H & HRCW_MODCK_H1111) |\
CFG_SBC_HRCW_BOOT_FLAGS)
/* no slaves */
#define CFG_HRCW_SLAVE1 0
#define CFG_HRCW_SLAVE2 0
#define CFG_HRCW_SLAVE3 0
#define CFG_HRCW_SLAVE4 0
#define CFG_HRCW_SLAVE5 0
#define CFG_HRCW_SLAVE6 0
#define CFG_HRCW_SLAVE7 0
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR CFG_IMMR
#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
* Note also that the logic that sets CFG_RAMBOOT is platform dependent.
*/
#define CFG_MONITOR_BASE (CFG_FLASH0_BASE + 0x00F00000)
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
# define CFG_RAMBOOT
#endif
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
#ifndef CFG_RAMBOOT
# define CFG_ENV_IS_IN_FLASH 1
# ifdef CFG_ENV_IN_OWN_SECT
# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
# define CFG_ENV_SECT_SIZE 0x40000
# else
# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
# define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
# endif /* CFG_ENV_IN_OWN_SECT */
#else
# define CFG_ENV_IS_IN_NVRAM 1
# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
# define CFG_ENV_SIZE 0x200
#endif /* CFG_RAMBOOT */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* HIDx - Hardware Implementation-dependent Registers 2-11
*-----------------------------------------------------------------------
* HID0 also contains cache control - initially enable both caches and
* invalidate contents, then the final state leaves only the instruction
* cache enabled. Note that Power-On and Hard reset invalidate the caches,
* but Soft reset does not.
*
* HID1 has only read-only information - nothing to set.
*/
#define CFG_HID0_INIT (/*HID0_ICE |*/\
/*HID0_DCE |*/\
HID0_ICFI |\
HID0_DCI |\
HID0_IFEM |\
HID0_ABE)
#define CFG_HID0_FINAL (/*HID0_ICE |*/\
HID0_IFEM |\
HID0_ABE |\
HID0_EMCP)
#define CFG_HID2 0
/*-----------------------------------------------------------------------
* RMR - Reset Mode Register
*-----------------------------------------------------------------------
*/
#define CFG_RMR 0
/*-----------------------------------------------------------------------
* BCR - Bus Configuration 4-25
*-----------------------------------------------------------------------
*/
#define CFG_BCR (BCR_EBM |\
BCR_PLDP |\
BCR_EAV |\
BCR_NPQM0)
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration 4-31
*-----------------------------------------------------------------------
*/
#define CFG_SIUMCR (SIUMCR_L2CPC01 |\
SIUMCR_APPC10 |\
SIUMCR_CS10PC01)
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9
* SYPCR can only be written once after reset!
*-----------------------------------------------------------------------
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
*/
#define CFG_SYPCR (SYPCR_SWTC |\
SYPCR_BMT |\
SYPCR_PBME |\
SYPCR_LBME |\
SYPCR_SWRI |\
SYPCR_SWP)
/*-----------------------------------------------------------------------
* TMCNTSC - Time Counter Status and Control 4-40
*-----------------------------------------------------------------------
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
* and enable Time Counter
*/
#define CFG_TMCNTSC (TMCNTSC_SEC |\
TMCNTSC_ALR |\
TMCNTSC_TCF |\
TMCNTSC_TCE)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 4-42
*-----------------------------------------------------------------------
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
* Periodic timer
*/
#define CFG_PISCR (PISCR_PS |\
PISCR_PTF |\
PISCR_PTE)
/*-----------------------------------------------------------------------
* SCCR - System Clock Control 9-8
*-----------------------------------------------------------------------
*/
#define CFG_SCCR (SCCR_DFBRG01)
/*-----------------------------------------------------------------------
* RCCR - RISC Controller Configuration 13-7
*-----------------------------------------------------------------------
*/
#define CFG_RCCR 0
/*
* Init Memory Controller:
*
* Bank Bus Machine PortSz Device
* ---- --- ------- ------ ------
* 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90)
* 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Hitachi HM5225325FBP-B60)
* 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Hitachi HM5225325FBP-B60)
* 3 unused
* 4 60x GPCM 8 bit Board Regs, LEDs, switches
* 5 unused
* 6 unused
* 7 unused
* 8 PCMCIA
* 9 unused
* 10 unused
* 11 unused
*/
/* Bank 0 - FLASH
*
*/
#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
BRx_PS_64 |\
BRx_DECC_NONE |\
BRx_MS_GPCM_P |\
BRx_V)
#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
ORxG_CSNT |\
ORxG_ACS_DIV1 |\
ORxG_SCY_6_CLK |\
ORxG_EHTR)
/* Bank 1 - SDRAM
*
*/
#define CFG_BR1_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
BRx_PS_64 |\
BRx_MS_SDRAM_P |\
BRx_V)
#define CFG_OR1_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
ORxS_BPD_4 |\
ORxS_ROWST_PBI0_A8 |\
ORxS_NUMR_12 |\
ORxS_IBID)
#define CFG_PSDMR 0x014DA412
#define CFG_PSRT 0x79
/* Bank 2 - SDRAM
*
*/
#define CFG_BR2_PRELIM ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
BRx_PS_32 |\
BRx_MS_SDRAM_L |\
BRx_V)
#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM1_SIZE) |\
ORxS_BPD_4 |\
ORxS_ROWST_PBI0_A9 |\
ORxS_NUMR_12)
#define CFG_LSDMR 0x0169A512
#define CFG_LSRT 0x79
#define CFG_MPTPR (0x0800 & MPTPR_PTP_MSK)
/* Bank 4 - On board registers
*
*/
#define CFG_BR4_PRELIM ((CFG_REGS_BASE & BRx_BA_MSK) |\
BRx_PS_8 |\
BRx_MS_GPCM_P |\
BRx_V)
#define CFG_OR4_PRELIM (ORxG_AM_MSK |\
ORxG_CSNT |\
ORxG_ACS_DIV1 |\
ORxG_SCY_5_CLK |\
ORxG_TRLX)
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#endif /* __CONFIG_H */

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include/configs/ep8260.h
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/*
* (C) Copyright 2002
* Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
*
* This file is based on similar values for other boards found in other
* U-Boot config files, and some that I found in the EP8260 manual.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*
* Note: my board is a "SBC 8260 H, V.1.1"
* - 64M 60x Bus SDRAM
* - 32M Local Bus SDRAM
* - 16M Flash (4 x AM29DL323DB90WDI)
* - 128k NVRAM with RTC
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* What is the oscillator's (UX2) frequency in Hz? */
#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
/*-----------------------------------------------------------------------
* MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
*-----------------------------------------------------------------------
* What should MODCK_H be? It is dependent on the oscillator
* frequency, MODCK[1-3], and desired CPM and core frequencies.
* Here are some example values (all frequencies are in MHz):
*
* MODCK_H MODCK[1-3] Osc CPM Core
* ------- ---------- --- --- ----
* 0x2 0x2 33 133 133
* 0x2 0x3 33 133 166
* 0x2 0x4 33 133 200
* 0x2 0x5 33 133 233
* 0x2 0x6 33 133 266
*
* 0x5 0x5 66 133 133
* 0x5 0x6 66 133 166
* 0x5 0x7 66 133 200 *
* 0x6 0x0 66 133 233
* 0x6 0x1 66 133 266
* 0x6 0x2 66 133 300
*/
#define CFG_SBC_MODCK_H 0x05
/* Define this if you want to boot from 0x00000100. If you don't define
* this, you will need to program the bootloader to 0xfff00000, and
* get the hardware reset config words at 0xfe000000. The simplest
* way to do that is to program the bootloader at both addresses.
* It is suggested that you just let U-Boot live at 0x00000000.
*/
/* #define CFG_SBC_BOOT_LOW 1 */ /* only for HRCW */
/* #undef CFG_SBC_BOOT_LOW */
/* The reset command will not work as expected if the reset address does
* not point to the correct address.
*/
#define CFG_RESET_ADDRESS 0xFFF00100
/* What should the base address of the main FLASH be and how big is
* it (in MBytes)? This must contain TEXT_BASE from board/ep8260/config.mk
* The main FLASH is whichever is connected to *CS0. U-Boot expects
* this to be the SIMM.
*/
#define CFG_FLASH0_BASE 0xFF000000
#define CFG_FLASH0_SIZE 16
/* What should the base address of the secondary FLASH be and how big
* is it (in Mbytes)? The secondary FLASH is whichever is connected
* to *CS6. U-Boot expects this to be the on board FLASH. If you don't
* want it enabled, don't define these constants.
*/
#define CFG_FLASH1_BASE 0
#define CFG_FLASH1_SIZE 0
#undef CFG_FLASH1_BASE
#undef CFG_FLASH1_SIZE
/* What should be the base address of SDRAM DIMM (60x bus) and how big is
* it (in Mbytes)?
*/
#define CFG_SDRAM0_BASE 0x00000000
#define CFG_SDRAM0_SIZE 64
/* define CFG_LSDRAM if you want to enable the 32M SDRAM on the
* local bus (8260 local bus is NOT cacheable!)
*/
/* #define CFG_LSDRAM */
#undef CFG_LSDRAM
#ifdef CFG_LSDRAM
/* What should be the base address of SDRAM DIMM (local bus) and how big is
* it (in Mbytes)?
*/
#define CFG_SDRAM1_BASE 0x04000000
#define CFG_SDRAM1_SIZE 32
#else
#define CFG_SDRAM1_BASE 0
#define CFG_SDRAM1_SIZE 0
#undef CFG_SDRAM1_BASE
#undef CFG_SDRAM1_SIZE
#endif /* CFG_LSDRAM */
/* What should be the base address of NVRAM and how big is
* it (in Bytes)
*/
#define CFG_NVRAM_BASE_ADDR 0xFa080000
#define CFG_NVRAM_SIZE (128*1024)-16
/* The RTC is a Dallas DS1556
*/
#define CONFIG_RTC_DS1556
/* What should be the base address of the LEDs and switch S0?
* If you don't want them enabled, don't define this.
*/
#define CFG_LED_BASE 0x00000000
#undef CFG_LED_BASE
/*
* select serial console configuration
*
* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
* for SCC).
*
* if CONFIG_CONS_NONE is defined, then the serial console routines must
* defined elsewhere.
*/
#define CONFIG_CONS_ON_SMC /* define if console on SMC */
#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
#undef CONFIG_CONS_NONE /* define if console on neither */
#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
/*
* select ethernet configuration
*
* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
* defined elsewhere (as for the console), or CFG_CMD_NET must be removed
* from CONFIG_COMMANDS to remove support for networking.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
#define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */
#if ( CONFIG_ETHER_INDEX == 3 )
/*
* - Rx-CLK is CLK15
* - Tx-CLK is CLK16
* - RAM for BD/Buffers is on the local Bus (see 28-13)
* - Enable Half Duplex in FSMR
*/
# define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
/*
* - RAM for BD/Buffers is on the local Bus (see 28-13)
*/
#ifdef CFG_LSDRAM
#define CFG_CPMFCR_RAMTYPE 3
#else /* CFG_LSDRAM */
#define CFG_CPMFCR_RAMTYPE 0
#endif /* CFG_LSDRAM */
/* - Enable Half Duplex in FSMR */
/* # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */
# define CFG_FCC_PSMR 0
#else /* CONFIG_ETHER_INDEX */
# error "on EP8260 ethernet must be FCC3"
#endif /* CONFIG_ETHER_INDEX */
/*
* select i2c support configuration
*
* Supported configurations are {none, software, hardware} drivers.
* If the software driver is chosen, there are some additional
* configuration items that the driver uses to drive the port pins.
*/
#undef CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
/*
* Software (bit-bang) I2C driver configuration
*/
#ifdef CONFIG_SOFT_I2C
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
#define I2C_ACTIVE (iop->pdir |= 0x00010000)
#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
#define I2C_READ ((iop->pdat & 0x00010000) != 0)
#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
else iop->pdat &= ~0x00010000
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
else iop->pdat &= ~0x00020000
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
#endif /* CONFIG_SOFT_I2C */
/* #define CONFIG_RTC_DS174x */
/* Define this to reserve an entire FLASH sector (256 KB) for
* environment variables. Otherwise, the environment will be
* put in the same sector as U-Boot, and changing variables
* will erase U-Boot temporarily
*/
#define CFG_ENV_IN_OWN_SECT
/* Define to allow the user to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
/* What should the console's baud rate be? */
/* #define CONFIG_BAUDRATE 57600 */
#define CONFIG_BAUDRATE 115200
/* Ethernet MAC address */
#define CONFIG_ETHADDR 00:10:EC:00:30:8C
#define CONFIG_IPADDR 192.168.254.130
#define CONFIG_SERVERIP 192.168.254.49
/* Set to a positive value to delay for running BOOTCOMMAND */
#define CONFIG_BOOTDELAY -1
/* undef this to save memory */
#define CFG_LONGHELP
/* Monitor Command Prompt */
#define CFG_PROMPT "=> "
/* Define this variable to enable the "hush" shell (from
Busybox) as command line interpreter, thus enabling
powerful command line syntax like
if...then...else...fi conditionals or `&&' and '||'
constructs ("shell scripts").
If undefined, you get the old, much simpler behaviour
with a somewhat smapper memory footprint.
*/
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
/* What U-Boot subsytems do you want enabled? */
/*
*/
#define CONFIG_COMMANDS ( CFG_CMD_ALL & \
~CFG_CMD_BSP & \
~CFG_CMD_DCR & \
~CFG_CMD_DHCP & \
~CFG_CMD_DOC & \
~CFG_CMD_EEPROM & \
~CFG_CMD_FDC & \
~CFG_CMD_HWFLOW & \
~CFG_CMD_IDE & \
~CFG_CMD_JFFS2 & \
~CFG_CMD_KGDB & \
~CFG_CMD_MII & \
~CFG_CMD_PCI & \
~CFG_CMD_PCMCIA & \
~CFG_CMD_SCSI & \
~CFG_CMD_USB & \
~CFG_CMD_VFD & \
~CFG_CMD_DTT )
/* Where do the internal registers live? */
#define CFG_IMMR 0xF0000000
#define CFG_DEFAULT_IMMR 0x00010000
/* Where do the on board registers (CS4) live? */
#define CFG_REGS_BASE 0xFA000000
/*****************************************************************************
*
* You should not have to modify any of the following settings
*
*****************************************************************************/
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_EP8260 11 /* on an Embedded Planet EP8260 Board, Rev. 11 */
#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
/* Print Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
#define CFG_MAXARGS 8 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#ifdef CFG_LSDRAM
#define CFG_MEMTEST_START 0x04000000 /* memtest works on */
#define CFG_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */
#else
#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
#define CFG_MEMTEST_END 0x02000000 /* 0-32 MB in SDRAM */
#endif /* CFG_LSDRAM */
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
#define CFG_LOAD_ADDR 0x00100000 /* default load address */
#define CFG_TFTP_LOADADDR 0x00100000 /* default load address for network file downloads */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/* valid baudrates */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
#define CFG_FLASH_BASE CFG_FLASH0_BASE
#define CFG_SDRAM_BASE CFG_SDRAM0_BASE
/*-----------------------------------------------------------------------
* Hard Reset Configuration Words
*/
#if defined(CFG_SBC_BOOT_LOW)
# define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
#else
# define CFG_SBC_HRCW_BOOT_FLAGS (0x00000000)
#endif /* defined(CFG_SBC_BOOT_LOW) */
/* get the HRCW ISB field from CFG_IMMR */
/*
#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\
((CFG_IMMR & 0x01000000) >> 7) |\
((CFG_IMMR & 0x00100000) >> 4) )
#define CFG_HRCW_MASTER (HRCW_EBM |\
HRCW_L2CPC01 |\
CFG_SBC_HRCW_IMMR |\
HRCW_APPC10 |\
HRCW_CS10PC01 |\
HRCW_MODCK_H0101 |\
CFG_SBC_HRCW_BOOT_FLAGS)
*/
#define CFG_HRCW_MASTER 0x10400245
/* no slaves */
#define CFG_HRCW_SLAVE1 0
#define CFG_HRCW_SLAVE2 0
#define CFG_HRCW_SLAVE3 0
#define CFG_HRCW_SLAVE4 0
#define CFG_HRCW_SLAVE5 0
#define CFG_HRCW_SLAVE6 0
#define CFG_HRCW_SLAVE7 0
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR CFG_IMMR
#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
* Note also that the logic that sets CFG_RAMBOOT is platform dependent.
*/
#define CFG_MONITOR_BASE TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
# define CFG_RAMBOOT
#endif
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
#ifndef CFG_RAMBOOT
# define CFG_ENV_IS_IN_FLASH 1
# ifdef CFG_ENV_IN_OWN_SECT
# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
# define CFG_ENV_SECT_SIZE 0x40000
# else
# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
# define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
# endif /* CFG_ENV_IN_OWN_SECT */
#else
# define CFG_ENV_IS_IN_NVRAM 1
# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
# define CFG_ENV_SIZE 0x200
#endif /* CFG_RAMBOOT */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* HIDx - Hardware Implementation-dependent Registers 2-11
*-----------------------------------------------------------------------
* HID0 also contains cache control - initially enable both caches and
* invalidate contents, then the final state leaves only the instruction
* cache enabled. Note that Power-On and Hard reset invalidate the caches,
* but Soft reset does not.
*
* HID1 has only read-only information - nothing to set.
*/
#define CFG_HID0_INIT (HID0_ICE |\
HID0_DCE |\
HID0_ICFI |\
HID0_DCI |\
HID0_IFEM |\
HID0_ABE)
#ifdef CFG_LSDRAM
/* 8260 local bus is NOT cacheable */
#define CFG_HID0_FINAL (/*HID0_ICE |*/\
HID0_IFEM |\
HID0_ABE |\
HID0_EMCP)
#else /* !CFG_LSDRAM */
#define CFG_HID0_FINAL (HID0_ICE |\
HID0_IFEM |\
HID0_ABE |\
HID0_EMCP)
#endif /* CFG_LSDRAM */
#define CFG_HID2 0
/*-----------------------------------------------------------------------
* RMR - Reset Mode Register
*-----------------------------------------------------------------------
*/
#define CFG_RMR 0
/*-----------------------------------------------------------------------
* BCR - Bus Configuration 4-25
*-----------------------------------------------------------------------
*/
/*#define CFG_BCR (BCR_EBM |\
BCR_PLDP |\
BCR_EAV |\
BCR_NPQM1)
*/
#define CFG_BCR 0x80C08000
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration 4-31
*-----------------------------------------------------------------------
*/
#define CFG_SIUMCR (SIUMCR_L2CPC01 |\
SIUMCR_APPC10 |\
SIUMCR_CS10PC01)
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9
* SYPCR can only be written once after reset!
*-----------------------------------------------------------------------
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
*/
#ifdef CFG_LSDRAM
#define CFG_SYPCR (SYPCR_SWTC |\
SYPCR_BMT |\
SYPCR_PBME |\
SYPCR_LBME |\
SYPCR_SWP)
#else
#define CFG_SYPCR (SYPCR_SWTC |\
SYPCR_BMT |\
SYPCR_PBME |\
SYPCR_SWP)
#endif
/*-----------------------------------------------------------------------
* TMCNTSC - Time Counter Status and Control 4-40
*-----------------------------------------------------------------------
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
* and enable Time Counter
*/
#define CFG_TMCNTSC (TMCNTSC_SEC |\
TMCNTSC_ALR |\
TMCNTSC_TCF |\
TMCNTSC_TCE)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 4-42
*-----------------------------------------------------------------------
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
* Periodic timer
*/
/*#define CFG_PISCR (PISCR_PS |\
PISCR_PTF |\
PISCR_PTE)*/
#define CFG_PISCR 0
/*-----------------------------------------------------------------------
* SCCR - System Clock Control 9-8
*-----------------------------------------------------------------------
*/
#define CFG_SCCR (SCCR_DFBRG01)
/*-----------------------------------------------------------------------
* RCCR - RISC Controller Configuration 13-7
*-----------------------------------------------------------------------
*/
#define CFG_RCCR 0
/*-----------------------------------------------------------------------
* MPTPR - Memory Refresh Timer Prescale Register 10-32
*-----------------------------------------------------------------------
*/
#define CFG_MPTPR (0x0A00 & MPTPR_PTP_MSK)
/*
* Init Memory Controller:
*
* Bank Bus Machine PortSz Device
* ---- --- ------- ------ ------
* 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90WDI)
* 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Micron 48LC8M16A2TG)
* 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Micron 48LC8M16A2TG)
* 3 unused
* 4 60x GPCM 8 bit Board Regs, NVRTC
* 5 unused
* 6 unused
* 7 unused
* 8 PCMCIA
* 9 unused
* 10 unused
* 11 unused
*/
/*-----------------------------------------------------------------------
* BRx - Base Register
* Ref: Section 10.3.1 on page 10-14
* ORx - Option Register
* Ref: Section 10.3.2 on page 10-18
*-----------------------------------------------------------------------
*/
/* Bank 0 - FLASH
*
*/
#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
BRx_PS_64 |\
BRx_DECC_NONE |\
BRx_MS_GPCM_P |\
BRx_V)
#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
ORxG_CSNT |\
ORxG_ACS_DIV1 |\
ORxG_SCY_6_CLK |\
ORxG_EHTR)
/* Bank 1 - SDRAM
* PSDRAM
*/
#define CFG_BR1_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
BRx_PS_64 |\
BRx_MS_SDRAM_P |\
BRx_V)
#define CFG_OR1_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
ORxS_BPD_4 |\
ORxS_ROWST_PBI1_A6 |\
ORxS_NUMR_12)
#define CFG_PSDMR 0xC34E2462
#define CFG_PSRT 0x64
#ifdef CFG_LSDRAM
/* Bank 2 - SDRAM
* LSDRAM
*/
#define CFG_BR2_PRELIM ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
BRx_PS_32 |\
BRx_MS_SDRAM_L |\
BRx_V)
#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM1_SIZE) |\
ORxS_BPD_4 |\
ORxS_ROWST_PBI0_A9 |\
ORxS_NUMR_12)
#define CFG_LSDMR 0x416A2562
#define CFG_LSRT 0x64
#else
#define CFG_LSRT 0x0
#endif /* CFG_LSDRAM */
/* Bank 4 - On board registers
* NVRTC and BCSR
*/
#define CFG_BR4_PRELIM ((CFG_REGS_BASE & BRx_BA_MSK) |\
BRx_PS_8 |\
BRx_MS_GPCM_P |\
BRx_V)
/*
#define CFG_OR4_PRELIM (ORxG_AM_MSK |\
ORxG_CSNT |\
ORxG_ACS_DIV1 |\
ORxG_SCY_10_CLK |\
ORxG_TRLX)
*/
#define CFG_OR4_PRELIM 0xfff00854
/* Bank 8 - On board registers
* PCMCIA (currently not working!)
*/
#define CFG_BR8_PRELIM ((CFG_REGS_BASE & BRx_BA_MSK) |\
BRx_PS_16 |\
BRx_MS_GPCM_P |\
BRx_V)
#define CFG_OR8_PRELIM (ORxG_AM_MSK |\
ORxG_CSNT |\
ORxG_ACS_DIV1 |\
ORxG_SETA |\
ORxG_SCY_10_CLK)
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#endif /* __CONFIG_H */

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include/hush.h
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/*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _HUSH_H_
#define _HUSH_H_
#define FLAG_EXIT_FROM_LOOP 1
#define FLAG_PARSE_SEMICOLON (1 << 1) /* symbol ';' is special for parser */
#define FLAG_REPARSING (1 << 2) /* >=2nd pass */
extern int u_boot_hush_start(void);
extern int parse_string_outer(char *, int);
extern int parse_file_outer(void);
#endif

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include/image.h
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/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __IMAGE_H__
#define __IMAGE_H__
/*
* Operating System Codes
*/
#define IH_OS_INVALID 0 /* Invalid OS */
#define IH_OS_OPENBSD 1 /* OpenBSD */
#define IH_OS_NETBSD 2 /* NetBSD */
#define IH_OS_FREEBSD 3 /* FreeBSD */
#define IH_OS_4_4BSD 4 /* 4.4BSD */
#define IH_OS_LINUX 5 /* Linux */
#define IH_OS_SVR4 6 /* SVR4 */
#define IH_OS_ESIX 7 /* Esix */
#define IH_OS_SOLARIS 8 /* Solaris */
#define IH_OS_IRIX 9 /* Irix */
#define IH_OS_SCO 10 /* SCO */
#define IH_OS_DELL 11 /* Dell */
#define IH_OS_NCR 12 /* NCR */
#define IH_OS_LYNXOS 13 /* LynxOS */
#define IH_OS_VXWORKS 14 /* VxWorks */
#define IH_OS_PSOS 15 /* pSOS */
#define IH_OS_QNX 16 /* QNX */
#define IH_OS_U_BOOT 17 /* Firmware */
/*
* CPU Architecture Codes (supported by Linux)
*/
#define IH_CPU_INVALID 0 /* Invalid CPU */
#define IH_CPU_ALPHA 1 /* Alpha */
#define IH_CPU_ARM 2 /* ARM */
#define IH_CPU_I386 3 /* Intel x86 */
#define IH_CPU_IA64 4 /* IA64 */
#define IH_CPU_MIPS 5 /* MIPS */
#define IH_CPU_MIPS64 6 /* MIPS 64 Bit */
#define IH_CPU_PPC 7 /* PowerPC */
#define IH_CPU_S390 8 /* IBM S390 */
#define IH_CPU_SH 9 /* SuperH */
#define IH_CPU_SPARC 10 /* Sparc */
#define IH_CPU_SPARC64 11 /* Sparc 64 Bit */
/*
* Image Types
*
* "Standalone Programs" are directly runnable in the environment
* provided by U-Boot; it is expected that (if they behave
* well) you can continue to work in U-Boot after return from
* the Standalone Program.
* "OS Kernel Images" are usually images of some Embedded OS which
* will take over control completely. Usually these programs
* will install their own set of exception handlers, device
* drivers, set up the MMU, etc. - this means, that you cannot
* expect to re-enter U-Boot except by resetting the CPU.
* "RAMDisk Images" are more or less just data blocks, and their
* parameters (address, size) are passed to an OS kernel that is
* being started.
* "Multi-File Images" contain several images, typically an OS
* (Linux) kernel image and one or more data images like
* RAMDisks. This construct is useful for instance when you want
* to boot over the network using BOOTP etc., where the boot
* server provides just a single image file, but you want to get
* for instance an OS kernel and a RAMDisk image.
*
* "Multi-File Images" start with a list of image sizes, each
* image size (in bytes) specified by an "uint32_t" in network
* byte order. This list is terminated by an "(uint32_t)0".
* Immediately after the terminating 0 follow the images, one by
* one, all aligned on "uint32_t" boundaries (size rounded up to
* a multiple of 4 bytes).
*
* "Firmware Images" are binary images containing firmware (like
* U-Boot or FPGA images) which usually will be programmed to
* flash memory.
*
* "Script files" are command sequences that will be executed by
* U-Boot's command interpreter; this feature is especially
* useful when you configure U-Boot to use a real shell (hush)
* as command interpreter.
*/
#define IH_TYPE_INVALID 0 /* Invalid Image */
#define IH_TYPE_STANDALONE 1 /* Standalone Program */
#define IH_TYPE_KERNEL 2 /* OS Kernel Image */
#define IH_TYPE_RAMDISK 3 /* RAMDisk Image */
#define IH_TYPE_MULTI 4 /* Multi-File Image */
#define IH_TYPE_FIRMWARE 5 /* Firmware Image */
#define IH_TYPE_SCRIPT 6 /* Script file */
/*
* Compression Types
*/
#define IH_COMP_NONE 0 /* No Compression Used */
#define IH_COMP_GZIP 1 /* gzip Compression Used */
#define IH_COMP_BZIP2 2 /* bzip2 Compression Used */
#define IH_MAGIC 0x27051956 /* Image Magic Number */
#define IH_NMLEN 32 /* Image Name Length */
#ifdef __CYGWIN__
typedef unsigned long uint32_t;
typedef unsigned char uint8_t;
#endif /* __CYGWIN__ */
/*
* all data in network byte order (aka natural aka bigendian)
*/
typedef struct image_header {
uint32_t ih_magic; /* Image Header Magic Number */
uint32_t ih_hcrc; /* Image Header CRC Checksum */
uint32_t ih_time; /* Image Creation Timestamp */
uint32_t ih_size; /* Image Data Size */
uint32_t ih_load; /* Data Load Address */
uint32_t ih_ep; /* Entry Point Address */
uint32_t ih_dcrc; /* Image Data CRC Checksum */
uint8_t ih_os; /* Operating System */
uint8_t ih_arch; /* CPU architecture */
uint8_t ih_type; /* Image Type */
uint8_t ih_comp; /* Compression Type */
uint8_t ih_name[IH_NMLEN]; /* Image Name */
} image_header_t;
#endif /* __IMAGE_H__ */

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include/malloc.h
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/*
A version of malloc/free/realloc written by Doug Lea and released to the
public domain. Send questions/comments/complaints/performance data
to dl@cs.oswego.edu
* VERSION 2.6.6 Sun Mar 5 19:10:03 2000 Doug Lea (dl at gee)
Note: There may be an updated version of this malloc obtainable at
ftp://g.oswego.edu/pub/misc/malloc.c
Check before installing!
* Why use this malloc?
This is not the fastest, most space-conserving, most portable, or
most tunable malloc ever written. However it is among the fastest
while also being among the most space-conserving, portable and tunable.
Consistent balance across these factors results in a good general-purpose
allocator. For a high-level description, see
http://g.oswego.edu/dl/html/malloc.html
* Synopsis of public routines
(Much fuller descriptions are contained in the program documentation below.)
malloc(size_t n);
Return a pointer to a newly allocated chunk of at least n bytes, or null
if no space is available.
free(Void_t* p);
Release the chunk of memory pointed to by p, or no effect if p is null.
realloc(Void_t* p, size_t n);
Return a pointer to a chunk of size n that contains the same data
as does chunk p up to the minimum of (n, p's size) bytes, or null
if no space is available. The returned pointer may or may not be
the same as p. If p is null, equivalent to malloc. Unless the
#define REALLOC_ZERO_BYTES_FREES below is set, realloc with a
size argument of zero (re)allocates a minimum-sized chunk.
memalign(size_t alignment, size_t n);
Return a pointer to a newly allocated chunk of n bytes, aligned
in accord with the alignment argument, which must be a power of
two.
valloc(size_t n);
Equivalent to memalign(pagesize, n), where pagesize is the page
size of the system (or as near to this as can be figured out from
all the includes/defines below.)
pvalloc(size_t n);
Equivalent to valloc(minimum-page-that-holds(n)), that is,
round up n to nearest pagesize.
calloc(size_t unit, size_t quantity);
Returns a pointer to quantity * unit bytes, with all locations
set to zero.
cfree(Void_t* p);
Equivalent to free(p).
malloc_trim(size_t pad);
Release all but pad bytes of freed top-most memory back
to the system. Return 1 if successful, else 0.
malloc_usable_size(Void_t* p);
Report the number usable allocated bytes associated with allocated
chunk p. This may or may not report more bytes than were requested,
due to alignment and minimum size constraints.
malloc_stats();
Prints brief summary statistics on stderr.
mallinfo()
Returns (by copy) a struct containing various summary statistics.
mallopt(int parameter_number, int parameter_value)
Changes one of the tunable parameters described below. Returns
1 if successful in changing the parameter, else 0.
* Vital statistics:
Alignment: 8-byte
8 byte alignment is currently hardwired into the design. This
seems to suffice for all current machines and C compilers.
Assumed pointer representation: 4 or 8 bytes
Code for 8-byte pointers is untested by me but has worked
reliably by Wolfram Gloger, who contributed most of the
changes supporting this.
Assumed size_t representation: 4 or 8 bytes
Note that size_t is allowed to be 4 bytes even if pointers are 8.
Minimum overhead per allocated chunk: 4 or 8 bytes
Each malloced chunk has a hidden overhead of 4 bytes holding size
and status information.
Minimum allocated size: 4-byte ptrs: 16 bytes (including 4 overhead)
8-byte ptrs: 24/32 bytes (including, 4/8 overhead)
When a chunk is freed, 12 (for 4byte ptrs) or 20 (for 8 byte
ptrs but 4 byte size) or 24 (for 8/8) additional bytes are
needed; 4 (8) for a trailing size field
and 8 (16) bytes for free list pointers. Thus, the minimum
allocatable size is 16/24/32 bytes.
Even a request for zero bytes (i.e., malloc(0)) returns a
pointer to something of the minimum allocatable size.
Maximum allocated size: 4-byte size_t: 2^31 - 8 bytes
8-byte size_t: 2^63 - 16 bytes
It is assumed that (possibly signed) size_t bit values suffice to
represent chunk sizes. `Possibly signed' is due to the fact
that `size_t' may be defined on a system as either a signed or
an unsigned type. To be conservative, values that would appear
as negative numbers are avoided.
Requests for sizes with a negative sign bit when the request
size is treaded as a long will return null.
Maximum overhead wastage per allocated chunk: normally 15 bytes
Alignnment demands, plus the minimum allocatable size restriction
make the normal worst-case wastage 15 bytes (i.e., up to 15
more bytes will be allocated than were requested in malloc), with
two exceptions:
1. Because requests for zero bytes allocate non-zero space,
the worst case wastage for a request of zero bytes is 24 bytes.
2. For requests >= mmap_threshold that are serviced via
mmap(), the worst case wastage is 8 bytes plus the remainder
from a system page (the minimal mmap unit); typically 4096 bytes.
* Limitations
Here are some features that are NOT currently supported
* No user-definable hooks for callbacks and the like.
* No automated mechanism for fully checking that all accesses
to malloced memory stay within their bounds.
* No support for compaction.
* Synopsis of compile-time options:
People have reported using previous versions of this malloc on all
versions of Unix, sometimes by tweaking some of the defines
below. It has been tested most extensively on Solaris and
Linux. It is also reported to work on WIN32 platforms.
People have also reported adapting this malloc for use in
stand-alone embedded systems.
The implementation is in straight, hand-tuned ANSI C. Among other
consequences, it uses a lot of macros. Because of this, to be at
all usable, this code should be compiled using an optimizing compiler
(for example gcc -O2) that can simplify expressions and control
paths.
__STD_C (default: derived from C compiler defines)
Nonzero if using ANSI-standard C compiler, a C++ compiler, or
a C compiler sufficiently close to ANSI to get away with it.
DEBUG (default: NOT defined)
Define to enable debugging. Adds fairly extensive assertion-based
checking to help track down memory errors, but noticeably slows down
execution.
REALLOC_ZERO_BYTES_FREES (default: NOT defined)
Define this if you think that realloc(p, 0) should be equivalent
to free(p). Otherwise, since malloc returns a unique pointer for
malloc(0), so does realloc(p, 0).
HAVE_MEMCPY (default: defined)
Define if you are not otherwise using ANSI STD C, but still
have memcpy and memset in your C library and want to use them.
Otherwise, simple internal versions are supplied.
USE_MEMCPY (default: 1 if HAVE_MEMCPY is defined, 0 otherwise)
Define as 1 if you want the C library versions of memset and
memcpy called in realloc and calloc (otherwise macro versions are used).
At least on some platforms, the simple macro versions usually
outperform libc versions.
HAVE_MMAP (default: defined as 1)
Define to non-zero to optionally make malloc() use mmap() to
allocate very large blocks.
HAVE_MREMAP (default: defined as 0 unless Linux libc set)
Define to non-zero to optionally make realloc() use mremap() to
reallocate very large blocks.
malloc_getpagesize (default: derived from system #includes)
Either a constant or routine call returning the system page size.
HAVE_USR_INCLUDE_MALLOC_H (default: NOT defined)
Optionally define if you are on a system with a /usr/include/malloc.h
that declares struct mallinfo. It is not at all necessary to
define this even if you do, but will ensure consistency.
INTERNAL_SIZE_T (default: size_t)
Define to a 32-bit type (probably `unsigned int') if you are on a
64-bit machine, yet do not want or need to allow malloc requests of
greater than 2^31 to be handled. This saves space, especially for
very small chunks.
INTERNAL_LINUX_C_LIB (default: NOT defined)
Defined only when compiled as part of Linux libc.
Also note that there is some odd internal name-mangling via defines
(for example, internally, `malloc' is named `mALLOc') needed
when compiling in this case. These look funny but don't otherwise
affect anything.
WIN32 (default: undefined)
Define this on MS win (95, nt) platforms to compile in sbrk emulation.
LACKS_UNISTD_H (default: undefined if not WIN32)
Define this if your system does not have a <unistd.h>.
LACKS_SYS_PARAM_H (default: undefined if not WIN32)
Define this if your system does not have a <sys/param.h>.
MORECORE (default: sbrk)
The name of the routine to call to obtain more memory from the system.
MORECORE_FAILURE (default: -1)
The value returned upon failure of MORECORE.
MORECORE_CLEARS (default 1)
True (1) if the routine mapped to MORECORE zeroes out memory (which
holds for sbrk).
DEFAULT_TRIM_THRESHOLD
DEFAULT_TOP_PAD
DEFAULT_MMAP_THRESHOLD
DEFAULT_MMAP_MAX
Default values of tunable parameters (described in detail below)
controlling interaction with host system routines (sbrk, mmap, etc).
These values may also be changed dynamically via mallopt(). The
preset defaults are those that give best performance for typical
programs/systems.
USE_DL_PREFIX (default: undefined)
Prefix all public routines with the string 'dl'. Useful to
quickly avoid procedure declaration conflicts and linker symbol
conflicts with existing memory allocation routines.
*/
/* Preliminaries */
#ifndef __STD_C
#ifdef __STDC__
#define __STD_C 1
#else
#if __cplusplus
#define __STD_C 1
#else
#define __STD_C 0
#endif /*__cplusplus*/
#endif /*__STDC__*/
#endif /*__STD_C*/
#ifndef Void_t
#if (__STD_C || defined(WIN32))
#define Void_t void
#else
#define Void_t char
#endif
#endif /*Void_t*/
#if __STD_C
#include <linux/stddef.h> /* for size_t */
#else
#include <sys/types.h>
#endif /* __STD_C */
#ifdef __cplusplus
extern "C" {
#endif
#if 0 /* not for U-Boot */
#include <stdio.h> /* needed for malloc_stats */
#endif
/*
Compile-time options
*/
/*
Debugging:
Because freed chunks may be overwritten with link fields, this
malloc will often die when freed memory is overwritten by user
programs. This can be very effective (albeit in an annoying way)
in helping track down dangling pointers.
If you compile with -DDEBUG, a number of assertion checks are
enabled that will catch more memory errors. You probably won't be
able to make much sense of the actual assertion errors, but they
should help you locate incorrectly overwritten memory. The
checking is fairly extensive, and will slow down execution
noticeably. Calling malloc_stats or mallinfo with DEBUG set will
attempt to check every non-mmapped allocated and free chunk in the
course of computing the summmaries. (By nature, mmapped regions
cannot be checked very much automatically.)
Setting DEBUG may also be helpful if you are trying to modify
this code. The assertions in the check routines spell out in more
detail the assumptions and invariants underlying the algorithms.
*/
#ifdef DEBUG
/* #include <assert.h> */
#define assert(x) ((void)0)
#else
#define assert(x) ((void)0)
#endif
/*
INTERNAL_SIZE_T is the word-size used for internal bookkeeping
of chunk sizes. On a 64-bit machine, you can reduce malloc
overhead by defining INTERNAL_SIZE_T to be a 32 bit `unsigned int'
at the expense of not being able to handle requests greater than
2^31. This limitation is hardly ever a concern; you are encouraged
to set this. However, the default version is the same as size_t.
*/
#ifndef INTERNAL_SIZE_T
#define INTERNAL_SIZE_T size_t
#endif
/*
REALLOC_ZERO_BYTES_FREES should be set if a call to
realloc with zero bytes should be the same as a call to free.
Some people think it should. Otherwise, since this malloc
returns a unique pointer for malloc(0), so does realloc(p, 0).
*/
/* #define REALLOC_ZERO_BYTES_FREES */
/*
WIN32 causes an emulation of sbrk to be compiled in
mmap-based options are not currently supported in WIN32.
*/
/* #define WIN32 */
#ifdef WIN32
#define MORECORE wsbrk
#define HAVE_MMAP 0
#define LACKS_UNISTD_H
#define LACKS_SYS_PARAM_H
/*
Include 'windows.h' to get the necessary declarations for the
Microsoft Visual C++ data structures and routines used in the 'sbrk'
emulation.
Define WIN32_LEAN_AND_MEAN so that only the essential Microsoft
Visual C++ header files are included.
*/
#define WIN32_LEAN_AND_MEAN
#include <windows.h>
#endif
/*
HAVE_MEMCPY should be defined if you are not otherwise using
ANSI STD C, but still have memcpy and memset in your C library
and want to use them in calloc and realloc. Otherwise simple
macro versions are defined here.
USE_MEMCPY should be defined as 1 if you actually want to
have memset and memcpy called. People report that the macro
versions are often enough faster than libc versions on many
systems that it is better to use them.
*/
#define HAVE_MEMCPY
#ifndef USE_MEMCPY
#ifdef HAVE_MEMCPY
#define USE_MEMCPY 1
#else
#define USE_MEMCPY 0
#endif
#endif
#if (__STD_C || defined(HAVE_MEMCPY))
#if __STD_C
void* memset(void*, int, size_t);
void* memcpy(void*, const void*, size_t);
#else
#ifdef WIN32
// On Win32 platforms, 'memset()' and 'memcpy()' are already declared in
// 'windows.h'
#else
Void_t* memset();
Void_t* memcpy();
#endif
#endif
#endif
#if USE_MEMCPY
/* The following macros are only invoked with (2n+1)-multiples of
INTERNAL_SIZE_T units, with a positive integer n. This is exploited
for fast inline execution when n is small. */
#define MALLOC_ZERO(charp, nbytes) \
do { \
INTERNAL_SIZE_T mzsz = (nbytes); \
if(mzsz <= 9*sizeof(mzsz)) { \
INTERNAL_SIZE_T* mz = (INTERNAL_SIZE_T*) (charp); \
if(mzsz >= 5*sizeof(mzsz)) { *mz++ = 0; \
*mz++ = 0; \
if(mzsz >= 7*sizeof(mzsz)) { *mz++ = 0; \
*mz++ = 0; \
if(mzsz >= 9*sizeof(mzsz)) { *mz++ = 0; \
*mz++ = 0; }}} \
*mz++ = 0; \
*mz++ = 0; \
*mz = 0; \
} else memset((charp), 0, mzsz); \
} while(0)
#define MALLOC_COPY(dest,src,nbytes) \
do { \
INTERNAL_SIZE_T mcsz = (nbytes); \
if(mcsz <= 9*sizeof(mcsz)) { \
INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) (src); \
INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) (dest); \
if(mcsz >= 5*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \
*mcdst++ = *mcsrc++; \
if(mcsz >= 7*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \
*mcdst++ = *mcsrc++; \
if(mcsz >= 9*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \
*mcdst++ = *mcsrc++; }}} \
*mcdst++ = *mcsrc++; \
*mcdst++ = *mcsrc++; \
*mcdst = *mcsrc ; \
} else memcpy(dest, src, mcsz); \
} while(0)
#else /* !USE_MEMCPY */
/* Use Duff's device for good zeroing/copying performance. */
#define MALLOC_ZERO(charp, nbytes) \
do { \
INTERNAL_SIZE_T* mzp = (INTERNAL_SIZE_T*)(charp); \
long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T), mcn; \
if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; } \
switch (mctmp) { \
case 0: for(;;) { *mzp++ = 0; \
case 7: *mzp++ = 0; \
case 6: *mzp++ = 0; \
case 5: *mzp++ = 0; \
case 4: *mzp++ = 0; \
case 3: *mzp++ = 0; \
case 2: *mzp++ = 0; \
case 1: *mzp++ = 0; if(mcn <= 0) break; mcn--; } \
} \
} while(0)
#define MALLOC_COPY(dest,src,nbytes) \
do { \
INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) src; \
INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) dest; \
long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T), mcn; \
if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; } \
switch (mctmp) { \
case 0: for(;;) { *mcdst++ = *mcsrc++; \
case 7: *mcdst++ = *mcsrc++; \
case 6: *mcdst++ = *mcsrc++; \
case 5: *mcdst++ = *mcsrc++; \
case 4: *mcdst++ = *mcsrc++; \
case 3: *mcdst++ = *mcsrc++; \
case 2: *mcdst++ = *mcsrc++; \
case 1: *mcdst++ = *mcsrc++; if(mcn <= 0) break; mcn--; } \
} \
} while(0)
#endif
/*
Define HAVE_MMAP to optionally make malloc() use mmap() to
allocate very large blocks. These will be returned to the
operating system immediately after a free().
*/
/***
#ifndef HAVE_MMAP
#define HAVE_MMAP 1
#endif
***/
#undef HAVE_MMAP /* Not available for U-Boot */
/*
Define HAVE_MREMAP to make realloc() use mremap() to re-allocate
large blocks. This is currently only possible on Linux with
kernel versions newer than 1.3.77.
*/
/***
#ifndef HAVE_MREMAP
#ifdef INTERNAL_LINUX_C_LIB
#define HAVE_MREMAP 1
#else
#define HAVE_MREMAP 0
#endif
#endif
***/
#undef HAVE_MREMAP /* Not available for U-Boot */
#if HAVE_MMAP
#include <unistd.h>
#include <fcntl.h>
#include <sys/mman.h>
#if !defined(MAP_ANONYMOUS) && defined(MAP_ANON)
#define MAP_ANONYMOUS MAP_ANON
#endif
#endif /* HAVE_MMAP */
/*
Access to system page size. To the extent possible, this malloc
manages memory from the system in page-size units.
The following mechanics for getpagesize were adapted from
bsd/gnu getpagesize.h
*/
#define LACKS_UNISTD_H /* Shortcut for U-Boot */
#define malloc_getpagesize 4096
#ifndef LACKS_UNISTD_H
# include <unistd.h>
#endif
#ifndef malloc_getpagesize
# ifdef _SC_PAGESIZE /* some SVR4 systems omit an underscore */
# ifndef _SC_PAGE_SIZE
# define _SC_PAGE_SIZE _SC_PAGESIZE
# endif
# endif
# ifdef _SC_PAGE_SIZE
# define malloc_getpagesize sysconf(_SC_PAGE_SIZE)
# else
# if defined(BSD) || defined(DGUX) || defined(HAVE_GETPAGESIZE)
extern size_t getpagesize();
# define malloc_getpagesize getpagesize()
# else
# ifdef WIN32
# define malloc_getpagesize (4096) /* TBD: Use 'GetSystemInfo' instead */
# else
# ifndef LACKS_SYS_PARAM_H
# include <sys/param.h>
# endif
# ifdef EXEC_PAGESIZE
# define malloc_getpagesize EXEC_PAGESIZE
# else
# ifdef NBPG
# ifndef CLSIZE
# define malloc_getpagesize NBPG
# else
# define malloc_getpagesize (NBPG * CLSIZE)
# endif
# else
# ifdef NBPC
# define malloc_getpagesize NBPC
# else
# ifdef PAGESIZE
# define malloc_getpagesize PAGESIZE
# else
# define malloc_getpagesize (4096) /* just guess */
# endif
# endif
# endif
# endif
# endif
# endif
# endif
#endif
/*
This version of malloc supports the standard SVID/XPG mallinfo
routine that returns a struct containing the same kind of
information you can get from malloc_stats. It should work on
any SVID/XPG compliant system that has a /usr/include/malloc.h
defining struct mallinfo. (If you'd like to install such a thing
yourself, cut out the preliminary declarations as described above
and below and save them in a malloc.h file. But there's no
compelling reason to bother to do this.)
The main declaration needed is the mallinfo struct that is returned
(by-copy) by mallinfo(). The SVID/XPG malloinfo struct contains a
bunch of fields, most of which are not even meaningful in this
version of malloc. Some of these fields are are instead filled by
mallinfo() with other numbers that might possibly be of interest.
HAVE_USR_INCLUDE_MALLOC_H should be set if you have a
/usr/include/malloc.h file that includes a declaration of struct
mallinfo. If so, it is included; else an SVID2/XPG2 compliant
version is declared below. These must be precisely the same for
mallinfo() to work.
*/
/* #define HAVE_USR_INCLUDE_MALLOC_H */
#if HAVE_USR_INCLUDE_MALLOC_H
#include "/usr/include/malloc.h"
#else
/* SVID2/XPG mallinfo structure */
struct mallinfo {
int arena; /* total space allocated from system */
int ordblks; /* number of non-inuse chunks */
int smblks; /* unused -- always zero */
int hblks; /* number of mmapped regions */
int hblkhd; /* total space in mmapped regions */
int usmblks; /* unused -- always zero */
int fsmblks; /* unused -- always zero */
int uordblks; /* total allocated space */
int fordblks; /* total non-inuse space */
int keepcost; /* top-most, releasable (via malloc_trim) space */
};
/* SVID2/XPG mallopt options */
#define M_MXFAST 1 /* UNUSED in this malloc */
#define M_NLBLKS 2 /* UNUSED in this malloc */
#define M_GRAIN 3 /* UNUSED in this malloc */
#define M_KEEP 4 /* UNUSED in this malloc */
#endif
/* mallopt options that actually do something */
#define M_TRIM_THRESHOLD -1
#define M_TOP_PAD -2
#define M_MMAP_THRESHOLD -3
#define M_MMAP_MAX -4
#ifndef DEFAULT_TRIM_THRESHOLD
#define DEFAULT_TRIM_THRESHOLD (128 * 1024)
#endif
/*
M_TRIM_THRESHOLD is the maximum amount of unused top-most memory
to keep before releasing via malloc_trim in free().
Automatic trimming is mainly useful in long-lived programs.
Because trimming via sbrk can be slow on some systems, and can
sometimes be wasteful (in cases where programs immediately
afterward allocate more large chunks) the value should be high
enough so that your overall system performance would improve by
releasing.
The trim threshold and the mmap control parameters (see below)
can be traded off with one another. Trimming and mmapping are
two different ways of releasing unused memory back to the
system. Between these two, it is often possible to keep
system-level demands of a long-lived program down to a bare
minimum. For example, in one test suite of sessions measuring
the XF86 X server on Linux, using a trim threshold of 128K and a
mmap threshold of 192K led to near-minimal long term resource
consumption.
If you are using this malloc in a long-lived program, it should
pay to experiment with these values. As a rough guide, you
might set to a value close to the average size of a process
(program) running on your system. Releasing this much memory
would allow such a process to run in memory. Generally, it's
worth it to tune for trimming rather tham memory mapping when a
program undergoes phases where several large chunks are
allocated and released in ways that can reuse each other's
storage, perhaps mixed with phases where there are no such
chunks at all. And in well-behaved long-lived programs,
controlling release of large blocks via trimming versus mapping
is usually faster.
However, in most programs, these parameters serve mainly as
protection against the system-level effects of carrying around
massive amounts of unneeded memory. Since frequent calls to
sbrk, mmap, and munmap otherwise degrade performance, the default
parameters are set to relatively high values that serve only as
safeguards.
The default trim value is high enough to cause trimming only in
fairly extreme (by current memory consumption standards) cases.
It must be greater than page size to have any useful effect. To
disable trimming completely, you can set to (unsigned long)(-1);
*/
#ifndef DEFAULT_TOP_PAD
#define DEFAULT_TOP_PAD (0)
#endif
/*
M_TOP_PAD is the amount of extra `padding' space to allocate or
retain whenever sbrk is called. It is used in two ways internally:
* When sbrk is called to extend the top of the arena to satisfy
a new malloc request, this much padding is added to the sbrk
request.
* When malloc_trim is called automatically from free(),
it is used as the `pad' argument.
In both cases, the actual amount of padding is rounded
so that the end of the arena is always a system page boundary.
The main reason for using padding is to avoid calling sbrk so
often. Having even a small pad greatly reduces the likelihood
that nearly every malloc request during program start-up (or
after trimming) will invoke sbrk, which needlessly wastes
time.
Automatic rounding-up to page-size units is normally sufficient
to avoid measurable overhead, so the default is 0. However, in
systems where sbrk is relatively slow, it can pay to increase
this value, at the expense of carrying around more memory than
the program needs.
*/
#ifndef DEFAULT_MMAP_THRESHOLD
#define DEFAULT_MMAP_THRESHOLD (128 * 1024)
#endif
/*
M_MMAP_THRESHOLD is the request size threshold for using mmap()
to service a request. Requests of at least this size that cannot
be allocated using already-existing space will be serviced via mmap.
(If enough normal freed space already exists it is used instead.)
Using mmap segregates relatively large chunks of memory so that
they can be individually obtained and released from the host
system. A request serviced through mmap is never reused by any
other request (at least not directly; the system may just so
happen to remap successive requests to the same locations).
Segregating space in this way has the benefit that mmapped space
can ALWAYS be individually released back to the system, which
helps keep the system level memory demands of a long-lived
program low. Mapped memory can never become `locked' between
other chunks, as can happen with normally allocated chunks, which
menas that even trimming via malloc_trim would not release them.
However, it has the disadvantages that:
1. The space cannot be reclaimed, consolidated, and then
used to service later requests, as happens with normal chunks.
2. It can lead to more wastage because of mmap page alignment
requirements
3. It causes malloc performance to be more dependent on host
system memory management support routines which may vary in
implementation quality and may impose arbitrary
limitations. Generally, servicing a request via normal
malloc steps is faster than going through a system's mmap.
All together, these considerations should lead you to use mmap
only for relatively large requests.
*/
#ifndef DEFAULT_MMAP_MAX
#if HAVE_MMAP
#define DEFAULT_MMAP_MAX (64)
#else
#define DEFAULT_MMAP_MAX (0)
#endif
#endif
/*
M_MMAP_MAX is the maximum number of requests to simultaneously
service using mmap. This parameter exists because:
1. Some systems have a limited number of internal tables for
use by mmap.
2. In most systems, overreliance on mmap can degrade overall
performance.
3. If a program allocates many large regions, it is probably
better off using normal sbrk-based allocation routines that
can reclaim and reallocate normal heap memory. Using a
small value allows transition into this mode after the
first few allocations.
Setting to 0 disables all use of mmap. If HAVE_MMAP is not set,
the default value is 0, and attempts to set it to non-zero values
in mallopt will fail.
*/
/*
USE_DL_PREFIX will prefix all public routines with the string 'dl'.
Useful to quickly avoid procedure declaration conflicts and linker
symbol conflicts with existing memory allocation routines.
*/
/* #define USE_DL_PREFIX */
/*
Special defines for linux libc
Except when compiled using these special defines for Linux libc
using weak aliases, this malloc is NOT designed to work in
multithreaded applications. No semaphores or other concurrency
control are provided to ensure that multiple malloc or free calls
don't run at the same time, which could be disasterous. A single
semaphore could be used across malloc, realloc, and free (which is
essentially the effect of the linux weak alias approach). It would
be hard to obtain finer granularity.
*/
#ifdef INTERNAL_LINUX_C_LIB
#if __STD_C
Void_t * __default_morecore_init (ptrdiff_t);
Void_t *(*__morecore)(ptrdiff_t) = __default_morecore_init;
#else
Void_t * __default_morecore_init ();
Void_t *(*__morecore)() = __default_morecore_init;
#endif
#define MORECORE (*__morecore)
#define MORECORE_FAILURE 0
#define MORECORE_CLEARS 1
#else /* INTERNAL_LINUX_C_LIB */
#if __STD_C
extern Void_t* sbrk(ptrdiff_t);
#else
extern Void_t* sbrk();
#endif
#ifndef MORECORE
#define MORECORE sbrk
#endif
#ifndef MORECORE_FAILURE
#define MORECORE_FAILURE -1
#endif
#ifndef MORECORE_CLEARS
#define MORECORE_CLEARS 1
#endif
#endif /* INTERNAL_LINUX_C_LIB */
#if defined(INTERNAL_LINUX_C_LIB) && defined(__ELF__)
#define cALLOc __libc_calloc
#define fREe __libc_free
#define mALLOc __libc_malloc
#define mEMALIGn __libc_memalign
#define rEALLOc __libc_realloc
#define vALLOc __libc_valloc
#define pvALLOc __libc_pvalloc
#define mALLINFo __libc_mallinfo
#define mALLOPt __libc_mallopt
#pragma weak calloc = __libc_calloc
#pragma weak free = __libc_free
#pragma weak cfree = __libc_free
#pragma weak malloc = __libc_malloc
#pragma weak memalign = __libc_memalign
#pragma weak realloc = __libc_realloc
#pragma weak valloc = __libc_valloc
#pragma weak pvalloc = __libc_pvalloc
#pragma weak mallinfo = __libc_mallinfo
#pragma weak mallopt = __libc_mallopt
#else
#ifdef USE_DL_PREFIX
#define cALLOc dlcalloc
#define fREe dlfree
#define mALLOc dlmalloc
#define mEMALIGn dlmemalign
#define rEALLOc dlrealloc
#define vALLOc dlvalloc
#define pvALLOc dlpvalloc
#define mALLINFo dlmallinfo
#define mALLOPt dlmallopt
#else /* USE_DL_PREFIX */
#define cALLOc calloc
#define fREe free
#define mALLOc malloc
#define mEMALIGn memalign
#define rEALLOc realloc
#define vALLOc valloc
#define pvALLOc pvalloc
#define mALLINFo mallinfo
#define mALLOPt mallopt
#endif /* USE_DL_PREFIX */
#endif
/* Public routines */
#if __STD_C
Void_t* mALLOc(size_t);
void fREe(Void_t*);
Void_t* rEALLOc(Void_t*, size_t);
Void_t* mEMALIGn(size_t, size_t);
Void_t* vALLOc(size_t);
Void_t* pvALLOc(size_t);
Void_t* cALLOc(size_t, size_t);
void cfree(Void_t*);
int malloc_trim(size_t);
size_t malloc_usable_size(Void_t*);
void malloc_stats(void);
int mALLOPt(int, int);
struct mallinfo mALLINFo(void);
#else
Void_t* mALLOc();
void fREe();
Void_t* rEALLOc();
Void_t* mEMALIGn();
Void_t* vALLOc();
Void_t* pvALLOc();
Void_t* cALLOc();
void cfree();
int malloc_trim();
size_t malloc_usable_size();
void malloc_stats();
int mALLOPt();
struct mallinfo mALLINFo();
#endif
#ifdef __cplusplus
}; /* end of extern "C" */
#endif

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include/version.h
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/*
* (C) Copyright 2000-2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __VERSION_H__
#define __VERSION_H__
#define U_BOOT_VERSION "U-Boot 0.1.0"
#endif /* __VERSION_H__ */

202
rtc/ds174x.c
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/*
* (C) Copyright 2001
* ARIO Data Networks, Inc. dchiu@ariodata.com
*
* Based on MontaVista DS1743 code and U-Boot mc146818 code
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Date & Time support for the DS174x RTC
*/
/*#define DEBUG*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#if defined(CONFIG_RTC_DS174x) && (CONFIG_COMMANDS & CFG_CMD_DATE)
static uchar rtc_read( unsigned int addr );
static void rtc_write( unsigned int addr, uchar val);
static uchar bin2bcd (unsigned int n);
static unsigned bcd2bin(uchar c);
#define RTC_BASE ( CFG_NVRAM_SIZE + CFG_NVRAM_BASE_ADDR )
#define RTC_YEAR ( RTC_BASE + 7 )
#define RTC_MONTH ( RTC_BASE + 6 )
#define RTC_DAY_OF_MONTH ( RTC_BASE + 5 )
#define RTC_DAY_OF_WEEK ( RTC_BASE + 4 )
#define RTC_HOURS ( RTC_BASE + 3 )
#define RTC_MINUTES ( RTC_BASE + 2 )
#define RTC_SECONDS ( RTC_BASE + 1 )
#define RTC_CENTURY ( RTC_BASE + 0 )
#define RTC_CONTROLA RTC_CENTURY
#define RTC_CONTROLB RTC_SECONDS
#define RTC_CONTROLC RTC_DAY_OF_WEEK
#define RTC_CA_WRITE 0x80
#define RTC_CA_READ 0x40
#define RTC_CB_OSC_DISABLE 0x80
#define RTC_CC_BATTERY_FLAG 0x80
#define RTC_CC_FREQ_TEST 0x40
/* ------------------------------------------------------------------------- */
void rtc_get( struct rtc_time *tmp )
{
uchar sec, min, hour;
uchar mday, wday, mon, year;
int century;
uchar reg_a;
reg_a = rtc_read( RTC_CONTROLA );
/* lock clock registers for read */
rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ ));
sec = rtc_read( RTC_SECONDS );
min = rtc_read( RTC_MINUTES );
hour = rtc_read( RTC_HOURS );
mday = rtc_read( RTC_DAY_OF_MONTH );
wday = rtc_read( RTC_DAY_OF_WEEK );
mon = rtc_read( RTC_MONTH );
year = rtc_read( RTC_YEAR );
century = rtc_read( RTC_CENTURY );
/* unlock clock registers after read */
rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ ));
#ifdef RTC_DEBUG
printf( "Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
"hr: %02x min: %02x sec: %02x\n",
year, mon_cent, mday, wday,
hour, min, sec );
#endif
tmp->tm_sec = bcd2bin( sec & 0x7F );
tmp->tm_min = bcd2bin( min & 0x7F );
tmp->tm_hour = bcd2bin( hour & 0x3F );
tmp->tm_mday = bcd2bin( mday & 0x3F );
tmp->tm_mon = bcd2bin( mon & 0x1F );
tmp->tm_wday = bcd2bin( wday & 0x07 );
/* glue year from century and year in century */
tmp->tm_year = bcd2bin( year ) +
( bcd2bin( century & 0x3F ) * 100 );
tmp->tm_yday = 0;
tmp->tm_isdst= 0;
#ifdef RTC_DEBUG
printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec );
#endif
}
void rtc_set( struct rtc_time *tmp )
{
uchar reg_a;
#ifdef RTC_DEBUG
printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
#endif
/* lock clock registers for write */
reg_a = rtc_read( RTC_CONTROLA );
rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE ));
rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon ));
rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday ));
rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday ));
rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour ));
rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min ));
rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec ));
/* break year up into century and year in century */
rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 ));
rtc_write( RTC_CENTURY, bin2bcd( tmp->tm_year / 100 ));
/* unlock clock registers after read */
rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE ));
}
void rtc_reset (void)
{
uchar reg_a, reg_b, reg_c;
reg_a = rtc_read( RTC_CONTROLA );
reg_b = rtc_read( RTC_CONTROLB );
if ( reg_b & RTC_CB_OSC_DISABLE )
{
printf( "real-time-clock was stopped. Now starting...\n" );
reg_a |= RTC_CA_WRITE;
reg_b &= ~RTC_CB_OSC_DISABLE;
rtc_write( RTC_CONTROLA, reg_a );
rtc_write( RTC_CONTROLB, reg_b );
}
/* make sure read/write clock register bits are cleared */
reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ );
rtc_write( RTC_CONTROLA, reg_a );
reg_c = rtc_read( RTC_CONTROLC );
if (( reg_c & RTC_CC_BATTERY_FLAG ) == 0 )
printf( "RTC battery low. Clock setting may not be reliable.\n" );
}
/* ------------------------------------------------------------------------- */
static uchar rtc_read( unsigned int addr )
{
uchar val = in8( addr );
#ifdef RTC_DEBUG
printf( "rtc_read: %x:%x\n", addr, val );
#endif
return( val );
}
static void rtc_write( unsigned int addr, uchar val )
{
#ifdef RTC_DEBUG
printf( "rtc_write: %x:%x\n", addr, val );
#endif
out8( addr, val );
}
static unsigned bcd2bin (uchar n)
{
return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F));
}
static unsigned char bin2bcd (unsigned int n)
{
return (((n / 10) << 4) | (n % 10));
}
#endif /* CONFIG_RTC_MC146818 && CFG_CMD_DATE */

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tools/easylogo/runme.sh
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#!/bin/sh
make
./easylogo linux_logo.tga u_boot_logo video_logo.h
mv video_logo.h ../../include

722
tools/mkimage.c
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/*
* (C) Copyright 2000-2002
* DENX Software Engineering
* Wolfgang Denk, wd@denx.de
* All rights reserved.
*/
#include <errno.h>
#include <fcntl.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#ifndef __WIN32__
#include <netinet/in.h> /* for host / network byte order conversions */
#endif
#include <sys/mman.h>
#include <sys/stat.h>
#include <time.h>
#include <unistd.h>
#if defined(__BEOS__) || defined(__NetBSD__) || defined(__APPLE__)
#include <inttypes.h>
#endif
#ifdef __WIN32__
typedef unsigned int __u32;
#define SWAP_LONG(x) \
((__u32)( \
(((__u32)(x) & (__u32)0x000000ffUL) << 24) | \
(((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \
(((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \
(((__u32)(x) & (__u32)0xff000000UL) >> 24) ))
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
#define ntohl(a) SWAP_LONG(a)
#define htonl(a) SWAP_LONG(a)
#endif /* __WIN32__ */
#include <image.h>
extern int errno;
#ifndef MAP_FAILED
#define MAP_FAILED (-1)
#endif
char *cmdname;
extern unsigned long crc32 (unsigned long crc, const char *buf, unsigned int len);
typedef struct table_entry {
int val; /* as defined in image.h */
char *sname; /* short (input) name */
char *lname; /* long (output) name */
} table_entry_t;
table_entry_t arch_name[] = {
{ IH_CPU_INVALID, NULL, "Invalid CPU", },
{ IH_CPU_ALPHA, "alpha", "Alpha", },
{ IH_CPU_ARM, "arm", "ARM", },
{ IH_CPU_I386, "x86", "Intel x86", },
{ IH_CPU_IA64, "ia64", "IA64", },
{ IH_CPU_MIPS, "mips", "MIPS", },
{ IH_CPU_MIPS64, "mips64", "MIPS 64 Bit", },
{ IH_CPU_PPC, "ppc", "PowerPC", },
{ IH_CPU_S390, "s390", "IBM S390", },
{ IH_CPU_SH, "sh", "SuperH", },
{ IH_CPU_SPARC, "sparc", "SPARC", },
{ IH_CPU_SPARC64, "sparc64", "SPARC 64 Bit", },
{ -1, "", "", },
};
table_entry_t os_name[] = {
{ IH_OS_INVALID, NULL, "Invalid OS", },
{ IH_OS_OPENBSD, "openbsd", "OpenBSD", },
{ IH_OS_NETBSD, "netbsd", "NetBSD", },
{ IH_OS_FREEBSD, "freebsd", "FreeBSD", },
{ IH_OS_4_4BSD, "4_4bsd", "4_4BSD", },
{ IH_OS_LINUX, "linux", "Linux", },
{ IH_OS_SVR4, "svr4", "SVR4", },
{ IH_OS_ESIX, "esix", "Esix", },
{ IH_OS_SOLARIS, "solaris", "Solaris", },
{ IH_OS_IRIX, "irix", "Irix", },
{ IH_OS_SCO, "sco", "SCO", },
{ IH_OS_DELL, "dell", "Dell", },
{ IH_OS_NCR, "ncr", "NCR", },
{ IH_OS_LYNXOS, "lynxos", "LynxOS", },
{ IH_OS_VXWORKS, "vxworks", "VxWorks", },
{ IH_OS_PSOS, "psos", "pSOS", },
{ IH_OS_QNX, "qnx", "QNX", },
{ IH_OS_U_BOOT, "u-boot", "U-Boot", },
{ -1, "", "", },
};
table_entry_t type_name[] = {
{ IH_TYPE_INVALID, NULL, "Invalid Image", },
{ IH_TYPE_STANDALONE, "standalone", "Standalone Program", },
{ IH_TYPE_KERNEL, "kernel", "Kernel Image", },
{ IH_TYPE_RAMDISK, "ramdisk", "RAMDisk Image", },
{ IH_TYPE_MULTI, "multi", "Multi-File Image", },
{ IH_TYPE_FIRMWARE, "firmware", "Firmware", },
{ IH_TYPE_SCRIPT, "script", "Script", },
{ -1, "", "", },
};
table_entry_t comp_name[] = {
{ IH_COMP_NONE, "none", "uncompressed", },
{ IH_COMP_GZIP, "gzip", "gzip compressed", },
{ IH_COMP_BZIP2, "bzip2", "bzip2 compressed", },
{ -1, "", "", },
};
static void copy_file (int, const char *, int);
static void usage (void);
static void print_header (image_header_t *);
static void print_type (image_header_t *);
static char *put_table_entry (table_entry_t *, char *, int);
static char *put_arch (int);
static char *put_type (int);
static char *put_os (int);
static char *put_comp (int);
static int get_table_entry (table_entry_t *, char *, char *);
static int get_arch(char *);
static int get_comp(char *);
static int get_os (char *);
static int get_type(char *);
char *datafile;
char *imagefile;
int dflag = 0;
int eflag = 0;
int lflag = 0;
int vflag = 0;
int xflag = 0;
int opt_os = IH_OS_LINUX;
int opt_arch = IH_CPU_PPC;
int opt_type = IH_TYPE_KERNEL;
int opt_comp = IH_COMP_GZIP;
image_header_t header;
image_header_t *hdr = &header;
int
main (int argc, char **argv)
{
int ifd;
uint32_t checksum;
uint32_t addr;
uint32_t ep;
struct stat sbuf;
unsigned char *ptr;
char *name = "";
cmdname = *argv;
addr = ep = 0;
while (--argc > 0 && **++argv == '-') {
while (*++*argv) {
switch (**argv) {
case 'l':
lflag = 1;
break;
case 'A':
if ((--argc <= 0) ||
(opt_arch = get_arch(*++argv)) < 0)
usage ();
goto NXTARG;
case 'C':
if ((--argc <= 0) ||
(opt_comp = get_comp(*++argv)) < 0)
usage ();
goto NXTARG;
case 'O':
if ((--argc <= 0) ||
(opt_os = get_os(*++argv)) < 0)
usage ();
goto NXTARG;
case 'T':
if ((--argc <= 0) ||
(opt_type = get_type(*++argv)) < 0)
usage ();
goto NXTARG;
case 'a':
if (--argc <= 0)
usage ();
addr = strtoul (*++argv, (char **)&ptr, 16);
if (*ptr) {
fprintf (stderr,
"%s: invalid load address %s\n",
cmdname, *argv);
exit (EXIT_FAILURE);
}
goto NXTARG;
case 'd':
if (--argc <= 0)
usage ();
datafile = *++argv;
dflag = 1;
goto NXTARG;
case 'e':
if (--argc <= 0)
usage ();
ep = strtoul (*++argv, (char **)&ptr, 16);
if (*ptr) {
fprintf (stderr,
"%s: invalid entry point %s\n",
cmdname, *argv);
exit (EXIT_FAILURE);
}
eflag = 1;
goto NXTARG;
case 'n':
if (--argc <= 0)
usage ();
name = *++argv;
goto NXTARG;
case 'v':
vflag++;
break;
case 'x':
xflag++;
break;
default:
usage ();
}
}
NXTARG: ;
}
if ((argc != 1) || ((lflag ^ dflag) == 0))
usage();
if (!eflag) {
ep = addr;
/* If XIP, entry point must be after the U-Boot header */
if (xflag)
ep += sizeof(image_header_t);
}
/*
* If XIP, ensure the entry point is equal to the load address plus
* the size of the U-Boot header.
*/
if (xflag) {
if (ep != addr + sizeof(image_header_t)) {
fprintf (stderr, "%s: For XIP, the entry point must be the load addr + %d\n",
cmdname, sizeof(image_header_t));
exit (EXIT_FAILURE);
}
}
imagefile = *argv;
if (lflag) {
ifd = open(imagefile, O_RDONLY);
} else {
#ifdef __WIN32__
ifd = open(imagefile, O_RDWR|O_CREAT|O_TRUNC|O_BINARY, 0666);
#else
ifd = open(imagefile, O_RDWR|O_CREAT|O_TRUNC, 0666);
#endif
}
if (ifd < 0) {
fprintf (stderr, "%s: Can't open %s: %s\n",
cmdname, imagefile, strerror(errno));
exit (EXIT_FAILURE);
}
if (lflag) {
int len;
char *data;
/*
* list header information of existing image
*/
if (fstat(ifd, &sbuf) < 0) {
fprintf (stderr, "%s: Can't stat %s: %s\n",
cmdname, imagefile, strerror(errno));
exit (EXIT_FAILURE);
}
if (sbuf.st_size < sizeof(image_header_t)) {
fprintf (stderr,
"%s: Bad size: \"%s\" is no valid image\n",
cmdname, imagefile);
exit (EXIT_FAILURE);
}
ptr = (unsigned char *)mmap(0, sbuf.st_size,
PROT_READ, MAP_SHARED, ifd, 0);
if ((caddr_t)ptr == (caddr_t)-1) {
fprintf (stderr, "%s: Can't read %s: %s\n",
cmdname, imagefile, strerror(errno));
exit (EXIT_FAILURE);
}
/*
* create copy of header so that we can blank out the
* checksum field for checking - this can't be done
* on the PROT_READ mapped data.
*/
memcpy (hdr, ptr, sizeof(image_header_t));
if (ntohl(hdr->ih_magic) != IH_MAGIC) {
fprintf (stderr,
"%s: Bad Magic Number: \"%s\" is no valid image\n",
cmdname, imagefile);
exit (EXIT_FAILURE);
}
data = (char *)hdr;
len = sizeof(image_header_t);
checksum = ntohl(hdr->ih_hcrc);
hdr->ih_hcrc = htonl(0); /* clear for re-calculation */
if (crc32 (0, data, len) != checksum) {
fprintf (stderr,
"*** Warning: \"%s\" has bad header checksum!\n",
imagefile);
}
data = (char *)(ptr + sizeof(image_header_t));
len = sbuf.st_size - sizeof(image_header_t) ;
if (crc32 (0, data, len) != ntohl(hdr->ih_dcrc)) {
fprintf (stderr,
"*** Warning: \"%s\" has corrupted data!\n",
imagefile);
}
/* for multi-file images we need the data part, too */
print_header ((image_header_t *)ptr);
(void) munmap((void *)ptr, sbuf.st_size);
(void) close (ifd);
exit (EXIT_SUCCESS);
}
/*
* Must be -w then:
*
* write dummy header, to be fixed later
*/
memset (hdr, 0, sizeof(image_header_t));
if (write(ifd, hdr, sizeof(image_header_t)) != sizeof(image_header_t)) {
fprintf (stderr, "%s: Write error on %s: %s\n",
cmdname, imagefile, strerror(errno));
exit (EXIT_FAILURE);
}
if (opt_type == IH_TYPE_MULTI || opt_type == IH_TYPE_SCRIPT) {
char *file = datafile;
unsigned long size;
for (;;) {
char *sep = NULL;
if (file) {
if ((sep = strchr(file, ':')) != NULL) {
*sep = '\0';
}
if (stat (file, &sbuf) < 0) {
fprintf (stderr, "%s: Can't stat %s: %s\n",
cmdname, file, strerror(errno));
exit (EXIT_FAILURE);
}
size = htonl(sbuf.st_size);
} else {
size = 0;
}
if (write(ifd, (char *)&size, sizeof(size)) != sizeof(size)) {
fprintf (stderr, "%s: Write error on %s: %s\n",
cmdname, imagefile, strerror(errno));
exit (EXIT_FAILURE);
}
if (!file) {
break;
}
if (sep) {
*sep = ':';
file = sep + 1;
} else {
file = NULL;
}
}
file = datafile;
for (;;) {
char *sep = strchr(file, ':');
if (sep) {
*sep = '\0';
copy_file (ifd, file, 1);
*sep++ = ':';
file = sep;
} else {
copy_file (ifd, file, 0);
break;
}
}
} else {
copy_file (ifd, datafile, 0);
}
/* We're a bit of paranoid */
#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__)
(void) fdatasync (ifd);
#else
(void) fsync (ifd);
#endif
if (fstat(ifd, &sbuf) < 0) {
fprintf (stderr, "%s: Can't stat %s: %s\n",
cmdname, imagefile, strerror(errno));
exit (EXIT_FAILURE);
}
ptr = (unsigned char *)mmap(0, sbuf.st_size,
PROT_READ|PROT_WRITE, MAP_SHARED, ifd, 0);
if (ptr == (unsigned char *)MAP_FAILED) {
fprintf (stderr, "%s: Can't map %s: %s\n",
cmdname, imagefile, strerror(errno));
exit (EXIT_FAILURE);
}
hdr = (image_header_t *)ptr;
checksum = crc32 (0,
(const char *)(ptr + sizeof(image_header_t)),
sbuf.st_size - sizeof(image_header_t)
);
/* Build new header */
hdr->ih_magic = htonl(IH_MAGIC);
hdr->ih_time = htonl(sbuf.st_mtime);
hdr->ih_size = htonl(sbuf.st_size - sizeof(image_header_t));
hdr->ih_load = htonl(addr);
hdr->ih_ep = htonl(ep);
hdr->ih_dcrc = htonl(checksum);
hdr->ih_os = opt_os;
hdr->ih_arch = opt_arch;
hdr->ih_type = opt_type;
hdr->ih_comp = opt_comp;
strncpy((char *)hdr->ih_name, name, IH_NMLEN);
checksum = crc32(0,(const char *)hdr,sizeof(image_header_t));
hdr->ih_hcrc = htonl(checksum);
print_header (hdr);
(void) munmap((void *)ptr, sbuf.st_size);
/* We're a bit of paranoid */
#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__)
(void) fdatasync (ifd);
#else
(void) fsync (ifd);
#endif
if (close(ifd)) {
fprintf (stderr, "%s: Write error on %s: %s\n",
cmdname, imagefile, strerror(errno));
exit (EXIT_FAILURE);
}
exit (EXIT_SUCCESS);
}
static void
copy_file (int ifd, const char *datafile, int pad)
{
int dfd;
struct stat sbuf;
unsigned char *ptr;
int tail;
int zero = 0;
int offset = 0;
int size;
if (vflag) {
fprintf (stderr, "Adding Image %s\n", datafile);
}
if ((dfd = open(datafile, O_RDONLY)) < 0) {
fprintf (stderr, "%s: Can't open %s: %s\n",
cmdname, datafile, strerror(errno));
exit (EXIT_FAILURE);
}
if (fstat(dfd, &sbuf) < 0) {
fprintf (stderr, "%s: Can't stat %s: %s\n",
cmdname, datafile, strerror(errno));
exit (EXIT_FAILURE);
}
ptr = (unsigned char *)mmap(0, sbuf.st_size,
PROT_READ, MAP_SHARED, dfd, 0);
if (ptr == (unsigned char *)MAP_FAILED) {
fprintf (stderr, "%s: Can't read %s: %s\n",
cmdname, datafile, strerror(errno));
exit (EXIT_FAILURE);
}
if (xflag) {
unsigned char *p = NULL;
/*
* XIP: do not append the image_header_t at the
* beginning of the file, but consume the space
* reserved for it.
*/
if (sbuf.st_size < sizeof(image_header_t)) {
fprintf (stderr,
"%s: Bad size: \"%s\" is too small for XIP\n",
cmdname, datafile);
exit (EXIT_FAILURE);
}
for (p=ptr; p < ptr+sizeof(image_header_t); p++) {
if ( *p != 0xff ) {
fprintf (stderr,
"%s: Bad file: \"%s\" has invalid buffer for XIP\n",
cmdname, datafile);
exit (EXIT_FAILURE);
}
}
offset = sizeof(image_header_t);
}
size = sbuf.st_size - offset;
if (write(ifd, ptr + offset, size) != size) {
fprintf (stderr, "%s: Write error on %s: %s\n",
cmdname, imagefile, strerror(errno));
exit (EXIT_FAILURE);
}
if (pad && ((tail = size % 4) != 0)) {
if (write(ifd, (char *)&zero, 4-tail) != 4-tail) {
fprintf (stderr, "%s: Write error on %s: %s\n",
cmdname, imagefile, strerror(errno));
exit (EXIT_FAILURE);
}
}
(void) munmap((void *)ptr, sbuf.st_size);
(void) close (dfd);
}
void
usage ()
{
fprintf (stderr, "Usage: %s -l image\n"
" -l ==> list image header information\n"
" %s -A arch -O os -T type -C comp "
"-a addr -e ep -n name -d data_file[:data_file...] image\n",
cmdname, cmdname);
fprintf (stderr, " -A ==> set architecture to 'arch'\n"
" -O ==> set operating system to 'os'\n"
" -T ==> set image type to 'type'\n"
" -C ==> set compression type 'comp'\n"
" -a ==> set load address to 'addr' (hex)\n"
" -e ==> set entry point to 'ep' (hex)\n"
" -n ==> set image name to 'name'\n"
" -d ==> use image data from 'datafile'\n"
" -x ==> set XIP (execute in place)\n"
);
exit (EXIT_FAILURE);
}
static void
print_header (image_header_t *hdr)
{
time_t timestamp;
uint32_t size;
timestamp = (time_t)ntohl(hdr->ih_time);
size = ntohl(hdr->ih_size);
printf ("Image Name: %.*s\n", IH_NMLEN, hdr->ih_name);
printf ("Created: %s", ctime(&timestamp));
printf ("Image Type: "); print_type(hdr);
printf ("Data Size: %d Bytes = %.2f kB = %.2f MB\n",
size, (double)size / 1.024e3, (double)size / 1.048576e6 );
printf ("Load Address: 0x%08x\n", ntohl(hdr->ih_load));
printf ("Entry Point: 0x%08x\n", ntohl(hdr->ih_ep));
if (hdr->ih_type == IH_TYPE_MULTI || hdr->ih_type == IH_TYPE_SCRIPT) {
int i, ptrs;
uint32_t pos;
unsigned long *len_ptr = (unsigned long *) (
(unsigned long)hdr + sizeof(image_header_t)
);
/* determine number of images first (to calculate image offsets) */
for (i=0; len_ptr[i]; ++i) /* null pointer terminates list */
;
ptrs = i; /* null pointer terminates list */
pos = sizeof(image_header_t) + ptrs * sizeof(long);
printf ("Contents:\n");
for (i=0; len_ptr[i]; ++i) {
size = ntohl(len_ptr[i]);
printf (" Image %d: %8d Bytes = %4d kB = %d MB\n",
i, size, size>>10, size>>20);
if (hdr->ih_type == IH_TYPE_SCRIPT && i > 0) {
/*
* the user may need to know offsets
* if planning to do something with
* multiple files
*/
printf (" Offset = %08x\n", pos);
}
/* copy_file() will pad the first files to even word align */
size += 3;
size &= ~3;
pos += size;
}
}
}
static void
print_type (image_header_t *hdr)
{
printf ("%s %s %s (%s)\n",
put_arch (hdr->ih_arch),
put_os (hdr->ih_os ),
put_type (hdr->ih_type),
put_comp (hdr->ih_comp)
);
}
static char *put_arch (int arch)
{
return (put_table_entry(arch_name, "Unknown Architecture", arch));
}
static char *put_os (int os)
{
return (put_table_entry(os_name, "Unknown OS", os));
}
static char *put_type (int type)
{
return (put_table_entry(type_name, "Unknown Image", type));
}
static char *put_comp (int comp)
{
return (put_table_entry(comp_name, "Unknown Compression", comp));
}
static char *put_table_entry (table_entry_t *table, char *msg, int type)
{
for (; table->val>=0; ++table) {
if (table->val == type)
return (table->lname);
}
return (msg);
}
static int get_arch(char *name)
{
return (get_table_entry(arch_name, "CPU", name));
}
static int get_comp(char *name)
{
return (get_table_entry(comp_name, "Compression", name));
}
static int get_os (char *name)
{
return (get_table_entry(os_name, "OS", name));
}
static int get_type(char *name)
{
return (get_table_entry(type_name, "Image", name));
}
static int get_table_entry (table_entry_t *table, char *msg, char *name)
{
table_entry_t *t;
int first = 1;
for (t=table; t->val>=0; ++t) {
if (t->sname && strcasecmp(t->sname, name)==0)
return (t->val);
}
fprintf (stderr, "\nInvalid %s Type - valid names are", msg);
for (t=table; t->val>=0; ++t) {
if (t->sname == NULL)
continue;
fprintf (stderr, "%c %s", (first) ? ':' : ',', t->sname);
first = 0;
}
fprintf (stderr, "\n");
return (-1);
}

68
tools/scripts/README
Unescape View File

@ -0,0 +1,68 @@
#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# The files in this directory are free software; you can redistribute
# them and/or modify them under the terms of the GNU General Public
# License as published by the Free Software Foundation; either
# version 2 of the License, or (at your option) any later version.
#
# These files are distributed in the hope that they will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
This directory contains scripts that help to perform certain actions
that need to be done frequently when working with U-Boot.
They are meant as EXAMPLE code, so it is very likely that you will
have to modify them before use.
Short description:
==================
dot.kermrc:
Example for "~/.kermrc" Kermit init file for use with U-Boot
by Wolfgang Denk, 24 Jun 2001
flash_param:
"kermit" script to automatically initialize the environment
variables on your target. This is most useful during
development when your environment variables are stored in an
embedded flash sector which is erased whenever you install a
new U-Boot image.
by Swen Anderson, 10 May 2001
send_cmd:
send_cmd U_BOOT_COMMAND
"kermit" script to send a U-Boot command and print the
results. When used from a shell with history (like the bash)
this indirectly adds kind of history to U-Boot ;-)
by Swen Anderson, 10 May 2001
send_image:
send_image FILE_NAME OFFSET
"kermit" script to automatically download a file to the
target using the "loadb" command (kermit binary protocol)
by Swen Anderson, 10 May 2001
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