Tom Rini
13 years ago
commit
5bb3505fa8
@ -1,50 +0,0 @@ |
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#
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# (C) Copyright 2000-2007
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(SOC).o
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COBJS = flash.o mmc.o mmc_hw.o spi.o
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SOBJS = $(obj)iap_entry.o
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SRCS := $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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all: $(obj).depend $(LIB) |
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$(LIB): $(OBJS) $(SOBJS) |
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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# this MUST be compiled as thumb code!
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$(SOBJS): |
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$(CC) $(AFLAGS) -march=armv4t -c -o $(SOBJS) iap_entry.S
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -1,249 +0,0 @@ |
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/*
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* (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com> |
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* |
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* Modified to remove all but the IAP-command related code by |
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* Gary Jennejohn <garyj@denx.de> |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/arch/hardware.h> |
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/* IAP commands use 32 bytes at the top of CPU internal sram, we
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use 512 bytes below that */ |
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#define COPY_BUFFER_LOCATION 0x40003de0 |
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#define IAP_LOCATION 0x7ffffff1 |
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#define IAP_CMD_PREPARE 50 |
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#define IAP_CMD_COPY 51 |
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#define IAP_CMD_ERASE 52 |
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#define IAP_CMD_CHECK 53 |
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#define IAP_CMD_ID 54 |
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#define IAP_CMD_VERSION 55 |
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#define IAP_CMD_COMPARE 56 |
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#define IAP_RET_CMD_SUCCESS 0 |
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static unsigned long command[5]; |
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static unsigned long result[2]; |
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extern void iap_entry(unsigned long * command, unsigned long * result); |
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/*-----------------------------------------------------------------------
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* |
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*/ |
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static int get_flash_sector(flash_info_t * info, ulong flash_addr) |
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{ |
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int i; |
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for(i = 1; i < (info->sector_count); i++) { |
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if (flash_addr < (info->start[i])) |
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break; |
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} |
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return (i-1); |
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} |
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/*-----------------------------------------------------------------------
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* This function assumes that flash_addr is aligned on 512 bytes boundary |
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* in flash. This function also assumes that prepare have been called |
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* for the sector in question. |
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*/ |
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int lpc2292_copy_buffer_to_flash(flash_info_t * info, ulong flash_addr) |
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{ |
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int first_sector; |
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int last_sector; |
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first_sector = get_flash_sector(info, flash_addr); |
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last_sector = get_flash_sector(info, flash_addr + 512 - 1); |
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/* prepare sectors for write */ |
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command[0] = IAP_CMD_PREPARE; |
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command[1] = first_sector; |
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command[2] = last_sector; |
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iap_entry(command, result); |
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if (result[0] != IAP_RET_CMD_SUCCESS) { |
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printf("IAP prepare failed\n"); |
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return ERR_PROG_ERROR; |
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} |
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command[0] = IAP_CMD_COPY; |
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command[1] = flash_addr; |
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command[2] = COPY_BUFFER_LOCATION; |
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command[3] = 512; |
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command[4] = CONFIG_SYS_SYS_CLK_FREQ >> 10; |
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iap_entry(command, result); |
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if (result[0] != IAP_RET_CMD_SUCCESS) { |
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printf("IAP copy failed\n"); |
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return 1; |
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} |
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return 0; |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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int lpc2292_flash_erase (flash_info_t * info, int s_first, int s_last) |
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{ |
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int flag; |
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int prot; |
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int sect; |
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prot = 0; |
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for (sect = s_first; sect <= s_last; ++sect) { |
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if (info->protect[sect]) { |
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prot++; |
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} |
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} |
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if (prot) |
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return ERR_PROTECTED; |
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flag = disable_interrupts(); |
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printf ("Erasing %d sectors starting at sector %2d.\n" |
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"This make take some time ... ", |
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s_last - s_first + 1, s_first); |
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command[0] = IAP_CMD_PREPARE; |
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command[1] = s_first; |
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command[2] = s_last; |
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iap_entry(command, result); |
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if (result[0] != IAP_RET_CMD_SUCCESS) { |
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printf("IAP prepare failed\n"); |
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return ERR_PROTECTED; |
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} |
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command[0] = IAP_CMD_ERASE; |
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command[1] = s_first; |
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command[2] = s_last; |
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command[3] = CONFIG_SYS_SYS_CLK_FREQ >> 10; |
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iap_entry(command, result); |
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if (result[0] != IAP_RET_CMD_SUCCESS) { |
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printf("IAP erase failed\n"); |
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return ERR_PROTECTED; |
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} |
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if (flag) |
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enable_interrupts(); |
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return ERR_OK; |
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} |
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int lpc2292_write_buff (flash_info_t * info, uchar * src, ulong addr, |
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ulong cnt) |
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{ |
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int first_copy_size; |
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int last_copy_size; |
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int first_block; |
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int last_block; |
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int nbr_mid_blocks; |
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uchar memmap_value; |
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ulong i; |
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uchar* src_org; |
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uchar* dst_org; |
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int ret = ERR_OK; |
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src_org = src; |
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dst_org = (uchar*)addr; |
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first_block = addr / 512; |
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last_block = (addr + cnt) / 512; |
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nbr_mid_blocks = last_block - first_block - 1; |
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first_copy_size = 512 - (addr % 512); |
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last_copy_size = (addr + cnt) % 512; |
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debug("\ncopy first block: (1) %lX -> %lX 0x200 bytes, " |
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"(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX 0x200 bytes\n", |
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(ulong)(first_block * 512), |
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(ulong)COPY_BUFFER_LOCATION, |
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(ulong)src, |
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(ulong)(COPY_BUFFER_LOCATION + 512 - first_copy_size), |
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first_copy_size, |
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(ulong)COPY_BUFFER_LOCATION, |
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(ulong)(first_block * 512)); |
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/* copy first block */ |
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memcpy((void*)COPY_BUFFER_LOCATION, |
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(void*)(first_block * 512), 512); |
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memcpy((void*)(COPY_BUFFER_LOCATION + 512 - first_copy_size), |
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src, first_copy_size); |
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lpc2292_copy_buffer_to_flash(info, first_block * 512); |
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src += first_copy_size; |
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addr += first_copy_size; |
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/* copy middle blocks */ |
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for (i = 0; i < nbr_mid_blocks; i++) { |
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debug("copy middle block: %lX -> %lX 512 bytes, " |
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"%lX -> %lX 512 bytes\n", |
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(ulong)src, |
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(ulong)COPY_BUFFER_LOCATION, |
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(ulong)COPY_BUFFER_LOCATION, |
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(ulong)addr); |
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memcpy((void*)COPY_BUFFER_LOCATION, src, 512); |
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lpc2292_copy_buffer_to_flash(info, addr); |
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src += 512; |
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addr += 512; |
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} |
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if (last_copy_size > 0) { |
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debug("copy last block: (1) %lX -> %lX 0x200 bytes, " |
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"(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX x200 bytes\n", |
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(ulong)(last_block * 512), |
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(ulong)COPY_BUFFER_LOCATION, |
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(ulong)src, |
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(ulong)(COPY_BUFFER_LOCATION), |
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last_copy_size, |
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(ulong)COPY_BUFFER_LOCATION, |
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(ulong)addr); |
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/* copy last block */ |
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memcpy((void*)COPY_BUFFER_LOCATION, |
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(void*)(last_block * 512), 512); |
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memcpy((void*)COPY_BUFFER_LOCATION, |
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src, last_copy_size); |
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lpc2292_copy_buffer_to_flash(info, addr); |
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} |
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/* verify write */ |
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memmap_value = GET8(MEMMAP); |
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disable_interrupts(); |
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PUT8(MEMMAP, 01); /* we must make sure that initial 64
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bytes are taken from flash when we |
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do the compare */ |
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for (i = 0; i < cnt; i++) { |
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if (*dst_org != *src_org){ |
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printf("Write failed. Byte %lX differs\n", i); |
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ret = ERR_PROG_ERROR; |
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break; |
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} |
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dst_org++; |
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src_org++; |
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} |
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PUT8(MEMMAP, memmap_value); |
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enable_interrupts(); |
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return ret; |
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} |
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@ -1,7 +0,0 @@ |
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IAP_ADDRESS: .word 0x7FFFFFF1 |
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.globl iap_entry
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iap_entry: |
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ldr r2, IAP_ADDRESS |
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bx r2 |
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mov pc, lr |
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@ -1,131 +0,0 @@ |
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/*
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <config.h> |
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#include <common.h> |
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#include <mmc.h> |
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#include <asm/errno.h> |
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#include <asm/arch/hardware.h> |
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#include <part.h> |
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#include <fat.h> |
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#include "mmc_hw.h" |
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#include <asm/arch/spi.h> |
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#ifdef CONFIG_MMC |
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#undef MMC_DEBUG |
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static block_dev_desc_t mmc_dev; |
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/* these are filled out by a call to mmc_hw_get_parameters */ |
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static int hw_size; /* in kbytes */ |
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static int hw_nr_sects; |
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static int hw_sect_size; /* in bytes */ |
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block_dev_desc_t * mmc_get_dev(int dev) |
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{ |
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return (block_dev_desc_t *)(&mmc_dev); |
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} |
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unsigned long mmc_block_read(int dev, |
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unsigned long start, |
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lbaint_t blkcnt, |
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void *buffer) |
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{ |
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unsigned long rc = 0; |
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unsigned char *p = (unsigned char *)buffer; |
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unsigned long i; |
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unsigned long addr = start; |
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#ifdef MMC_DEBUG |
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printf("mmc_block_read: start=%lu, blkcnt=%lu\n", start, |
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(unsigned long)blkcnt); |
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#endif |
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for(i = 0; i < (unsigned long)blkcnt; i++) { |
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#ifdef MMC_DEBUG |
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printf("mmc_read_sector: addr=%lu, buffer=%p\n", addr, p); |
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#endif |
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(void)mmc_read_sector(addr, p); |
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rc++; |
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addr++; |
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p += hw_sect_size; |
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} |
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return rc; |
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} |
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/*-----------------------------------------------------------------------------
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* Read hardware paramterers (sector size, size, number of sectors) |
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*/ |
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static int mmc_hw_get_parameters(void) |
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{ |
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unsigned char csddata[16]; |
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unsigned int sizemult; |
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unsigned int size; |
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mmc_read_csd(csddata); |
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hw_sect_size = 1<<(csddata[5] & 0x0f); |
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size = ((csddata[6]&0x03)<<10)+(csddata[7]<<2)+(csddata[8]&0xc0); |
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sizemult = ((csddata[10] & 0x80)>>7)+((csddata[9] & 0x03)<<1); |
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hw_nr_sects = (size+1)*(1<<(sizemult+2)); |
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hw_size = hw_nr_sects*hw_sect_size/1024; |
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#ifdef MMC_DEBUG |
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printf("mmc_hw_get_parameters: hw_sect_size=%d, hw_nr_sects=%d, " |
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"hw_size=%d\n", hw_sect_size, hw_nr_sects, hw_size); |
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#endif |
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return 0; |
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} |
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int mmc_legacy_init(int verbose) |
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{ |
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int ret = -ENODEV; |
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if (verbose) |
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printf("mmc_legacy_init\n"); |
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spi_init(); |
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/* this meeds to be done twice */ |
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mmc_hw_init(); |
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udelay(1000); |
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mmc_hw_init(); |
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mmc_hw_get_parameters(); |
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mmc_dev.if_type = IF_TYPE_MMC; |
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mmc_dev.part_type = PART_TYPE_DOS; |
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mmc_dev.dev = 0; |
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mmc_dev.lun = 0; |
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mmc_dev.type = 0; |
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mmc_dev.blksz = hw_sect_size; |
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mmc_dev.lba = hw_nr_sects; |
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sprintf((char*)mmc_dev.vendor, "Unknown vendor"); |
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sprintf((char*)mmc_dev.product, "Unknown product"); |
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sprintf((char*)mmc_dev.revision, "N/A"); |
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mmc_dev.removable = 0; /* should be true??? */ |
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mmc_dev.block_read = mmc_block_read; |
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fat_register_device(&mmc_dev, 1); |
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|
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ret = 0; |
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|
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return ret; |
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} |
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|
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#endif /* CONFIG_MMC */ |
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@ -1,233 +0,0 @@ |
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/*
|
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This code was original written by Ulrich Radig and modified by |
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Embedded Artists AB (www.embeddedartists.com). |
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|
||||
This program is free software; you can redistribute it and/or modify |
||||
it under the terms of the GNU General Public License as published by |
||||
the Free Software Foundation; either version 2 of the License, or |
||||
(at your option) any later version. |
||||
|
||||
This program is distributed in the hope that it will be useful, |
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
GNU General Public License for more details. |
||||
|
||||
You should have received a copy of the GNU General Public License |
||||
along with this program; if not, write to the Free Software |
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
||||
*/ |
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|
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#include <config.h> |
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#include <common.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/spi.h> |
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|
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#define MMC_Enable() PUT32(IO1CLR, 1l << 22) |
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#define MMC_Disable() PUT32(IO1SET, 1l << 22) |
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#define mmc_spi_cfg() spi_set_clock(8); spi_set_cfg(0, 1, 0); |
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|
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static unsigned char Write_Command_MMC (unsigned char *CMD); |
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static void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer, |
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unsigned short int Bytes); |
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|
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/* initialize the hardware */ |
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int mmc_hw_init(void) |
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{ |
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unsigned long a; |
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unsigned short int Timeout = 0; |
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unsigned char b; |
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unsigned char CMD[] = {0x40, 0x00, 0x00, 0x00, 0x00, 0x95}; |
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|
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/* set-up GPIO and SPI */ |
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(*((volatile unsigned long *)PINSEL2)) &= ~(1l << 3); /* clear bit 3 */ |
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(*((volatile unsigned long *)IO1DIR)) |= (1l << 22); /* set bit 22 (output) */ |
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|
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MMC_Disable(); |
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|
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spi_lock(); |
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spi_set_clock(248); |
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spi_set_cfg(0, 1, 0); |
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MMC_Enable(); |
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|
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/* waste some time */ |
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for(a=0; a < 20000; a++) |
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asm("nop"); |
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|
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/* Put the MMC/SD-card into SPI-mode */ |
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for (b = 0; b < 10; b++) /* Sends min 74+ clocks to the MMC/SD-card */ |
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spi_write(0xff); |
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|
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/* Sends command CMD0 to MMC/SD-card */ |
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while (Write_Command_MMC(CMD) != 1) { |
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if (Timeout++ > 200) { |
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MMC_Disable(); |
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spi_unlock(); |
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return(1); /* Abort with command 1 (return 1) */ |
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} |
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} |
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/* Sends Command CMD1 an MMC/SD-card */ |
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Timeout = 0; |
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CMD[0] = 0x41;/* Command 1 */ |
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CMD[5] = 0xFF; |
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|
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while (Write_Command_MMC(CMD) != 0) { |
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if (Timeout++ > 200) { |
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MMC_Disable(); |
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spi_unlock(); |
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return (2); /* Abort with command 2 (return 2) */ |
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} |
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} |
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|
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MMC_Disable(); |
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spi_unlock(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/* ############################################################################
|
||||
Sends a command to the MMC/SD-card |
||||
######################################################################### */ |
||||
static unsigned char Write_Command_MMC (unsigned char *CMD) |
||||
{ |
||||
unsigned char a, tmp = 0xff; |
||||
unsigned short int Timeout = 0; |
||||
|
||||
MMC_Disable(); |
||||
spi_write(0xFF); |
||||
MMC_Enable(); |
||||
|
||||
for (a = 0; a < 0x06; a++) |
||||
spi_write(*CMD++); |
||||
|
||||
while (tmp == 0xff) { |
||||
tmp = spi_read(); |
||||
if (Timeout++ > 5000) |
||||
break; |
||||
} |
||||
|
||||
return (tmp); |
||||
} |
||||
|
||||
/* ############################################################################
|
||||
Routine to read the CID register from the MMC/SD-card (16 bytes) |
||||
######################################################################### */ |
||||
void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer, unsigned short |
||||
int Bytes) |
||||
{ |
||||
unsigned short int a; |
||||
|
||||
spi_lock(); |
||||
mmc_spi_cfg(); |
||||
MMC_Enable(); |
||||
|
||||
if (Write_Command_MMC(CMD) != 0) { |
||||
MMC_Disable(); |
||||
spi_unlock(); |
||||
return; |
||||
} |
||||
|
||||
while (spi_read() != 0xfe) {}; |
||||
for (a = 0; a < Bytes; a++) |
||||
*Buffer++ = spi_read(); |
||||
|
||||
/* Read the CRC-byte */ |
||||
spi_read(); /* CRC - byte is discarded */ |
||||
spi_read(); /* CRC - byte is discarded */ |
||||
/* set MMC_Chip_Select to high (MMC/SD-card Inaktiv) */ |
||||
MMC_Disable(); |
||||
spi_unlock(); |
||||
|
||||
return; |
||||
} |
||||
|
||||
/* ############################################################################
|
||||
Routine to read a block (512 bytes) from the MMC/SD-card |
||||
######################################################################### */ |
||||
unsigned char mmc_read_sector (unsigned long addr,unsigned char *Buffer) |
||||
{ |
||||
/* Command 16 to read aBlocks from the MMC/SD - caed */ |
||||
unsigned char CMD[] = {0x51,0x00,0x00,0x00,0x00,0xFF}; |
||||
|
||||
/* The address on the MMC/SD-card is in bytes,
|
||||
addr is transformed from blocks to bytes and the result is |
||||
placed into the command */ |
||||
|
||||
addr = addr << 9; /* addr = addr * 512 */ |
||||
|
||||
CMD[1] = ((addr & 0xFF000000) >> 24); |
||||
CMD[2] = ((addr & 0x00FF0000) >> 16); |
||||
CMD[3] = ((addr & 0x0000FF00) >> 8 ); |
||||
|
||||
MMC_Read_Block(CMD, Buffer, 512); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
/* ############################################################################
|
||||
Routine to write a block (512 byte) to the MMC/SD-card |
||||
######################################################################### */ |
||||
unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer) |
||||
{ |
||||
unsigned char tmp, a; |
||||
unsigned short int b; |
||||
/* Command 24 to write a block to the MMC/SD - card */ |
||||
unsigned char CMD[] = {0x58, 0x00, 0x00, 0x00, 0x00, 0xFF}; |
||||
|
||||
/* The address on the MMC/SD-card is in bytes,
|
||||
addr is transformed from blocks to bytes and the result is |
||||
placed into the command */ |
||||
|
||||
addr = addr << 9; /* addr = addr * 512 */ |
||||
|
||||
CMD[1] = ((addr & 0xFF000000) >> 24); |
||||
CMD[2] = ((addr & 0x00FF0000) >> 16); |
||||
CMD[3] = ((addr & 0x0000FF00) >> 8 ); |
||||
|
||||
spi_lock(); |
||||
mmc_spi_cfg(); |
||||
MMC_Enable(); |
||||
|
||||
/* Send command CMD24 to the MMC/SD-card (Write 1 Block/512 Bytes) */ |
||||
tmp = Write_Command_MMC(CMD); |
||||
if (tmp != 0) { |
||||
MMC_Disable(); |
||||
spi_unlock(); |
||||
return(tmp); |
||||
} |
||||
|
||||
/* Do a short delay and send a clock-pulse to the MMC/SD-card */ |
||||
for (a = 0; a < 100; a++) |
||||
spi_read(); |
||||
|
||||
/* Send a start byte to the MMC/SD-card */ |
||||
spi_write(0xFE); |
||||
|
||||
/* Write the block (512 bytes) to the MMC/SD-card */ |
||||
for (b = 0; b < 512; b++) |
||||
spi_write(*Buffer++); |
||||
|
||||
/* write the CRC-Byte */ |
||||
spi_write(0xFF); /* write a dummy CRC */ |
||||
spi_write(0xFF); /* CRC code is not used */ |
||||
|
||||
/* Wait for MMC/SD-card busy */ |
||||
while (spi_read() != 0xff) {}; |
||||
|
||||
/* set MMC_Chip_Select to high (MMC/SD-card inactive) */ |
||||
MMC_Disable(); |
||||
spi_unlock(); |
||||
return (0); |
||||
} |
||||
|
||||
/* #########################################################################
|
||||
Routine to read the CSD register from the MMC/SD-card (16 bytes) |
||||
######################################################################### */ |
||||
unsigned char mmc_read_csd (unsigned char *Buffer) |
||||
{ |
||||
/* Command to read the CSD register */ |
||||
unsigned char CMD[] = {0x49, 0x00, 0x00, 0x00, 0x00, 0xFF}; |
||||
|
||||
MMC_Read_Block(CMD, Buffer, 16); |
||||
|
||||
return (0); |
||||
} |
||||
@ -1,29 +0,0 @@ |
||||
/*
|
||||
This module implements a linux character device driver for the 24c256 chip. |
||||
Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com) |
||||
|
||||
This program is free software; you can redistribute it and/or modify |
||||
it under the terms of the GNU General Public License as published by |
||||
the Free Software Foundation; either version 2 of the License, or |
||||
(at your option) any later version. |
||||
|
||||
This program is distributed in the hope that it will be useful, |
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
GNU General Public License for more details. |
||||
|
||||
You should have received a copy of the GNU General Public License |
||||
along with this program; if not, write to the Free Software |
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef _MMC_HW_ |
||||
#define _MMC_HW_ |
||||
|
||||
unsigned char mmc_read_csd(unsigned char *Buffer); |
||||
unsigned char mmc_read_sector (unsigned long addr, |
||||
unsigned char *Buffer); |
||||
unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer); |
||||
int mmc_hw_init(void); |
||||
|
||||
#endif /* _MMC_HW_ */ |
||||
@ -1,40 +0,0 @@ |
||||
/*
|
||||
This module implements an interface to the SPI on the lpc22xx. |
||||
Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com) |
||||
|
||||
This program is free software; you can redistribute it and/or modify |
||||
it under the terms of the GNU General Public License as published by |
||||
the Free Software Foundation; either version 2 of the License, or |
||||
(at your option) any later version. |
||||
|
||||
This program is distributed in the hope that it will be useful, |
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
GNU General Public License for more details. |
||||
|
||||
You should have received a copy of the GNU General Public License |
||||
along with this program; if not, write to the Free Software |
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <common.h> |
||||
#include <asm/errno.h> |
||||
#include <asm/arch/hardware.h> |
||||
#include <asm/arch/spi.h> |
||||
|
||||
unsigned long spi_flags; |
||||
unsigned char spi_idle = 0x00; |
||||
|
||||
int spi_init(void) |
||||
{ |
||||
unsigned long pinsel0_value; |
||||
|
||||
/* activate spi pins */ |
||||
pinsel0_value = GET32(PINSEL0); |
||||
pinsel0_value &= ~(0xFFl << 8); |
||||
pinsel0_value |= (0x55l << 8); |
||||
PUT32(PINSEL0, pinsel0_value); |
||||
|
||||
return 0; |
||||
} |
||||
@ -1,45 +0,0 @@ |
||||
#
|
||||
# (C) Copyright 2000-2008
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(SOC).o
|
||||
|
||||
COBJS-y += cache.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
|
||||
|
||||
all: $(obj).depend $(LIB) |
||||
|
||||
$(LIB): $(OBJS) |
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -1,86 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Alex Zuepke <azu@sysgo.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/hardware.h> |
||||
|
||||
void icache_enable (void) |
||||
{ |
||||
s32 i; |
||||
|
||||
/* disable all cache bits */ |
||||
CLR_REG( REG_SYSCFG, 0x3F); |
||||
|
||||
/* 8KB cache, write enable */ |
||||
SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01); |
||||
|
||||
/* clear TAG RAM bits */ |
||||
for ( i = 0; i < 256; i++) |
||||
PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000); |
||||
|
||||
/* clear SET0 RAM */ |
||||
for(i=0; i < 1024; i++) |
||||
PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000); |
||||
|
||||
/* clear SET1 RAM */ |
||||
for(i=0; i < 1024; i++) |
||||
PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000); |
||||
|
||||
/* enable cache */ |
||||
SET_REG( REG_SYSCFG, CACHE_ENABLE); |
||||
|
||||
} |
||||
|
||||
void icache_disable (void) |
||||
{ |
||||
/* disable all cache bits */ |
||||
CLR_REG( REG_SYSCFG, 0x3F); |
||||
} |
||||
|
||||
int icache_status (void) |
||||
{ |
||||
return GET_REG( REG_SYSCFG) & CACHE_ENABLE; |
||||
} |
||||
|
||||
void dcache_enable (void) |
||||
{ |
||||
/* we don't have seperate instruction/data caches */ |
||||
icache_enable(); |
||||
} |
||||
|
||||
void dcache_disable (void) |
||||
{ |
||||
/* we don't have seperate instruction/data caches */ |
||||
icache_disable(); |
||||
} |
||||
|
||||
int dcache_status (void) |
||||
{ |
||||
/* we don't have seperate instruction/data caches */ |
||||
return icache_status(); |
||||
} |
||||
@ -0,0 +1,33 @@ |
||||
/*
|
||||
* mux.c |
||||
* |
||||
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation version 2. |
||||
* |
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any |
||||
* kind, whether express or implied; without even the implied warranty |
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/mux.h> |
||||
#include <asm/arch/hardware.h> |
||||
#include <asm/io.h> |
||||
|
||||
/*
|
||||
* Configure the pin mux for the module |
||||
*/ |
||||
void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux) |
||||
{ |
||||
int i; |
||||
|
||||
if (!mod_pin_mux) |
||||
return; |
||||
|
||||
for (i = 0; mod_pin_mux[i].reg_offset != -1; i++) |
||||
MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset); |
||||
} |
||||
@ -0,0 +1,261 @@ |
||||
/*
|
||||
* mux.h |
||||
* |
||||
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation version 2. |
||||
* |
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any |
||||
* kind, whether express or implied; without even the implied warranty |
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
*/ |
||||
|
||||
#ifndef _MUX_H_ |
||||
#define _MUX_H_ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
|
||||
#define MUX_CFG(value, offset) \ |
||||
__raw_writel(value, (CTRL_BASE + offset)); |
||||
|
||||
/* PAD Control Fields */ |
||||
#define SLEWCTRL (0x1 << 6) |
||||
#define RXACTIVE (0x1 << 5) |
||||
#define PULLUP_EN (0x1 << 4) /* Pull UP Selection */ |
||||
#define PULLUDEN (0x0 << 3) /* Pull up enabled */ |
||||
#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ |
||||
#define MODE(val) val /* used for Readability */ |
||||
|
||||
/*
|
||||
* PAD CONTROL OFFSETS |
||||
* Field names corresponds to the pad signal name |
||||
*/ |
||||
struct pad_signals { |
||||
int gpmc_ad0; |
||||
int gpmc_ad1; |
||||
int gpmc_ad2; |
||||
int gpmc_ad3; |
||||
int gpmc_ad4; |
||||
int gpmc_ad5; |
||||
int gpmc_ad6; |
||||
int gpmc_ad7; |
||||
int gpmc_ad8; |
||||
int gpmc_ad9; |
||||
int gpmc_ad10; |
||||
int gpmc_ad11; |
||||
int gpmc_ad12; |
||||
int gpmc_ad13; |
||||
int gpmc_ad14; |
||||
int gpmc_ad15; |
||||
int gpmc_a0; |
||||
int gpmc_a1; |
||||
int gpmc_a2; |
||||
int gpmc_a3; |
||||
int gpmc_a4; |
||||
int gpmc_a5; |
||||
int gpmc_a6; |
||||
int gpmc_a7; |
||||
int gpmc_a8; |
||||
int gpmc_a9; |
||||
int gpmc_a10; |
||||
int gpmc_a11; |
||||
int gpmc_wait0; |
||||
int gpmc_wpn; |
||||
int gpmc_be1n; |
||||
int gpmc_csn0; |
||||
int gpmc_csn1; |
||||
int gpmc_csn2; |
||||
int gpmc_csn3; |
||||
int gpmc_clk; |
||||
int gpmc_advn_ale; |
||||
int gpmc_oen_ren; |
||||
int gpmc_wen; |
||||
int gpmc_be0n_cle; |
||||
int lcd_data0; |
||||
int lcd_data1; |
||||
int lcd_data2; |
||||
int lcd_data3; |
||||
int lcd_data4; |
||||
int lcd_data5; |
||||
int lcd_data6; |
||||
int lcd_data7; |
||||
int lcd_data8; |
||||
int lcd_data9; |
||||
int lcd_data10; |
||||
int lcd_data11; |
||||
int lcd_data12; |
||||
int lcd_data13; |
||||
int lcd_data14; |
||||
int lcd_data15; |
||||
int lcd_vsync; |
||||
int lcd_hsync; |
||||
int lcd_pclk; |
||||
int lcd_ac_bias_en; |
||||
int mmc0_dat3; |
||||
int mmc0_dat2; |
||||
int mmc0_dat1; |
||||
int mmc0_dat0; |
||||
int mmc0_clk; |
||||
int mmc0_cmd; |
||||
int mii1_col; |
||||
int mii1_crs; |
||||
int mii1_rxerr; |
||||
int mii1_txen; |
||||
int mii1_rxdv; |
||||
int mii1_txd3; |
||||
int mii1_txd2; |
||||
int mii1_txd1; |
||||
int mii1_txd0; |
||||
int mii1_txclk; |
||||
int mii1_rxclk; |
||||
int mii1_rxd3; |
||||
int mii1_rxd2; |
||||
int mii1_rxd1; |
||||
int mii1_rxd0; |
||||
int rmii1_refclk; |
||||
int mdio_data; |
||||
int mdio_clk; |
||||
int spi0_sclk; |
||||
int spi0_d0; |
||||
int spi0_d1; |
||||
int spi0_cs0; |
||||
int spi0_cs1; |
||||
int ecap0_in_pwm0_out; |
||||
int uart0_ctsn; |
||||
int uart0_rtsn; |
||||
int uart0_rxd; |
||||
int uart0_txd; |
||||
int uart1_ctsn; |
||||
int uart1_rtsn; |
||||
int uart1_rxd; |
||||
int uart1_txd; |
||||
int i2c0_sda; |
||||
int i2c0_scl; |
||||
int mcasp0_aclkx; |
||||
int mcasp0_fsx; |
||||
int mcasp0_axr0; |
||||
int mcasp0_ahclkr; |
||||
int mcasp0_aclkr; |
||||
int mcasp0_fsr; |
||||
int mcasp0_axr1; |
||||
int mcasp0_ahclkx; |
||||
int xdma_event_intr0; |
||||
int xdma_event_intr1; |
||||
int nresetin_out; |
||||
int porz; |
||||
int nnmi; |
||||
int osc0_in; |
||||
int osc0_out; |
||||
int rsvd1; |
||||
int tms; |
||||
int tdi; |
||||
int tdo; |
||||
int tck; |
||||
int ntrst; |
||||
int emu0; |
||||
int emu1; |
||||
int osc1_in; |
||||
int osc1_out; |
||||
int pmic_power_en; |
||||
int rtc_porz; |
||||
int rsvd2; |
||||
int ext_wakeup; |
||||
int enz_kaldo_1p8v; |
||||
int usb0_dm; |
||||
int usb0_dp; |
||||
int usb0_ce; |
||||
int usb0_id; |
||||
int usb0_vbus; |
||||
int usb0_drvvbus; |
||||
int usb1_dm; |
||||
int usb1_dp; |
||||
int usb1_ce; |
||||
int usb1_id; |
||||
int usb1_vbus; |
||||
int usb1_drvvbus; |
||||
int ddr_resetn; |
||||
int ddr_csn0; |
||||
int ddr_cke; |
||||
int ddr_ck; |
||||
int ddr_nck; |
||||
int ddr_casn; |
||||
int ddr_rasn; |
||||
int ddr_wen; |
||||
int ddr_ba0; |
||||
int ddr_ba1; |
||||
int ddr_ba2; |
||||
int ddr_a0; |
||||
int ddr_a1; |
||||
int ddr_a2; |
||||
int ddr_a3; |
||||
int ddr_a4; |
||||
int ddr_a5; |
||||
int ddr_a6; |
||||
int ddr_a7; |
||||
int ddr_a8; |
||||
int ddr_a9; |
||||
int ddr_a10; |
||||
int ddr_a11; |
||||
int ddr_a12; |
||||
int ddr_a13; |
||||
int ddr_a14; |
||||
int ddr_a15; |
||||
int ddr_odt; |
||||
int ddr_d0; |
||||
int ddr_d1; |
||||
int ddr_d2; |
||||
int ddr_d3; |
||||
int ddr_d4; |
||||
int ddr_d5; |
||||
int ddr_d6; |
||||
int ddr_d7; |
||||
int ddr_d8; |
||||
int ddr_d9; |
||||
int ddr_d10; |
||||
int ddr_d11; |
||||
int ddr_d12; |
||||
int ddr_d13; |
||||
int ddr_d14; |
||||
int ddr_d15; |
||||
int ddr_dqm0; |
||||
int ddr_dqm1; |
||||
int ddr_dqs0; |
||||
int ddr_dqsn0; |
||||
int ddr_dqs1; |
||||
int ddr_dqsn1; |
||||
int ddr_vref; |
||||
int ddr_vtp; |
||||
int ddr_strben0; |
||||
int ddr_strben1; |
||||
int ain7; |
||||
int ain6; |
||||
int ain5; |
||||
int ain4; |
||||
int ain3; |
||||
int ain2; |
||||
int ain1; |
||||
int ain0; |
||||
int vrefp; |
||||
int vrefn; |
||||
}; |
||||
|
||||
struct module_pin_mux { |
||||
short reg_offset; |
||||
unsigned char val; |
||||
}; |
||||
|
||||
/* Pad control register offset */ |
||||
#define PAD_CTRL_BASE 0x800 |
||||
#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \ |
||||
(PAD_CTRL_BASE))->x) |
||||
|
||||
/*
|
||||
* Configure the pin mux for the module |
||||
*/ |
||||
void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux); |
||||
|
||||
#endif |
||||
@ -1,182 +0,0 @@ |
||||
/* * include/asm-armnommu/arch-netarm/netarm_dma_module.h
|
||||
* |
||||
* Copyright (C) 2000 NETsilicon, Inc. |
||||
* Copyright (C) 2000 WireSpeed Communications Corporation |
||||
* |
||||
* This software is copyrighted by WireSpeed. LICENSEE agrees that |
||||
* it will not delete this copyright notice, trademarks or protective |
||||
* notices from any copy made by LICENSEE. |
||||
* |
||||
* This software is provided "AS-IS" and any express or implied |
||||
* warranties or conditions, including but not limited to any |
||||
* implied warranties of merchantability and fitness for a particular |
||||
* purpose regarding this software. In no event shall WireSpeed |
||||
* be liable for any indirect, consequential, or incidental damages, |
||||
* loss of profits or revenue, loss of use or data, or interruption |
||||
* of business, whether the alleged damages are labeled in contract, |
||||
* tort, or indemnity. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
* |
||||
* author(s) : Joe deBlaquiere |
||||
* David Smith |
||||
*/ |
||||
|
||||
#ifndef __NETARM_DMA_MODULE_REGISTERS_H |
||||
#define __NETARM_DMA_MODULE_REGISTERS_H |
||||
|
||||
/* GEN unit register offsets */ |
||||
|
||||
#define NETARM_DMA_MODULE_BASE (0xFF900000) |
||||
|
||||
#define get_dma_reg_addr(c) ((volatile unsigned int *)(NETARM_DMA_MODULE_BASE + (c))) |
||||
|
||||
#define NETARM_DMA1A_BFR_DESCRPTOR_PTR (0x00) |
||||
#define NETARM_DMA1A_CONTROL (0x10) |
||||
#define NETARM_DMA1A_STATUS (0x14) |
||||
#define NETARM_DMA1B_BFR_DESCRPTOR_PTR (0x20) |
||||
#define NETARM_DMA1B_CONTROL (0x30) |
||||
#define NETARM_DMA1B_STATUS (0x34) |
||||
#define NETARM_DMA1C_BFR_DESCRPTOR_PTR (0x40) |
||||
#define NETARM_DMA1C_CONTROL (0x50) |
||||
#define NETARM_DMA1C_STATUS (0x54) |
||||
#define NETARM_DMA1D_BFR_DESCRPTOR_PTR (0x60) |
||||
#define NETARM_DMA1D_CONTROL (0x70) |
||||
#define NETARM_DMA1D_STATUS (0x74) |
||||
|
||||
#define NETARM_DMA2_BFR_DESCRPTOR_PTR (0x80) |
||||
#define NETARM_DMA2_CONTROL (0x90) |
||||
#define NETARM_DMA2_STATUS (0x94) |
||||
|
||||
#define NETARM_DMA3_BFR_DESCRPTOR_PTR (0xA0) |
||||
#define NETARM_DMA3_CONTROL (0xB0) |
||||
#define NETARM_DMA3_STATUS (0xB4) |
||||
|
||||
#define NETARM_DMA4_BFR_DESCRPTOR_PTR (0xC0) |
||||
#define NETARM_DMA4_CONTROL (0xD0) |
||||
#define NETARM_DMA4_STATUS (0xD4) |
||||
|
||||
#define NETARM_DMA5_BFR_DESCRPTOR_PTR (0xE0) |
||||
#define NETARM_DMA5_CONTROL (0xF0) |
||||
#define NETARM_DMA5_STATUS (0xF4) |
||||
|
||||
#define NETARM_DMA6_BFR_DESCRPTOR_PTR (0x100) |
||||
#define NETARM_DMA6_CONTROL (0x110) |
||||
#define NETARM_DMA6_STATUS (0x114) |
||||
|
||||
#define NETARM_DMA7_BFR_DESCRPTOR_PTR (0x120) |
||||
#define NETARM_DMA7_CONTROL (0x130) |
||||
#define NETARM_DMA7_STATUS (0x134) |
||||
|
||||
#define NETARM_DMA8_BFR_DESCRPTOR_PTR (0x140) |
||||
#define NETARM_DMA8_CONTROL (0x150) |
||||
#define NETARM_DMA8_STATUS (0x154) |
||||
|
||||
#define NETARM_DMA9_BFR_DESCRPTOR_PTR (0x160) |
||||
#define NETARM_DMA9_CONTROL (0x170) |
||||
#define NETARM_DMA9_STATUS (0x174) |
||||
|
||||
#define NETARM_DMA10_BFR_DESCRPTOR_PTR (0x180) |
||||
#define NETARM_DMA10_CONTROL (0x190) |
||||
#define NETARM_DMA10_STATUS (0x194) |
||||
|
||||
/* select bitfield defintions */ |
||||
|
||||
/* DMA Control Register ( 0xFF90_0XX0 ) */ |
||||
|
||||
#define NETARM_DMA_CTL_ENABLE (0x80000000) |
||||
|
||||
#define NETARM_DMA_CTL_ABORT (0x40000000) |
||||
|
||||
#define NETARM_DMA_CTL_BUS_100_PERCENT (0x00000000) |
||||
#define NETARM_DMA_CTL_BUS_75_PERCENT (0x10000000) |
||||
#define NETARM_DMA_CTL_BUS_50_PERCENT (0x20000000) |
||||
#define NETARM_DMA_CTL_BUS_25_PERCENT (0x30000000) |
||||
|
||||
#define NETARM_DMA_CTL_BUS_MASK (0x30000000) |
||||
|
||||
#define NETARM_DMA_CTL_MODE_FB_TO_MEM (0x00000000) |
||||
#define NETARM_DMA_CTL_MODE_FB_FROM_MEM (0x04000000) |
||||
#define NETARM_DMA_CTL_MODE_MEM_TO_MEM (0x08000000) |
||||
|
||||
#define NETARM_DMA_CTL_BURST_NONE (0x00000000) |
||||
#define NETARM_DMA_CTL_BURST_8_BYTE (0x01000000) |
||||
#define NETARM_DMA_CTL_BURST_16_BYTE (0x02000000) |
||||
|
||||
#define NETARM_DMA_CTL_BURST_MASK (0x03000000) |
||||
|
||||
#define NETARM_DMA_CTL_SRC_INCREMENT (0x00200000) |
||||
|
||||
#define NETARM_DMA_CTL_DST_INCREMENT (0x00100000) |
||||
|
||||
/* these apply only to ext xfers on DMA 3 or 4 */ |
||||
|
||||
#define NETARM_DMA_CTL_CH_3_4_REQ_EXT (0x00800000) |
||||
|
||||
#define NETARM_DMA_CTL_CH_3_4_DATA_32 (0x00000000) |
||||
#define NETARM_DMA_CTL_CH_3_4_DATA_16 (0x00010000) |
||||
#define NETARM_DMA_CTL_CH_3_4_DATA_8 (0x00020000) |
||||
|
||||
#define NETARM_DMA_CTL_STATE(X) ((X) & 0xFC00) |
||||
#define NETARM_DMA_CTL_INDEX(X) ((X) & 0x03FF) |
||||
|
||||
/* DMA Status Register ( 0xFF90_0XX4 ) */ |
||||
|
||||
#define NETARM_DMA_STAT_NC_INTPEN (0x80000000) |
||||
#define NETARM_DMA_STAT_EC_INTPEN (0x40000000) |
||||
#define NETARM_DMA_STAT_NR_INTPEN (0x20000000) |
||||
#define NETARM_DMA_STAT_CA_INTPEN (0x10000000) |
||||
#define NETARM_DMA_STAT_INTPEN_MASK (0xF0000000) |
||||
|
||||
#define NETARM_DMA_STAT_NC_INT_EN (0x00800000) |
||||
#define NETARM_DMA_STAT_EC_INT_EN (0x00400000) |
||||
#define NETARM_DMA_STAT_NR_INT_EN (0x00200000) |
||||
#define NETARM_DMA_STAT_CA_INT_EN (0x00100000) |
||||
#define NETARM_DMA_STAT_INT_EN_MASK (0x00F00000) |
||||
|
||||
#define NETARM_DMA_STAT_WRAP (0x00080000) |
||||
#define NETARM_DMA_STAT_IDONE (0x00040000) |
||||
#define NETARM_DMA_STAT_LAST (0x00020000) |
||||
#define NETARM_DMA_STAT_FULL (0x00010000) |
||||
|
||||
#define NETARM_DMA_STAT_BUFLEN(X) ((X) & 0x7FFF) |
||||
|
||||
/* DMA Buffer Descriptor Word 0 bitfields. */ |
||||
|
||||
#define NETARM_DMA_BD0_WRAP (0x80000000) |
||||
#define NETARM_DMA_BD0_IDONE (0x40000000) |
||||
#define NETARM_DMA_BD0_LAST (0x20000000) |
||||
#define NETARM_DMA_BD0_BUFPTR_MASK (0x1FFFFFFF) |
||||
|
||||
/* DMA Buffer Descriptor Word 1 bitfields. */ |
||||
|
||||
#define NETARM_DMA_BD1_STATUS_MASK (0xFFFF0000) |
||||
#define NETARM_DMA_BD1_FULL (0x00008000) |
||||
#define NETARM_DMA_BD1_BUFLEN_MASK (0x00007FFF) |
||||
|
||||
#ifndef __ASSEMBLER__ |
||||
|
||||
typedef struct __NETARM_DMA_Buff_Desc_FlyBy |
||||
{ |
||||
unsigned int word0; |
||||
unsigned int word1; |
||||
} NETARM_DMA_Buff_Desc_FlyBy, *pNETARM_DMA_Buff_Desc_FlyBy ; |
||||
|
||||
typedef struct __NETARM_DMA_Buff_Desc_M_to_M |
||||
{ |
||||
unsigned int word0; |
||||
unsigned int word1; |
||||
unsigned int word2; |
||||
unsigned int word3; |
||||
} NETARM_DMA_Buff_Desc_M_to_M, *pNETARM_DMA_Buff_Desc_M_to_M ; |
||||
|
||||
#endif |
||||
|
||||
#endif |
||||
@ -1,121 +0,0 @@ |
||||
/*
|
||||
* include/asm-armnommu/arch-netarm/netarm_eni_module.h |
||||
* |
||||
* Copyright (C) 2000 NETsilicon, Inc. |
||||
* Copyright (C) 2000 WireSpeed Communications Corporation |
||||
* |
||||
* This software is copyrighted by WireSpeed. LICENSEE agrees that |
||||
* it will not delete this copyright notice, trademarks or protective |
||||
* notices from any copy made by LICENSEE. |
||||
* |
||||
* This software is provided "AS-IS" and any express or implied |
||||
* warranties or conditions, including but not limited to any |
||||
* implied warranties of merchantability and fitness for a particular |
||||
* purpose regarding this software. In no event shall WireSpeed |
||||
* be liable for any indirect, consequential, or incidental damages, |
||||
* loss of profits or revenue, loss of use or data, or interruption |
||||
* of business, whether the alleged damages are labeled in contract, |
||||
* tort, or indemnity. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
* |
||||
* author(s) : David Smith |
||||
*/ |
||||
|
||||
#ifndef __NETARM_ENI_MODULE_REGISTERS_H |
||||
#define __NETARM_ENI_MODULE_REGISTERS_H |
||||
|
||||
/* ENI unit register offsets */ |
||||
|
||||
/* #ifdef CONFIG_ARCH_NETARM */ |
||||
#define NETARM_ENI_MODULE_BASE (0xFFA00000) |
||||
/* #endif / * CONFIG_ARCH_NETARM */ |
||||
|
||||
#define get_eni_reg_addr(c) ((volatile unsigned int *)(NETARM_ENI_MODULE_BASE + (c))) |
||||
#define get_eni_ctl_reg_addr(minor) \ |
||||
(get_eni_reg_addr(NETARM_ENI_1284_PORT1_CONTROL) + (minor)) |
||||
|
||||
#define NETARM_ENI_GENERAL_CONTROL (0x00) |
||||
#define NETARM_ENI_STATUS_CONTROL (0x04) |
||||
#define NETARM_ENI_FIFO_MODE_DATA (0x08) |
||||
|
||||
#define NETARM_ENI_1284_PORT1_CONTROL (0x10) |
||||
#define NETARM_ENI_1284_PORT2_CONTROL (0x14) |
||||
#define NETARM_ENI_1284_PORT3_CONTROL (0x18) |
||||
#define NETARM_ENI_1284_PORT4_CONTROL (0x1c) |
||||
|
||||
#define NETARM_ENI_1284_CHANNEL1_DATA (0x20) |
||||
#define NETARM_ENI_1284_CHANNEL2_DATA (0x24) |
||||
#define NETARM_ENI_1284_CHANNEL3_DATA (0x28) |
||||
#define NETARM_ENI_1284_CHANNEL4_DATA (0x2c) |
||||
|
||||
#define NETARM_ENI_ENI_CONTROL (0x30) |
||||
#define NETARM_ENI_ENI_PULSED_INTR (0x34) |
||||
#define NETARM_ENI_ENI_SHARED_RAM_ADDR (0x38) |
||||
#define NETARM_ENI_ENI_SHARED (0x3c) |
||||
|
||||
/* select bitfield defintions */ |
||||
|
||||
/* General Control Register (0xFFA0_0000) */ |
||||
|
||||
#define NETARM_ENI_GCR_ENIMODE_IEEE1284 (0x00000001) |
||||
#define NETARM_ENI_GCR_ENIMODE_SHRAM16 (0x00000004) |
||||
#define NETARM_ENI_GCR_ENIMODE_SHRAM8 (0x00000005) |
||||
#define NETARM_ENI_GCR_ENIMODE_FIFO16 (0x00000006) |
||||
#define NETARM_ENI_GCR_ENIMODE_FIFO8 (0x00000007) |
||||
|
||||
#define NETARM_ENI_GCR_ENIMODE_MASK (0x00000007) |
||||
|
||||
/* IEEE 1284 Port Control Registers 1-4 (0xFFA0_0010, 0xFFA0_0014,
|
||||
0xFFA0_0018, 0xFFA0_001c) */ |
||||
|
||||
#define NETARM_ENI_1284PC_PORT_ENABLE (0x80000000) |
||||
#define NETARM_ENI_1284PC_DMA_ENABLE (0x40000000) |
||||
#define NETARM_ENI_1284PC_OBE_INT_EN (0x20000000) |
||||
#define NETARM_ENI_1284PC_ACK_INT_EN (0x10000000) |
||||
#define NETARM_ENI_1284PC_ECP_MODE (0x08000000) |
||||
#define NETARM_ENI_1284PC_LOOPBACK_MODE (0x04000000) |
||||
|
||||
#define NETARM_ENI_1284PC_STROBE_TIME0 (0x00000000) /* 0.5 uS */ |
||||
#define NETARM_ENI_1284PC_STROBE_TIME1 (0x01000000) /* 1.0 uS */ |
||||
#define NETARM_ENI_1284PC_STROBE_TIME2 (0x02000000) /* 5.0 uS */ |
||||
#define NETARM_ENI_1284PC_STROBE_TIME3 (0x03000000) /* 10.0 uS */ |
||||
#define NETARM_ENI_1284PC_STROBE_MASK (0x03000000) |
||||
|
||||
#define NETARM_ENI_1284PC_MAN_STROBE_EN (0x00800000) |
||||
#define NETARM_ENI_1284PC_FAST_MODE (0x00400000) |
||||
#define NETARM_ENI_1284PC_BIDIR_MODE (0x00200000) |
||||
|
||||
#define NETARM_ENI_1284PC_MAN_STROBE (0x00080000) |
||||
#define NETARM_ENI_1284PC_AUTO_FEED (0x00040000) |
||||
#define NETARM_ENI_1284PC_INIT (0x00020000) |
||||
#define NETARM_ENI_1284PC_HSELECT (0x00010000) |
||||
#define NETARM_ENI_1284PC_FE_INT_EN (0x00008000) |
||||
#define NETARM_ENI_1284PC_EPP_MODE (0x00004000) |
||||
#define NETARM_ENI_1284PC_IBR_INT_EN (0x00002000) |
||||
#define NETARM_ENI_1284PC_IBR (0x00001000) |
||||
|
||||
#define NETARM_ENI_1284PC_RXFDB_1BYTE (0x00000400) |
||||
#define NETARM_ENI_1284PC_RXFDB_2BYTE (0x00000800) |
||||
#define NETARM_ENI_1284PC_RXFDB_3BYTE (0x00000c00) |
||||
#define NETARM_ENI_1284PC_RXFDB_4BYTE (0x00000000) |
||||
|
||||
#define NETARM_ENI_1284PC_RBCC (0x00000200) |
||||
#define NETARM_ENI_1284PC_RBCT (0x00000100) |
||||
#define NETARM_ENI_1284PC_ACK (0x00000080) |
||||
#define NETARM_ENI_1284PC_FIFO_E (0x00000040) |
||||
#define NETARM_ENI_1284PC_OBE (0x00000020) |
||||
#define NETARM_ENI_1284PC_ACK_INT (0x00000010) |
||||
#define NETARM_ENI_1284PC_BUSY (0x00000008) |
||||
#define NETARM_ENI_1284PC_PE (0x00000004) |
||||
#define NETARM_ENI_1284PC_PSELECT (0x00000002) |
||||
#define NETARM_ENI_1284PC_FAULT (0x00000001) |
||||
|
||||
#endif /* __NETARM_ENI_MODULE_REGISTERS_H */ |
||||
@ -1,160 +0,0 @@ |
||||
/*
|
||||
* include/asm-armnommu/arch-netarm/netarm_eth_module.h |
||||
* |
||||
* Copyright (C) 2000 NETsilicon, Inc. |
||||
* Copyright (C) 2000 WireSpeed Communications Corporation |
||||
* |
||||
* This software is copyrighted by WireSpeed. LICENSEE agrees that |
||||
* it will not delete this copyright notice, trademarks or protective |
||||
* notices from any copy made by LICENSEE. |
||||
* |
||||
* This software is provided "AS-IS" and any express or implied |
||||
* warranties or conditions, including but not limited to any |
||||
* implied warranties of merchantability and fitness for a particular |
||||
* purpose regarding this software. In no event shall WireSpeed |
||||
* be liable for any indirect, consequential, or incidental damages, |
||||
* loss of profits or revenue, loss of use or data, or interruption |
||||
* of business, whether the alleged damages are labeled in contract, |
||||
* tort, or indemnity. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
* |
||||
* author(s) : Jackie Smith Cashion |
||||
* David Smith |
||||
*/ |
||||
|
||||
#ifndef __NETARM_ETH_MODULE_REGISTERS_H |
||||
#define __NETARM_ETH_MODULE_REGISTERS_H |
||||
|
||||
/* ETH unit register offsets */ |
||||
|
||||
#define NETARM_ETH_MODULE_BASE (0xFF800000) |
||||
|
||||
#define get_eth_reg_addr(c) ((volatile unsigned int *)(NETARM_ETH_MODULE_BASE + (c))) |
||||
|
||||
#define NETARM_ETH_GEN_CTRL (0x000) /* Ethernet Gen Control Reg */ |
||||
#define NETARM_ETH_GEN_STAT (0x004) /* Ethernet Gen Status Reg */ |
||||
#define NETARM_ETH_FIFO_DAT1 (0x008) /* Fifo Data Reg 1 */ |
||||
#define NETARM_ETH_FIFO_DAT2 (0x00C) /* Fifo Data Reg 2 */ |
||||
#define NETARM_ETH_TX_STAT (0x010) /* Transmit Status Reg */ |
||||
#define NETARM_ETH_RX_STAT (0x014) /* Receive Status Reg */ |
||||
|
||||
#define NETARM_ETH_MAC_CFG (0x400) /* MAC Configuration Reg */ |
||||
#define NETARM_ETH_PCS_CFG (0x408) /* PCS Configuration Reg */ |
||||
#define NETARM_ETH_STL_CFG (0x410) /* STL Configuration Reg */ |
||||
#define NETARM_ETH_B2B_IPG_GAP_TMR (0x440) /* Back-to-back IPG |
||||
Gap Timer Reg */ |
||||
#define NETARM_ETH_NB2B_IPG_GAP_TMR (0x444) /* Non Back-to-back |
||||
IPG Gap Timer Reg */ |
||||
#define NETARM_ETH_MII_CMD (0x540) /* MII (PHY) Command Reg */ |
||||
#define NETARM_ETH_MII_ADDR (0x544) /* MII Address Reg */ |
||||
#define NETARM_ETH_MII_WRITE (0x548) /* MII Write Data Reg */ |
||||
#define NETARM_ETH_MII_READ (0x54C) /* MII Read Data Reg */ |
||||
#define NETARM_ETH_MII_IND (0x550) /* MII Indicators Reg */ |
||||
#define NETARM_ETH_MIB_CRCEC (0x580) /* (MIB) CRC Error Counter */ |
||||
#define NETARM_ETH_MIB_AEC (0x584) /* Alignment Error Counter */ |
||||
#define NETARM_ETH_MIB_CEC (0x588) /* Code Error Counter */ |
||||
#define NETARM_ETH_MIB_LFC (0x58C) /* Long Frame Counter */ |
||||
#define NETARM_ETH_MIB_SFC (0x590) /* Short Frame Counter */ |
||||
#define NETARM_ETH_MIB_LCC (0x594) /* Late Collision Counter */ |
||||
#define NETARM_ETH_MIB_EDC (0x598) /* Excessive Deferral |
||||
Counter */ |
||||
#define NETARM_ETH_MIB_MCC (0x59C) /* Maximum Collision Counter */ |
||||
#define NETARM_ETH_SAL_FILTER (0x5C0) /* SAL Station Address |
||||
Filter Reg */ |
||||
#define NETARM_ETH_SAL_STATION_ADDR_1 (0x5C4) /* SAL Station Address |
||||
Reg */ |
||||
#define NETARM_ETH_SAL_STATION_ADDR_2 (0x5C8) |
||||
#define NETARM_ETH_SAL_STATION_ADDR_3 (0x5CC) |
||||
#define NETARM_ETH_SAL_HASH_TBL_1 (0x5D0) /* SAL Multicast Hash Table*/ |
||||
#define NETARM_ETH_SAL_HASH_TBL_2 (0x5D4) |
||||
#define NETARM_ETH_SAL_HASH_TBL_3 (0x5D8) |
||||
#define NETARM_ETH_SAL_HASH_TBL_4 (0x5DC) |
||||
|
||||
/* select bitfield defintions */ |
||||
|
||||
/* Ethernet General Control Register (0xFF80_0000) */ |
||||
|
||||
#define NETARM_ETH_GCR_ERX (0x80000000) /* Enable Receive FIFO */ |
||||
#define NETARM_ETH_GCR_ERXDMA (0x40000000) /* Enable Receive DMA */ |
||||
#define NETARM_ETH_GCR_ETX (0x00800000) /* Enable Transmit FIFO */ |
||||
#define NETARM_ETH_GCR_ETXDMA (0x00400000) /* Enable Transmit DMA */ |
||||
#define NETARM_ETH_GCR_ETXWM_50 (0x00100000) /* Transmit FIFO Water |
||||
Mark. Start transmit |
||||
when FIFO is 50% |
||||
full. */ |
||||
#define NETARM_ETH_GCR_PNA (0x00000400) /* pSOS pNA Buffer |
||||
Descriptor Format */ |
||||
|
||||
/* Ethernet General Status Register (0xFF80_0004) */ |
||||
|
||||
#define NETARM_ETH_GST_RXFDB (0x30000000) |
||||
#define NETARM_ETH_GST_RXREGR (0x08000000) /* Receive Register |
||||
Ready */ |
||||
#define NETARM_ETH_GST_RXFIFOH (0x04000000) |
||||
#define NETARM_ETH_GST_RXBR (0x02000000) |
||||
#define NETARM_ETH_GST_RXSKIP (0x01000000) |
||||
|
||||
#define NETARM_ETH_GST_TXBC (0x00020000) |
||||
|
||||
|
||||
/* Ethernet Transmit Status Register (0xFF80_0010) */ |
||||
|
||||
#define NETARM_ETH_TXSTAT_TXOK (0x00008000) |
||||
|
||||
|
||||
/* Ethernet Receive Status Register (0xFF80_0014) */ |
||||
|
||||
#define NETARM_ETH_RXSTAT_SIZE (0xFFFF0000) |
||||
#define NETARM_ETH_RXSTAT_RXOK (0x00002000) |
||||
|
||||
|
||||
/* PCS Configuration Register (0xFF80_0408) */ |
||||
|
||||
#define NETARM_ETH_PCSC_NOCFR (0x1) /* Disable Ciphering */ |
||||
#define NETARM_ETH_PCSC_ENJAB (0x2) /* Enable Jabber Protection */ |
||||
#define NETARM_ETH_PCSC_CLKS_25M (0x0) /* 25 MHz Clock Speed Select */ |
||||
#define NETARM_ETH_PCSC_CLKS_33M (0x4) /* 33 MHz Clock Speed Select */ |
||||
|
||||
/* STL Configuration Register (0xFF80_0410) */ |
||||
|
||||
#define NETARM_ETH_STLC_RXEN (0x2) /* Enable Packet Receiver */ |
||||
#define NETARM_ETH_STLC_AUTOZ (0x4) /* Auto Zero Statistics */ |
||||
|
||||
/* MAC Configuration Register (0xFF80_0400) */ |
||||
|
||||
#define NETARM_ETH_MACC_HUGEN (0x1) /* Enable Unlimited Transmit |
||||
Frame Sizes */ |
||||
#define NETARM_ETH_MACC_PADEN (0x4) /* Automatic Pad Fill Frames |
||||
to 64 Bytes */ |
||||
#define NETARM_ETH_MACC_CRCEN (0x8) /* Append CRC to Transmit |
||||
Frames */ |
||||
|
||||
/* MII (PHY) Command Register (0xFF80_0540) */ |
||||
|
||||
#define NETARM_ETH_MIIC_RSTAT (0x1) /* Single Scan for Read Data */ |
||||
|
||||
/* MII Indicators Register (0xFF80_0550) */ |
||||
|
||||
#define NETARM_ETH_MIII_BUSY (0x1) /* MII I/F Busy with |
||||
Read/Write */ |
||||
|
||||
/* SAL Station Address Filter Register (0xFF80_05C0) */ |
||||
|
||||
#define NETARM_ETH_SALF_PRO (0x8) /* Enable Promiscuous Mode */ |
||||
#define NETARM_ETH_SALF_PRM (0x4) /* Accept All Multicast |
||||
Packets */ |
||||
#define NETARM_ETH_SALF_PRA (0x2) /* Accept Mulitcast Packets |
||||
using Hash Table */ |
||||
#define NETARM_ETH_SALF_BROAD (0x1) /* Accept All Broadcast |
||||
Packets */ |
||||
|
||||
|
||||
#endif /* __NETARM_GEN_MODULE_REGISTERS_H */ |
||||
@ -1,186 +0,0 @@ |
||||
/*
|
||||
* include/asm-armnommu/arch-netarm/netarm_gen_module.h |
||||
* |
||||
* Copyright (C) 2005 |
||||
* Art Shipkowski, Videon Central, Inc., <art@videon-central.com> |
||||
* |
||||
* Copyright (C) 2000, 2001 NETsilicon, Inc. |
||||
* Copyright (C) 2000, 2001 Red Hat, Inc. |
||||
* |
||||
* This software is copyrighted by Red Hat. LICENSEE agrees that |
||||
* it will not delete this copyright notice, trademarks or protective |
||||
* notices from any copy made by LICENSEE. |
||||
* |
||||
* This software is provided "AS-IS" and any express or implied |
||||
* warranties or conditions, including but not limited to any |
||||
* implied warranties of merchantability and fitness for a particular |
||||
* purpose regarding this software. In no event shall Red Hat |
||||
* be liable for any indirect, consequential, or incidental damages, |
||||
* loss of profits or revenue, loss of use or data, or interruption |
||||
* of business, whether the alleged damages are labeled in contract, |
||||
* tort, or indemnity. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
* |
||||
* author(s) : Joe deBlaquiere |
||||
* |
||||
* Modified to support NS7520 by Art Shipkowski. |
||||
*/ |
||||
|
||||
#ifndef __NETARM_GEN_MODULE_REGISTERS_H |
||||
#define __NETARM_GEN_MODULE_REGISTERS_H |
||||
|
||||
/* GEN unit register offsets */ |
||||
|
||||
#define NETARM_GEN_MODULE_BASE (0xFFB00000) |
||||
|
||||
#define get_gen_reg_addr(c) ((volatile unsigned int *)(NETARM_GEN_MODULE_BASE + (c))) |
||||
|
||||
#define NETARM_GEN_SYSTEM_CONTROL (0x00) |
||||
#define NETARM_GEN_STATUS_CONTROL (0x04) |
||||
#define NETARM_GEN_PLL_CONTROL (0x08) |
||||
#define NETARM_GEN_SOFTWARE_SERVICE (0x0c) |
||||
|
||||
#define NETARM_GEN_TIMER1_CONTROL (0x10) |
||||
#define NETARM_GEN_TIMER1_STATUS (0x14) |
||||
#define NETARM_GEN_TIMER2_CONTROL (0x18) |
||||
#define NETARM_GEN_TIMER2_STATUS (0x1c) |
||||
|
||||
#define NETARM_GEN_PORTA (0x20) |
||||
#ifndef CONFIG_NETARM_NS7520 |
||||
#define NETARM_GEN_PORTB (0x24) |
||||
#endif |
||||
#define NETARM_GEN_PORTC (0x28) |
||||
|
||||
#define NETARM_GEN_INTR_ENABLE (0x30) |
||||
#define NETARM_GEN_INTR_ENABLE_SET (0x34) |
||||
#define NETARM_GEN_INTR_ENABLE_CLR (0x38) |
||||
#define NETARM_GEN_INTR_STATUS_EN (0x34) |
||||
#define NETARM_GEN_INTR_STATUS_RAW (0x38) |
||||
|
||||
#define NETARM_GEN_CACHE_CONTROL1 (0x40) |
||||
#define NETARM_GEN_CACHE_CONTROL2 (0x44) |
||||
|
||||
/* select bitfield definitions */ |
||||
|
||||
/* System Control Register ( 0xFFB0_0000 ) */ |
||||
|
||||
#define NETARM_GEN_SYS_CFG_LENDIAN (0x80000000) |
||||
#define NETARM_GEN_SYS_CFG_BENDIAN (0x00000000) |
||||
|
||||
#define NETARM_GEN_SYS_CFG_BUSQRTR (0x00000000) |
||||
#define NETARM_GEN_SYS_CFG_BUSHALF (0x20000000) |
||||
#define NETARM_GEN_SYS_CFG_BUSFULL (0x40000000) |
||||
|
||||
#define NETARM_GEN_SYS_CFG_BCLK_DISABLE (0x10000000) |
||||
|
||||
#define NETARM_GEN_SYS_CFG_WDOG_EN (0x01000000) |
||||
#define NETARM_GEN_SYS_CFG_WDOG_IRQ (0x00000000) |
||||
#define NETARM_GEN_SYS_CFG_WDOG_FIQ (0x00400000) |
||||
#define NETARM_GEN_SYS_CFG_WDOG_RST (0x00800000) |
||||
#define NETARM_GEN_SYS_CFG_WDOG_24 (0x00000000) |
||||
#define NETARM_GEN_SYS_CFG_WDOG_26 (0x00100000) |
||||
#define NETARM_GEN_SYS_CFG_WDOG_28 (0x00200000) |
||||
#define NETARM_GEN_SYS_CFG_WDOG_29 (0x00300000) |
||||
|
||||
#define NETARM_GEN_SYS_CFG_BUSMON_EN (0x00040000) |
||||
#define NETARM_GEN_SYS_CFG_BUSMON_128 (0x00000000) |
||||
#define NETARM_GEN_SYS_CFG_BUSMON_64 (0x00010000) |
||||
#define NETARM_GEN_SYS_CFG_BUSMON_32 (0x00020000) |
||||
#define NETARM_GEN_SYS_CFG_BUSMON_16 (0x00030000) |
||||
|
||||
#define NETARM_GEN_SYS_CFG_USER_EN (0x00008000) |
||||
#define NETARM_GEN_SYS_CFG_BUSER_EN (0x00004000) |
||||
|
||||
#define NETARM_GEN_SYS_CFG_BUSARB_INT (0x00002000) |
||||
#define NETARM_GEN_SYS_CFG_BUSARB_EXT (0x00000000) |
||||
|
||||
#define NETARM_GEN_SYS_CFG_DMATST (0x00001000) |
||||
|
||||
#define NETARM_GEN_SYS_CFG_TEALAST (0x00000800) |
||||
|
||||
#define NETARM_GEN_SYS_CFG_ALIGN_ABORT (0x00000400) |
||||
|
||||
#define NETARM_GEN_SYS_CFG_CACHE_EN (0x00000200) |
||||
|
||||
#define NETARM_GEN_SYS_CFG_WRI_BUF_EN (0x00000100) |
||||
|
||||
#define NETARM_GEN_SYS_CFG_CACHE_INIT (0x00000080) |
||||
|
||||
/* PLL Control Register ( 0xFFB0_0008 ) */ |
||||
|
||||
#define NETARM_GEN_PLL_CTL_PLLCNT_MASK (0x0F000000) |
||||
|
||||
#define NETARM_GEN_PLL_CTL_PLLCNT(x) (((x)<<24) & \ |
||||
NETARM_GEN_PLL_CTL_PLLCNT_MASK) |
||||
|
||||
/* Defaults for POLTST and ICP Fields in PLL CTL */ |
||||
#define NETARM_GEN_PLL_CTL_OUTDIV(x) (x) |
||||
#define NETARM_GEN_PLL_CTL_INDIV(x) ((x)<<6) |
||||
#define NETARM_GEN_PLL_CTL_POLTST_DEF (0x00000E00) |
||||
#define NETARM_GEN_PLL_CTL_ICP_DEF (0x0000003C) |
||||
|
||||
|
||||
/* Software Service Register ( 0xFFB0_000C ) */ |
||||
|
||||
#define NETARM_GEN_SW_SVC_RESETA (0x123) |
||||
#define NETARM_GEN_SW_SVC_RESETB (0x321) |
||||
|
||||
/* PORT C Register ( 0xFFB0_0028 ) */ |
||||
|
||||
#ifndef CONFIG_NETARM_NS7520 |
||||
#define NETARM_GEN_PORT_MODE(x) (((x)<<24) + (0xFF00)) |
||||
#define NETARM_GEN_PORT_DIR(x) (((x)<<16) + (0xFF00)) |
||||
#else |
||||
#define NETARM_GEN_PORT_MODE(x) ((x)<<24) |
||||
#define NETARM_GEN_PORT_DIR(x) ((x)<<16) |
||||
#define NETARM_GEN_PORT_CSF(x) ((x)<<8) |
||||
#endif |
||||
|
||||
/* Timer Registers ( 0xFFB0_0010 0xFFB0_0018 ) */ |
||||
|
||||
#define NETARM_GEN_TCTL_ENABLE (0x80000000) |
||||
#define NETARM_GEN_TCTL_INT_ENABLE (0x40000000) |
||||
|
||||
#define NETARM_GEN_TCTL_USE_IRQ (0x00000000) |
||||
#define NETARM_GEN_TCTL_USE_FIQ (0x20000000) |
||||
|
||||
#define NETARM_GEN_TCTL_USE_PRESCALE (0x10000000) |
||||
#define NETARM_GEN_TCTL_INIT_COUNT(x) ((x) & 0x1FF) |
||||
|
||||
#define NETARM_GEN_TSTAT_INTPEN (0x40000000) |
||||
#if ~defined(CONFIG_NETARM_NS7520) |
||||
#define NETARM_GEN_TSTAT_CTC_MASK (0x000001FF) |
||||
#else |
||||
#define NETARM_GEN_TSTAT_CTC_MASK (0x0FFFFFFF) |
||||
#endif |
||||
|
||||
/* prescale to msecs conversion */ |
||||
|
||||
#if !defined(CONFIG_NETARM_PLL_BYPASS) |
||||
#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 20480 ) * ( 0x1FF - ( (x) & \ |
||||
NETARM_GEN_TSTAT_CTC_MASK ) + \
|
||||
1 ) ) / (NETARM_XTAL_FREQ/1000) ) |
||||
|
||||
#define NETARM_GEN_TIMER_SET_HZ(x) ( ( ((NETARM_XTAL_FREQ/(20480*(x)))-1) & \ |
||||
NETARM_GEN_TSTAT_CTC_MASK ) | \
|
||||
NETARM_GEN_TCTL_USE_PRESCALE ) |
||||
|
||||
#else |
||||
#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 4096 ) * ( 0x1FF - ( (x) & \ |
||||
NETARM_GEN_TSTAT_CTC_MASK ) + \
|
||||
1 ) ) / (NETARM_XTAL_FREQ/1000) ) |
||||
|
||||
#define NETARM_GEN_TIMER_SET_HZ(x) ( ( ((NETARM_XTAL_FREQ/(4096*(x)))-1) & \ |
||||
NETARM_GEN_TSTAT_CTC_MASK ) | \
|
||||
NETARM_GEN_TCTL_USE_PRESCALE ) |
||||
#endif |
||||
|
||||
#endif |
||||
@ -1,184 +0,0 @@ |
||||
/*
|
||||
* include/asm-armnommu/arch-netarm/netarm_mem_module.h |
||||
* |
||||
* Copyright (C) 2005 |
||||
* Art Shipkowski, Videon Central, Inc., <art@videon-central.com> |
||||
* |
||||
* Copyright (C) 2000, 2001 NETsilicon, Inc. |
||||
* Copyright (C) 2000, 2001 Red Hat, Inc. |
||||
* |
||||
* This software is copyrighted by Red Hat. LICENSEE agrees that |
||||
* it will not delete this copyright notice, trademarks or protective |
||||
* notices from any copy made by LICENSEE. |
||||
* |
||||
* This software is provided "AS-IS" and any express or implied |
||||
* warranties or conditions, including but not limited to any |
||||
* implied warranties of merchantability and fitness for a particular |
||||
* purpose regarding this software. In no event shall Red Hat |
||||
* be liable for any indirect, consequential, or incidental damages, |
||||
* loss of profits or revenue, loss of use or data, or interruption |
||||
* of business, whether the alleged damages are labeled in contract, |
||||
* tort, or indemnity. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
* |
||||
* author(s) : Joe deBlaquiere |
||||
* |
||||
* Modified to support NS7520 by Art Shipkowski. |
||||
*/ |
||||
|
||||
#ifndef __NETARM_MEM_MODULE_REGISTERS_H |
||||
#define __NETARM_MEM_MODULE_REGISTERS_H |
||||
|
||||
/* GEN unit register offsets */ |
||||
|
||||
#define NETARM_MEM_MODULE_BASE (0xFFC00000) |
||||
|
||||
#define NETARM_MEM_MODULE_CONFIG (0x00) |
||||
#define NETARM_MEM_CS0_BASE_ADDR (0x10) |
||||
#define NETARM_MEM_CS0_OPTIONS (0x14) |
||||
#define NETARM_MEM_CS1_BASE_ADDR (0x20) |
||||
#define NETARM_MEM_CS1_OPTIONS (0x24) |
||||
#define NETARM_MEM_CS2_BASE_ADDR (0x30) |
||||
#define NETARM_MEM_CS2_OPTIONS (0x34) |
||||
#define NETARM_MEM_CS3_BASE_ADDR (0x40) |
||||
#define NETARM_MEM_CS3_OPTIONS (0x44) |
||||
#define NETARM_MEM_CS4_BASE_ADDR (0x50) |
||||
#define NETARM_MEM_CS4_OPTIONS (0x54) |
||||
|
||||
/* select bitfield defintions */ |
||||
|
||||
/* Module Configuration Register ( 0xFFC0_0000 ) */ |
||||
|
||||
#define NETARM_MEM_CFG_REFR_COUNT_MASK (0xFF000000) |
||||
#define NETARM_MEM_CFG_REFRESH_EN (0x00800000) |
||||
|
||||
#define NETARM_MEM_CFG_REFR_CYCLE_8CLKS (0x00000000) |
||||
#define NETARM_MEM_CFG_REFR_CYCLE_6CLKS (0x00200000) |
||||
#define NETARM_MEM_CFG_REFR_CYCLE_5CLKS (0x00400000) |
||||
#define NETARM_MEM_CFG_REFR_CYCLE_4CLKS (0x00600000) |
||||
|
||||
#define NETARM_MEM_CFG_PORTC_AMUX (0x00100000) |
||||
|
||||
#define NETARM_MEM_CFG_A27_ADDR (0x00080000) |
||||
#define NETARM_MEM_CFG_A27_CS0OE (0x00000000) |
||||
|
||||
#define NETARM_MEM_CFG_A26_ADDR (0x00040000) |
||||
#define NETARM_MEM_CFG_A26_CS0WE (0x00000000) |
||||
|
||||
#define NETARM_MEM_CFG_A25_ADDR (0x00020000) |
||||
#define NETARM_MEM_CFG_A25_BLAST (0x00000000) |
||||
|
||||
#define NETARM_MEM_CFG_PORTC_AMUX2 (0x00010000) |
||||
|
||||
|
||||
/* range on this period is about 1 to 275 usec (with 18.432MHz clock) */ |
||||
/* the expression will round down, so make sure to reverse it to verify */ |
||||
/* it is what you want. period = [( count + 1 ) * 20] / Fcrystal */ |
||||
/* (note: Fxtal = Fcrystal/5, see HWRefGuide sections 8.2.5 and 11.3.2) */ |
||||
|
||||
#define NETARM_MEM_REFR_PERIOD_USEC(p) (NETARM_MEM_CFG_REFR_COUNT_MASK & \ |
||||
(((((NETARM_XTAL_FREQ/(1000))*p)/(20000) \
|
||||
) - (1) ) << (24))) |
||||
|
||||
#if 0 |
||||
/* range on this period is about 1 to 275 usec (with 18.432MHz clock) */ |
||||
/* the expression will round down, so make sure to reverse it toverify */ |
||||
/* it is what you want. period = [( count + 1 ) * 4] / Fxtal */ |
||||
|
||||
#define NETARM_MEM_REFR_PERIOD_USEC(p) (NETARM_MEM_CFG_REFR_COUNT_MASK & \ |
||||
(((((NETARM_XTAL_FREQ/(1000))*p)/(4000) \
|
||||
) - (1) ) << (24))) |
||||
#endif |
||||
|
||||
/* Base Address Registers (0xFFC0_00X0) */ |
||||
|
||||
#define NETARM_MEM_BAR_BASE_MASK (0xFFFFF000) |
||||
|
||||
/* macro to define base */ |
||||
|
||||
#define NETARM_MEM_BAR_BASE(x) ((x) & NETARM_MEM_BAR_BASE_MASK) |
||||
|
||||
#define NETARM_MEM_BAR_DRAM_FP (0x00000000) |
||||
#define NETARM_MEM_BAR_DRAM_EDO (0x00000100) |
||||
#define NETARM_MEM_BAR_DRAM_SYNC (0x00000200) |
||||
|
||||
#define NETARM_MEM_BAR_DRAM_MUX_INT (0x00000000) |
||||
#define NETARM_MEM_BAR_DRAM_MUX_EXT (0x00000080) |
||||
|
||||
#define NETARM_MEM_BAR_DRAM_MUX_BAL (0x00000000) |
||||
#define NETARM_MEM_BAR_DRAM_MUX_UNBAL (0x00000020) |
||||
|
||||
#define NETARM_MEM_BAR_1BCLK_IDLE (0x00000010) |
||||
|
||||
#define NETARM_MEM_BAR_DRAM_SEL (0x00000008) |
||||
|
||||
#define NETARM_MEM_BAR_BURST_EN (0x00000004) |
||||
|
||||
#define NETARM_MEM_BAR_WRT_PROT (0x00000002) |
||||
|
||||
#define NETARM_MEM_BAR_VALID (0x00000001) |
||||
|
||||
/* Option Registers (0xFFC0_00X4) */ |
||||
|
||||
/* macro to define which bits of the base are significant */ |
||||
|
||||
#define NETARM_MEM_OPT_BASE_USE(x) ((x) & NETARM_MEM_BAR_BASE_MASK) |
||||
|
||||
#define NETARM_MEM_OPT_WAIT_MASK (0x00000F00) |
||||
|
||||
#define NETARM_MEM_OPT_WAIT_STATES(x) (((x) << 8 ) & NETARM_MEM_OPT_WAIT_MASK ) |
||||
|
||||
#define NETARM_MEM_OPT_BCYC_1 (0x00000000) |
||||
#define NETARM_MEM_OPT_BCYC_2 (0x00000040) |
||||
#define NETARM_MEM_OPT_BCYC_3 (0x00000080) |
||||
#define NETARM_MEM_OPT_BCYC_4 (0x000000C0) |
||||
|
||||
#define NETARM_MEM_OPT_BSIZE_2 (0x00000000) |
||||
#define NETARM_MEM_OPT_BSIZE_4 (0x00000010) |
||||
#define NETARM_MEM_OPT_BSIZE_8 (0x00000020) |
||||
#define NETARM_MEM_OPT_BSIZE_16 (0x00000030) |
||||
|
||||
#define NETARM_MEM_OPT_32BIT (0x00000000) |
||||
#define NETARM_MEM_OPT_16BIT (0x00000004) |
||||
#define NETARM_MEM_OPT_8BIT (0x00000008) |
||||
#define NETARM_MEM_OPT_32BIT_EXT_ACK (0x0000000C) |
||||
|
||||
#define NETARM_MEM_OPT_BUS_SIZE_MASK (0x0000000C) |
||||
|
||||
#define NETARM_MEM_OPT_READ_ASYNC (0x00000000) |
||||
#define NETARM_MEM_OPT_READ_SYNC (0x00000002) |
||||
|
||||
#define NETARM_MEM_OPT_WRITE_ASYNC (0x00000000) |
||||
#define NETARM_MEM_OPT_WRITE_SYNC (0x00000001) |
||||
|
||||
#ifdef CONFIG_NETARM_NS7520 |
||||
/* The NS7520 has a second options register for each chip select */ |
||||
#define NETARM_MEM_CS0_OPTIONS_B (0x18) |
||||
#define NETARM_MEM_CS1_OPTIONS_B (0x28) |
||||
#define NETARM_MEM_CS2_OPTIONS_B (0x38) |
||||
#define NETARM_MEM_CS3_OPTIONS_B (0x48) |
||||
#define NETARM_MEM_CS4_OPTIONS_B (0x58) |
||||
|
||||
/* Option B Registers (0xFFC0_00x8) */ |
||||
#define NETARM_MEM_OPTB_SYNC_1_STAGE (0x00000001) |
||||
#define NETARM_MEM_OPTB_SYNC_2_STAGE (0x00000002) |
||||
#define NETARM_MEM_OPTB_BCYC_PLUS0 (0x00000000) |
||||
#define NETARM_MEM_OPTB_BCYC_PLUS4 (0x00000004) |
||||
#define NETARM_MEM_OPTB_BCYC_PLUS8 (0x00000008) |
||||
#define NETARM_MEM_OPTB_BCYC_PLUS12 (0x0000000C) |
||||
|
||||
#define NETARM_MEM_OPTB_WAIT_PLUS0 (0x00000000) |
||||
#define NETARM_MEM_OPTB_WAIT_PLUS16 (0x00000010) |
||||
#define NETARM_MEM_OPTB_WAIT_PLUS32 (0x00000020) |
||||
#define NETARM_MEM_OPTB_WAIT_PLUS48 (0x00000030) |
||||
#endif |
||||
|
||||
#endif |
||||
@ -1,96 +0,0 @@ |
||||
/*
|
||||
* linux/include/asm-arm/arch-netarm/netarm_registers.h |
||||
* |
||||
* Copyright (C) 2005 |
||||
* Art Shipkowski, Videon Central, Inc., <art@videon-central.com> |
||||
* |
||||
* Copyright (C) 2000, 2001 NETsilicon, Inc. |
||||
* Copyright (C) 2000, 2001 WireSpeed Communications Corporation |
||||
* |
||||
* This software is copyrighted by WireSpeed. LICENSEE agrees that |
||||
* it will not delete this copyright notice, trademarks or protective |
||||
* notices from any copy made by LICENSEE. |
||||
* |
||||
* This software is provided "AS-IS" and any express or implied |
||||
* warranties or conditions, including but not limited to any |
||||
* implied warranties of merchantability and fitness for a particular |
||||
* purpose regarding this software. In no event shall WireSpeed |
||||
* be liable for any indirect, consequential, or incidental damages, |
||||
* loss of profits or revenue, loss of use or data, or interruption |
||||
* of business, whether the alleged damages are labeled in contract, |
||||
* tort, or indemnity. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
* |
||||
* author(s) : Joe deBlaquiere |
||||
* |
||||
* Modified to support NS7520 by Art Shipkowski. |
||||
*/ |
||||
|
||||
#ifndef __NET_ARM_REGISTERS_H |
||||
#define __NET_ARM_REGISTERS_H |
||||
|
||||
#include <config.h> |
||||
|
||||
/* fundamental constants : */ |
||||
/* the input crystal/clock frequency ( in Hz ) */ |
||||
#define NETARM_XTAL_FREQ_25MHz (18432000) |
||||
#define NETARM_XTAL_FREQ_33MHz (23698000) |
||||
#define NETARM_XTAL_FREQ_48MHz (48000000) |
||||
#define NETARM_XTAL_FREQ_55MHz (55000000) |
||||
#define NETARM_XTAL_FREQ_EMLIN1 (20000000) |
||||
|
||||
/* the frequency of SYS_CLK */ |
||||
#if defined(CONFIG_NETARM_EMLIN) |
||||
|
||||
/* EMLIN board: 33 MHz (exp.) */ |
||||
#define NETARM_PLL_COUNT_VAL 6 |
||||
#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz |
||||
|
||||
#elif defined(CONFIG_NETARM_NET40_REV2) |
||||
|
||||
/* NET+40 Rev2 boards: 33 MHz (with NETARM_XTAL_FREQ_25MHz) */ |
||||
#define NETARM_PLL_COUNT_VAL 6 |
||||
#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz |
||||
|
||||
#elif defined(CONFIG_NETARM_NET40_REV4) |
||||
|
||||
/* NET+40 Rev4 boards with EDO must clock slower: 25 MHz (with
|
||||
NETARM_XTAL_FREQ_25MHz) 4 */ |
||||
#define NETARM_PLL_COUNT_VAL 4 |
||||
#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz |
||||
|
||||
#elif defined(CONFIG_NETARM_NET50) |
||||
|
||||
/* NET+50 boards: 40 MHz (with NETARM_XTAL_FREQ_25MHz) */ |
||||
#define NETARM_PLL_COUNT_VAL 8 |
||||
#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz |
||||
|
||||
#else /* CONFIG_NETARM_NS7520 */ |
||||
|
||||
#define NETARM_PLL_COUNT_VAL 0 |
||||
|
||||
#if defined(CONFIG_BOARD_UNC20) |
||||
#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_48MHz |
||||
#else |
||||
#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_55MHz |
||||
#endif |
||||
|
||||
#endif |
||||
|
||||
/* #include "arm_registers.h" */ |
||||
#include <asm/arch/netarm_gen_module.h> |
||||
#include <asm/arch/netarm_mem_module.h> |
||||
#include <asm/arch/netarm_ser_module.h> |
||||
#include <asm/arch/netarm_eni_module.h> |
||||
#include <asm/arch/netarm_dma_module.h> |
||||
#include <asm/arch/netarm_eth_module.h> |
||||
|
||||
#endif |
||||
@ -1,347 +0,0 @@ |
||||
/*
|
||||
* linux/include/asm-arm/arch-netarm/netarm_ser_module.h |
||||
* |
||||
* Copyright (C) 2000 NETsilicon, Inc. |
||||
* Copyright (C) 2000 Red Hat, Inc. |
||||
* |
||||
* This software is copyrighted by Red Hat. LICENSEE agrees that |
||||
* it will not delete this copyright notice, trademarks or protective |
||||
* notices from any copy made by LICENSEE. |
||||
* |
||||
* This software is provided "AS-IS" and any express or implied |
||||
* warranties or conditions, including but not limited to any |
||||
* implied warranties of merchantability and fitness for a particular |
||||
* purpose regarding this software. In no event shall Red Hat |
||||
* be liable for any indirect, consequential, or incidental damages, |
||||
* loss of profits or revenue, loss of use or data, or interruption |
||||
* of business, whether the alleged damages are labeled in contract, |
||||
* tort, or indemnity. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
* |
||||
* author(s) : Joe deBlaquiere |
||||
* Clark Williams |
||||
*/ |
||||
|
||||
#ifndef __NETARM_SER_MODULE_REGISTERS_H |
||||
#define __NETARM_SER_MODULE_REGISTERS_H |
||||
|
||||
#ifndef __ASSEMBLER__ |
||||
|
||||
/* (--sub)#include "types.h" */ |
||||
|
||||
/* serial channel control structure */ |
||||
typedef struct { |
||||
u32 ctrl_a; |
||||
u32 ctrl_b; |
||||
u32 status_a; |
||||
u32 bitrate; |
||||
u32 fifo; |
||||
u32 rx_buf_timer; |
||||
u32 rx_char_timer; |
||||
u32 rx_match; |
||||
u32 rx_match_mask; |
||||
u32 ctrl_c; |
||||
u32 status_b; |
||||
u32 status_c; |
||||
u32 fifo_last; |
||||
u32 unused[3]; |
||||
} netarm_serial_channel_t; |
||||
|
||||
#endif |
||||
|
||||
/* SER unit register offsets */ |
||||
|
||||
/* #ifdef CONFIG_ARCH_NETARM */ |
||||
#define NETARM_SER_MODULE_BASE (0xFFD00000) |
||||
/* #else */ |
||||
/* extern serial_channel_t netarm_dummy_registers[]; */ |
||||
/* #define NETARM_SER_MODULE_BASE (netarm_dummy_registers) */ |
||||
/* #ifndef NETARM_XTAL_FREQ */ |
||||
/* #define NETARM_XTAL_FREQ 18432000 */ |
||||
/* #endif */ |
||||
/* #endif */ |
||||
|
||||
/* calculate the sysclk value from the pll setting */ |
||||
#define NETARM_PLLED_SYSCLK_FREQ (( NETARM_XTAL_FREQ / 5 ) * \ |
||||
( NETARM_PLL_COUNT_VAL + 3 )) |
||||
|
||||
#define get_serial_channel(c) (&(((netarm_serial_channel_t *)NETARM_SER_MODULE_BASE)[c])) |
||||
|
||||
#define NETARM_SER_CH1_CTRL_A (0x00) |
||||
#define NETARM_SER_CH1_CTRL_B (0x04) |
||||
#define NETARM_SER_CH1_STATUS_A (0x08) |
||||
#define NETARM_SER_CH1_BITRATE (0x0C) |
||||
#define NETARM_SER_CH1_FIFO (0x10) |
||||
#define NETARM_SER_CH1_RX_BUF_TMR (0x14) |
||||
#define NETARM_SER_CH1_RX_CHAR_TMR (0x18) |
||||
#define NETARM_SER_CH1_RX_MATCH (0x1c) |
||||
#define NETARM_SER_CH1_RX_MATCH_MASK (0x20) |
||||
#define NETARM_SER_CH1_CTRL_C (0x24) |
||||
#define NETARM_SER_CH1_STATUS_B (0x28) |
||||
#define NETARM_SER_CH1_STATUS_C (0x2c) |
||||
#define NETARM_SER_CH1_FIFO_LAST (0x30) |
||||
|
||||
#define NETARM_SER_CH2_CTRL_A (0x40) |
||||
#define NETARM_SER_CH2_CTRL_B (0x44) |
||||
#define NETARM_SER_CH2_STATUS_A (0x48) |
||||
#define NETARM_SER_CH2_BITRATE (0x4C) |
||||
#define NETARM_SER_CH2_FIFO (0x50) |
||||
#define NETARM_SER_CH2_RX_BUF_TMR (0x54) |
||||
#define NETARM_SER_CH2_RX_CHAR_TMR (0x58) |
||||
#define NETARM_SER_CH2_RX_MATCH (0x5c) |
||||
#define NETARM_SER_CH2_RX_MATCH_MASK (0x60) |
||||
#define NETARM_SER_CH2_CTRL_C (0x64) |
||||
#define NETARM_SER_CH2_STATUS_B (0x68) |
||||
#define NETARM_SER_CH2_STATUS_C (0x6c) |
||||
#define NETARM_SER_CH2_FIFO_LAST (0x70) |
||||
|
||||
/* select bitfield defintions */ |
||||
|
||||
/* Control Register A */ |
||||
|
||||
#define NETARM_SER_CTLA_ENABLE (0x80000000) |
||||
#define NETARM_SER_CTLA_BRK (0x40000000) |
||||
|
||||
#define NETARM_SER_CTLA_STICKP (0x20000000) |
||||
|
||||
#define NETARM_SER_CTLA_P_EVEN (0x18000000) |
||||
#define NETARM_SER_CTLA_P_ODD (0x08000000) |
||||
#define NETARM_SER_CTLA_P_NONE (0x00000000) |
||||
|
||||
/* if you read the errata, you will find that the STOP bits don't work right */ |
||||
#define NETARM_SER_CTLA_2STOP (0x00000000) |
||||
#define NETARM_SER_CTLA_3STOP (0x04000000) |
||||
|
||||
#define NETARM_SER_CTLA_5BITS (0x00000000) |
||||
#define NETARM_SER_CTLA_6BITS (0x01000000) |
||||
#define NETARM_SER_CTLA_7BITS (0x02000000) |
||||
#define NETARM_SER_CTLA_8BITS (0x03000000) |
||||
|
||||
#define NETARM_SER_CTLA_CTSTX (0x00800000) |
||||
#define NETARM_SER_CTLA_RTSRX (0x00400000) |
||||
|
||||
#define NETARM_SER_CTLA_LOOP_REM (0x00200000) |
||||
#define NETARM_SER_CTLA_LOOP_LOC (0x00100000) |
||||
|
||||
#define NETARM_SER_CTLA_GPIO2 (0x00080000) |
||||
#define NETARM_SER_CTLA_GPIO1 (0x00040000) |
||||
|
||||
#define NETARM_SER_CTLA_DTR_EN (0x00020000) |
||||
#define NETARM_SER_CTLA_RTS_EN (0x00010000) |
||||
|
||||
#define NETARM_SER_CTLA_IE_RX_BRK (0x00008000) |
||||
#define NETARM_SER_CTLA_IE_RX_FRMERR (0x00004000) |
||||
#define NETARM_SER_CTLA_IE_RX_PARERR (0x00002000) |
||||
#define NETARM_SER_CTLA_IE_RX_OVERRUN (0x00001000) |
||||
#define NETARM_SER_CTLA_IE_RX_RDY (0x00000800) |
||||
#define NETARM_SER_CTLA_IE_RX_HALF (0x00000400) |
||||
#define NETARM_SER_CTLA_IE_RX_FULL (0x00000200) |
||||
#define NETARM_SER_CTLA_IE_RX_DMAEN (0x00000100) |
||||
#define NETARM_SER_CTLA_IE_RX_DCD (0x00000080) |
||||
#define NETARM_SER_CTLA_IE_RX_RI (0x00000040) |
||||
#define NETARM_SER_CTLA_IE_RX_DSR (0x00000020) |
||||
|
||||
#define NETARM_SER_CTLA_IE_RX_ALL (NETARM_SER_CTLA_IE_RX_BRK \ |
||||
|NETARM_SER_CTLA_IE_RX_FRMERR \
|
||||
|NETARM_SER_CTLA_IE_RX_PARERR \
|
||||
|NETARM_SER_CTLA_IE_RX_OVERRUN \
|
||||
|NETARM_SER_CTLA_IE_RX_RDY \
|
||||
|NETARM_SER_CTLA_IE_RX_HALF \
|
||||
|NETARM_SER_CTLA_IE_RX_FULL \
|
||||
|NETARM_SER_CTLA_IE_RX_DMAEN \
|
||||
|NETARM_SER_CTLA_IE_RX_DCD \
|
||||
|NETARM_SER_CTLA_IE_RX_RI \
|
||||
|NETARM_SER_CTLA_IE_RX_DSR) |
||||
|
||||
#define NETARM_SER_CTLA_IE_TX_CTS (0x00000010) |
||||
#define NETARM_SER_CTLA_IE_TX_EMPTY (0x00000008) |
||||
#define NETARM_SER_CTLA_IE_TX_HALF (0x00000004) |
||||
#define NETARM_SER_CTLA_IE_TX_FULL (0x00000002) |
||||
#define NETARM_SER_CTLA_IE_TX_DMAEN (0x00000001) |
||||
|
||||
#define NETARM_SER_CTLA_IE_TX_ALL (NETARM_SER_CTLA_IE_TX_CTS \ |
||||
|NETARM_SER_CTLA_IE_TX_EMPTY \
|
||||
|NETARM_SER_CTLA_IE_TX_HALF \
|
||||
|NETARM_SER_CTLA_IE_TX_FULL \
|
||||
|NETARM_SER_CTLA_IE_TX_DMAEN) |
||||
|
||||
/* Control Register B */ |
||||
|
||||
#define NETARM_SER_CTLB_MATCH1_EN (0x80000000) |
||||
#define NETARM_SER_CTLB_MATCH2_EN (0x40000000) |
||||
#define NETARM_SER_CTLB_MATCH3_EN (0x20000000) |
||||
#define NETARM_SER_CTLB_MATCH4_EN (0x10000000) |
||||
|
||||
#define NETARM_SER_CTLB_RBGT_EN (0x08000000) |
||||
#define NETARM_SER_CTLB_RCGT_EN (0x04000000) |
||||
|
||||
#define NETARM_SER_CTLB_UART_MODE (0x00000000) |
||||
#define NETARM_SER_CTLB_HDLC_MODE (0x00100000) |
||||
#define NETARM_SER_CTLB_SPI_MAS_MODE (0x00200000) |
||||
#define NETARM_SER_CTLB_SPI_SLV_MODE (0x00300000) |
||||
|
||||
#define NETARM_SER_CTLB_REV_BIT_ORDER (0x00080000) |
||||
|
||||
#define NETARM_SER_CTLB_MAM1 (0x00040000) |
||||
#define NETARM_SER_CTLB_MAM2 (0x00020000) |
||||
|
||||
/* Status Register A */ |
||||
|
||||
#define NETARM_SER_STATA_MATCH1 (0x80000000) |
||||
#define NETARM_SER_STATA_MATCH2 (0x40000000) |
||||
#define NETARM_SER_STATA_MATCH3 (0x20000000) |
||||
#define NETARM_SER_STATA_MATCH4 (0x10000000) |
||||
|
||||
#define NETARM_SER_STATA_BGAP (0x80000000) |
||||
#define NETARM_SER_STATA_CGAP (0x40000000) |
||||
|
||||
#define NETARM_SER_STATA_RX_1B (0x00100000) |
||||
#define NETARM_SER_STATA_RX_2B (0x00200000) |
||||
#define NETARM_SER_STATA_RX_3B (0x00300000) |
||||
#define NETARM_SER_STATA_RX_4B (0x00000000) |
||||
|
||||
/* downshifted values */ |
||||
|
||||
#define NETARM_SER_STATA_RXFDB_1BYTES (0x001) |
||||
#define NETARM_SER_STATA_RXFDB_2BYTES (0x002) |
||||
#define NETARM_SER_STATA_RXFDB_3BYTES (0x003) |
||||
#define NETARM_SER_STATA_RXFDB_4BYTES (0x000) |
||||
|
||||
#define NETARM_SER_STATA_RXFDB_MASK (0x00300000) |
||||
#define NETARM_SER_STATA_RXFDB(x) (((x) & NETARM_SER_STATA_RXFDB_MASK) \ |
||||
>> 20) |
||||
|
||||
#define NETARM_SER_STATA_DCD (0x00080000) |
||||
#define NETARM_SER_STATA_RI (0x00040000) |
||||
#define NETARM_SER_STATA_DSR (0x00020000) |
||||
#define NETARM_SER_STATA_CTS (0x00010000) |
||||
|
||||
#define NETARM_SER_STATA_RX_BRK (0x00008000) |
||||
#define NETARM_SER_STATA_RX_FRMERR (0x00004000) |
||||
#define NETARM_SER_STATA_RX_PARERR (0x00002000) |
||||
#define NETARM_SER_STATA_RX_OVERRUN (0x00001000) |
||||
#define NETARM_SER_STATA_RX_RDY (0x00000800) |
||||
#define NETARM_SER_STATA_RX_HALF (0x00000400) |
||||
#define NETARM_SER_STATA_RX_CLOSED (0x00000200) |
||||
#define NETARM_SER_STATA_RX_FULL (0x00000100) |
||||
#define NETARM_SER_STATA_RX_DCD (0x00000080) |
||||
#define NETARM_SER_STATA_RX_RI (0x00000040) |
||||
#define NETARM_SER_STATA_RX_DSR (0x00000020) |
||||
|
||||
#define NETARM_SER_STATA_TX_CTS (0x00000010) |
||||
#define NETARM_SER_STATA_TX_RDY (0x00000008) |
||||
#define NETARM_SER_STATA_TX_HALF (0x00000004) |
||||
#define NETARM_SER_STATA_TX_FULL (0x00000002) |
||||
#define NETARM_SER_STATA_TX_DMAEN (0x00000001) |
||||
|
||||
/* you have to clear all receive signals to get the fifo to move forward */ |
||||
#define NETARM_SER_STATA_CLR_ALL (NETARM_SER_STATA_RX_BRK | \ |
||||
NETARM_SER_STATA_RX_FRMERR | \
|
||||
NETARM_SER_STATA_RX_PARERR | \
|
||||
NETARM_SER_STATA_RX_OVERRUN | \
|
||||
NETARM_SER_STATA_RX_HALF | \
|
||||
NETARM_SER_STATA_RX_CLOSED | \
|
||||
NETARM_SER_STATA_RX_FULL | \
|
||||
NETARM_SER_STATA_RX_DCD | \
|
||||
NETARM_SER_STATA_RX_RI | \
|
||||
NETARM_SER_STATA_RX_DSR | \
|
||||
NETARM_SER_STATA_TX_CTS ) |
||||
|
||||
/* Bit Rate Registers */ |
||||
|
||||
#define NETARM_SER_BR_EN (0x80000000) |
||||
#define NETARM_SER_BR_TMODE (0x40000000) |
||||
|
||||
#define NETARM_SER_BR_RX_CLK_INT (0x00000000) |
||||
#define NETARM_SER_BR_RX_CLK_EXT (0x20000000) |
||||
#define NETARM_SER_BR_TX_CLK_INT (0x00000000) |
||||
#define NETARM_SER_BR_TX_CLK_EXT (0x10000000) |
||||
|
||||
#define NETARM_SER_BR_RX_CLK_DRV (0x08000000) |
||||
#define NETARM_SER_BR_TX_CLK_DRV (0x04000000) |
||||
|
||||
#define NETARM_SER_BR_CLK_EXT_5 (0x00000000) |
||||
#define NETARM_SER_BR_CLK_SYSTEM (0x01000000) |
||||
#define NETARM_SER_BR_CLK_OUT1A (0x02000000) |
||||
#define NETARM_SER_BR_CLK_OUT2A (0x03000000) |
||||
|
||||
#define NETARM_SER_BR_TX_CLK_INV (0x00800000) |
||||
#define NETARM_SER_BR_RX_CLK_INV (0x00400000) |
||||
|
||||
/* complete settings assuming system clock input is 18MHz */ |
||||
|
||||
#define NETARM_SER_BR_MASK (0x000007FF) |
||||
|
||||
/* bit rate determined from equation Fbr = Fxtal / [ 10 * ( N + 1 ) ] */ |
||||
/* from section 7.5.4 of HW Ref Guide */ |
||||
|
||||
/* #ifdef CONFIG_NETARM_PLL_BYPASS */ |
||||
#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \ |
||||
NETARM_SER_BR_RX_CLK_INT | \
|
||||
NETARM_SER_BR_TX_CLK_INT | \
|
||||
NETARM_SER_BR_CLK_EXT_5 | \
|
||||
( ( ( ( NETARM_XTAL_FREQ / \
|
||||
( x * 10 ) ) - 1 ) / 16 ) & \
|
||||
NETARM_SER_BR_MASK ) ) |
||||
/*
|
||||
#else |
||||
#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \ |
||||
NETARM_SER_BR_RX_CLK_INT | \
|
||||
NETARM_SER_BR_TX_CLK_INT | \
|
||||
NETARM_SER_BR_CLK_SYSTEM | \
|
||||
( ( ( ( NETARM_PLLED_SYSCLK_FREQ / \
|
||||
( x * 2 ) ) - 1 ) / 16 ) & \
|
||||
NETARM_SER_BR_MASK ) ) |
||||
#endif |
||||
*/ |
||||
|
||||
/* Receive Buffer Gap Timer */ |
||||
|
||||
#define NETARM_SER_RX_GAP_TIMER_EN (0x80000000) |
||||
#define NETARM_SER_RX_GAP_MASK (0x00003FFF) |
||||
|
||||
/* rx gap is a function of bit rate x */ |
||||
|
||||
/* #ifdef CONFIG_NETARM_PLL_BYPASS */ |
||||
#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ |
||||
( ( ( ( 10 * NETARM_XTAL_FREQ ) / \
|
||||
( x * 5 * 512 ) ) - 1 ) & \
|
||||
NETARM_SER_RX_GAP_MASK ) ) |
||||
/*
|
||||
#else |
||||
#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ |
||||
( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) / \
|
||||
( x * 512 ) ) - 1 ) & \
|
||||
NETARM_SER_RX_GAP_MASK ) ) |
||||
#endif |
||||
*/ |
||||
|
||||
#if 0 |
||||
#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ |
||||
( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) / \
|
||||
( x * 5 * 512 ) ) - 1 ) & \
|
||||
NETARM_SER_RX_GAP_MASK ) ) |
||||
#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ |
||||
( ( ( ( 10 * NETARM_XTAL_FREQ ) / \
|
||||
( x * 512 ) ) - 1 ) & \
|
||||
NETARM_SER_RX_GAP_MASK ) ) |
||||
#endif |
||||
|
||||
#define MIN_BAUD_RATE 600 |
||||
#define MAX_BAUD_RATE 115200 |
||||
|
||||
/* the default BAUD rate for the BOOTLOADER, there is a separate */ |
||||
/* setting in the serial driver <arch/armnommu/drivers/char/serial-netarm.h> */ |
||||
#define DEFAULT_BAUD_RATE 9600 |
||||
#define NETARM_SER_FIFO_SIZE 32 |
||||
#define MIN_GAP 0 |
||||
|
||||
#endif |
||||
@ -1,33 +0,0 @@ |
||||
#ifndef __ASM_ARCH_HARDWARE_H |
||||
#define __ASM_ARCH_HARDWARE_H |
||||
|
||||
/*
|
||||
* Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
|
||||
* Curt Brune <curt@cucy.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#if defined(CONFIG_LPC2292) |
||||
#include <asm/arch-lpc2292/lpc2292_registers.h> |
||||
#else |
||||
#error No hardware file defined for this configuration |
||||
#endif |
||||
|
||||
#endif /* __ASM_ARCH_HARDWARE_H */ |
||||
@ -1,225 +0,0 @@ |
||||
#ifndef __LPC2292_REGISTERS_H |
||||
#define __LPC2292_REGISTERS_H |
||||
|
||||
#include <config.h> |
||||
|
||||
/* Macros for reading/writing registers */ |
||||
#define PUT8(reg, value) (*(volatile unsigned char*)(reg) = (value)) |
||||
#define PUT16(reg, value) (*(volatile unsigned short*)(reg) = (value)) |
||||
#define PUT32(reg, value) (*(volatile unsigned int*)(reg) = (value)) |
||||
#define GET8(reg) (*(volatile unsigned char*)(reg)) |
||||
#define GET16(reg) (*(volatile unsigned short*)(reg)) |
||||
#define GET32(reg) (*(volatile unsigned int*)(reg)) |
||||
|
||||
/* External Memory Controller */ |
||||
|
||||
#define BCFG0 0xFFE00000 /* 32-bits */ |
||||
#define BCFG1 0xFFE00004 /* 32-bits */ |
||||
#define BCFG2 0xFFE00008 /* 32-bits */ |
||||
#define BCFG3 0xFFE0000c /* 32-bits */ |
||||
|
||||
/* System Control Block */ |
||||
|
||||
#define EXTINT 0xE01FC140 |
||||
#define EXTWAKE 0xE01FC144 |
||||
#define EXTMODE 0xE01FC148 |
||||
#define EXTPOLAR 0xE01FC14C |
||||
#define MEMMAP 0xE01FC040 |
||||
#define PLLCON 0xE01FC080 |
||||
#define PLLCFG 0xE01FC084 |
||||
#define PLLSTAT 0xE01FC088 |
||||
#define PLLFEED 0xE01FC08C |
||||
#define PCON 0xE01FC0C0 |
||||
#define PCONP 0xE01FC0C4 |
||||
#define VPBDIV 0xE01FC100 |
||||
|
||||
/* Memory Acceleration Module */ |
||||
|
||||
#define MAMCR 0xE01FC000 |
||||
#define MAMTIM 0xE01FC004 |
||||
|
||||
/* Vectored Interrupt Controller */ |
||||
|
||||
#define VICIRQStatus 0xFFFFF000 |
||||
#define VICFIQStatus 0xFFFFF004 |
||||
#define VICRawIntr 0xFFFFF008 |
||||
#define VICIntSelect 0xFFFFF00C |
||||
#define VICIntEnable 0xFFFFF010 |
||||
#define VICIntEnClr 0xFFFFF014 |
||||
#define VICSoftInt 0xFFFFF018 |
||||
#define VICSoftIntClear 0xFFFFF01C |
||||
#define VICProtection 0xFFFFF020 |
||||
#define VICVectAddr 0xFFFFF030 |
||||
#define VICDefVectAddr 0xFFFFF034 |
||||
#define VICVectAddr0 0xFFFFF100 |
||||
#define VICVectAddr1 0xFFFFF104 |
||||
#define VICVectAddr2 0xFFFFF108 |
||||
#define VICVectAddr3 0xFFFFF10C |
||||
#define VICVectAddr4 0xFFFFF110 |
||||
#define VICVectAddr5 0xFFFFF114 |
||||
#define VICVectAddr6 0xFFFFF118 |
||||
#define VICVectAddr7 0xFFFFF11C |
||||
#define VICVectAddr8 0xFFFFF120 |
||||
#define VICVectAddr9 0xFFFFF124 |
||||
#define VICVectAddr10 0xFFFFF128 |
||||
#define VICVectAddr11 0xFFFFF12C |
||||
#define VICVectAddr12 0xFFFFF130 |
||||
#define VICVectAddr13 0xFFFFF134 |
||||
#define VICVectAddr14 0xFFFFF138 |
||||
#define VICVectAddr15 0xFFFFF13C |
||||
#define VICVectCntl0 0xFFFFF200 |
||||
#define VICVectCntl1 0xFFFFF204 |
||||
#define VICVectCntl2 0xFFFFF208 |
||||
#define VICVectCntl3 0xFFFFF20C |
||||
#define VICVectCntl4 0xFFFFF210 |
||||
#define VICVectCntl5 0xFFFFF214 |
||||
#define VICVectCntl6 0xFFFFF218 |
||||
#define VICVectCntl7 0xFFFFF21C |
||||
#define VICVectCntl8 0xFFFFF220 |
||||
#define VICVectCntl9 0xFFFFF224 |
||||
#define VICVectCntl10 0xFFFFF228 |
||||
#define VICVectCntl11 0xFFFFF22C |
||||
#define VICVectCntl12 0xFFFFF230 |
||||
#define VICVectCntl13 0xFFFFF234 |
||||
#define VICVectCntl14 0xFFFFF238 |
||||
#define VICVectCntl15 0xFFFFF23C |
||||
|
||||
/* Pin connect block */ |
||||
|
||||
#define PINSEL0 0xE002C000 /* 32 bits */ |
||||
#define PINSEL1 0xE002C004 /* 32 bits */ |
||||
#define PINSEL2 0xE002C014 /* 32 bits */ |
||||
|
||||
/* GPIO */ |
||||
|
||||
#define IO0PIN 0xE0028000 |
||||
#define IO0SET 0xE0028004 |
||||
#define IO0DIR 0xE0028008 |
||||
#define IO0CLR 0xE002800C |
||||
#define IO1PIN 0xE0028010 |
||||
#define IO1SET 0xE0028014 |
||||
#define IO1DIR 0xE0028018 |
||||
#define IO1CLR 0xE002801C |
||||
#define IO2PIN 0xE0028020 |
||||
#define IO2SET 0xE0028024 |
||||
#define IO2DIR 0xE0028028 |
||||
#define IO2CLR 0xE002802C |
||||
#define IO3PIN 0xE0028030 |
||||
#define IO3SET 0xE0028034 |
||||
#define IO3DIR 0xE0028038 |
||||
#define IO3CLR 0xE002803C |
||||
|
||||
/* Uarts */ |
||||
|
||||
#define U0RBR 0xE000C000 |
||||
#define U0THR 0xE000C000 |
||||
#define U0IER 0xE000C004 |
||||
#define U0IIR 0xE000C008 |
||||
#define U0FCR 0xE000C008 |
||||
#define U0LCR 0xE000C00C |
||||
#define U0LSR 0xE000C014 |
||||
#define U0SCR 0xE000C01C |
||||
#define U0DLL 0xE000C000 |
||||
#define U0DLM 0xE000C004 |
||||
|
||||
#define U1RBR 0xE0010000 |
||||
#define U1THR 0xE0010000 |
||||
#define U1IER 0xE0010004 |
||||
#define U1IIR 0xE0010008 |
||||
#define U1FCR 0xE0010008 |
||||
#define U1LCR 0xE001000C |
||||
#define U1MCR 0xE0010010 |
||||
#define U1LSR 0xE0010014 |
||||
#define U1MSR 0xE0010018 |
||||
#define U1SCR 0xE001001C |
||||
#define U1DLL 0xE0010000 |
||||
#define U1DLM 0xE0010004 |
||||
|
||||
/* I2C */ |
||||
|
||||
#define I2CONSET 0xE001C000 |
||||
#define I2STAT 0xE001C004 |
||||
#define I2DAT 0xE001C008 |
||||
#define I2ADR 0xE001C00C |
||||
#define I2SCLH 0xE001C010 |
||||
#define I2SCLL 0xE001C014 |
||||
#define I2CONCLR 0xE001C018 |
||||
|
||||
/* SPI */ |
||||
|
||||
#define S0SPCR 0xE0020000 |
||||
#define S0SPSR 0xE0020004 |
||||
#define S0SPDR 0xE0020008 |
||||
#define S0SPCCR 0xE002000C |
||||
#define S0SPINT 0xE002001C |
||||
|
||||
#define S1SPCR 0xE0030000 |
||||
#define S1SPSR 0xE0030004 |
||||
#define S1SPDR 0xE0030008 |
||||
#define S1SPCCR 0xE003000C |
||||
#define S1SPINT 0xE003001C |
||||
|
||||
/* CAN controller */ |
||||
|
||||
/* skip for now */ |
||||
|
||||
/* Timers */ |
||||
|
||||
#define T0IR 0xE0004000 |
||||
#define T0TCR 0xE0004004 |
||||
#define T0TC 0xE0004008 |
||||
#define T0PR 0xE000400C |
||||
#define T0PC 0xE0004010 |
||||
#define T0MCR 0xE0004014 |
||||
#define T0MR0 0xE0004018 |
||||
#define T0MR1 0xE000401C |
||||
#define T0MR2 0xE0004020 |
||||
#define T0MR3 0xE0004024 |
||||
#define T0CCR 0xE0004028 |
||||
#define T0CR0 0xE000402C |
||||
#define T0CR1 0xE0004030 |
||||
#define T0CR2 0xE0004034 |
||||
#define T0CR3 0xE0004038 |
||||
#define T0EMR 0xE000403C |
||||
|
||||
#define T1IR 0xE0008000 |
||||
#define T1TCR 0xE0008004 |
||||
#define T1TC 0xE0008008 |
||||
#define T1PR 0xE000800C |
||||
#define T1PC 0xE0008010 |
||||
#define T1MCR 0xE0008014 |
||||
#define T1MR0 0xE0008018 |
||||
#define T1MR1 0xE000801C |
||||
#define T1MR2 0xE0008020 |
||||
#define T1MR3 0xE0008024 |
||||
#define T1CCR 0xE0008028 |
||||
#define T1CR0 0xE000802C |
||||
#define T1CR1 0xE0008030 |
||||
#define T1CR2 0xE0008034 |
||||
#define T1CR3 0xE0008038 |
||||
#define T1EMR 0xE000803C |
||||
|
||||
/* PWM */ |
||||
|
||||
/* skip for now */ |
||||
|
||||
/* A/D converter */ |
||||
|
||||
/* skip for now */ |
||||
|
||||
/* Real Time Clock */ |
||||
|
||||
/* skip for now */ |
||||
|
||||
/* Watchdog */ |
||||
|
||||
#define WDMOD 0xE0000000 |
||||
#define WDTC 0xE0000004 |
||||
#define WDFEED 0xE0000008 |
||||
#define WDTV 0xE000000C |
||||
|
||||
/* EmbeddedICE LOGIC */ |
||||
|
||||
/* skip for now */ |
||||
|
||||
#endif |
||||
@ -1,82 +0,0 @@ |
||||
/*
|
||||
This file defines the interface to the lpc22xx SPI module. |
||||
Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com) |
||||
|
||||
This file may be included in software not adhering to the GPL. |
||||
|
||||
This program is free software; you can redistribute it and/or modify |
||||
it under the terms of the GNU General Public License as published by |
||||
the Free Software Foundation; either version 2 of the License, or |
||||
(at your option) any later version. |
||||
|
||||
This program is distributed in the hope that it will be useful, |
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
GNU General Public License for more details. |
||||
|
||||
You should have received a copy of the GNU General Public License |
||||
along with this program; if not, write to the Free Software |
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef SPI_H |
||||
#define SPI_H |
||||
|
||||
#include <config.h> |
||||
#include <common.h> |
||||
#include <asm/errno.h> |
||||
#include <asm/arch/hardware.h> |
||||
|
||||
#define SPIF 0x80 |
||||
|
||||
#define spi_lock() disable_interrupts(); |
||||
#define spi_unlock() enable_interrupts(); |
||||
|
||||
extern unsigned long spi_flags; |
||||
extern unsigned char spi_idle; |
||||
|
||||
int spi_init(void); |
||||
|
||||
static inline unsigned char spi_read(void) |
||||
{ |
||||
unsigned char b; |
||||
|
||||
PUT8(S0SPDR, spi_idle); |
||||
while (!(GET8(S0SPSR) & SPIF)); |
||||
b = GET8(S0SPDR); |
||||
|
||||
return b; |
||||
} |
||||
|
||||
static inline void spi_write(unsigned char b) |
||||
{ |
||||
PUT8(S0SPDR, b); |
||||
while (!(GET8(S0SPSR) & SPIF)); |
||||
GET8(S0SPDR); /* this will clear the SPIF bit */ |
||||
} |
||||
|
||||
static inline void spi_set_clock(unsigned char clk_value) |
||||
{ |
||||
PUT8(S0SPCCR, clk_value); |
||||
} |
||||
|
||||
static inline void spi_set_cfg(unsigned char phase, |
||||
unsigned char polarity, |
||||
unsigned char lsbf) |
||||
{ |
||||
unsigned char v = 0x20; /* master bit set */ |
||||
|
||||
if (phase) |
||||
v |= 0x08; /* set phase bit */ |
||||
if (polarity) { |
||||
v |= 0x10; /* set polarity bit */ |
||||
spi_idle = 0xFF; |
||||
} else { |
||||
spi_idle = 0x00; |
||||
} |
||||
if (lsbf) |
||||
v |= 0x40; /* set lsbf bit */ |
||||
|
||||
PUT8(S0SPCR, v); |
||||
} |
||||
#endif /* SPI_H */ |
||||
@ -1,272 +0,0 @@ |
||||
#ifndef __HW_S3C4510_H |
||||
#define __HW_S3C4510_H |
||||
|
||||
/*
|
||||
* Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
|
||||
* Curt Brune <curt@cucy.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
* Description: Samsung S3C4510B register layout |
||||
*/ |
||||
|
||||
/*------------------------------------------------------------------------
|
||||
* ASIC Address Definition |
||||
*----------------------------------------------------------------------*/ |
||||
|
||||
/* L1 8KB on chip SRAM base address */ |
||||
#define SRAM_BASE (0x03fe0000) |
||||
|
||||
/* Special Register Start Address After System Reset */ |
||||
#define REG_BASE (0x03ff0000) |
||||
#define SPSTR (REG_BASE) |
||||
|
||||
/* *********************** */ |
||||
/* System Manager Register */ |
||||
/* *********************** */ |
||||
#define REG_SYSCFG (REG_BASE+0x0000) |
||||
|
||||
#define REG_CLKCON (REG_BASE+0x3000) |
||||
#define REG_EXTACON0 (REG_BASE+0x3008) |
||||
#define REG_EXTACON1 (REG_BASE+0x300c) |
||||
#define REG_EXTDBWTH (REG_BASE+0x3010) |
||||
#define REG_ROMCON0 (REG_BASE+0x3014) |
||||
#define REG_ROMCON1 (REG_BASE+0x3018) |
||||
#define REG_ROMCON2 (REG_BASE+0x301c) |
||||
#define REG_ROMCON3 (REG_BASE+0x3020) |
||||
#define REG_ROMCON4 (REG_BASE+0x3024) |
||||
#define REG_ROMCON5 (REG_BASE+0x3028) |
||||
#define REG_DRAMCON0 (REG_BASE+0x302c) |
||||
#define REG_DRAMCON1 (REG_BASE+0x3030) |
||||
#define REG_DRAMCON2 (REG_BASE+0x3034) |
||||
#define REG_DRAMCON3 (REG_BASE+0x3038) |
||||
#define REG_REFEXTCON (REG_BASE+0x303c) |
||||
|
||||
/* *********************** */ |
||||
/* Ethernet BDMA Register */ |
||||
/* *********************** */ |
||||
#define REG_BDMATXCON (REG_BASE+0x9000) |
||||
#define REG_BDMARXCON (REG_BASE+0x9004) |
||||
#define REG_BDMATXPTR (REG_BASE+0x9008) |
||||
#define REG_BDMARXPTR (REG_BASE+0x900c) |
||||
#define REG_BDMARXLSZ (REG_BASE+0x9010) |
||||
#define REG_BDMASTAT (REG_BASE+0x9014) |
||||
|
||||
/* Content Address Memory */ |
||||
#define REG_CAM_BASE (REG_BASE+0x9100) |
||||
|
||||
#define REG_BDMATXBUF (REG_BASE+0x9200) |
||||
#define REG_BDMARXBUF (REG_BASE+0x9800) |
||||
|
||||
/* *********************** */ |
||||
/* Ethernet MAC Register */ |
||||
/* *********************** */ |
||||
#define REG_MACCON (REG_BASE+0xa000) |
||||
#define REG_CAMCON (REG_BASE+0xa004) |
||||
#define REG_MACTXCON (REG_BASE+0xa008) |
||||
#define REG_MACTXSTAT (REG_BASE+0xa00c) |
||||
#define REG_MACRXCON (REG_BASE+0xa010) |
||||
#define REG_MACRXSTAT (REG_BASE+0xa014) |
||||
#define REG_STADATA (REG_BASE+0xa018) |
||||
#define REG_STACON (REG_BASE+0xa01c) |
||||
#define REG_CAMEN (REG_BASE+0xa028) |
||||
#define REG_EMISSCNT (REG_BASE+0xa03c) |
||||
#define REG_EPZCNT (REG_BASE+0xa040) |
||||
#define REG_ERMPZCNT (REG_BASE+0xa044) |
||||
#define REG_ETXSTAT (REG_BASE+0x9040) |
||||
#define REG_MACRXDESTR (REG_BASE+0xa064) |
||||
#define REG_MACRXSTATEM (REG_BASE+0xa090) |
||||
#define REG_MACRXFIFO (REG_BASE+0xa200) |
||||
|
||||
/********************/ |
||||
/* I2C Bus Register */ |
||||
/********************/ |
||||
#define REG_I2C_CON (REG_BASE+0xf000) |
||||
#define REG_I2C_BUF (REG_BASE+0xf004) |
||||
#define REG_I2C_PS (REG_BASE+0xf008) |
||||
#define REG_I2C_COUNT (REG_BASE+0xf00c) |
||||
|
||||
/********************/ |
||||
/* GDMA 0 */ |
||||
/********************/ |
||||
#define REG_GDMACON0 (REG_BASE+0xb000) |
||||
#define REG_GDMA0_RUN_ENABLE (REG_BASE+0xb020) |
||||
#define REG_GDMASRC0 (REG_BASE+0xb004) |
||||
#define REG_GDMADST0 (REG_BASE+0xb008) |
||||
#define REG_GDMACNT0 (REG_BASE+0xb00c) |
||||
|
||||
/********************/ |
||||
/* GDMA 1 */ |
||||
/********************/ |
||||
#define REG_GDMACON1 (REG_BASE+0xc000) |
||||
#define REG_GDMA1_RUN_ENABLE (REG_BASE+0xc020) |
||||
#define REG_GDMASRC1 (REG_BASE+0xc004) |
||||
#define REG_GDMADST1 (REG_BASE+0xc008) |
||||
#define REG_GDMACNT1 (REG_BASE+0xc00c) |
||||
|
||||
/********************/ |
||||
/* UART 0 */ |
||||
/********************/ |
||||
#define UART0_BASE (REG_BASE+0xd000) |
||||
#define REG_UART0_LCON (REG_BASE+0xd000) |
||||
#define REG_UART0_CTRL (REG_BASE+0xd004) |
||||
#define REG_UART0_STAT (REG_BASE+0xd008) |
||||
#define REG_UART0_TXB (REG_BASE+0xd00c) |
||||
#define REG_UART0_RXB (REG_BASE+0xd010) |
||||
#define REG_UART0_BAUD_DIV (REG_BASE+0xd014) |
||||
#define REG_UART0_BAUD_CNT (REG_BASE+0xd018) |
||||
#define REG_UART0_BAUD_CLK (REG_BASE+0xd01C) |
||||
|
||||
/********************/ |
||||
/* UART 1 */ |
||||
/********************/ |
||||
#define UART1_BASE (REG_BASE+0xe000) |
||||
#define REG_UART1_LCON (REG_BASE+0xe000) |
||||
#define REG_UART1_CTRL (REG_BASE+0xe004) |
||||
#define REG_UART1_STAT (REG_BASE+0xe008) |
||||
#define REG_UART1_TXB (REG_BASE+0xe00c) |
||||
#define REG_UART1_RXB (REG_BASE+0xe010) |
||||
#define REG_UART1_BAUD_DIV (REG_BASE+0xe014) |
||||
#define REG_UART1_BAUD_CNT (REG_BASE+0xe018) |
||||
#define REG_UART1_BAUD_CLK (REG_BASE+0xe01C) |
||||
|
||||
/********************/ |
||||
/* Timer Register */ |
||||
/********************/ |
||||
#define REG_TMOD (REG_BASE+0x6000) |
||||
#define REG_TDATA0 (REG_BASE+0x6004) |
||||
#define REG_TDATA1 (REG_BASE+0x6008) |
||||
#define REG_TCNT0 (REG_BASE+0x600c) |
||||
#define REG_TCNT1 (REG_BASE+0x6010) |
||||
|
||||
/**********************/ |
||||
/* I/O Port Interface */ |
||||
/**********************/ |
||||
#define REG_IOPMODE (REG_BASE+0x5000) |
||||
#define REG_IOPCON (REG_BASE+0x5004) |
||||
#define REG_IOPDATA (REG_BASE+0x5008) |
||||
|
||||
/*********************************/ |
||||
/* Interrupt Controller Register */ |
||||
/*********************************/ |
||||
#define REG_INTMODE (REG_BASE+0x4000) |
||||
#define REG_INTPEND (REG_BASE+0x4004) |
||||
#define REG_INTMASK (REG_BASE+0x4008) |
||||
|
||||
#define REG_INTPRI0 (REG_BASE+0x400c) |
||||
#define REG_INTPRI1 (REG_BASE+0x4010) |
||||
#define REG_INTPRI2 (REG_BASE+0x4014) |
||||
#define REG_INTPRI3 (REG_BASE+0x4018) |
||||
#define REG_INTPRI4 (REG_BASE+0x401c) |
||||
#define REG_INTPRI5 (REG_BASE+0x4020) |
||||
#define REG_INTOFFSET (REG_BASE+0x4024) |
||||
#define REG_INTPNDPRI (REG_BASE+0x4028) |
||||
#define REG_INTPNDTST (REG_BASE+0x402C) |
||||
|
||||
/*********************************/ |
||||
/* CACHE CONTROL MASKS */ |
||||
/*********************************/ |
||||
#define CACHE_STALL (0x00000001) |
||||
#define CACHE_ENABLE (0x00000002) |
||||
#define CACHE_WRITE_BUFF (0x00000004) |
||||
#define CACHE_MODE (0x00000030) |
||||
#define CACHE_MODE_00 (0x00000000) |
||||
#define CACHE_MODE_01 (0x00000010) |
||||
#define CACHE_MODE_10 (0x00000020) |
||||
|
||||
/*********************************/ |
||||
/* CACHE RAM BASE ADDRESSES */ |
||||
/*********************************/ |
||||
#define CACHE_SET0_RAM (0x10000000) |
||||
#define CACHE_SET1_RAM (0x10800000) |
||||
#define CACHE_TAG_RAM (0x11000000) |
||||
|
||||
/*********************************/ |
||||
/* CACHE_DISABLE MASK */ |
||||
/*********************************/ |
||||
#define CACHE_DISABLE_MASK (0x04000000) |
||||
|
||||
#define GET_REG(reg) (*((volatile u32 *)(reg))) |
||||
#define PUT_REG(reg, val) (*((volatile u32 *)(reg)) = ((u32)(val))) |
||||
#define SET_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) | mask)) |
||||
#define CLR_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) & ~mask)) |
||||
#define PUT_U16(reg, val) (*((volatile u16 *)(reg)) = ((u16)(val))) |
||||
#define PUT__U8(reg, val) (*((volatile u8 *)(reg)) = (( u8)((val)&0xFF))) |
||||
#define GET__U8(reg) (*((volatile u8 *)(reg))) |
||||
|
||||
#define PUT_LED(val) (PUT_REG(REG_IOPDATA, (~val)&0xFF)) |
||||
#define GET_LED() ((~GET_REG( REG_IOPDATA)) & 0xFF) |
||||
#define SET_LED(val) { u32 led = GET_LED(); led |= 1 << (val); PUT_LED( led); } |
||||
#define CLR_LED(val) { u32 led = GET_LED(); led &= ~(1 << (val)); PUT_LED( led); } |
||||
|
||||
/***********************************/ |
||||
/* CLOCK CONSTANTS -- 50 MHz Clock */ |
||||
/***********************************/ |
||||
|
||||
#define CLK_FREQ_MHZ (50) |
||||
#define t_data_us(t) ((t)*CLK_FREQ_MHZ-1) /* t is time tick,unit[us] */ |
||||
#define t_data_ms(t) (t_data_us((t)*1000)) /* t is time tick,unit[ms] */ |
||||
|
||||
/*********************************************************/ |
||||
/* TIMER MODE REGISTER */ |
||||
/*********************************************************/ |
||||
#define TM0_RUN 0x01 /* Timer 0 enable */ |
||||
#define TM0_TOGGLE 0x02 /* 0, interval mode */ |
||||
#define TM0_OUT_1 0x04 /* Timer 0 Initial TOUT0 value */ |
||||
#define TM1_RUN 0x08 /* Timer 1 enable */ |
||||
#define TM1_TOGGLE 0x10 /* 0, interval mode */ |
||||
#define TM1_OUT_1 0x20 /* Timer 0 Initial TOUT0 value */ |
||||
|
||||
|
||||
/*********************************/ |
||||
/* INTERRUPT SOURCES */ |
||||
/*********************************/ |
||||
#define INT_EXTINT0 0 |
||||
#define INT_EXTINT1 1 |
||||
#define INT_EXTINT2 2 |
||||
#define INT_EXTINT3 3 |
||||
#define INT_UARTTX0 4 |
||||
#define INT_UARTRX0 5 |
||||
#define INT_UARTTX1 6 |
||||
#define INT_UARTRX1 7 |
||||
#define INT_GDMA0 8 |
||||
#define INT_GDMA1 9 |
||||
#define INT_TIMER0 10 |
||||
#define INT_TIMER1 11 |
||||
#define INT_HDLCTXA 12 |
||||
#define INT_HDLCRXA 13 |
||||
#define INT_HDLCTXB 14 |
||||
#define INT_HDLCRXB 15 |
||||
#define INT_BDMATX 16 |
||||
#define INT_BDMARX 17 |
||||
#define INT_MACTX 18 |
||||
#define INT_MACRX 19 |
||||
#define INT_IIC 20 |
||||
#define INT_GLOBAL 21 |
||||
#define N_IRQS (21) |
||||
|
||||
#ifndef __ASSEMBLER__ |
||||
struct _irq_handler { |
||||
void *m_data; |
||||
void (*m_func)( void *data); |
||||
}; |
||||
|
||||
#endif |
||||
|
||||
#endif /* __S3C4510_h */ |
||||
@ -1,45 +0,0 @@ |
||||
#
|
||||
# (C) Copyright 2004-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := sx1.o
|
||||
SOBJS := lowlevel_init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
||||
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -1,19 +0,0 @@ |
||||
#
|
||||
# (C) Copyright 2004
|
||||
# Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
|
||||
#
|
||||
# SX1 board with OMAP1510 (ARM925T) cpu
|
||||
# see http://www.ti.com/ for more information on Texas Insturments
|
||||
#
|
||||
# SX1 has 1 bank of 256 MB SDRAM
|
||||
# Physical Address:
|
||||
# 1000'0000 to 2000'0000
|
||||
#
|
||||
#
|
||||
# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 (mem base + reserved)
|
||||
#
|
||||
# we load ourself to 1108'0000
|
||||
#
|
||||
#
|
||||
|
||||
CONFIG_SYS_TEXT_BASE = 0x11080000
|
||||
@ -1,397 +0,0 @@ |
||||
/* |
||||
* Board specific setup info |
||||
* |
||||
* (C) Copyright 2003 |
||||
* Texas Instruments, <www.ti.com> |
||||
* |
||||
* -- Some bits of code used from rrload's head_OMAP1510.s -- |
||||
* Copyright (C) 2002 RidgeRun, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <version.h> |
||||
|
||||
#if defined(CONFIG_OMAP1510) |
||||
#include <./configs/omap1510.h> |
||||
#endif |
||||
|
||||
#define OMAP1510_CLKS ((1<<EN_XORPCK)|(1<<EN_PERCK)|(1<<EN_TIMCK)|(1<<EN_GPIOCK)) |
||||
|
||||
|
||||
_TEXT_BASE: |
||||
.word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */ |
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init: |
||||
|
||||
/* |
||||
* Configure 1510 pins functions to match our board. |
||||
*/ |
||||
ldr r0, REG_PULL_DWN_CTRL_0 |
||||
ldr r1, VAL_PULL_DWN_CTRL_0 |
||||
str r1, [r0] |
||||
ldr r0, REG_PULL_DWN_CTRL_1 |
||||
ldr r1, VAL_PULL_DWN_CTRL_1 |
||||
str r1, [r0] |
||||
ldr r0, REG_PULL_DWN_CTRL_2 |
||||
ldr r1, VAL_PULL_DWN_CTRL_2 |
||||
str r1, [r0] |
||||
ldr r0, REG_PULL_DWN_CTRL_3 |
||||
ldr r1, VAL_PULL_DWN_CTRL_3 |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_4 |
||||
ldr r1, VAL_FUNC_MUX_CTRL_4 |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_5 |
||||
ldr r1, VAL_FUNC_MUX_CTRL_5 |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_6 |
||||
ldr r1, VAL_FUNC_MUX_CTRL_6 |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_7 |
||||
ldr r1, VAL_FUNC_MUX_CTRL_7 |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_8 |
||||
ldr r1, VAL_FUNC_MUX_CTRL_8 |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_9 |
||||
ldr r1, VAL_FUNC_MUX_CTRL_9 |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_A |
||||
ldr r1, VAL_FUNC_MUX_CTRL_A |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_B |
||||
ldr r1, VAL_FUNC_MUX_CTRL_B |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_C |
||||
ldr r1, VAL_FUNC_MUX_CTRL_C |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_D |
||||
ldr r1, VAL_FUNC_MUX_CTRL_D |
||||
str r1, [r0] |
||||
ldr r0, REG_VOLTAGE_CTRL_0 |
||||
ldr r1, VAL_VOLTAGE_CTRL_0 |
||||
str r1, [r0] |
||||
ldr r0, REG_TEST_DBG_CTRL_0 |
||||
ldr r1, VAL_TEST_DBG_CTRL_0 |
||||
str r1, [r0] |
||||
ldr r0, REG_MOD_CONF_CTRL_0 |
||||
ldr r1, VAL_MOD_CONF_CTRL_0 |
||||
str r1, [r0] |
||||
|
||||
/* Move to 1510 mode */ |
||||
ldr r0, REG_COMP_MODE_CTRL_0 |
||||
ldr r1, VAL_COMP_MODE_CTRL_0 |
||||
str r1, [r0] |
||||
|
||||
/* Set up Traffic Ctlr*/ |
||||
ldr r0, REG_TC_IMIF_PRIO |
||||
mov r1, #0x0 |
||||
str r1, [r0] |
||||
ldr r0, REG_TC_EMIFS_PRIO |
||||
str r1, [r0] |
||||
ldr r0, REG_TC_EMIFF_PRIO |
||||
str r1, [r0] |
||||
|
||||
ldr r0, REG_TC_EMIFS_CONFIG |
||||
ldr r1, [r0] |
||||
bic r1, r1, #0x08 /* clear the global power-down enable PDE bit */ |
||||
bic r1, r1, #0x01 /* write protect flash by clearing the WP bit */ |
||||
str r1, [r0] /* EMIFS GlB Configuration. (value 0x12 most likely) */ |
||||
|
||||
ldr r0, _GPIO_PIN_CONTROL_REG |
||||
mov r1,#0 |
||||
orr r1, r1, #0x0001 /* M_PCM_SYNC */ |
||||
orr r1, r1, #0x4000 /* IPC_ACTIVE */ |
||||
strh r1,[r0] |
||||
|
||||
ldr r0, _GPIO_DIR_CONTROL_REG |
||||
mov r1,#0 |
||||
bic r1, r1, #0x0001 /* M_PCM_SYNC */ |
||||
bic r1, r1, #0x4000 /* IPC_ACTIVE */ |
||||
strh r1,[r0] |
||||
|
||||
ldr r0, _GPIO_DATA_OUTPUT_REG |
||||
mov r1,#0 |
||||
bic r1, r1, #0x0001 /* M_PCM_SYNC */ |
||||
orr r1, r1, #0x4000 /* IPC_ACTIVE */ |
||||
strh r1,[r0] |
||||
|
||||
/* Setup some clock domains */ |
||||
ldr r1, =OMAP1510_CLKS |
||||
ldr r0, REG_ARM_IDLECT2 |
||||
strh r1, [r0] /* CLKM, Clock domain control. */ |
||||
|
||||
mov r1, #0x01 /* PER_EN bit */ |
||||
ldr r0, REG_ARM_RSTCT2 |
||||
strh r1, [r0] /* CLKM; Peripheral reset. */
|
||||
|
||||
/* Set CLKM to Sync-Scalable */ |
||||
/* I supposidly need to enable the dsp clock before switching */ |
||||
mov r1, #0x1000 |
||||
ldr r0, REG_ARM_SYSST |
||||
strh r1, [r0] |
||||
mov r0, #0x400 |
||||
1: |
||||
subs r0, r0, #0x1 /* wait for any bubbles to finish */ |
||||
bne 1b |
||||
|
||||
ldr r1, VAL_ARM_CKCTL /* use 12Mhz ref, PER must be <= 50Mhz so /2 */ |
||||
ldr r0, REG_ARM_CKCTL |
||||
strh r1, [r0] |
||||
|
||||
/* setup DPLL 1 */ |
||||
ldr r1, VAL_DPLL1_CTL |
||||
ldr r0, REG_DPLL1_CTL |
||||
strh r1, [r0] |
||||
ands r1, r1, #0x10 /* Check if PLL is enabled. */ |
||||
beq lock_end /* Do not look for lock if BYPASS selected */ |
||||
2: |
||||
ldrh r1, [r0] |
||||
ands r1, r1, #0x01 /* Check the LOCK bit. */ |
||||
beq 2b /* ...loop until bit goes hi. */ |
||||
lock_end: |
||||
|
||||
/* Set memory timings corresponding to the new clock speed */ |
||||
|
||||
/* Check execution location to determine current execution location |
||||
* and branch to appropriate initialization code. |
||||
*/ |
||||
mov r0, #0x10000000 /* Load physical SDRAM base. */ |
||||
mov r1, pc /* Get current execution location. */ |
||||
cmp r1, r0 /* Compare. */ |
||||
bge skip_sdram /* Skip over EMIF-fast initialization if running from SDRAM. */ |
||||
|
||||
/* |
||||
* Delay for SDRAM initialization. |
||||
*/ |
||||
mov r3, #0x1800 /* value should be checked */ |
||||
3: |
||||
subs r3, r3, #0x1 /* Decrement count */ |
||||
bne 3b |
||||
|
||||
/* |
||||
* Set SDRAM control values. Disable refresh before MRS command. |
||||
*/ |
||||
ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG /* get good value */ |
||||
bic r3, r0, #0xC /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */ |
||||
orr r3, r3, #0x8000000 /* (BIT27) Disable CLK when Power down or Self-Refresh */ |
||||
orr r3, r3, #0x4000000 /* BIT26 Power Down Enable */ |
||||
ldr r2, REG_TC_EMIFF_SDRAM_CONFIG /* Point to configuration register. */ |
||||
str r3, [r2] /* Store the passed value with AR disabled. */ |
||||
|
||||
ldr r1, VAL_TC_EMIFF_MRS /* get MRS value */ |
||||
ldr r2, REG_TC_EMIFF_MRS /* Point to MRS register. */ |
||||
str r1, [r2] /* Store the passed value.*/ |
||||
|
||||
ldr r2, REG_TC_EMIFF_SDRAM_CONFIG /* Point to configuration register. */ |
||||
str r0, [r2] /* Store the passed value. */ |
||||
|
||||
/* |
||||
* Delay for SDRAM initialization. |
||||
*/ |
||||
mov r3, #0x1800 |
||||
4: |
||||
subs r3, r3, #1 /* Decrement count. */ |
||||
bne 4b |
||||
|
||||
skip_sdram: |
||||
|
||||
/* slow interface */ |
||||
ldr r1, VAL_TC_EMIFS_CS0_CONFIG |
||||
ldr r0, REG_TC_EMIFS_CS0_CONFIG |
||||
str r1, [r0] /* Chip Select 0 */ |
||||
ldr r1, VAL_TC_EMIFS_CS1_CONFIG |
||||
ldr r0, REG_TC_EMIFS_CS1_CONFIG |
||||
str r1, [r0] /* Chip Select 1 */ |
||||
ldr r1, VAL_TC_EMIFS_CS2_CONFIG |
||||
ldr r0, REG_TC_EMIFS_CS2_CONFIG |
||||
str r1, [r0] /* Chip Select 2 */ |
||||
ldr r1, VAL_TC_EMIFS_CS3_CONFIG |
||||
ldr r0, REG_TC_EMIFS_CS3_CONFIG |
||||
str r1, [r0] /* Chip Select 3 */ |
||||
|
||||
/* back to arch calling code */ |
||||
mov pc, lr |
||||
|
||||
/* the literal pools origin */ |
||||
.ltorg |
||||
|
||||
/* OMAP configuration registers */ |
||||
REG_FUNC_MUX_CTRL_0: /* 32 bits */ |
||||
.word 0xfffe1000
|
||||
REG_FUNC_MUX_CTRL_1: /* 32 bits */ |
||||
.word 0xfffe1004
|
||||
REG_FUNC_MUX_CTRL_2: /* 32 bits */ |
||||
.word 0xfffe1008
|
||||
REG_COMP_MODE_CTRL_0: /* 32 bits */ |
||||
.word 0xfffe100c
|
||||
REG_FUNC_MUX_CTRL_3: /* 32 bits */ |
||||
.word 0xfffe1010
|
||||
REG_FUNC_MUX_CTRL_4: /* 32 bits */ |
||||
.word 0xfffe1014
|
||||
REG_FUNC_MUX_CTRL_5: /* 32 bits */ |
||||
.word 0xfffe1018
|
||||
REG_FUNC_MUX_CTRL_6: /* 32 bits */ |
||||
.word 0xfffe101c
|
||||
REG_FUNC_MUX_CTRL_7: /* 32 bits */ |
||||
.word 0xfffe1020
|
||||
REG_FUNC_MUX_CTRL_8: /* 32 bits */ |
||||
.word 0xfffe1024
|
||||
REG_FUNC_MUX_CTRL_9: /* 32 bits */ |
||||
.word 0xfffe1028
|
||||
REG_FUNC_MUX_CTRL_A: /* 32 bits */ |
||||
.word 0xfffe102C
|
||||
REG_FUNC_MUX_CTRL_B: /* 32 bits */ |
||||
.word 0xfffe1030
|
||||
REG_FUNC_MUX_CTRL_C: /* 32 bits */ |
||||
.word 0xfffe1034
|
||||
REG_FUNC_MUX_CTRL_D: /* 32 bits */ |
||||
.word 0xfffe1038
|
||||
REG_PULL_DWN_CTRL_0: /* 32 bits */ |
||||
.word 0xfffe1040
|
||||
REG_PULL_DWN_CTRL_1: /* 32 bits */ |
||||
.word 0xfffe1044
|
||||
REG_PULL_DWN_CTRL_2: /* 32 bits */ |
||||
.word 0xfffe1048
|
||||
REG_PULL_DWN_CTRL_3: /* 32 bits */ |
||||
.word 0xfffe104c
|
||||
REG_VOLTAGE_CTRL_0: /* 32 bits */ |
||||
.word 0xfffe1060
|
||||
REG_TEST_DBG_CTRL_0: /* 32 bits */ |
||||
.word 0xfffe1070
|
||||
REG_MOD_CONF_CTRL_0: /* 32 bits */ |
||||
.word 0xfffe1080
|
||||
REG_TC_IMIF_PRIO: /* 32 bits */ |
||||
.word 0xfffecc00
|
||||
REG_TC_EMIFS_PRIO: /* 32 bits */ |
||||
.word 0xfffecc04
|
||||
REG_TC_EMIFF_PRIO: /* 32 bits */ |
||||
.word 0xfffecc08
|
||||
REG_TC_EMIFS_CONFIG: /* 32 bits */ |
||||
.word 0xfffecc0c
|
||||
REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */ |
||||
.word 0xfffecc10
|
||||
REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */ |
||||
.word 0xfffecc14
|
||||
REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */ |
||||
.word 0xfffecc18
|
||||
REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */ |
||||
.word 0xfffecc1c
|
||||
REG_TC_EMIFF_SDRAM_CONFIG: /* 32 bits */ |
||||
.word 0xfffecc20
|
||||
REG_TC_EMIFF_MRS: /* 32 bits */ |
||||
.word 0xfffecc24
|
||||
/* MPU clock/reset/power mode control registers */ |
||||
REG_ARM_CKCTL: /* 16 bits */ |
||||
.word 0xfffece00
|
||||
REG_ARM_IDLECT2: /* 16 bits */ |
||||
.word 0xfffece08
|
||||
REG_ARM_RSTCT2: /* 16 bits */ |
||||
.word 0xfffece14
|
||||
REG_ARM_SYSST: /* 16 bits */ |
||||
.word 0xfffece18
|
||||
/* DPLL control registers */ |
||||
REG_DPLL1_CTL: /* 16 bits */ |
||||
.word 0xfffecf00
|
||||
/* identification code register */ |
||||
REG_IDCODE: /* 32 bits */ |
||||
.word 0xfffed404
|
||||
|
||||
/* SX1 specific */ |
||||
_GPIO_PIN_CONTROL_REG: |
||||
.word GPIO_PIN_CONTROL_REG
|
||||
_GPIO_DIR_CONTROL_REG: |
||||
.word GPIO_DIR_CONTROL_REG
|
||||
_GPIO_DATA_OUTPUT_REG: |
||||
.word GPIO_DATA_OUTPUT_REG
|
||||
|
||||
VAL_COMP_MODE_CTRL_0: |
||||
.word 0x0000eaef
|
||||
VAL_FUNC_MUX_CTRL_4: |
||||
.word 0x00000000
|
||||
VAL_FUNC_MUX_CTRL_5: |
||||
.word 0x00000000
|
||||
VAL_FUNC_MUX_CTRL_6: |
||||
.word 0x00000001
|
||||
VAL_FUNC_MUX_CTRL_7: |
||||
.word 0x00001000
|
||||
VAL_FUNC_MUX_CTRL_8: |
||||
.word 0x00001240 /*[Knoller] Value of Symbian Image Wing B2*/ |
||||
VAL_FUNC_MUX_CTRL_9: |
||||
.word 0x00201008
|
||||
VAL_FUNC_MUX_CTRL_A: |
||||
.word 0x00001000
|
||||
VAL_FUNC_MUX_CTRL_B: |
||||
.word 0x00000000
|
||||
VAL_FUNC_MUX_CTRL_C: |
||||
.word 0x09008001 /*[Knoller] Value of Symbian Image Wing B2*/ |
||||
VAL_FUNC_MUX_CTRL_D: |
||||
.word 0x00000000
|
||||
VAL_PULL_DWN_CTRL_0: |
||||
.word 0xfffeffff
|
||||
VAL_PULL_DWN_CTRL_1: |
||||
.word 0xd1ffffec
|
||||
VAL_PULL_DWN_CTRL_2: |
||||
.word 0xffa80c5b
|
||||
VAL_PULL_DWN_CTRL_3: |
||||
.word 0xffffc0fe
|
||||
VAL_VOLTAGE_CTRL_0: |
||||
.word 0x00000007
|
||||
VAL_TEST_DBG_CTRL_0: |
||||
/* The OMAP5910 TRM says this register must be 0, but HelenConfRegs |
||||
* says to write a 7. Don't know what the right thing is to do, so |
||||
* I'm leaving it at 7 since that's what was already here. |
||||
*/ |
||||
.word 0x00000007
|
||||
VAL_MOD_CONF_CTRL_0: |
||||
.word 0x0da20000 /*[Knoller] Value of Symbian Image Wing B2*/ |
||||
|
||||
VAL_ARM_CKCTL: |
||||
.word 0x010D
|
||||
|
||||
VAL_DPLL1_CTL: |
||||
.word 0x3A33 /*[Hertle] Value of Symbian Image*/ |
||||
|
||||
VAL_TC_EMIFS_CS1_CONFIG_PRELIM: |
||||
.word 0x00001149
|
||||
|
||||
VAL_TC_EMIFS_CS2_CONFIG_PRELIM: |
||||
.word 0x00004158
|
||||
|
||||
VAL_TC_EMIFS_CS0_CONFIG: |
||||
.word 0x00213090 /*[Knoller] Value of Symbian Image Wing B2*/ |
||||
|
||||
VAL_TC_EMIFS_CS1_CONFIG: |
||||
.word 0x00215070 /*[Knoller] Value of Symbian Image Wing B2*/ |
||||
|
||||
VAL_TC_EMIFS_CS2_CONFIG: |
||||
.word 0x00001139 /*[Knoller] Value of Symbian Image Wing B2*/ |
||||
|
||||
VAL_TC_EMIFS_CS3_CONFIG: |
||||
.word 0x00001139 /*[Knoller] Value of Symbian Image Wing B2*/ |
||||
|
||||
VAL_TC_EMIFF_SDRAM_CONFIG: |
||||
.word 0x0105f0b4 /*[Knoller] Value of Symbian Image Wing B2*/ |
||||
|
||||
|
||||
VAL_TC_EMIFF_MRS: |
||||
.word 0x00000027 /*[Knoller] Value of Symbian Image Wing B2*/ |
||||
@ -1,123 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2004 |
||||
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
||||
* |
||||
* (C) Copyright 2003 |
||||
* Texas Instruments, <www.ti.com> |
||||
* Kshitij Gupta <Kshitij@ti.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
static void flash__init (void); |
||||
static void ether__init (void); |
||||
|
||||
static inline void delay (unsigned long loops) |
||||
{ |
||||
__asm__ volatile ("1:\n" |
||||
"subs %0, %1, #1\n" |
||||
"bne 1b":"=r" (loops):"0" (loops)); |
||||
} |
||||
|
||||
/*
|
||||
* Miscellaneous platform dependent initialisations |
||||
*/ |
||||
|
||||
int board_init (void) |
||||
{ |
||||
/* arch number of SX1 Board */ |
||||
gd->bd->bi_arch_number = MACH_TYPE_SX1; |
||||
|
||||
/* adress of boot parameters */ |
||||
gd->bd->bi_boot_params = 0x10000100; |
||||
|
||||
/* kk - this speeds up your boot a quite a bit. However to make it
|
||||
* work, you need make sure your kernel startup flush bug is fixed. |
||||
* ... rkw ... |
||||
*/ |
||||
icache_enable (); |
||||
|
||||
flash__init (); |
||||
ether__init (); |
||||
return 0; |
||||
} |
||||
|
||||
|
||||
int misc_init_r (void) |
||||
{ |
||||
/* volatile ushort *gdir = (ushort *) (GPIO_DIR_CONTROL_REG); */ |
||||
/* volatile ushort *mdir = (ushort *) (MPUIO_DIR_CONTROL_REG); */ |
||||
|
||||
/* setup gpio direction to match board (no floats!) */ |
||||
/**gdir = 0xCFF9; */ |
||||
/**mdir = 0x103F; */ |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
/******************************
|
||||
Routine: |
||||
Description: |
||||
******************************/ |
||||
static void flash__init (void) |
||||
{ |
||||
#define CS0_CHIP_SELECT_REG 0xfffecc10 |
||||
#define CS3_CHIP_SELECT_REG 0xfffecc1c |
||||
#define EMIFS_GlB_Config_REG 0xfffecc0c |
||||
|
||||
unsigned int regval; |
||||
|
||||
regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG); |
||||
regval = regval | 0x0001; /* Turn off write protection for flash devices. */ |
||||
if (regval & 0x0002) { |
||||
regval = regval & 0xfffd; /* Swap CS0 and CS3 so that flash is visible at 0x0 and eeprom at 0x0c000000. */ |
||||
/* If, instead, you want to reference flash at 0x0c000000, then it seemed the following were necessary. */ |
||||
/* *((volatile unsigned int *)CS0_CHIP_SELECT_REG) = 0x202090; / * Overrides head.S setting of 0x212090 */ |
||||
/* *((volatile unsigned int *)CS3_CHIP_SELECT_REG) = 0x202090; / * Let's flash chips be fully functional. */ |
||||
} |
||||
*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval; |
||||
} |
||||
|
||||
|
||||
/******************************
|
||||
Routine: |
||||
Description: |
||||
******************************/ |
||||
static void ether__init (void) |
||||
{ |
||||
#define ETH_CONTROL_REG 0x0800000b |
||||
/* take the Ethernet controller out of reset and wait
|
||||
* for the EEPROM load to complete. |
||||
*/ |
||||
*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; |
||||
udelay (3); |
||||
} |
||||
|
||||
|
||||
int dram_init (void) |
||||
{ |
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,376 @@ |
||||
/*
|
||||
* board.c |
||||
* |
||||
* Board functions for TI AM335X based boards |
||||
* |
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <errno.h> |
||||
#include <spl.h> |
||||
#include <asm/arch/cpu.h> |
||||
#include <asm/arch/hardware.h> |
||||
#include <asm/arch/omap.h> |
||||
#include <asm/arch/ddr_defs.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/gpio.h> |
||||
#include <asm/arch/mmc_host_def.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <asm/io.h> |
||||
#include <asm/emif.h> |
||||
#include <asm/gpio.h> |
||||
#include <i2c.h> |
||||
#include <miiphy.h> |
||||
#include <cpsw.h> |
||||
#include "board.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; |
||||
#ifdef CONFIG_SPL_BUILD |
||||
static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; |
||||
#endif |
||||
|
||||
/* MII mode defines */ |
||||
#define MII_MODE_ENABLE 0x0 |
||||
#define RGMII_MODE_ENABLE 0xA |
||||
|
||||
/* GPIO that controls power to DDR on EVM-SK */ |
||||
#define GPIO_DDR_VTT_EN 7 |
||||
|
||||
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; |
||||
|
||||
static struct am335x_baseboard_id __attribute__((section (".data"))) header; |
||||
|
||||
static inline int board_is_bone(void) |
||||
{ |
||||
return !strncmp(header.name, "A335BONE", HDR_NAME_LEN); |
||||
} |
||||
|
||||
static inline int board_is_bone_lt(void) |
||||
{ |
||||
return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN); |
||||
} |
||||
|
||||
static inline int board_is_evm_sk(void) |
||||
{ |
||||
return !strncmp("A335X_SK", header.name, HDR_NAME_LEN); |
||||
} |
||||
|
||||
/*
|
||||
* Read header information from EEPROM into global structure. |
||||
*/ |
||||
static int read_eeprom(void) |
||||
{ |
||||
/* Check if baseboard eeprom is available */ |
||||
if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { |
||||
puts("Could not probe the EEPROM; something fundamentally " |
||||
"wrong on the I2C bus.\n"); |
||||
return -ENODEV; |
||||
} |
||||
|
||||
/* read the eeprom using i2c */ |
||||
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header, |
||||
sizeof(header))) { |
||||
puts("Could not read the EEPROM; something fundamentally" |
||||
" wrong on the I2C bus.\n"); |
||||
return -EIO; |
||||
} |
||||
|
||||
if (header.magic != 0xEE3355AA) { |
||||
/*
|
||||
* read the eeprom using i2c again, |
||||
* but use only a 1 byte address |
||||
*/ |
||||
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, |
||||
(uchar *)&header, sizeof(header))) { |
||||
puts("Could not read the EEPROM; something " |
||||
"fundamentally wrong on the I2C bus.\n"); |
||||
return -EIO; |
||||
} |
||||
|
||||
if (header.magic != 0xEE3355AA) { |
||||
printf("Incorrect magic number (0x%x) in EEPROM\n", |
||||
header.magic); |
||||
return -EINVAL; |
||||
} |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/* UART Defines */ |
||||
#ifdef CONFIG_SPL_BUILD |
||||
#define UART_RESET (0x1 << 1) |
||||
#define UART_CLK_RUNNING_MASK 0x1 |
||||
#define UART_SMART_IDLE_EN (0x1 << 0x3) |
||||
|
||||
static void rtc32k_enable(void) |
||||
{ |
||||
struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE; |
||||
|
||||
/*
|
||||
* Unlock the RTC's registers. For more details please see the |
||||
* RTC_SS section of the TRM. In order to unlock we need to |
||||
* write these specific values (keys) in this order. |
||||
*/ |
||||
writel(0x83e70b13, &rtc->kick0r); |
||||
writel(0x95a4f1e0, &rtc->kick1r); |
||||
|
||||
/* Enable the RTC 32K OSC by setting bits 3 and 6. */ |
||||
writel((1 << 3) | (1 << 6), &rtc->osc); |
||||
} |
||||
|
||||
static const struct ddr_data ddr2_data = { |
||||
.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | |
||||
(MT47H128M16RT25E_RD_DQS<<20) | |
||||
(MT47H128M16RT25E_RD_DQS<<10) | |
||||
(MT47H128M16RT25E_RD_DQS<<0)), |
||||
.datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) | |
||||
(MT47H128M16RT25E_WR_DQS<<20) | |
||||
(MT47H128M16RT25E_WR_DQS<<10) | |
||||
(MT47H128M16RT25E_WR_DQS<<0)), |
||||
.datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) | |
||||
(MT47H128M16RT25E_PHY_WRLVL<<20) | |
||||
(MT47H128M16RT25E_PHY_WRLVL<<10) | |
||||
(MT47H128M16RT25E_PHY_WRLVL<<0)), |
||||
.datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) | |
||||
(MT47H128M16RT25E_PHY_GATELVL<<20) | |
||||
(MT47H128M16RT25E_PHY_GATELVL<<10) | |
||||
(MT47H128M16RT25E_PHY_GATELVL<<0)), |
||||
.datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) | |
||||
(MT47H128M16RT25E_PHY_FIFO_WE<<20) | |
||||
(MT47H128M16RT25E_PHY_FIFO_WE<<10) | |
||||
(MT47H128M16RT25E_PHY_FIFO_WE<<0)), |
||||
.datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) | |
||||
(MT47H128M16RT25E_PHY_WR_DATA<<20) | |
||||
(MT47H128M16RT25E_PHY_WR_DATA<<10) | |
||||
(MT47H128M16RT25E_PHY_WR_DATA<<0)), |
||||
.datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY, |
||||
.datadldiff0 = PHY_DLL_LOCK_DIFF, |
||||
}; |
||||
|
||||
static const struct cmd_control ddr2_cmd_ctrl_data = { |
||||
.cmd0csratio = MT47H128M16RT25E_RATIO, |
||||
.cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, |
||||
.cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT, |
||||
|
||||
.cmd1csratio = MT47H128M16RT25E_RATIO, |
||||
.cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, |
||||
.cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT, |
||||
|
||||
.cmd2csratio = MT47H128M16RT25E_RATIO, |
||||
.cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, |
||||
.cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT, |
||||
}; |
||||
|
||||
static const struct emif_regs ddr2_emif_reg_data = { |
||||
.sdram_config = MT47H128M16RT25E_EMIF_SDCFG, |
||||
.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, |
||||
.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, |
||||
.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, |
||||
.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, |
||||
.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, |
||||
}; |
||||
|
||||
static const struct ddr_data ddr3_data = { |
||||
.datardsratio0 = MT41J128MJT125_RD_DQS, |
||||
.datawdsratio0 = MT41J128MJT125_WR_DQS, |
||||
.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, |
||||
.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, |
||||
.datadldiff0 = PHY_DLL_LOCK_DIFF, |
||||
}; |
||||
|
||||
static const struct cmd_control ddr3_cmd_ctrl_data = { |
||||
.cmd0csratio = MT41J128MJT125_RATIO, |
||||
.cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF, |
||||
.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, |
||||
|
||||
.cmd1csratio = MT41J128MJT125_RATIO, |
||||
.cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF, |
||||
.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, |
||||
|
||||
.cmd2csratio = MT41J128MJT125_RATIO, |
||||
.cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF, |
||||
.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, |
||||
}; |
||||
|
||||
static struct emif_regs ddr3_emif_reg_data = { |
||||
.sdram_config = MT41J128MJT125_EMIF_SDCFG, |
||||
.ref_ctrl = MT41J128MJT125_EMIF_SDREF, |
||||
.sdram_tim1 = MT41J128MJT125_EMIF_TIM1, |
||||
.sdram_tim2 = MT41J128MJT125_EMIF_TIM2, |
||||
.sdram_tim3 = MT41J128MJT125_EMIF_TIM3, |
||||
.zq_config = MT41J128MJT125_ZQ_CFG, |
||||
.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY, |
||||
}; |
||||
#endif |
||||
|
||||
/*
|
||||
* early system init of muxing and clocks. |
||||
*/ |
||||
void s_init(void) |
||||
{ |
||||
/* WDT1 is already running when the bootloader gets control
|
||||
* Disable it to avoid "random" resets |
||||
*/ |
||||
writel(0xAAAA, &wdtimer->wdtwspr); |
||||
while (readl(&wdtimer->wdtwwps) != 0x0) |
||||
; |
||||
writel(0x5555, &wdtimer->wdtwspr); |
||||
while (readl(&wdtimer->wdtwwps) != 0x0) |
||||
; |
||||
|
||||
#ifdef CONFIG_SPL_BUILD |
||||
/* Setup the PLLs and the clocks for the peripherals */ |
||||
pll_init(); |
||||
|
||||
/* Enable RTC32K clock */ |
||||
rtc32k_enable(); |
||||
|
||||
/* UART softreset */ |
||||
u32 regVal; |
||||
|
||||
enable_uart0_pin_mux(); |
||||
|
||||
regVal = readl(&uart_base->uartsyscfg); |
||||
regVal |= UART_RESET; |
||||
writel(regVal, &uart_base->uartsyscfg); |
||||
while ((readl(&uart_base->uartsyssts) & |
||||
UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) |
||||
; |
||||
|
||||
/* Disable smart idle */ |
||||
regVal = readl(&uart_base->uartsyscfg); |
||||
regVal |= UART_SMART_IDLE_EN; |
||||
writel(regVal, &uart_base->uartsyscfg); |
||||
|
||||
gd = &gdata; |
||||
|
||||
preloader_console_init(); |
||||
|
||||
/* Initalize the board header */ |
||||
enable_i2c0_pin_mux(); |
||||
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
||||
if (read_eeprom() < 0) |
||||
puts("Could not get board ID.\n"); |
||||
|
||||
enable_board_pin_mux(&header); |
||||
if (board_is_evm_sk()) { |
||||
/*
|
||||
* EVM SK 1.2A and later use gpio0_7 to enable DDR3. |
||||
* This is safe enough to do on older revs. |
||||
*/ |
||||
gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); |
||||
gpio_direction_output(GPIO_DDR_VTT_EN, 1); |
||||
} |
||||
|
||||
if (board_is_evm_sk() || board_is_bone_lt()) |
||||
config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, |
||||
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data); |
||||
else |
||||
config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data, |
||||
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data); |
||||
#endif |
||||
} |
||||
|
||||
/*
|
||||
* Basic board specific setup. Pinmux has been handled already. |
||||
*/ |
||||
int board_init(void) |
||||
{ |
||||
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
||||
if (read_eeprom() < 0) |
||||
puts("Could not get board ID.\n"); |
||||
|
||||
gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_DRIVER_TI_CPSW |
||||
static void cpsw_control(int enabled) |
||||
{ |
||||
/* VTP can be added here */ |
||||
|
||||
return; |
||||
} |
||||
|
||||
static struct cpsw_slave_data cpsw_slaves[] = { |
||||
{ |
||||
.slave_reg_ofs = 0x208, |
||||
.sliver_reg_ofs = 0xd80, |
||||
.phy_id = 0, |
||||
}, |
||||
{ |
||||
.slave_reg_ofs = 0x308, |
||||
.sliver_reg_ofs = 0xdc0, |
||||
.phy_id = 1, |
||||
}, |
||||
}; |
||||
|
||||
static struct cpsw_platform_data cpsw_data = { |
||||
.mdio_base = AM335X_CPSW_MDIO_BASE, |
||||
.cpsw_base = AM335X_CPSW_BASE, |
||||
.mdio_div = 0xff, |
||||
.channels = 8, |
||||
.cpdma_reg_ofs = 0x800, |
||||
.slaves = 1, |
||||
.slave_data = cpsw_slaves, |
||||
.ale_reg_ofs = 0xd00, |
||||
.ale_entries = 1024, |
||||
.host_port_reg_ofs = 0x108, |
||||
.hw_stats_reg_ofs = 0x900, |
||||
.mac_control = (1 << 5), |
||||
.control = cpsw_control, |
||||
.host_port_num = 0, |
||||
.version = CPSW_CTRL_VERSION_2, |
||||
}; |
||||
|
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
uint8_t mac_addr[6]; |
||||
uint32_t mac_hi, mac_lo; |
||||
|
||||
if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { |
||||
debug("<ethaddr> not set. Reading from E-fuse\n"); |
||||
/* try reading mac address from efuse */ |
||||
mac_lo = readl(&cdev->macid0l); |
||||
mac_hi = readl(&cdev->macid0h); |
||||
mac_addr[0] = mac_hi & 0xFF; |
||||
mac_addr[1] = (mac_hi & 0xFF00) >> 8; |
||||
mac_addr[2] = (mac_hi & 0xFF0000) >> 16; |
||||
mac_addr[3] = (mac_hi & 0xFF000000) >> 24; |
||||
mac_addr[4] = mac_lo & 0xFF; |
||||
mac_addr[5] = (mac_lo & 0xFF00) >> 8; |
||||
|
||||
if (is_valid_ether_addr(mac_addr)) |
||||
eth_setenv_enetaddr("ethaddr", mac_addr); |
||||
else |
||||
return -1; |
||||
} |
||||
|
||||
if (board_is_bone() || board_is_bone_lt()) { |
||||
writel(MII_MODE_ENABLE, &cdev->miisel); |
||||
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = |
||||
PHY_INTERFACE_MODE_MII; |
||||
} else { |
||||
writel(RGMII_MODE_ENABLE, &cdev->miisel); |
||||
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = |
||||
PHY_INTERFACE_MODE_RGMII; |
||||
} |
||||
|
||||
return cpsw_register(&cpsw_data); |
||||
} |
||||
#endif |
||||
@ -0,0 +1,49 @@ |
||||
/*
|
||||
* board.h |
||||
* |
||||
* TI AM335x boards information header |
||||
* |
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
*/ |
||||
|
||||
#ifndef _BOARD_H_ |
||||
#define _BOARD_H_ |
||||
|
||||
/*
|
||||
* TI AM335x parts define a system EEPROM that defines certain sub-fields. |
||||
* We use these fields to in turn see what board we are on, and what |
||||
* that might require us to set or not set. |
||||
*/ |
||||
#define HDR_NO_OF_MAC_ADDR 3 |
||||
#define HDR_ETH_ALEN 6 |
||||
#define HDR_NAME_LEN 8 |
||||
|
||||
struct am335x_baseboard_id { |
||||
unsigned int magic; |
||||
char name[HDR_NAME_LEN]; |
||||
char version[4]; |
||||
char serial[12]; |
||||
char config[32]; |
||||
char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN]; |
||||
}; |
||||
|
||||
/*
|
||||
* We have three pin mux functions that must exist. We must be able to enable |
||||
* uart0, for initial output and i2c0 to read the main EEPROM. We then have a |
||||
* main pinmux function that can be overridden to enable all other pinmux that |
||||
* is required on the board. |
||||
*/ |
||||
void enable_uart0_pin_mux(void); |
||||
void enable_i2c0_pin_mux(void); |
||||
void enable_board_pin_mux(struct am335x_baseboard_id *header); |
||||
#endif |
||||
@ -1,352 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2004 IMMS gGmbH <www.imms.de> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
* author(s): Thomas Elste, <info@elste.org> |
||||
* (some parts derived from uCLinux Netarm Ethernet Driver) |
||||
*/ |
||||
|
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <net.h> |
||||
#include "netarm_eth.h" |
||||
#include <asm/arch/netarm_registers.h> |
||||
|
||||
static int na_mii_poll_busy (void); |
||||
|
||||
static void na_get_mac_addr (void) |
||||
{ |
||||
unsigned short p[3]; |
||||
char *m_addr; |
||||
char ethaddr[20]; |
||||
|
||||
m_addr = (char *) p; |
||||
|
||||
p[0] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_1); |
||||
p[1] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_2); |
||||
p[2] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_3); |
||||
|
||||
sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", |
||||
m_addr[0], m_addr[1], |
||||
m_addr[2], m_addr[3], m_addr[4], m_addr[5]); |
||||
|
||||
printf ("HW-MAC Address: %s\n", ethaddr); |
||||
|
||||
/* set env, todo: check if already an adress is set */ |
||||
setenv ("ethaddr", ethaddr); |
||||
} |
||||
|
||||
static void na_mii_write (int reg, int value) |
||||
{ |
||||
int mii_addr; |
||||
|
||||
/* Select register */ |
||||
mii_addr = CONFIG_SYS_ETH_PHY_ADDR + reg; |
||||
SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr); |
||||
/* Write value */ |
||||
SET_EADDR (NETARM_ETH_MII_WRITE, value); |
||||
na_mii_poll_busy (); |
||||
} |
||||
|
||||
static unsigned int na_mii_read (int reg) |
||||
{ |
||||
int mii_addr, val; |
||||
|
||||
/* Select register */ |
||||
mii_addr = CONFIG_SYS_ETH_PHY_ADDR + reg; |
||||
SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr); |
||||
/* do one management cycle */ |
||||
SET_EADDR (NETARM_ETH_MII_CMD, |
||||
GET_EADDR (NETARM_ETH_MII_CMD) | NETARM_ETH_MIIC_RSTAT); |
||||
na_mii_poll_busy (); |
||||
/* Return read value */ |
||||
val = GET_EADDR (NETARM_ETH_MII_READ); |
||||
return val; |
||||
} |
||||
|
||||
static int na_mii_poll_busy (void) |
||||
{ |
||||
ulong start; |
||||
/* arm simple, non interrupt dependent timer */ |
||||
start = get_timer(0)); |
||||
while (get_timer(start) < NA_MII_POLL_BUSY_DELAY) { |
||||
if (!(GET_EADDR (NETARM_ETH_MII_IND) & NETARM_ETH_MIII_BUSY)) { |
||||
return 1; |
||||
} |
||||
} |
||||
printf ("na_mii_busy timeout\n"); |
||||
return (0); |
||||
} |
||||
|
||||
static int na_mii_identify_phy (void) |
||||
{ |
||||
int id_reg_a = 0; |
||||
|
||||
/* get phy id register */ |
||||
id_reg_a = na_mii_read (MII_PHY_ID); |
||||
|
||||
if (id_reg_a == 0x0043) { |
||||
/* This must be an Enable or a Lucent LU3X31 PHY chip */ |
||||
return 1; |
||||
} else if (id_reg_a == 0x0013) { |
||||
/* it is an Intel LXT971A */ |
||||
return 1; |
||||
} |
||||
return (0); |
||||
} |
||||
|
||||
static int na_mii_negotiate (void) |
||||
{ |
||||
int i = 0; |
||||
|
||||
/* Enable auto-negotiation */ |
||||
na_mii_write (MII_PHY_AUTONEGADV, 0x01e1); |
||||
/* FIXME: 0x01E1 is 100Mb half and full duplex, 0x0061 is 10Mb only */ |
||||
/* Restart auto-negotiation */ |
||||
na_mii_write (MII_PHY_CONTROL, 0x1200); |
||||
|
||||
/* status register is 0xffff after setting the autoneg restart bit */ |
||||
while (na_mii_read (MII_PHY_STATUS) == 0xffff) { |
||||
i++; |
||||
} |
||||
|
||||
/* na_mii_read uses the timer already, so we can't use it again for
|
||||
timeout checking. |
||||
Instead we just try some times. |
||||
*/ |
||||
for (i = 0; i < 40000; i++) { |
||||
if ((na_mii_read (MII_PHY_STATUS) & 0x0024) == 0x0024) { |
||||
return 0; |
||||
} |
||||
} |
||||
/*
|
||||
printf("*Warning* autonegotiation timeout, status: 0x%x\n",na_mii_read(MII_PHY_STATUS)); |
||||
*/ |
||||
return (1); |
||||
} |
||||
|
||||
static unsigned int na_mii_check_speed (void) |
||||
{ |
||||
unsigned int status; |
||||
|
||||
/* Read Status register */ |
||||
status = na_mii_read (MII_PHY_STATUS); |
||||
/* Check link status. If 0, default to 100 Mbps. */ |
||||
if ((status & 0x0004) == 0) { |
||||
printf ("*Warning* no link detected, set default speed to 100Mbs\n"); |
||||
return 1; |
||||
} else { |
||||
if ((na_mii_read (17) & 0x4000) != 0) { |
||||
printf ("100Mbs link detected\n"); |
||||
return 1; |
||||
} else { |
||||
printf ("10Mbs link detected\n"); |
||||
return 0; |
||||
} |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
static int reset_eth (void) |
||||
{ |
||||
int pt; |
||||
ulong start; |
||||
|
||||
na_get_mac_addr (); |
||||
pt = na_mii_identify_phy (); |
||||
|
||||
/* reset the phy */ |
||||
na_mii_write (MII_PHY_CONTROL, 0x8000); |
||||
start = get_timer(0); |
||||
while (get_timer(start) < NA_MII_NEGOTIATE_DELAY) { |
||||
if ((na_mii_read (MII_PHY_STATUS) & 0x8000) == 0) { |
||||
break; |
||||
} |
||||
} |
||||
if (get_timer(start) >= NA_MII_NEGOTIATE_DELAY) |
||||
printf ("phy reset timeout\n"); |
||||
|
||||
/* set the PCS reg */ |
||||
SET_EADDR (NETARM_ETH_PCS_CFG, NETARM_ETH_PCSC_CLKS_25M | |
||||
NETARM_ETH_PCSC_ENJAB | NETARM_ETH_PCSC_NOCFR); |
||||
|
||||
na_mii_negotiate (); |
||||
na_mii_check_speed (); |
||||
|
||||
/* Delay 10 millisecond. (Maybe this should be 1 second.) */ |
||||
udelay (10000); |
||||
|
||||
/* Turn receive on.
|
||||
Enable statistics register autozero on read. |
||||
Do not insert MAC address on transmit. |
||||
Do not enable special test modes. */ |
||||
SET_EADDR (NETARM_ETH_STL_CFG, |
||||
(NETARM_ETH_STLC_AUTOZ | NETARM_ETH_STLC_RXEN)); |
||||
|
||||
/* Set the inter-packet gap delay to 0.96us for MII.
|
||||
The NET+ARM H/W Reference Guide indicates that the Back-to-back IPG |
||||
Gap Timer Register should be set to 0x15 and the Non Back-to-back IPG |
||||
Gap Timer Register should be set to 0x00000C12 for the MII PHY. */ |
||||
SET_EADDR (NETARM_ETH_B2B_IPG_GAP_TMR, 0x15); |
||||
SET_EADDR (NETARM_ETH_NB2B_IPG_GAP_TMR, 0x00000C12); |
||||
|
||||
/* Add CRC to end of packets.
|
||||
Pad packets to minimum length of 64 bytes. |
||||
Allow unlimited length transmit packets. |
||||
Receive all broadcast packets. |
||||
NOTE: Multicast addressing is NOT enabled here currently. */ |
||||
SET_EADDR (NETARM_ETH_MAC_CFG, |
||||
(NETARM_ETH_MACC_CRCEN | |
||||
NETARM_ETH_MACC_PADEN | NETARM_ETH_MACC_HUGEN)); |
||||
SET_EADDR (NETARM_ETH_SAL_FILTER, NETARM_ETH_SALF_BROAD); |
||||
|
||||
/* enable fifos */ |
||||
SET_EADDR (NETARM_ETH_GEN_CTRL, |
||||
(NETARM_ETH_GCR_ERX | NETARM_ETH_GCR_ETX)); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
|
||||
extern int eth_init (bd_t * bd) |
||||
{ |
||||
reset_eth (); |
||||
return 0; |
||||
} |
||||
|
||||
extern void eth_halt (void) |
||||
{ |
||||
SET_EADDR (NETARM_ETH_GEN_CTRL, 0); |
||||
} |
||||
|
||||
/* Get a data block via Ethernet */ |
||||
extern int eth_rx (void) |
||||
{ |
||||
int i; |
||||
unsigned short rxlen; |
||||
unsigned int *addr; |
||||
unsigned int rxstatus, lastrxlen; |
||||
char *pa; |
||||
|
||||
/* RXBR is 1, data block was received */ |
||||
if ((GET_EADDR (NETARM_ETH_GEN_STAT) & NETARM_ETH_GST_RXBR) == 0) |
||||
return 0; |
||||
|
||||
/* get status register and the length of received block */ |
||||
rxstatus = GET_EADDR (NETARM_ETH_RX_STAT); |
||||
rxlen = (rxstatus & NETARM_ETH_RXSTAT_SIZE) >> 16; |
||||
|
||||
if (rxlen == 0) |
||||
return 0; |
||||
|
||||
/* clear RXBR to make fifo available */ |
||||
SET_EADDR (NETARM_ETH_GEN_STAT, |
||||
GET_EADDR (NETARM_ETH_GEN_STAT) & ~NETARM_ETH_GST_RXBR); |
||||
|
||||
/* clear TXBC to make fifo available */ |
||||
/* According to NETARM50 data manual you just have to clear
|
||||
RXBR but that has no effect. Only after clearing TXBC the |
||||
Fifo becomes readable. */ |
||||
SET_EADDR (NETARM_ETH_GEN_STAT, |
||||
GET_EADDR (NETARM_ETH_GEN_STAT) & ~NETARM_ETH_GST_TXBC); |
||||
|
||||
addr = (unsigned int *) NetRxPackets[0]; |
||||
pa = (char *) NetRxPackets[0]; |
||||
|
||||
/* read the fifo */ |
||||
for (i = 0; i < rxlen / 4; i++) { |
||||
*addr = GET_EADDR (NETARM_ETH_FIFO_DAT1); |
||||
addr++; |
||||
} |
||||
|
||||
if (GET_EADDR (NETARM_ETH_GEN_STAT) & NETARM_ETH_GST_RXREGR) { |
||||
/* RXFDB indicates wether the last word is 1,2,3 or 4 bytes long */ |
||||
lastrxlen = |
||||
(GET_EADDR (NETARM_ETH_GEN_STAT) & |
||||
NETARM_ETH_GST_RXFDB) >> 28; |
||||
*addr = GET_EADDR (NETARM_ETH_FIFO_DAT1); |
||||
switch (lastrxlen) { |
||||
case 1: |
||||
*addr &= 0xff000000; |
||||
break; |
||||
case 2: |
||||
*addr &= 0xffff0000; |
||||
break; |
||||
case 3: |
||||
*addr &= 0xffffff00; |
||||
break; |
||||
} |
||||
} |
||||
|
||||
/* Pass the packet up to the protocol layers. */ |
||||
NetReceive (NetRxPackets[0], rxlen); |
||||
|
||||
return rxlen; |
||||
} |
||||
|
||||
/* Send a data block via Ethernet. */ |
||||
extern int eth_send(void *packet, int length) |
||||
{ |
||||
int i, length32; |
||||
char *pa; |
||||
unsigned int *pa32, lastp = 0, rest; |
||||
|
||||
pa = (char *) packet; |
||||
pa32 = (unsigned int *) packet; |
||||
length32 = length / 4; |
||||
rest = length % 4; |
||||
|
||||
/* make sure there's no garbage in the last word */ |
||||
switch (rest) { |
||||
case 0: |
||||
lastp = pa32[length32]; |
||||
length32--; |
||||
break; |
||||
case 1: |
||||
lastp = pa32[length32] & 0x000000ff; |
||||
break; |
||||
case 2: |
||||
lastp = pa32[length32] & 0x0000ffff; |
||||
break; |
||||
case 3: |
||||
lastp = pa32[length32] & 0x00ffffff; |
||||
break; |
||||
} |
||||
|
||||
/* write to the fifo */ |
||||
for (i = 0; i < length32; i++) |
||||
SET_EADDR (NETARM_ETH_FIFO_DAT1, pa32[i]); |
||||
|
||||
/* the last word is written to an extra register, this
|
||||
starts the transmission */ |
||||
SET_EADDR (NETARM_ETH_FIFO_DAT2, lastp); |
||||
|
||||
/* NETARM_ETH_TXSTAT_TXOK should be checked, to know if the transmission
|
||||
went fine. But we can't use the timer for a timeout loop because |
||||
of it is used already in upper layers. So we just try some times. */ |
||||
i = 0; |
||||
while (i < 50000) { |
||||
if ((GET_EADDR (NETARM_ETH_TX_STAT) & NETARM_ETH_TXSTAT_TXOK) |
||||
== NETARM_ETH_TXSTAT_TXOK) |
||||
return 0; |
||||
i++; |
||||
} |
||||
|
||||
printf ("eth_send timeout\n"); |
||||
return 1; |
||||
} |
||||
@ -1,42 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2003 IMMS gGmbH <www.imms.de> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
* author(s): Thomas Elste, <info@elste.org> |
||||
*/ |
||||
|
||||
#include <asm/types.h> |
||||
#include <config.h> |
||||
|
||||
#ifdef CONFIG_DRIVER_NETARMETH |
||||
|
||||
#define SET_EADDR(ad,val) *(volatile unsigned int*)(ad + NETARM_ETH_MODULE_BASE) = val |
||||
#define GET_EADDR(ad) (*(volatile unsigned int*)(ad + NETARM_ETH_MODULE_BASE)) |
||||
|
||||
#define NA_MII_POLL_BUSY_DELAY 900 |
||||
|
||||
/* MII negotiation timeout value
|
||||
500 jiffies = 5 seconds */ |
||||
#define NA_MII_NEGOTIATE_DELAY 30 |
||||
|
||||
/* Registers in the physical layer chip */ |
||||
#define MII_PHY_CONTROL 0 |
||||
#define MII_PHY_STATUS 1 |
||||
#define MII_PHY_ID 2 |
||||
#define MII_PHY_AUTONEGADV 4 |
||||
|
||||
#endif /* CONFIG_DRIVER_NETARMETH */ |
||||
@ -1,231 +0,0 @@ |
||||
/*
|
||||
* Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
|
||||
* Curt Brune <curt@cucy.com> |
||||
* |
||||
* (C) Copyright 2004 |
||||
* DAVE Srl |
||||
* http://www.dave-tech.it
|
||||
* http://www.wawnet.biz
|
||||
* mailto:info@wawnet.biz |
||||
* |
||||
* (C) Copyright 2002-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Alex Zuepke <azu@sysgo.de> |
||||
* |
||||
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
||||
* |
||||
* MODULE: $Id:$ |
||||
* Description: UART/Serial interface for Samsung S3C4510B SoC |
||||
* Runtime Env: ARM7TDMI |
||||
* Change History: |
||||
* 03-02-04 Create (Curt Brune) curt@cucy.com |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
#include <asm/hardware.h> |
||||
#include "s3c4510b_uart.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
static UART *uart; |
||||
|
||||
/* flush serial input queue. returns 0 on success or negative error
|
||||
* number otherwise |
||||
*/ |
||||
static int serial_flush_input(void) |
||||
{ |
||||
volatile u32 tmp; |
||||
|
||||
/* keep on reading as long as the receiver is not empty */ |
||||
while( uart->m_stat.bf.rxReady) { |
||||
tmp = uart->m_rx; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
|
||||
/* flush output queue. returns 0 on success or negative error number
|
||||
* otherwise |
||||
*/ |
||||
static int serial_flush_output(void) |
||||
{ |
||||
/* wait until the transmitter is no longer busy */ |
||||
while( !uart->m_stat.bf.txBufEmpty); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
|
||||
static void s3c4510b_serial_setbrg(void) |
||||
{ |
||||
UART_LINE_CTRL ulctrl; |
||||
UART_CTRL uctrl; |
||||
UART_BAUD_DIV ubd; |
||||
|
||||
serial_flush_output(); |
||||
serial_flush_input(); |
||||
|
||||
/* control register */ |
||||
uctrl.ui = 0x0; |
||||
uctrl.bf.rxMode = 0x1; |
||||
uctrl.bf.rxIrq = 0x0; |
||||
uctrl.bf.txMode = 0x1; |
||||
uctrl.bf.DSR = 0x0; |
||||
uctrl.bf.sendBreak = 0x0; |
||||
uctrl.bf.loopBack = 0x0; |
||||
uart->m_ctrl.ui = uctrl.ui; |
||||
|
||||
/* line control register */ |
||||
ulctrl.ui = 0x0; |
||||
ulctrl.bf.wordLen = 0x3; /* 8 bit data */ |
||||
ulctrl.bf.nStop = 0x0; /* 1 stop bit */ |
||||
ulctrl.bf.parity = 0x0; /* no parity */ |
||||
ulctrl.bf.clk = 0x0; /* internal clock */ |
||||
ulctrl.bf.infra_red = 0x0; /* no infra_red */ |
||||
uart->m_lineCtrl.ui = ulctrl.ui; |
||||
|
||||
ubd.ui = 0x0; |
||||
|
||||
/* see table on page 10-15 in SAMSUNG S3C4510B manual */ |
||||
/* get correct divisor */ |
||||
switch(gd->baudrate) { |
||||
case 1200: ubd.bf.cnt0 = 1301; break; |
||||
case 2400: ubd.bf.cnt0 = 650; break; |
||||
case 4800: ubd.bf.cnt0 = 324; break; |
||||
case 9600: ubd.bf.cnt0 = 162; break; |
||||
case 19200: ubd.bf.cnt0 = 80; break; |
||||
case 38400: ubd.bf.cnt0 = 40; break; |
||||
case 57600: ubd.bf.cnt0 = 26; break; |
||||
case 115200: ubd.bf.cnt0 = 13; break; |
||||
} |
||||
|
||||
uart->m_baudDiv.ui = ubd.ui; |
||||
uart->m_baudCnt = 0x0; |
||||
uart->m_baudClk = 0x0; |
||||
|
||||
} |
||||
|
||||
|
||||
/*
|
||||
* Initialise the serial port with the given baudrate. The settings |
||||
* are always 8 data bits, no parity, 1 stop bit, no start bits. |
||||
* |
||||
*/ |
||||
static int s3c4510b_serial_init(void) |
||||
{ |
||||
|
||||
#if CONFIG_SERIAL1 == 1 |
||||
uart = (UART *)UART0_BASE; |
||||
#elif CONFIG_SERIAL1 == 2 |
||||
uart = (UART *)UART1_BASE; |
||||
#else |
||||
#error CONFIG_SERIAL1 not equal to 1 or 2 |
||||
#endif |
||||
|
||||
serial_setbrg (); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
|
||||
/*
|
||||
* Output a single byte to the serial port. |
||||
*/ |
||||
static void s3c4510_serial_putc(const char c) |
||||
{ |
||||
/* wait for room in the transmit FIFO */ |
||||
while( !uart->m_stat.bf.txBufEmpty); |
||||
|
||||
uart->m_tx = c; |
||||
|
||||
/*
|
||||
to be polite with serial console add a line feed |
||||
to the carriage return character |
||||
*/ |
||||
if (c=='\n') |
||||
serial_putc('\r'); |
||||
} |
||||
|
||||
/*
|
||||
* Test if an input byte is ready from the serial port. Returns non-zero on |
||||
* success, 0 otherwise. |
||||
*/ |
||||
static int s3c4510b_serial_tstc(void) |
||||
{ |
||||
return uart->m_stat.bf.rxReady; |
||||
} |
||||
|
||||
/*
|
||||
* Read a single byte from the serial port. Returns 1 on success, 0 |
||||
* otherwise. When the function is succesfull, the character read is |
||||
* written into its argument c. |
||||
*/ |
||||
static int s3c4510b_serial_getc(void) |
||||
{ |
||||
int rv; |
||||
|
||||
for(;;) { |
||||
rv = serial_tstc(); |
||||
|
||||
if (rv) { |
||||
return uart->m_rx & 0xFF; |
||||
} |
||||
} |
||||
} |
||||
|
||||
static void s3c4510b_serial_puts(const char *s) |
||||
{ |
||||
default_serial_puts(s); |
||||
|
||||
/* busy wait for tx complete */ |
||||
while (!uart->m_stat.bf.txComplete); |
||||
|
||||
/* clear break */ |
||||
uart->m_ctrl.bf.sendBreak = 0; |
||||
|
||||
} |
||||
|
||||
static struct serial_device s3c4510b_serial_drv = { |
||||
.name = "s3c4510b_serial", |
||||
.start = s3c4510b_serial_init, |
||||
.stop = NULL, |
||||
.setbrg = s3c4510b_serial_setbrg, |
||||
.putc = s3c4510b_serial_putc, |
||||
.puts = s3c4510b_serial_puts, |
||||
.getc = s3c4510b_serial_getc, |
||||
.tstc = s3c4510b_serial_tstc, |
||||
}; |
||||
|
||||
void s3c4510b_serial_initialize(void) |
||||
{ |
||||
serial_register(&s3c4510b_serial_drv); |
||||
} |
||||
|
||||
__weak struct serial_device *default_serial_console(void) |
||||
{ |
||||
return &s3c4510b_serial_drv; |
||||
} |
||||
@ -1,109 +0,0 @@ |
||||
#ifndef __UART_H |
||||
#define __UART_H |
||||
|
||||
/*
|
||||
* Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
|
||||
* Curt Brune <curt@cucy.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
* Description: S3C4510B UART register layout |
||||
*/ |
||||
|
||||
/* UART LINE CONTROL register */ |
||||
typedef struct __BF_UART_LINE_CTRL { |
||||
u32 wordLen: 2; |
||||
u32 nStop: 1; |
||||
u32 parity: 3; |
||||
u32 clk: 1; |
||||
u32 infra_red: 1; |
||||
u32 unused:24; |
||||
} BF_UART_LINE_CTRL; |
||||
|
||||
typedef union _UART_LINE_CTRL { |
||||
u32 ui; |
||||
BF_UART_LINE_CTRL bf; |
||||
} UART_LINE_CTRL; |
||||
|
||||
/* UART CONTROL register */ |
||||
typedef struct __BF_UART_CTRL { |
||||
u32 rxMode: 2; |
||||
u32 rxIrq: 1; |
||||
u32 txMode: 2; |
||||
u32 DSR: 1; |
||||
u32 sendBreak: 1; |
||||
u32 loopBack: 1; |
||||
u32 unused:24; |
||||
} BF_UART_CTRL; |
||||
|
||||
typedef union _UART_CTRL { |
||||
u32 ui; |
||||
BF_UART_CTRL bf; |
||||
} UART_CTRL; |
||||
|
||||
/* UART STATUS register */ |
||||
typedef struct __BF_UART_STAT { |
||||
u32 overrun: 1; |
||||
u32 parity: 1; |
||||
u32 frame: 1; |
||||
u32 breakIrq: 1; |
||||
u32 DTR: 1; |
||||
u32 rxReady: 1; |
||||
u32 txBufEmpty: 1; |
||||
u32 txComplete: 1; |
||||
u32 unused:24; |
||||
} BF_UART_STAT; |
||||
|
||||
typedef union _UART_STAT { |
||||
u32 ui; |
||||
BF_UART_STAT bf; |
||||
} UART_STAT; |
||||
|
||||
/* UART BAUD_DIV register */ |
||||
typedef struct __BF_UART_BAUD_DIV { |
||||
u32 cnt1: 4; |
||||
u32 cnt0:12; |
||||
u32 unused:16; |
||||
} BF_UART_BAUD_DIV; |
||||
|
||||
typedef union _UART_BAUD_DIV { |
||||
u32 ui; |
||||
BF_UART_BAUD_DIV bf; |
||||
} UART_BAUD_DIV; |
||||
|
||||
/* UART register block */ |
||||
typedef struct __UART { |
||||
volatile UART_LINE_CTRL m_lineCtrl; |
||||
volatile UART_CTRL m_ctrl; |
||||
volatile UART_STAT m_stat; |
||||
volatile u32 m_tx; |
||||
volatile u32 m_rx; |
||||
volatile UART_BAUD_DIV m_baudDiv; |
||||
volatile u32 m_baudCnt; |
||||
volatile u32 m_baudClk; |
||||
} UART; |
||||
|
||||
#define NL 0x0A |
||||
#define CR 0x0D |
||||
#define BSP 0x08 |
||||
#define ESC 0x1B |
||||
#define CTRLZ 0x1A |
||||
#define RUBOUT 0x7F |
||||
|
||||
#endif |
||||
@ -1,134 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2002-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Alex Zuepke <azu@sysgo.de> |
||||
* |
||||
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <clps7111.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
static void clps7111_serial_setbrg(void) |
||||
{ |
||||
unsigned int reg = 0; |
||||
|
||||
switch (gd->baudrate) { |
||||
case 1200: reg = 191; break; |
||||
case 9600: reg = 23; break; |
||||
case 19200: reg = 11; break; |
||||
case 38400: reg = 5; break; |
||||
case 57600: reg = 3; break; |
||||
case 115200: reg = 1; break; |
||||
default: hang (); break; |
||||
} |
||||
|
||||
/* init serial serial 1,2 */ |
||||
IO_SYSCON1 = SYSCON1_UART1EN; |
||||
IO_SYSCON2 = SYSCON2_UART2EN; |
||||
|
||||
reg |= UBRLCR_WRDLEN8; |
||||
|
||||
IO_UBRLCR1 = reg; |
||||
IO_UBRLCR2 = reg; |
||||
} |
||||
|
||||
|
||||
/*
|
||||
* Initialise the serial port with the given baudrate. The settings |
||||
* are always 8 data bits, no parity, 1 stop bit, no start bits. |
||||
* |
||||
*/ |
||||
static int clps7111_serial_init(void) |
||||
{ |
||||
serial_setbrg (); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
|
||||
/*
|
||||
* Output a single byte to the serial port. |
||||
*/ |
||||
static void clps7111_serial_putc(const char c) |
||||
{ |
||||
int tmo; |
||||
|
||||
/* If \n, also do \r */ |
||||
if (c == '\n') |
||||
serial_putc ('\r'); |
||||
|
||||
tmo = get_timer (0) + 1 * CONFIG_SYS_HZ; |
||||
while (IO_SYSFLG1 & SYSFLG1_UTXFF) |
||||
if (get_timer (0) > tmo) |
||||
break; |
||||
|
||||
IO_UARTDR1 = c; |
||||
} |
||||
|
||||
/*
|
||||
* Read a single byte from the serial port. Returns 1 on success, 0 |
||||
* otherwise. When the function is succesfull, the character read is |
||||
* written into its argument c. |
||||
*/ |
||||
static int clps7111_serial_tstc(void) |
||||
{ |
||||
return !(IO_SYSFLG1 & SYSFLG1_URXFE); |
||||
} |
||||
|
||||
/*
|
||||
* Read a single byte from the serial port. Returns 1 on success, 0 |
||||
* otherwise. When the function is succesfull, the character read is |
||||
* written into its argument c. |
||||
*/ |
||||
static int clps7111_serial_getc(void) |
||||
{ |
||||
while (IO_SYSFLG1 & SYSFLG1_URXFE); |
||||
|
||||
return IO_UARTDR1 & 0xff; |
||||
} |
||||
|
||||
static struct serial_device clps7111_serial_drv = { |
||||
.name = "clps7111_serial", |
||||
.start = clps7111_serial_init, |
||||
.stop = NULL, |
||||
.setbrg = clps7111_serial_setbrg, |
||||
.putc = clps7111_serial_putc, |
||||
.puts = default_serial_puts, |
||||
.getc = clps7111_serial_getc, |
||||
.tstc = clps7111_serial_tstc, |
||||
}; |
||||
|
||||
void clps7111_serial_initialize(void) |
||||
{ |
||||
serial_register(&clps7111_serial_drv); |
||||
} |
||||
|
||||
__weak struct serial_device *default_serial_console(void) |
||||
{ |
||||
return &clps7111_serial_drv; |
||||
} |
||||
@ -1,117 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2002-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Alex Zuepke <azu@sysgo.de> |
||||
* |
||||
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/hardware.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
static void lpc2292_serial_setbrg(void) |
||||
{ |
||||
unsigned short divisor = 0; |
||||
|
||||
switch (gd->baudrate) { |
||||
case 1200: divisor = 3072; break; |
||||
case 9600: divisor = 384; break; |
||||
case 19200: divisor = 192; break; |
||||
case 38400: divisor = 96; break; |
||||
case 57600: divisor = 64; break; |
||||
case 115200: divisor = 32; break; |
||||
default: hang (); break; |
||||
} |
||||
|
||||
/* init serial UART0 */ |
||||
PUT8(U0LCR, 0); |
||||
PUT8(U0IER, 0); |
||||
PUT8(U0LCR, 0x80); /* DLAB=1 */ |
||||
PUT8(U0DLL, (unsigned char)(divisor & 0x00FF)); |
||||
PUT8(U0DLM, (unsigned char)(divisor >> 8)); |
||||
PUT8(U0LCR, 0x03); /* 8N1, DLAB=0 */ |
||||
PUT8(U0FCR, 1); /* Enable RX and TX FIFOs */ |
||||
} |
||||
|
||||
static int lpc2292_serial_init(void) |
||||
{ |
||||
unsigned long pinsel0; |
||||
|
||||
serial_setbrg (); |
||||
|
||||
pinsel0 = GET32(PINSEL0); |
||||
pinsel0 &= ~(0x00000003); |
||||
pinsel0 |= 5; |
||||
PUT32(PINSEL0, pinsel0); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
static void lpc2292_serial_putc(const char c) |
||||
{ |
||||
if (c == '\n') |
||||
{ |
||||
while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */ |
||||
PUT8(U0THR, '\r'); |
||||
} |
||||
|
||||
while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */ |
||||
PUT8(U0THR, c); |
||||
} |
||||
|
||||
static int lpc2292_serial_getc(void) |
||||
{ |
||||
while((GET8(U0LSR) & 1) == 0); |
||||
return GET8(U0RBR); |
||||
} |
||||
|
||||
/* Test if there is a byte to read */ |
||||
static int lpc2292_serial_tstc(void) |
||||
{ |
||||
return (GET8(U0LSR) & 1); |
||||
} |
||||
|
||||
static struct serial_device lpc2292_serial_drv = { |
||||
.name = "lpc2292_serial", |
||||
.start = lpc2292_serial_init, |
||||
.stop = NULL, |
||||
.setbrg = lpc2292_serial_setbrg, |
||||
.putc = lpc2292_serial_putc, |
||||
.puts = default_serial_puts, |
||||
.getc = lpc2292_serial_getc, |
||||
.tstc = lpc2292_serial_tstc, |
||||
}; |
||||
|
||||
void lpc2292_serial_initialize(void) |
||||
{ |
||||
serial_register(&lpc2292_serial_drv); |
||||
} |
||||
|
||||
__weak struct serial_device *default_serial_console(void) |
||||
{ |
||||
return &lpc2292_serial_drv; |
||||
} |
||||
@ -1,204 +0,0 @@ |
||||
/*
|
||||
* Serial Port stuff - taken from Linux |
||||
* |
||||
* (C) Copyright 2002 |
||||
* MAZeT GmbH <www.mazet.de> |
||||
* Stephan Linz <linz@mazet.de>, <linz@li-pro.net> |
||||
* |
||||
* (c) 2004 |
||||
* IMMS gGmbH <www.imms.de> |
||||
* Thomas Elste <info@elste.org> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/hardware.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define PORTA (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTA)) |
||||
#if !defined(CONFIG_NETARM_NS7520) |
||||
#define PORTB (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTB)) |
||||
#else |
||||
#define PORTC (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTC)) |
||||
#endif |
||||
|
||||
/* wait until transmitter is ready for another character */ |
||||
#define TXWAITRDY(registers) \ |
||||
{ \
|
||||
ulong tmo = get_timer(0) + 1 * CONFIG_SYS_HZ; \
|
||||
while (((registers)->status_a & NETARM_SER_STATA_TX_RDY) == 0 ) { \
|
||||
if (get_timer(0) > tmo) \
|
||||
break; \
|
||||
} \
|
||||
} |
||||
|
||||
|
||||
volatile netarm_serial_channel_t *serial_reg_ch1 = get_serial_channel(0); |
||||
volatile netarm_serial_channel_t *serial_reg_ch2 = get_serial_channel(1); |
||||
|
||||
extern void _netarm_led_FAIL1(void); |
||||
|
||||
/*
|
||||
* Setup both serial i/f with given baudrate |
||||
*/ |
||||
static void netarm_serial_setbrg(void) |
||||
{ |
||||
/* set 0 ... make sure pins are configured for serial */ |
||||
#if !defined(CONFIG_NETARM_NS7520) |
||||
PORTA = PORTB = |
||||
NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0); |
||||
#else |
||||
PORTA = NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0); |
||||
PORTC = NETARM_GEN_PORT_CSF (0xef) | NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0); |
||||
#endif |
||||
|
||||
/* first turn em off */ |
||||
serial_reg_ch1->ctrl_a = serial_reg_ch2->ctrl_a = 0; |
||||
|
||||
/* clear match register, we don't need it */ |
||||
serial_reg_ch1->rx_match = serial_reg_ch2->rx_match = 0; |
||||
|
||||
/* setup bit rate generator and rx buffer gap timer (1 byte only) */ |
||||
if ((gd->baudrate >= MIN_BAUD_RATE) |
||||
&& (gd->baudrate <= MAX_BAUD_RATE)) { |
||||
serial_reg_ch1->bitrate = serial_reg_ch2->bitrate = |
||||
NETARM_SER_BR_X16 (gd->baudrate); |
||||
serial_reg_ch1->rx_buf_timer = serial_reg_ch2->rx_buf_timer = |
||||
0; |
||||
serial_reg_ch1->rx_char_timer = serial_reg_ch2->rx_char_timer = |
||||
NETARM_SER_RXGAP (gd->baudrate); |
||||
} else { |
||||
hang (); |
||||
} |
||||
|
||||
/* setup port mode */ |
||||
serial_reg_ch1->ctrl_b = serial_reg_ch2->ctrl_b = |
||||
( NETARM_SER_CTLB_RCGT_EN | |
||||
NETARM_SER_CTLB_UART_MODE); |
||||
serial_reg_ch1->ctrl_a = serial_reg_ch2->ctrl_a = |
||||
( NETARM_SER_CTLA_ENABLE | |
||||
NETARM_SER_CTLA_P_NONE | |
||||
/* see errata */ |
||||
NETARM_SER_CTLA_2STOP | |
||||
NETARM_SER_CTLA_8BITS | |
||||
NETARM_SER_CTLA_DTR_EN | |
||||
NETARM_SER_CTLA_RTS_EN); |
||||
} |
||||
|
||||
|
||||
/*
|
||||
* Initialise the serial port with the given baudrate. The settings |
||||
* are always 8 data bits, no parity, 1 stop bit, no start bits. |
||||
*/ |
||||
static int netarm_serial_init(void) |
||||
{ |
||||
serial_setbrg (); |
||||
return 0; |
||||
} |
||||
|
||||
|
||||
/*
|
||||
* Output a single byte to the serial port. |
||||
*/ |
||||
static void netarm_serial_putc(const char c) |
||||
{ |
||||
volatile unsigned char *fifo; |
||||
|
||||
/* If \n, also do \r */ |
||||
if (c == '\n') |
||||
serial_putc ('\r'); |
||||
|
||||
fifo = (volatile unsigned char *) &(serial_reg_ch1->fifo); |
||||
TXWAITRDY (serial_reg_ch1); |
||||
*fifo = c; |
||||
} |
||||
|
||||
/*
|
||||
* Test of a single byte from the serial port. Returns 1 on success, 0 |
||||
* otherwise. |
||||
*/ |
||||
static int netarm_serial_tstc(void) |
||||
{ |
||||
return serial_reg_ch1->status_a & NETARM_SER_STATA_RX_RDY; |
||||
} |
||||
|
||||
/*
|
||||
* Read a single byte from the serial port. Returns 1 on success, 0 |
||||
* otherwise. |
||||
*/ |
||||
static int netarm_serial_getc(void) |
||||
{ |
||||
unsigned int ch_uint; |
||||
volatile unsigned int *fifo; |
||||
volatile unsigned char *fifo_char = NULL; |
||||
int buf_count = 0; |
||||
|
||||
while (!(serial_reg_ch1->status_a & NETARM_SER_STATA_RX_RDY)) |
||||
/* NOP */ ; |
||||
|
||||
fifo = (volatile unsigned int *) &(serial_reg_ch1->fifo); |
||||
fifo_char = (unsigned char *) &ch_uint; |
||||
ch_uint = *fifo; |
||||
|
||||
buf_count = NETARM_SER_STATA_RXFDB (serial_reg_ch1->status_a); |
||||
switch (buf_count) { |
||||
case NETARM_SER_STATA_RXFDB_4BYTES: |
||||
buf_count = 4; |
||||
break; |
||||
case NETARM_SER_STATA_RXFDB_3BYTES: |
||||
buf_count = 3; |
||||
break; |
||||
case NETARM_SER_STATA_RXFDB_2BYTES: |
||||
buf_count = 2; |
||||
break; |
||||
case NETARM_SER_STATA_RXFDB_1BYTES: |
||||
buf_count = 1; |
||||
break; |
||||
default: |
||||
/* panic, be never here */ |
||||
break; |
||||
} |
||||
|
||||
serial_reg_ch1->status_a |= NETARM_SER_STATA_RX_CLOSED; |
||||
|
||||
return ch_uint & 0xff; |
||||
} |
||||
|
||||
static struct serial_device netarm_serial_drv = { |
||||
.name = "netarm_serial", |
||||
.start = netarm_serial_init, |
||||
.stop = NULL, |
||||
.setbrg = netarm_serial_setbrg, |
||||
.putc = netarm_serial_putc, |
||||
.puts = default_serial_puts, |
||||
.getc = netarm_serial_getc, |
||||
.tstc = netarm_serial_tstc, |
||||
}; |
||||
|
||||
void netarm_serial_initialize(void) |
||||
{ |
||||
serial_register(&netarm_serial_drv); |
||||
} |
||||
|
||||
__weak struct serial_device *default_serial_console(void) |
||||
{ |
||||
return &netarm_serial_drv; |
||||
} |
||||
@ -1,276 +0,0 @@ |
||||
/*
|
||||
* linux/include/asm-arm/hardware/clps7111.h |
||||
* |
||||
* This file contains the hardware definitions of the CLPS7111 internal |
||||
* registers. |
||||
* |
||||
* Copyright (C) 2000 Deep Blue Solutions Ltd. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
||||
*/ |
||||
#ifndef __ASM_HARDWARE_CLPS7111_H |
||||
#define __ASM_HARDWARE_CLPS7111_H |
||||
|
||||
#define CLPS7111_PHYS_BASE (0x80000000) |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
#define clps_readb(off) __raw_readb(CLPS7111_BASE + (off)) |
||||
#define clps_readl(off) __raw_readl(CLPS7111_BASE + (off)) |
||||
#define clps_writeb(val,off) __raw_writeb(val, CLPS7111_BASE + (off)) |
||||
#define clps_writel(val,off) __raw_writel(val, CLPS7111_BASE + (off)) |
||||
#endif |
||||
|
||||
#define PADR (0x0000) |
||||
#define PBDR (0x0001) |
||||
#define PDDR (0x0003) |
||||
#define PADDR (0x0040) |
||||
#define PBDDR (0x0041) |
||||
#define PDDDR (0x0043) |
||||
#define PEDR (0x0080) |
||||
#define PEDDR (0x00c0) |
||||
#define SYSCON1 (0x0100) |
||||
#define SYSFLG1 (0x0140) |
||||
#define MEMCFG1 (0x0180) |
||||
#define MEMCFG2 (0x01c0) |
||||
#define DRFPR (0x0200) |
||||
#define INTSR1 (0x0240) |
||||
#define INTMR1 (0x0280) |
||||
#define LCDCON (0x02c0) |
||||
#define TC1D (0x0300) |
||||
#define TC2D (0x0340) |
||||
#define RTCDR (0x0380) |
||||
#define RTCMR (0x03c0) |
||||
#define PMPCON (0x0400) |
||||
#define CODR (0x0440) |
||||
#define UARTDR1 (0x0480) |
||||
#define UBRLCR1 (0x04c0) |
||||
#define SYNCIO (0x0500) |
||||
#define PALLSW (0x0540) |
||||
#define PALMSW (0x0580) |
||||
#define STFCLR (0x05c0) |
||||
#define BLEOI (0x0600) |
||||
#define MCEOI (0x0640) |
||||
#define TEOI (0x0680) |
||||
#define TC1EOI (0x06c0) |
||||
#define TC2EOI (0x0700) |
||||
#define RTCEOI (0x0740) |
||||
#define UMSEOI (0x0780) |
||||
#define COEOI (0x07c0) |
||||
#define HALT (0x0800) |
||||
#define STDBY (0x0840) |
||||
|
||||
#define FBADDR (0x1000) |
||||
#define SYSCON2 (0x1100) |
||||
#define SYSFLG2 (0x1140) |
||||
#define INTSR2 (0x1240) |
||||
#define INTMR2 (0x1280) |
||||
#define UARTDR2 (0x1480) |
||||
#define UBRLCR2 (0x14c0) |
||||
#define SS2DR (0x1500) |
||||
#define SRXEOF (0x1600) |
||||
#define SS2POP (0x16c0) |
||||
#define KBDEOI (0x1700) |
||||
|
||||
/* common bits: SYSCON1 / SYSCON2 */ |
||||
#define SYSCON_UARTEN (1 << 8) |
||||
|
||||
#define SYSCON1_KBDSCAN(x) ((x) & 15) |
||||
#define SYSCON1_KBDSCANMASK (15) |
||||
#define SYSCON1_TC1M (1 << 4) |
||||
#define SYSCON1_TC1S (1 << 5) |
||||
#define SYSCON1_TC2M (1 << 6) |
||||
#define SYSCON1_TC2S (1 << 7) |
||||
#define SYSCON1_UART1EN SYSCON_UARTEN |
||||
#define SYSCON1_BZTOG (1 << 9) |
||||
#define SYSCON1_BZMOD (1 << 10) |
||||
#define SYSCON1_DBGEN (1 << 11) |
||||
#define SYSCON1_LCDEN (1 << 12) |
||||
#define SYSCON1_CDENTX (1 << 13) |
||||
#define SYSCON1_CDENRX (1 << 14) |
||||
#define SYSCON1_SIREN (1 << 15) |
||||
#define SYSCON1_ADCKSEL(x) (((x) & 3) << 16) |
||||
#define SYSCON1_ADCKSEL_MASK (3 << 16) |
||||
#define SYSCON1_EXCKEN (1 << 18) |
||||
#define SYSCON1_WAKEDIS (1 << 19) |
||||
#define SYSCON1_IRTXM (1 << 20) |
||||
|
||||
/* common bits: SYSFLG1 / SYSFLG2 */ |
||||
#define SYSFLG_UBUSY (1 << 11) |
||||
#define SYSFLG_URXFE (1 << 22) |
||||
#define SYSFLG_UTXFF (1 << 23) |
||||
|
||||
#define SYSFLG1_MCDR (1 << 0) |
||||
#define SYSFLG1_DCDET (1 << 1) |
||||
#define SYSFLG1_WUDR (1 << 2) |
||||
#define SYSFLG1_WUON (1 << 3) |
||||
#define SYSFLG1_CTS (1 << 8) |
||||
#define SYSFLG1_DSR (1 << 9) |
||||
#define SYSFLG1_DCD (1 << 10) |
||||
#define SYSFLG1_UBUSY SYSFLG_UBUSY |
||||
#define SYSFLG1_NBFLG (1 << 12) |
||||
#define SYSFLG1_RSTFLG (1 << 13) |
||||
#define SYSFLG1_PFFLG (1 << 14) |
||||
#define SYSFLG1_CLDFLG (1 << 15) |
||||
#define SYSFLG1_URXFE SYSFLG_URXFE |
||||
#define SYSFLG1_UTXFF SYSFLG_UTXFF |
||||
#define SYSFLG1_CRXFE (1 << 24) |
||||
#define SYSFLG1_CTXFF (1 << 25) |
||||
#define SYSFLG1_SSIBUSY (1 << 26) |
||||
#define SYSFLG1_ID (1 << 29) |
||||
|
||||
#define SYSFLG2_SSRXOF (1 << 0) |
||||
#define SYSFLG2_RESVAL (1 << 1) |
||||
#define SYSFLG2_RESFRM (1 << 2) |
||||
#define SYSFLG2_SS2RXFE (1 << 3) |
||||
#define SYSFLG2_SS2TXFF (1 << 4) |
||||
#define SYSFLG2_SS2TXUF (1 << 5) |
||||
#define SYSFLG2_CKMODE (1 << 6) |
||||
#define SYSFLG2_UBUSY SYSFLG_UBUSY |
||||
#define SYSFLG2_URXFE SYSFLG_URXFE |
||||
#define SYSFLG2_UTXFF SYSFLG_UTXFF |
||||
|
||||
#define LCDCON_GSEN (1 << 30) |
||||
#define LCDCON_GSMD (1 << 31) |
||||
|
||||
#define SYSCON2_SERSEL (1 << 0) |
||||
#define SYSCON2_KBD6 (1 << 1) |
||||
#define SYSCON2_DRAMZ (1 << 2) |
||||
#define SYSCON2_KBWEN (1 << 3) |
||||
#define SYSCON2_SS2TXEN (1 << 4) |
||||
#define SYSCON2_PCCARD1 (1 << 5) |
||||
#define SYSCON2_PCCARD2 (1 << 6) |
||||
#define SYSCON2_SS2RXEN (1 << 7) |
||||
#define SYSCON2_UART2EN SYSCON_UARTEN |
||||
#define SYSCON2_SS2MAEN (1 << 9) |
||||
#define SYSCON2_OSTB (1 << 12) |
||||
#define SYSCON2_CLKENSL (1 << 13) |
||||
#define SYSCON2_BUZFREQ (1 << 14) |
||||
|
||||
/* common bits: UARTDR1 / UARTDR2 */ |
||||
#define UARTDR_FRMERR (1 << 8) |
||||
#define UARTDR_PARERR (1 << 9) |
||||
#define UARTDR_OVERR (1 << 10) |
||||
|
||||
/* common bits: UBRLCR1 / UBRLCR2 */ |
||||
#define UBRLCR_BAUD_MASK ((1 << 12) - 1) |
||||
#define UBRLCR_BREAK (1 << 12) |
||||
#define UBRLCR_PRTEN (1 << 13) |
||||
#define UBRLCR_EVENPRT (1 << 14) |
||||
#define UBRLCR_XSTOP (1 << 15) |
||||
#define UBRLCR_FIFOEN (1 << 16) |
||||
#define UBRLCR_WRDLEN5 (0 << 17) |
||||
#define UBRLCR_WRDLEN6 (1 << 17) |
||||
#define UBRLCR_WRDLEN7 (2 << 17) |
||||
#define UBRLCR_WRDLEN8 (3 << 17) |
||||
#define UBRLCR_WRDLEN_MASK (3 << 17) |
||||
|
||||
#define SYNCIO_SMCKEN (1 << 13) |
||||
#define SYNCIO_TXFRMEN (1 << 14) |
||||
|
||||
#define SYSCON3 0x2200 /* System Control register 3 ----------------------- */ |
||||
#define ADCCON 0x00000001 /* ADC configuration */ |
||||
#define CLKCTL 0x00000006 /* processor clock control */ |
||||
#define CLKCTL_18 0x0 /* 18.432 MHz */ |
||||
#define CLKCTL_36 0x2 /* 36.864 MHz */ |
||||
#define CLKCTL_49 0x4 /* 49.152 MHz */ |
||||
#define CLKCTL_73 0x6 /* 73.728 MHz */ |
||||
#define MCPSEL 0x00000008 /* MCP select */ |
||||
#define ADCCKNSEN 0x000010 /* ADC clock sense */ |
||||
#define VERSN 0x000000e0 /* additional version bits */ |
||||
#define VERSN_SHIFT 5 |
||||
#define FASTWAKE 0x0000100 /* Wakeup clock select: 0=8Hz, 1=4kHz */ |
||||
|
||||
#define INTSR3 0x2240 /* Interrupt Status register 3 --------------------- */ |
||||
#define MCPINT 0x00000001 /* MCP interface interrupt (FIQ) */ |
||||
|
||||
#define INTMR3 0x2280 /* Interrupt Mask register 3 ----------------------- */ |
||||
#define LEDFLSH 0x22C0 /* LED Flash control register ---------------------- */ |
||||
#define LEDFLSH_RATE 0x03 /* flash rate */ |
||||
#define LEDFLSH_RATE_SHIFT 0 |
||||
#define LEDFLSH_DUTY 0x3c /* duty ratio */ |
||||
#define LEDFLSH_DUTY_SHIFT 2 |
||||
#define LEDFLSH_ENABLE 0x40 /* enable */ |
||||
|
||||
#define IO_START CLPS7111_PHYS_BASE |
||||
|
||||
#define IO(offset) (IO_START + (offset)) |
||||
|
||||
#define IO_BYTE(offset) (*(volatile unsigned char *)(IO_START + (offset))) |
||||
#define IO_WORD(offset) (*(volatile unsigned long *)(IO_START + (offset))) |
||||
|
||||
#define IO_PADR IO_BYTE(PADR) |
||||
#define IO_PBDR IO_BYTE(PBDR) |
||||
#define IO_PDDR IO_BYTE(PDDR) |
||||
#define IO_PADDR IO_BYTE(PADDR) |
||||
#define IO_PBDDR IO_BYTE(PBDDR) |
||||
#define IO_PDDDR IO_BYTE(PDDDR) |
||||
#define IO_PEDR IO_BYTE(PEDR) |
||||
#define IO_PEDDR IO_BYTE(PEDDR) |
||||
#define IO_SYSCON IO_WORD(SYSCON) |
||||
#define IO_SYSFLG IO_WORD(SYSFLG) |
||||
#define IO_MEMCFG1 IO_WORD(MEMCFG1) |
||||
#define IO_MEMCFG2 IO_WORD(MEMCFG2) |
||||
#define IO_DRFPR IO_WORD(DRFPR) |
||||
#define IO_INTSR IO_WORD(INTSR) |
||||
#define IO_INTMR IO_WORD(INTMR) |
||||
#define IO_LCDCON IO_WORD(LCDCON) |
||||
#define IO_TC1D IO_WORD(TC1D) |
||||
#define IO_TC2D IO_WORD(TC2D) |
||||
#define IO_RTCDR IO_WORD(RTCDR) |
||||
#define IO_RTCMR IO_WORD(RTCMR) |
||||
#define IO_PMPCON IO_WORD(PMPCON) |
||||
#define IO_CODR IO_BYTE(CODR) |
||||
#define IO_UARTDR IO_WORD(UARTDR) |
||||
#define IO_UBRLCR IO_WORD(UBRLCR) |
||||
#define IO_SYNCIO IO_WORD(SYNCIO) |
||||
#define IO_PALLSW IO_WORD(PALLSW) |
||||
#define IO_PALMSW IO_WORD(PALMSW) |
||||
#define IO_STFCLR IO_WORD(STFCLR) |
||||
#define IO_BLEOI IO_WORD(BLEOI) |
||||
#define IO_MCEOI IO_WORD(MCEOI) |
||||
#define IO_TEOI IO_WORD(TEOI) |
||||
#define IO_TC1EOI IO_WORD(TC1EOI) |
||||
#define IO_TC2EOI IO_WORD(TC2EOI) |
||||
#define IO_RTCEOI IO_WORD(RTCEOI) |
||||
#define IO_UMSEOI IO_WORD(UMSEOI) |
||||
#define IO_COEOI IO_WORD(COEOI) |
||||
#define IO_HALT IO_WORD(HALT) |
||||
#define IO_STDBY IO_WORD(STDBY) |
||||
#define IO_SYSCON1 IO_WORD(SYSCON1) |
||||
#define IO_SYSFLG1 IO_WORD(SYSFLG1) |
||||
#define IO_INTSR1 IO_WORD(INTSR1) |
||||
#define IO_INTMR1 IO_WORD(INTMR1) |
||||
#define IO_UARTDR1 IO_WORD(UARTDR1) |
||||
#define IO_UBRLCR1 IO_WORD(UBRLCR1) |
||||
#define IO_FRBADDR IO_WORD(FRBADDR) |
||||
#define IO_SYSCON2 IO_WORD(SYSCON2) |
||||
#define IO_SYSFLG2 IO_WORD(SYSFLG2) |
||||
#define IO_INTSR2 IO_WORD(INTSR2) |
||||
#define IO_INTMR2 IO_WORD(INTMR2) |
||||
#define IO_UARTDR2 IO_WORD(UARTDR2) |
||||
#define IO_UBRLCR2 IO_WORD(UBRLCR2) |
||||
#define IO_KBDEOI IO_WORD(KBDEOI) |
||||
|
||||
#define IO_MCCR IO_WORD(MCCR) |
||||
#define IO_MCDR0 IO_WORD(MCDR0) |
||||
#define IO_MCDR1 IO_WORD(MCDR1) |
||||
#define IO_MCDR2 IO_WORD(MCDR2) |
||||
#define IO_MCSR IO_WORD(MCSR) |
||||
#define IO_SYSCON3 IO_WORD(SYSCON3) |
||||
#define IO_INTSR3 IO_WORD(INTSR3) |
||||
#define IO_INTMR3 IO_WORD(INTMR3) |
||||
#define IO_LEDFLSH IO_WORD(LEDFLSH) |
||||
|
||||
#endif /* __ASM_HARDWARE_CLPS7111_H */ |
||||
@ -1,189 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#define CONFIG_ARM925T 1 /* This is an arm925t CPU */ |
||||
#define CONFIG_OMAP 1 /* in a TI OMAP core */ |
||||
#define CONFIG_OMAP1510 1 /* which is in a 1510 (helen) */ |
||||
#define CONFIG_OMAP_SX1 1 /* a SX1 Board */ |
||||
|
||||
/* input clock of PLL */ |
||||
#define CONFIG_SYS_CLK_FREQ 12000000 /* the SX1 has 12MHz input clock */ |
||||
|
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
||||
#define CONFIG_INITRD_TAG 1 |
||||
|
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
||||
|
||||
/*
|
||||
* Hardware drivers |
||||
*/ |
||||
|
||||
/*
|
||||
* NS16550 Configuration |
||||
*/ |
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4) |
||||
#define CONFIG_SYS_NS16550_CLK (CONFIG_SYS_CLK_FREQ) /* can be 12M/32Khz or 48Mhz */ |
||||
#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */ |
||||
|
||||
/*
|
||||
* select serial console configuration |
||||
*/ |
||||
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SX1 */ |
||||
|
||||
/*
|
||||
* USB device configuration |
||||
*/ |
||||
#define CONFIG_USB_DEVICE 1 |
||||
#define CONFIG_USB_TTY 1 |
||||
|
||||
#define CONFIG_USBD_VENDORID 0x1234 |
||||
#define CONFIG_USBD_PRODUCTID 0x5678 |
||||
#define CONFIG_USBD_MANUFACTURER "Siemens" |
||||
#define CONFIG_USBD_PRODUCT_NAME "SX1" |
||||
|
||||
/*
|
||||
* I2C configuration |
||||
*/ |
||||
#define CONFIG_HARD_I2C |
||||
#define CONFIG_SYS_I2C_SPEED 100000 |
||||
#define CONFIG_SYS_I2C_SLAVE 1 |
||||
#define CONFIG_DRIVER_OMAP1510_I2C |
||||
|
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
|
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_I2C |
||||
|
||||
#undef CONFIG_CMD_NET |
||||
|
||||
|
||||
#include <configs/omap1510.h> |
||||
|
||||
#define CONFIG_BOOTARGS "mem=16M console=ttyS0,115200n8 root=/dev/mtdblock3 rw" |
||||
#ifdef CONFIG_STDOUT_USBTTY |
||||
#define CONFIG_PREBOOT "setenv stdout usbtty;setenv stdin usbtty" |
||||
#endif |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_PROMPT "SX1# " /* Monitor Command Prompt */ |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */ |
||||
|
||||
/* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1.
|
||||
* This time is further subdivided by a local divisor. |
||||
*/ |
||||
#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE /* use timer 1 */ |
||||
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ |
||||
#define CONFIG_SYS_HZ 1000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
||||
#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ |
||||
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ |
||||
|
||||
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
||||
#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ |
||||
|
||||
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization |
||||
* V1 |
||||
* PHYS_FLASH_SIZE_1 (16 << 10) 16 MB |
||||
* PHYS_FLASH_SIZE_2 (8 << 10) 8 MB |
||||
* V2 only 1 flash |
||||
* PHYS_FLASH_SIZE_1 (32 << 10) 32 MB |
||||
*/ |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
||||
#define PHYS_FLASH_SECT_SIZE (128*1024) /* Size of a sector (128kB) */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT (256) /* max number of sectors on one chip */ |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SECT_SIZE) /* addr of environment */ |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ |
||||
#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE /* Reserve 1 sector */ |
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, PHYS_FLASH_2 } |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH driver setup |
||||
*/ |
||||
#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ |
||||
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ |
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ |
||||
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ |
||||
|
||||
/* timeout values are in ticks */ |
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ |
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE |
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE /* Total Size of Environment Sector */ |
||||
#define CONFIG_ENV_OFFSET ( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */ |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#define CONFIG_ENV_SIZE_REDUND 0x20000 |
||||
#define CONFIG_ENV_OFFSET_REDUND 0x40000 |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
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Reference in new issue