Now that we have serdes support for all 85xx/86xx/Pxxx chips we can replace the is_fsl_pci_cfg() code with the is_serdes_configured(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>master
Kumar Gala
14 years ago
parent
a6da8b8195
commit
5d27e02c04
@ -1,204 +0,0 @@ |
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/*
|
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* Copyright 2009-2010 Freescale Semiconductor, Inc. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#include <common.h> |
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#include <asm/fsl_law.h> |
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#include <pci.h> |
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struct pci_info { |
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u32 cfg; |
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}; |
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/* The cfg field is a bit mask in which each bit represents the value of
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* cfg_IO_ports[] signal and the bit is set if the interface would be |
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* enabled based on the value of cfg_IO_ports[] signal |
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* |
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* On MPC86xx/PQ3 based systems: |
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* we extract cfg_IO_ports from GUTS register PORDEVSR |
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* |
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* cfg_IO_ports only exist on systems w/PCIe (we set cfg 0 for systems |
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* without PCIe) |
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*/ |
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|
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#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8560) |
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static struct pci_info pci_config_info[] = |
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{ |
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[LAW_TRGT_IF_PCI] = { |
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.cfg = 0, |
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}, |
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}; |
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#elif defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) |
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static struct pci_info pci_config_info[] = |
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{ |
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[LAW_TRGT_IF_PCI] = { |
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.cfg = 0, |
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}, |
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}; |
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#elif defined(CONFIG_MPC8536) |
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static struct pci_info pci_config_info[] = |
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{ |
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}; |
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#elif defined(CONFIG_MPC8544) |
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static struct pci_info pci_config_info[] = |
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{ |
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[LAW_TRGT_IF_PCI] = { |
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.cfg = 0, |
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}, |
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[LAW_TRGT_IF_PCIE_1] = { |
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.cfg = (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) | |
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(1 << 6) | (1 << 7), |
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}, |
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[LAW_TRGT_IF_PCIE_2] = { |
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.cfg = (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7), |
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}, |
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[LAW_TRGT_IF_PCIE_3] = { |
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.cfg = (1 << 6) | (1 << 7), |
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}, |
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}; |
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#elif defined(CONFIG_MPC8548) |
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static struct pci_info pci_config_info[] = |
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{ |
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[LAW_TRGT_IF_PCI_1] = { |
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.cfg = 0, |
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}, |
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[LAW_TRGT_IF_PCI_2] = { |
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.cfg = 0, |
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}, |
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/* PCI_2 is always host and we dont use iosel to determine enable/disable */ |
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[LAW_TRGT_IF_PCIE_1] = { |
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.cfg = (1 << 3) | (1 << 4) | (1 << 7), |
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}, |
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}; |
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#elif defined(CONFIG_MPC8568) |
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static struct pci_info pci_config_info[] = |
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{ |
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[LAW_TRGT_IF_PCI] = { |
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.cfg = 0, |
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}, |
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[LAW_TRGT_IF_PCIE_1] = { |
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.cfg = (1 << 3) | (1 << 4) | (1 << 7), |
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}, |
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}; |
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#elif defined(CONFIG_MPC8569) |
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static struct pci_info pci_config_info[] = |
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{ |
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[LAW_TRGT_IF_PCIE_1] = { |
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.cfg = (1 << 0) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | |
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(1 << 8) | (1 << 0xc) | (1 << 0xf), |
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}, |
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}; |
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#elif defined(CONFIG_MPC8572) |
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static struct pci_info pci_config_info[] = |
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{ |
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[LAW_TRGT_IF_PCIE_1] = { |
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.cfg = (1 << 2) | (1 << 3) | (1 << 7) | |
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(1 << 0xb) | (1 << 0xc) | (1 << 0xf), |
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}, |
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[LAW_TRGT_IF_PCIE_2] = { |
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.cfg = (1 << 3) | (1 << 7), |
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}, |
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[LAW_TRGT_IF_PCIE_3] = { |
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.cfg = (1 << 7), |
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}, |
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}; |
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#elif defined(CONFIG_MPC8610) |
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static struct pci_info pci_config_info[] = |
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{ |
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[LAW_TRGT_IF_PCI_1] = { |
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.cfg = 0, |
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}, |
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[LAW_TRGT_IF_PCIE_1] = { |
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.cfg = (1 << 1) | (1 << 4), |
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}, |
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[LAW_TRGT_IF_PCIE_2] = { |
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.cfg = (1 << 0) | (1 << 4), |
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}, |
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}; |
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#elif defined(CONFIG_MPC8641) |
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static struct pci_info pci_config_info[] = |
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{ |
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[LAW_TRGT_IF_PCIE_1] = { |
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.cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6) | |
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(1 << 7) | (1 << 0xf), |
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}, |
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[LAW_TRGT_IF_PCIE_2] = { |
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.cfg = (1 << 3) | (1 << 0xe) | (1 << 0xf), |
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}, |
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}; |
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#elif defined(CONFIG_P1011) || defined(CONFIG_P1020) || \ |
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defined(CONFIG_P1012) || defined(CONFIG_P1021) |
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static struct pci_info pci_config_info[] = |
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{ |
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[LAW_TRGT_IF_PCIE_1] = { |
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.cfg = (1 << 0) | (1 << 6) | (1 << 0xe) | (1 << 0xf), |
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}, |
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[LAW_TRGT_IF_PCIE_2] = { |
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.cfg = (1 << 0xe), |
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}, |
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}; |
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#elif defined(CONFIG_P1013) || defined(CONFIG_P1022) |
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static struct pci_info pci_config_info[] = |
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{ |
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[LAW_TRGT_IF_PCIE_1] = { |
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.cfg = (1 << 6) | (1 << 7) | (1 << 9) | (1 << 0xa) | |
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(1 << 0xb) | (1 << 0xd) | (1 << 0xe) | |
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(1 << 0xf) | (1 << 0x15) | (1 << 0x16) | |
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(1 << 0x17) | (1 << 0x18) | (1 << 0x19) | |
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(1 << 0x1a) | (1 << 0x1b) | (1 << 0x1c) | |
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(1 << 0x1d) | (1 << 0x1e) | (1 << 0x1f), |
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}, |
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[LAW_TRGT_IF_PCIE_2] = { |
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.cfg = (1 << 1) | (1 << 6) | (1 << 7) | (1 << 9) | |
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(1 << 0xd) | (1 << 0x15) | (1 << 0x16) | (1 << 0x17) | |
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(1 << 0x18) | (1 << 0x19) | (1 << 0x1a) | (1 << 0x1b), |
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}, |
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[LAW_TRGT_IF_PCIE_3] = { |
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.cfg = (1 << 0) | (1 << 1) | (1 << 6) | (1 << 7) | (1 << 9) | |
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(1 << 0xa) | (1 << 0xb) | (1 << 0xd) | (1 << 0x15) | |
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(1 << 0x16) | (1 << 0x17) | (1 << 0x18) | (1 << 0x1c), |
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}, |
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}; |
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#elif defined(CONFIG_P2010) || defined(CONFIG_P2020) |
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static struct pci_info pci_config_info[] = |
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{ |
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[LAW_TRGT_IF_PCIE_1] = { |
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.cfg = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6) | |
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(1 << 0xd) | (1 << 0xe) | (1 << 0xf), |
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}, |
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[LAW_TRGT_IF_PCIE_2] = { |
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.cfg = (1 << 2) | (1 << 0xe), |
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}, |
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[LAW_TRGT_IF_PCIE_3] = { |
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.cfg = (1 << 2) | (1 << 4), |
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}, |
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}; |
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#elif defined(CONFIG_FSL_CORENET) |
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#else |
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#error Need to define pci_config_info for processor |
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#endif |
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#ifndef CONFIG_FSL_CORENET |
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int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel) |
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{ |
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return ((1 << io_sel) & pci_config_info[trgt].cfg); |
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} |
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#endif |
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