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/*
|
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* (C) Copyright 2002 |
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com. |
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* Keith Outwater, keith_outwater@mvis.com |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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* |
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*/ |
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|
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/*
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* Configuration support for Xilinx Virtex2 devices. Based |
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* on spartan2.c (Rich Ireland, rireland@enterasys.com). |
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*/ |
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#include <common.h> |
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#include <virtex2.h> |
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#if (CONFIG_FPGA & (CFG_XILINX | CFG_VIRTEX2)) |
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#ifdef FPGA_DEBUG |
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#define PRINTF(fmt,args...) printf (fmt ,##args) |
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#else |
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#define PRINTF(fmt,args...) |
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#endif |
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|
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/*
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* If the SelectMap interface can be overrun by the processor, define |
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* CFG_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board configuration |
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* file and add board-specific support for checking BUSY status. By default, |
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* assume that the SelectMap interface cannot be overrun. |
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*/ |
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#ifndef CFG_FPGA_CHECK_BUSY |
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#undef CFG_FPGA_CHECK_BUSY |
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#endif |
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|
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#ifndef CONFIG_FPGA_DELAY |
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#define CONFIG_FPGA_DELAY() |
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#endif |
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|
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#ifndef CFG_FPGA_PROG_FEEDBACK |
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#define CFG_FPGA_PROG_FEEDBACK |
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#endif |
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/*
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* Don't allow config cycle to be interrupted |
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*/ |
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#ifndef CFG_FPGA_CHECK_CTRLC |
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#undef CFG_FPGA_CHECK_CTRLC |
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#endif |
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|
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/*
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* Check for errors during configuration by default |
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*/ |
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#ifndef CFG_FPGA_CHECK_ERROR |
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#define CFG_FPGA_CHECK_ERROR |
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#endif |
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/*
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* The default timeout in mS for INIT_B to deassert after PROG_B has |
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* been deasserted. Per the latest Virtex II Handbook (page 347), the |
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* max time from PORG_B deassertion to INIT_B deassertion is 4uS per |
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* data frame for the XC2V8000. The XC2V8000 has 2860 data frames |
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* which yields 11.44 mS. So let's make it bigger in order to handle |
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* an XC2V1000, if anyone can ever get ahold of one. |
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*/ |
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#ifndef CFG_FPGA_WAIT_INIT |
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#define CFG_FPGA_WAIT_INIT 500 /* time in milliseconds */ |
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#endif |
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/*
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* The default timeout for waiting for BUSY to deassert during configuration. |
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* This is normally not necessary since for most reasonable configuration |
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* clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary. |
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*/ |
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#ifndef CFG_FPGA_WAIT_BUSY |
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#define CFG_FPGA_WAIT_BUSY 5 /* time in milliseconds */ |
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#endif |
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|
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/* Default timeout for waiting for FPGA to enter operational mode after
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* configuration data has been written. |
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*/ |
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#ifndef CFG_FPGA_WAIT_CONFIG |
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#define CFG_FPGA_WAIT_CONFIG 200 /* time in milliseconds */ |
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#endif |
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static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize); |
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static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize); |
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static int Virtex2_ssm_reloc (Xilinx_desc * desc, ulong reloc_offset); |
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static int Virtex2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize); |
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static int Virtex2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize); |
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static int Virtex2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset); |
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int Virtex2_load (Xilinx_desc * desc, void *buf, size_t bsize) |
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{ |
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int ret_val = FPGA_FAIL; |
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switch (desc->iface) { |
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case slave_serial: |
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PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__); |
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ret_val = Virtex2_ss_load (desc, buf, bsize); |
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break; |
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case slave_selectmap: |
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PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__); |
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ret_val = Virtex2_ssm_load (desc, buf, bsize); |
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break; |
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default: |
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printf ("%s: Unsupported interface type, %d\n", |
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__FUNCTION__, desc->iface); |
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} |
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return ret_val; |
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} |
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int Virtex2_dump (Xilinx_desc * desc, void *buf, size_t bsize) |
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{ |
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int ret_val = FPGA_FAIL; |
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switch (desc->iface) { |
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case slave_serial: |
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PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__); |
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ret_val = Virtex2_ss_dump (desc, buf, bsize); |
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break; |
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case slave_parallel: |
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PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__); |
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ret_val = Virtex2_ssm_dump (desc, buf, bsize); |
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break; |
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default: |
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printf ("%s: Unsupported interface type, %d\n", |
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__FUNCTION__, desc->iface); |
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} |
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return ret_val; |
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} |
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int Virtex2_info (Xilinx_desc * desc) |
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{ |
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return FPGA_SUCCESS; |
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} |
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int Virtex2_reloc (Xilinx_desc * desc, ulong reloc_offset) |
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{ |
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int ret_val = FPGA_FAIL; |
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if (desc->family != Xilinx_Virtex2) { |
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printf ("%s: Unsupported family type, %d\n", |
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__FUNCTION__, desc->family); |
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return FPGA_FAIL; |
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} else |
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switch (desc->iface) { |
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case slave_serial: |
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ret_val = Virtex2_ss_reloc (desc, reloc_offset); |
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break; |
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case slave_selectmap: |
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ret_val = Virtex2_ssm_reloc (desc, reloc_offset); |
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break; |
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default: |
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printf ("%s: Unsupported interface type, %d\n", |
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__FUNCTION__, desc->iface); |
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} |
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return ret_val; |
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} |
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/*
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* Virtex-II Slave SelectMap configuration loader. Configuration via |
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* SelectMap is as follows: |
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* 1. Set the FPGA's PROG_B line low. |
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* 2. Set the FPGA's PROG_B line high. Wait for INIT_B to go high. |
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* 3. Write data to the SelectMap port. If INIT_B goes low at any time |
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* this process, a configuration error (most likely CRC failure) has |
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* ocurred. At this point a status word may be read from the |
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* SelectMap interface to determine the source of the problem (You |
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* could, for instance, put this in you 'abort' function handler). |
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* 4. After all data has been written, test the state of the FPGA |
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* INIT_B and DONE lines. If both are high, configuration has |
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* succeeded. Congratulations! |
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*/ |
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static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize) |
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{ |
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int ret_val = FPGA_FAIL; |
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Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns; |
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PRINTF ("%s:%d: Start with interface functions @ 0x%p\n", |
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__FUNCTION__, __LINE__, fn); |
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if (fn) { |
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size_t bytecount = 0; |
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unsigned char *data = (unsigned char *) buf; |
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int cookie = desc->cookie; |
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unsigned long ts; |
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/* Gotta split this one up (so the stack won't blow??) */ |
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PRINTF ("%s:%d: Function Table:\n" |
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" base 0x%p\n" |
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" struct 0x%p\n" |
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" pre 0x%p\n" |
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" prog 0x%p\n" |
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" init 0x%p\n" |
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" error 0x%p\n", |
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__FUNCTION__, __LINE__, |
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&fn, fn, fn->pre, fn->pgm, fn->init, fn->err); |
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PRINTF (" clock 0x%p\n" |
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" cs 0x%p\n" |
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" write 0x%p\n" |
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" rdata 0x%p\n" |
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" wdata 0x%p\n" |
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" busy 0x%p\n" |
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" abort 0x%p\n" |
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" post 0x%p\n\n", |
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fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, |
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fn->busy, fn->abort, fn->post); |
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#ifdef CFG_FPGA_PROG_FEEDBACK |
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printf ("Initializing FPGA Device %d...\n", cookie); |
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#endif |
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/*
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* Run the pre configuration function if there is one. |
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*/ |
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if (*fn->pre) { |
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(*fn->pre) (cookie); |
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} |
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/*
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* Assert the program line. The minimum pulse width for |
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* Virtex II devices is 300 nS (Tprogram parameter in datasheet). |
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* There is no maximum value for the pulse width. Check to make |
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* sure that INIT_B goes low after assertion of PROG_B |
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*/ |
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(*fn->pgm) (TRUE, TRUE, cookie); |
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udelay (10); |
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ts = get_timer (0); |
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do { |
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if (get_timer (ts) > CFG_FPGA_WAIT_INIT) { |
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printf ("%s:%d: ** Timeout after %d mS waiting for INIT" |
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" to assert.\n", __FUNCTION__, __LINE__, |
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CFG_FPGA_WAIT_INIT); |
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(*fn->abort) (cookie); |
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return FPGA_FAIL; |
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} |
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} while (!(*fn->init) (cookie)); |
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(*fn->pgm) (FALSE, TRUE, cookie); |
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CONFIG_FPGA_DELAY (); |
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(*fn->clk) (TRUE, TRUE, cookie); |
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/*
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* Start a timer and wait for INIT_B to go high |
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*/ |
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ts = get_timer (0); |
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do { |
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CONFIG_FPGA_DELAY (); |
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if (get_timer (ts) > CFG_FPGA_WAIT_INIT) { |
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printf ("%s:%d: ** Timeout after %d mS waiting for INIT" |
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" to deassert.\n", __FUNCTION__, __LINE__, |
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CFG_FPGA_WAIT_INIT); |
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(*fn->abort) (cookie); |
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return FPGA_FAIL; |
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} |
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} while ((*fn->init) (cookie) && (*fn->busy) (cookie)); |
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(*fn->wr) (TRUE, TRUE, cookie); |
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(*fn->cs) (TRUE, TRUE, cookie); |
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udelay (10000); |
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/*
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* Load the data byte by byte |
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*/ |
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while (bytecount < bsize) { |
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#ifdef CFG_FPGA_CHECK_CTRLC |
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if (ctrlc ()) { |
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(*fn->abort) (cookie); |
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return FPGA_FAIL; |
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} |
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#endif |
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#ifdef CFG_FPGA_CHECK_ERROR |
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if ((*fn->init) (cookie)) { |
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printf ("%s:%d: ** Error: INIT asserted during" |
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" configuration\n", __FUNCTION__, __LINE__); |
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(*fn->abort) (cookie); |
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return FPGA_FAIL; |
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} |
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#endif |
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(*fn->wdata) (data[bytecount++], TRUE, cookie); |
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CONFIG_FPGA_DELAY (); |
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/*
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* Cycle the clock pin |
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*/ |
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(*fn->clk) (FALSE, TRUE, cookie); |
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CONFIG_FPGA_DELAY (); |
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(*fn->clk) (TRUE, TRUE, cookie); |
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#ifdef CFG_FPGA_CHECK_BUSY |
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ts = get_timer (0); |
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while ((*fn->busy) (cookie)) { |
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if (get_timer (ts) > CFG_FPGA_WAIT_BUSY) { |
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printf ("%s:%d: ** Timeout after %d mS waiting for" |
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" BUSY to deassert\n", |
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__FUNCTION__, __LINE__, CFG_FPGA_WAIT_BUSY); |
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(*fn->abort) (cookie); |
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return FPGA_FAIL; |
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} |
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} |
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#endif |
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#ifdef CFG_FPGA_PROG_FEEDBACK |
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if (bytecount % (bsize / 40) == 0) |
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putc ('.'); |
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#endif |
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} |
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/*
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* Finished writing the data; deassert FPGA CS_B and WRITE_B signals. |
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*/ |
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CONFIG_FPGA_DELAY (); |
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(*fn->cs) (FALSE, TRUE, cookie); |
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(*fn->wr) (FALSE, TRUE, cookie); |
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#ifdef CFG_FPGA_PROG_FEEDBACK |
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putc ('\n'); |
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#endif |
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/*
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* Check for successful configuration. FPGA INIT_B and DONE should |
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* both be high upon successful configuration. |
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*/ |
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ts = get_timer (0); |
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ret_val = FPGA_SUCCESS; |
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while (((*fn->done) (cookie) == FPGA_FAIL) || (*fn->init) (cookie)) { |
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if (get_timer (ts) > CFG_FPGA_WAIT_CONFIG) { |
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printf ("%s:%d: ** Timeout after %d mS waiting for DONE to" |
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"assert and INIT to deassert\n", |
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__FUNCTION__, __LINE__, CFG_FPGA_WAIT_CONFIG); |
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(*fn->abort) (cookie); |
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ret_val = FPGA_FAIL; |
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break; |
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} |
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} |
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if (ret_val == FPGA_SUCCESS) { |
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#ifdef CFG_FPGA_PROG_FEEDBACK |
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printf ("Initialization of FPGA device %d complete\n", cookie); |
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#endif |
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/*
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* Run the post configuration function if there is one. |
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*/ |
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if (*fn->post) { |
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(*fn->post) (cookie); |
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} |
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} else { |
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#ifdef CFG_FPGA_PROG_FEEDBACK |
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printf ("** Initialization of FPGA device %d FAILED\n", |
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cookie); |
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#endif |
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} |
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} else { |
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printf ("%s:%d: NULL Interface function table!\n", |
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__FUNCTION__, __LINE__); |
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} |
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return ret_val; |
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} |
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/*
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* Read the FPGA configuration data |
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*/ |
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static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize) |
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{ |
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int ret_val = FPGA_FAIL; |
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Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns; |
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if (fn) { |
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unsigned char *data = (unsigned char *) buf; |
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size_t bytecount = 0; |
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int cookie = desc->cookie; |
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printf ("Starting Dump of FPGA Device %d...\n", cookie); |
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(*fn->cs) (TRUE, TRUE, cookie); |
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(*fn->clk) (TRUE, TRUE, cookie); |
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while (bytecount < bsize) { |
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#ifdef CFG_FPGA_CHECK_CTRLC |
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if (ctrlc ()) { |
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(*fn->abort) (cookie); |
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return FPGA_FAIL; |
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} |
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#endif |
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/*
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* Cycle the clock and read the data |
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*/ |
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(*fn->clk) (FALSE, TRUE, cookie); |
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(*fn->clk) (TRUE, TRUE, cookie); |
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(*fn->rdata) (&(data[bytecount++]), cookie); |
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#ifdef CFG_FPGA_PROG_FEEDBACK |
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if (bytecount % (bsize / 40) == 0) |
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putc ('.'); |
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#endif |
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} |
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/*
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* Deassert CS_B and cycle the clock to deselect the device. |
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*/ |
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(*fn->cs) (FALSE, FALSE, cookie); |
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(*fn->clk) (FALSE, TRUE, cookie); |
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(*fn->clk) (TRUE, TRUE, cookie); |
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#ifdef CFG_FPGA_PROG_FEEDBACK |
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putc ('\n'); |
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#endif |
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puts ("Done.\n"); |
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} else { |
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printf ("%s:%d: NULL Interface function table!\n", |
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__FUNCTION__, __LINE__); |
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} |
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return ret_val; |
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} |
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/*
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* Relocate the addresses in the function table from FLASH (or ROM, |
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* or whatever) to RAM. |
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*/ |
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static int Virtex2_ssm_reloc (Xilinx_desc * desc, ulong reloc_offset) |
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{ |
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ulong addr; |
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int ret_val = FPGA_FAIL; |
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Xilinx_Virtex2_Slave_SelectMap_fns *fn_r, *fn = |
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(Xilinx_Virtex2_Slave_SelectMap_fns *) (desc->iface_fns); |
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if (fn) { |
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/*
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* Get the relocated table address |
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*/ |
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addr = (ulong) fn + reloc_offset; |
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fn_r = (Xilinx_Virtex2_Slave_SelectMap_fns *) addr; |
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|
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/*
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* Check to see if the table has already been relocated. If not, do |
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* a sanity check to make sure there is a faithful copy of the |
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* FLASH based function table in RAM, then adjust the table. |
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*/ |
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if (!fn_r->relocated) { |
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if (memcmp |
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(fn_r, fn, sizeof (Xilinx_Virtex2_Slave_SelectMap_fns)) |
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== 0) { |
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desc->iface_fns = fn_r; |
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} else { |
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PRINTF ("%s:%d: Invalid function table at 0x%p\n", |
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__FUNCTION__, __LINE__, fn_r); |
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return FPGA_FAIL; |
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} |
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PRINTF ("%s:%d: Relocating descriptor at 0x%p\n", |
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__FUNCTION__, __LINE__, desc); |
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addr = (ulong) (fn->pre) + reloc_offset; |
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fn_r->pre = (Xilinx_pre_fn) addr; |
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addr = (ulong) (fn->pgm) + reloc_offset; |
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fn_r->pgm = (Xilinx_pgm_fn) addr; |
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addr = (ulong) (fn->init) + reloc_offset; |
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fn_r->init = (Xilinx_init_fn) addr; |
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addr = (ulong) (fn->done) + reloc_offset; |
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fn_r->done = (Xilinx_done_fn) addr; |
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addr = (ulong) (fn->err) + reloc_offset; |
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fn_r->err = (Xilinx_err_fn) addr; |
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addr = (ulong) (fn->clk) + reloc_offset; |
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fn_r->clk = (Xilinx_clk_fn) addr; |
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addr = (ulong) (fn->cs) + reloc_offset; |
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fn_r->cs = (Xilinx_cs_fn) addr; |
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addr = (ulong) (fn->wr) + reloc_offset; |
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fn_r->wr = (Xilinx_wr_fn) addr; |
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addr = (ulong) (fn->rdata) + reloc_offset; |
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fn_r->rdata = (Xilinx_rdata_fn) addr; |
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addr = (ulong) (fn->wdata) + reloc_offset; |
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fn_r->wdata = (Xilinx_wdata_fn) addr; |
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addr = (ulong) (fn->busy) + reloc_offset; |
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fn_r->busy = (Xilinx_busy_fn) addr; |
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addr = (ulong) (fn->abort) + reloc_offset; |
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fn_r->abort = (Xilinx_abort_fn) addr; |
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addr = (ulong) (fn->post) + reloc_offset; |
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fn_r->post = (Xilinx_post_fn) addr; |
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fn_r->relocated = TRUE; |
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} else { |
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printf ("%s:%d: Function table @0x%p has already been relocated\n", __FUNCTION__, __LINE__, fn_r); |
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desc->iface_fns = fn_r; |
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} |
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ret_val = FPGA_SUCCESS; |
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} else { |
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printf ("%s: NULL Interface function table!\n", __FUNCTION__); |
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} |
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return ret_val; |
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} |
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|
||||
static int Virtex2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) |
||||
{ |
||||
printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__); |
||||
return FPGA_FAIL; |
||||
} |
||||
|
||||
static int Virtex2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize) |
||||
{ |
||||
printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__); |
||||
return FPGA_FAIL; |
||||
} |
||||
|
||||
static int Virtex2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset) |
||||
{ |
||||
int ret_val = FPGA_FAIL; |
||||
Xilinx_Virtex2_Slave_Serial_fns *fn = |
||||
(Xilinx_Virtex2_Slave_Serial_fns *) (desc->iface_fns); |
||||
|
||||
if (fn) { |
||||
printf ("%s:%d: Slave Serial Loading is unsupported\n", |
||||
__FUNCTION__, __LINE__); |
||||
} else { |
||||
printf ("%s:%d: NULL Interface function table!\n", |
||||
__FUNCTION__, __LINE__); |
||||
} |
||||
return ret_val; |
||||
} |
||||
#endif |
||||
|
||||
/* vim: set ts=4 tw=78: */ |
@ -0,0 +1,269 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Rich Ireland, Enterasys Networks, rireland@enterasys.com. |
||||
* Keith Outwater, keith_outwater@mvis.com |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
/*
|
||||
* Xilinx FPGA support |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <virtex2.h> |
||||
#include <spartan2.h> |
||||
|
||||
#if (CONFIG_FPGA & CFG_FPGA_XILINX) |
||||
|
||||
#if 0 |
||||
#define FPGA_DEBUG |
||||
#endif |
||||
|
||||
/* Define FPGA_DEBUG to get debug printf's */ |
||||
#ifdef FPGA_DEBUG |
||||
#define PRINTF(fmt,args...) printf (fmt ,##args) |
||||
#else |
||||
#define PRINTF(fmt,args...) |
||||
#endif |
||||
|
||||
/* Local Static Functions */ |
||||
static int xilinx_validate (Xilinx_desc * desc, char *fn); |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize) |
||||
{ |
||||
int ret_val = FPGA_FAIL; /* assume a failure */ |
||||
|
||||
if (!xilinx_validate (desc, __FUNCTION__)) { |
||||
printf ("%s: Invalid device descriptor\n", __FUNCTION__); |
||||
} else |
||||
switch (desc->family) { |
||||
case Xilinx_Spartan2: |
||||
#if (CONFIG_FPGA & CFG_SPARTAN2) |
||||
PRINTF ("%s: Launching the Spartan-II Loader...\n", |
||||
__FUNCTION__); |
||||
ret_val = Spartan2_load (desc, buf, bsize); |
||||
#else |
||||
printf ("%s: No support for Spartan-II devices.\n", |
||||
__FUNCTION__); |
||||
#endif |
||||
break; |
||||
case Xilinx_Virtex2: |
||||
#if (CONFIG_FPGA & CFG_VIRTEX2) |
||||
PRINTF ("%s: Launching the Virtex-II Loader...\n", |
||||
__FUNCTION__); |
||||
ret_val = Virtex2_load (desc, buf, bsize); |
||||
#else |
||||
printf ("%s: No support for Virtex-II devices.\n", |
||||
__FUNCTION__); |
||||
#endif |
||||
break; |
||||
|
||||
default: |
||||
printf ("%s: Unsupported family type, %d\n", |
||||
__FUNCTION__, desc->family); |
||||
} |
||||
|
||||
return ret_val; |
||||
} |
||||
|
||||
int xilinx_dump (Xilinx_desc * desc, void *buf, size_t bsize) |
||||
{ |
||||
int ret_val = FPGA_FAIL; /* assume a failure */ |
||||
|
||||
if (!xilinx_validate (desc, __FUNCTION__)) { |
||||
printf ("%s: Invalid device descriptor\n", __FUNCTION__); |
||||
} else |
||||
switch (desc->family) { |
||||
case Xilinx_Spartan2: |
||||
#if (CONFIG_FPGA & CFG_SPARTAN2) |
||||
PRINTF ("%s: Launching the Spartan-II Reader...\n", |
||||
__FUNCTION__); |
||||
ret_val = Spartan2_dump (desc, buf, bsize); |
||||
#else |
||||
printf ("%s: No support for Spartan-II devices.\n", |
||||
__FUNCTION__); |
||||
#endif |
||||
break; |
||||
case Xilinx_Virtex2: |
||||
#if (CONFIG_FPGA & CFG_VIRTEX2) |
||||
PRINTF ("%s: Launching the Virtex-II Reader...\n", |
||||
__FUNCTION__); |
||||
ret_val = Virtex2_dump (desc, buf, bsize); |
||||
#else |
||||
printf ("%s: No support for Virtex-II devices.\n", |
||||
__FUNCTION__); |
||||
#endif |
||||
break; |
||||
|
||||
default: |
||||
printf ("%s: Unsupported family type, %d\n", |
||||
__FUNCTION__, desc->family); |
||||
} |
||||
|
||||
return ret_val; |
||||
} |
||||
|
||||
int xilinx_info (Xilinx_desc * desc) |
||||
{ |
||||
int ret_val = FPGA_FAIL; |
||||
|
||||
if (xilinx_validate (desc, __FUNCTION__)) { |
||||
printf ("Family: \t"); |
||||
switch (desc->family) { |
||||
case Xilinx_Spartan2: |
||||
printf ("Spartan-II\n"); |
||||
break; |
||||
case Xilinx_Virtex2: |
||||
printf ("Virtex-II\n"); |
||||
break; |
||||
/* Add new family types here */ |
||||
default: |
||||
printf ("Unknown family type, %d\n", desc->family); |
||||
} |
||||
|
||||
printf ("Interface type:\t"); |
||||
switch (desc->iface) { |
||||
case slave_serial: |
||||
printf ("Slave Serial\n"); |
||||
break; |
||||
case master_serial: /* Not used */ |
||||
printf ("Master Serial\n"); |
||||
break; |
||||
case slave_parallel: |
||||
printf ("Slave Parallel\n"); |
||||
break; |
||||
case jtag_mode: /* Not used */ |
||||
printf ("JTAG Mode\n"); |
||||
break; |
||||
case slave_selectmap: |
||||
printf ("Slave SelectMap Mode\n"); |
||||
break; |
||||
case master_selectmap: |
||||
printf ("Master SelectMap Mode\n"); |
||||
break; |
||||
/* Add new interface types here */ |
||||
default: |
||||
printf ("Unsupported interface type, %d\n", desc->iface); |
||||
} |
||||
|
||||
printf ("Device Size: \t%d bytes\n" |
||||
"Cookie: \t0x%x (%d)\n", |
||||
desc->size, desc->cookie, desc->cookie); |
||||
|
||||
if (desc->iface_fns) { |
||||
printf ("Device Function Table @ 0x%p\n", desc->iface_fns); |
||||
switch (desc->family) { |
||||
case Xilinx_Spartan2: |
||||
#if (CONFIG_FPGA & CFG_SPARTAN2) |
||||
Spartan2_info (desc); |
||||
#else |
||||
/* just in case */ |
||||
printf ("%s: No support for Spartan-II devices.\n", |
||||
__FUNCTION__); |
||||
#endif |
||||
break; |
||||
case Xilinx_Virtex2: |
||||
#if (CONFIG_FPGA & CFG_VIRTEX2) |
||||
Virtex2_info (desc); |
||||
#else |
||||
/* just in case */ |
||||
printf ("%s: No support for Virtex-II devices.\n", |
||||
__FUNCTION__); |
||||
#endif |
||||
break; |
||||
/* Add new family types here */ |
||||
default: |
||||
/* we don't need a message here - we give one up above */ |
||||
} |
||||
} else |
||||
printf ("No Device Function Table.\n"); |
||||
|
||||
ret_val = FPGA_SUCCESS; |
||||
} else { |
||||
printf ("%s: Invalid device descriptor\n", __FUNCTION__); |
||||
} |
||||
|
||||
return ret_val; |
||||
} |
||||
|
||||
int xilinx_reloc (Xilinx_desc * desc, ulong reloc_offset) |
||||
{ |
||||
int ret_val = FPGA_FAIL; /* assume a failure */ |
||||
|
||||
if (!xilinx_validate (desc, __FUNCTION__)) { |
||||
printf ("%s: Invalid device descriptor\n", __FUNCTION__); |
||||
} else |
||||
switch (desc->family) { |
||||
case Xilinx_Spartan2: |
||||
#if (CONFIG_FPGA & CFG_SPARTAN2) |
||||
ret_val = Spartan2_reloc (desc, reloc_offset); |
||||
#else |
||||
printf ("%s: No support for Spartan-II devices.\n", |
||||
__FUNCTION__); |
||||
#endif |
||||
break; |
||||
case Xilinx_Virtex2: |
||||
#if (CONFIG_FPGA & CFG_VIRTEX2) |
||||
ret_val = Virtex2_reloc (desc, reloc_offset); |
||||
#else |
||||
printf ("%s: No support for Virtex-II devices.\n", |
||||
__FUNCTION__); |
||||
#endif |
||||
break; |
||||
/* Add new family types here */ |
||||
default: |
||||
printf ("%s: Unsupported family type, %d\n", |
||||
__FUNCTION__, desc->family); |
||||
} |
||||
|
||||
return ret_val; |
||||
} |
||||
|
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
static int xilinx_validate (Xilinx_desc * desc, char *fn) |
||||
{ |
||||
int ret_val = FALSE; |
||||
|
||||
if (desc) { |
||||
if ((desc->family > min_xilinx_type) && |
||||
(desc->family < max_xilinx_type)) { |
||||
if ((desc->iface > min_xilinx_iface_type) && |
||||
(desc->iface < max_xilinx_iface_type)) { |
||||
if (desc->size) { |
||||
ret_val = TRUE; |
||||
} else |
||||
printf ("%s: NULL part size\n", fn); |
||||
} else |
||||
printf ("%s: Invalid Interface type, %d\n", |
||||
fn, desc->iface); |
||||
} else |
||||
printf ("%s: Invalid family type, %d\n", fn, desc->family); |
||||
} else |
||||
printf ("%s: NULL descriptor!\n", fn); |
||||
|
||||
return ret_val; |
||||
} |
||||
|
||||
#endif /* CONFIG_FPGA & CFG_FPGA_XILINX */ |
@ -0,0 +1,191 @@ |
||||
/*
|
||||
* (C) Copyright 2001, 2002 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* Keith Outwater, keith_outwater@mvis.com` |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* Date & Time support (no alarms) for Dallas Semiconductor (now Maxim) |
||||
* DS1337 Real Time Clock (RTC). |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <rtc.h> |
||||
#include <i2c.h> |
||||
|
||||
#if defined(CONFIG_RTC_DS1337) && (CONFIG_COMMANDS & CFG_CMD_DATE) |
||||
|
||||
/*---------------------------------------------------------------------*/ |
||||
#undef DEBUG_RTC |
||||
|
||||
#ifdef DEBUG_RTC |
||||
#define DEBUGR(fmt,args...) printf(fmt ,##args) |
||||
#else |
||||
#define DEBUGR(fmt,args...) |
||||
#endif |
||||
/*---------------------------------------------------------------------*/ |
||||
|
||||
/*
|
||||
* RTC register addresses |
||||
*/ |
||||
#define RTC_SEC_REG_ADDR 0x0 |
||||
#define RTC_MIN_REG_ADDR 0x1 |
||||
#define RTC_HR_REG_ADDR 0x2 |
||||
#define RTC_DAY_REG_ADDR 0x3 |
||||
#define RTC_DATE_REG_ADDR 0x4 |
||||
#define RTC_MON_REG_ADDR 0x5 |
||||
#define RTC_YR_REG_ADDR 0x6 |
||||
#define RTC_CTL_REG_ADDR 0x0e |
||||
#define RTC_STAT_REG_ADDR 0x0f |
||||
|
||||
/*
|
||||
* RTC control register bits |
||||
*/ |
||||
#define RTC_CTL_BIT_A1IE 0x1 /* Alarm 1 interrupt enable */ |
||||
#define RTC_CTL_BIT_A2IE 0x2 /* Alarm 2 interrupt enable */ |
||||
#define RTC_CTL_BIT_INTCN 0x4 /* Interrupt control */ |
||||
#define RTC_CTL_BIT_RS1 0x8 /* Rate select 1 */ |
||||
#define RTC_CTL_BIT_RS2 0x10 /* Rate select 2 */ |
||||
#define RTC_CTL_BIT_DOSC 0x80 /* Disable Oscillator */ |
||||
|
||||
/*
|
||||
* RTC status register bits |
||||
*/ |
||||
#define RTC_STAT_BIT_A1F 0x1 /* Alarm 1 flag */ |
||||
#define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */ |
||||
#define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */ |
||||
|
||||
|
||||
static uchar rtc_read (uchar reg); |
||||
static void rtc_write (uchar reg, uchar val); |
||||
static uchar bin2bcd (unsigned int n); |
||||
static unsigned bcd2bin (uchar c); |
||||
|
||||
|
||||
/*
|
||||
* Get the current time from the RTC |
||||
*/ |
||||
void rtc_get (struct rtc_time *tmp) |
||||
{ |
||||
uchar sec, min, hour, mday, wday, mon_cent, year, control, status; |
||||
|
||||
control = rtc_read (RTC_CTL_REG_ADDR); |
||||
status = rtc_read (RTC_STAT_REG_ADDR); |
||||
sec = rtc_read (RTC_SEC_REG_ADDR); |
||||
min = rtc_read (RTC_MIN_REG_ADDR); |
||||
hour = rtc_read (RTC_HR_REG_ADDR); |
||||
wday = rtc_read (RTC_DAY_REG_ADDR); |
||||
mday = rtc_read (RTC_DATE_REG_ADDR); |
||||
mon_cent = rtc_read (RTC_MON_REG_ADDR); |
||||
year = rtc_read (RTC_YR_REG_ADDR); |
||||
|
||||
DEBUGR ("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x " |
||||
"hr: %02x min: %02x sec: %02x control: %02x status: %02x\n", |
||||
year, mon_cent, mday, wday, hour, min, sec, control, status); |
||||
|
||||
if (status & RTC_STAT_BIT_OSF) { |
||||
printf ("### Warning: RTC oscillator has stopped\n"); |
||||
/* clear the OSF flag */ |
||||
rtc_write (RTC_STAT_REG_ADDR, |
||||
rtc_read (RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF); |
||||
} |
||||
|
||||
tmp->tm_sec = bcd2bin (sec & 0x7F); |
||||
tmp->tm_min = bcd2bin (min & 0x7F); |
||||
tmp->tm_hour = bcd2bin (hour & 0x3F); |
||||
tmp->tm_mday = bcd2bin (mday & 0x3F); |
||||
tmp->tm_mon = bcd2bin (mon_cent & 0x1F); |
||||
tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900); |
||||
tmp->tm_wday = bcd2bin ((wday - 1) & 0x07); |
||||
tmp->tm_yday = 0; |
||||
tmp->tm_isdst= 0; |
||||
|
||||
DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", |
||||
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, |
||||
tmp->tm_hour, tmp->tm_min, tmp->tm_sec); |
||||
} |
||||
|
||||
|
||||
/*
|
||||
* Set the RTC |
||||
*/ |
||||
void rtc_set (struct rtc_time *tmp) |
||||
{ |
||||
uchar century; |
||||
|
||||
DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", |
||||
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, |
||||
tmp->tm_hour, tmp->tm_min, tmp->tm_sec); |
||||
|
||||
rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100)); |
||||
|
||||
century = (tmp->tm_year >= 2000) ? 0x80 : 0; |
||||
rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) | century); |
||||
|
||||
rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1)); |
||||
rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday)); |
||||
rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour)); |
||||
rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min)); |
||||
rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec)); |
||||
} |
||||
|
||||
|
||||
/*
|
||||
* Reset the RTC. We also enable the oscillator output on the |
||||
* SQW/INTB* pin and program it for 32,768 Hz output. Note that |
||||
* according to the datasheet, turning on the square wave output |
||||
* increases the current drain on the backup battery from about |
||||
* 600 nA to 2uA. |
||||
*/ |
||||
void rtc_reset (void) |
||||
{ |
||||
rtc_write (RTC_CTL_REG_ADDR, RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2); |
||||
} |
||||
|
||||
|
||||
/*
|
||||
* Helper functions |
||||
*/ |
||||
|
||||
static |
||||
uchar rtc_read (uchar reg) |
||||
{ |
||||
return (i2c_reg_read (CFG_I2C_RTC_ADDR, reg)); |
||||
} |
||||
|
||||
|
||||
static void rtc_write (uchar reg, uchar val) |
||||
{ |
||||
i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val); |
||||
} |
||||
|
||||
static unsigned bcd2bin (uchar n) |
||||
{ |
||||
return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); |
||||
} |
||||
|
||||
static unsigned char bin2bcd (unsigned int n) |
||||
{ |
||||
return (((n / 10) << 4) | (n % 10)); |
||||
} |
||||
|
||||
#endif /* CONFIG_RTC_DS1337 && (CFG_COMMANDS & CFG_CMD_DATE) */ |
Loading…
Reference in new issue