Wolfgang Denk
17 years ago
commit
5db6138565
@ -0,0 +1,50 @@ |
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#
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# (C) Copyright 2003-2008
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# Wolfgang Denk, DENX Software Engineering, wd <at> denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS := at91cap9adk.o led.o nand.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,283 @@ |
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/*
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* (C) Copyright 2007-2008 |
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* Stelian Pop <stelian.pop <at> leadtechdesign.com> |
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* Lead Tech Design <www.leadtechdesign.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/arch/AT91CAP9.h> |
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#define MP_BLOCK_3_BASE 0xFDF00000 |
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DECLARE_GLOBAL_DATA_PTR; |
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/* ------------------------------------------------------------------------- */ |
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/*
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* Miscelaneous platform dependent initialisations |
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*/ |
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static void at91cap9_serial_hw_init(void) |
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{ |
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#ifdef CONFIG_USART0 |
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AT91C_BASE_PIOA->PIO_PDR = AT91C_PA22_TXD0 | AT91C_PA23_RXD0; |
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AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US0; |
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#endif |
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#ifdef CONFIG_USART1 |
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AT91C_BASE_PIOD->PIO_PDR = AT91C_PD0_TXD1 | AT91C_PD1_RXD1; |
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AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US1; |
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#endif |
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#ifdef CONFIG_USART2 |
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AT91C_BASE_PIOD->PIO_PDR = AT91C_PD2_TXD2 | AT91C_PD3_RXD2; |
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AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US2; |
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#endif |
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#ifdef CONFIG_USART3 /* DBGU */ |
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AT91C_BASE_PIOC->PIO_PDR = AT91C_PC31_DTXD | AT91C_PC30_DRXD; |
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AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SYS; |
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#endif |
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} |
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static void at91cap9_nor_hw_init(void) |
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{ |
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/* Ensure EBI supply is 3.3V */ |
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AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_SUP_3V3; |
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/* Configure SMC CS0 for parallel flash */ |
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AT91C_BASE_SMC->SMC_SETUP0 = AT91C_FLASH_NWE_SETUP | |
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AT91C_FLASH_NCS_WR_SETUP | |
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AT91C_FLASH_NRD_SETUP | |
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AT91C_FLASH_NCS_RD_SETUP; |
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AT91C_BASE_SMC->SMC_PULSE0 = AT91C_FLASH_NWE_PULSE | |
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AT91C_FLASH_NCS_WR_PULSE | |
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AT91C_FLASH_NRD_PULSE | |
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AT91C_FLASH_NCS_RD_PULSE; |
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AT91C_BASE_SMC->SMC_CYCLE0 = AT91C_FLASH_NWE_CYCLE | |
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AT91C_FLASH_NRD_CYCLE; |
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AT91C_BASE_SMC->SMC_CTRL0 = AT91C_SMC_READMODE | |
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AT91C_SMC_WRITEMODE | |
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AT91C_SMC_NWAITM_NWAIT_DISABLE | |
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AT91C_SMC_BAT_BYTE_WRITE | |
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AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS | |
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(AT91C_SMC_TDF & (1 << 16)); |
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} |
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#ifdef CONFIG_CMD_NAND |
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static void at91cap9_nand_hw_init(void) |
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{ |
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/* Enable CS3 */ |
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AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_CS3A_SM | AT91C_EBI_SUP_3V3; |
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/* Configure SMC CS3 for NAND/SmartMedia */ |
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AT91C_BASE_SMC->SMC_SETUP3 = AT91C_SM_NWE_SETUP | |
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AT91C_SM_NCS_WR_SETUP | |
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AT91C_SM_NRD_SETUP | |
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AT91C_SM_NCS_RD_SETUP; |
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AT91C_BASE_SMC->SMC_PULSE3 = AT91C_SM_NWE_PULSE | |
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AT91C_SM_NCS_WR_PULSE | |
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AT91C_SM_NRD_PULSE | |
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AT91C_SM_NCS_RD_PULSE; |
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AT91C_BASE_SMC->SMC_CYCLE3 = AT91C_SM_NWE_CYCLE | |
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AT91C_SM_NRD_CYCLE; |
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AT91C_BASE_SMC->SMC_CTRL3 = AT91C_SMC_READMODE | |
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AT91C_SMC_WRITEMODE | |
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AT91C_SMC_NWAITM_NWAIT_DISABLE | |
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AT91C_SMC_DBW_WIDTH_EIGTH_BITS | |
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AT91C_SM_TDF; |
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AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCD; |
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/* RDY/BSY is not connected */ |
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/* Enable NandFlash */ |
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AT91C_BASE_PIOD->PIO_PER = AT91C_PIO_PD15; |
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AT91C_BASE_PIOD->PIO_OER = AT91C_PIO_PD15; |
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} |
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#endif |
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#ifdef CONFIG_HAS_DATAFLASH |
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static void at91cap9_spi_hw_init(void) |
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{ |
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AT91C_BASE_PIOD->PIO_BSR = AT91C_PD0_SPI0_NPCS2D | |
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AT91C_PD1_SPI0_NPCS3D; |
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AT91C_BASE_PIOD->PIO_PDR = AT91C_PD0_SPI0_NPCS2D | |
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AT91C_PD1_SPI0_NPCS3D; |
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AT91C_BASE_PIOA->PIO_ASR = AT91C_PA28_SPI0_NPCS3A; |
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AT91C_BASE_PIOA->PIO_BSR = AT91C_PA4_SPI0_NPCS2A | |
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AT91C_PA1_SPI0_MOSI | |
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AT91C_PA0_SPI0_MISO | |
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AT91C_PA3_SPI0_NPCS1 | |
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AT91C_PA5_SPI0_NPCS0 | |
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AT91C_PA2_SPI0_SPCK; |
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AT91C_BASE_PIOA->PIO_PDR = AT91C_PA28_SPI0_NPCS3A | |
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AT91C_PA4_SPI0_NPCS2A | |
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AT91C_PA1_SPI0_MOSI | |
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AT91C_PA0_SPI0_MISO | |
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AT91C_PA3_SPI0_NPCS1 | |
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AT91C_PA5_SPI0_NPCS0 | |
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AT91C_PA2_SPI0_SPCK; |
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/* Enable Clock */ |
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AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI0; |
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} |
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#endif |
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#ifdef CONFIG_MACB |
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static void at91cap9_macb_hw_init(void) |
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{ |
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unsigned int gpio; |
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/* Enable clock */ |
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AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC; |
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/*
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* Disable pull-up on: |
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* RXDV (PB22) => PHY normal mode (not Test mode) |
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* ERX0 (PB25) => PHY ADDR0 |
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* ERX1 (PB26) => PHY ADDR1 => PHYADDR = 0x0 |
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* |
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* PHY has internal pull-down |
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*/ |
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AT91C_BASE_PIOB->PIO_PPUDR = AT91C_PB22_E_RXDV | |
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AT91C_PB25_E_RX0 | |
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AT91C_PB26_E_RX1; |
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/* Need to reset PHY -> 500ms reset */ |
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AT91C_BASE_RSTC->RSTC_RMR = (AT91C_RSTC_KEY & (0xA5 << 24)) | |
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(AT91C_RSTC_ERSTL & (0x0D << 8)) | |
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AT91C_RSTC_URSTEN; |
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AT91C_BASE_RSTC->RSTC_RCR = (AT91C_RSTC_KEY & (0xA5 << 24)) | |
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AT91C_RSTC_EXTRST; |
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/* Wait for end hardware reset */ |
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while (!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL)); |
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/* Re-enable pull-up */ |
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AT91C_BASE_PIOB->PIO_PPUER = AT91C_PB22_E_RXDV | |
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AT91C_PB25_E_RX0 | |
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AT91C_PB26_E_RX1; |
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#ifdef CONFIG_RMII |
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gpio = AT91C_PB30_E_MDIO | |
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AT91C_PB29_E_MDC | |
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AT91C_PB21_E_TXCK | |
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AT91C_PB27_E_RXER | |
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AT91C_PB25_E_RX0 | |
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AT91C_PB22_E_RXDV | |
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AT91C_PB26_E_RX1 | |
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AT91C_PB28_E_TXEN | |
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AT91C_PB23_E_TX0 | |
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AT91C_PB24_E_TX1; |
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AT91C_BASE_PIOB->PIO_ASR = gpio; |
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AT91C_BASE_PIOB->PIO_BSR = 0; |
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AT91C_BASE_PIOB->PIO_PDR = gpio; |
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#else |
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#error AT91CAP9A-DK works only in RMII mode |
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#endif |
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/* Unlock EMAC, 3 0 2 1 sequence */ |
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#define MP_MAC_KEY0 0x5969cb2a |
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#define MP_MAC_KEY1 0xb4a1872e |
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#define MP_MAC_KEY2 0x05683fbc |
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#define MP_MAC_KEY3 0x3634fba4 |
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#define UNLOCK_MAC 0x00000008 |
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*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x3c)) = MP_MAC_KEY3; |
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*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x30)) = MP_MAC_KEY0; |
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*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x38)) = MP_MAC_KEY2; |
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*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x34)) = MP_MAC_KEY1; |
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*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x40)) = UNLOCK_MAC; |
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} |
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#endif |
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#ifdef CONFIG_USB_OHCI_NEW |
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static void at91cap9_uhp_hw_init(void) |
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{ |
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/* Unlock USB OHCI, 3 2 0 1 sequence */ |
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#define MP_OHCI_KEY0 0x896c11ca |
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#define MP_OHCI_KEY1 0x68ebca21 |
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#define MP_OHCI_KEY2 0x4823efbc |
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#define MP_OHCI_KEY3 0x8651aae4 |
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#define UNLOCK_OHCI 0x00000010 |
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*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x3c)) = MP_OHCI_KEY3; |
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*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x38)) = MP_OHCI_KEY2; |
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*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x30)) = MP_OHCI_KEY0; |
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*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x34)) = MP_OHCI_KEY1; |
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*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x40)) = UNLOCK_OHCI; |
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} |
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#endif |
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int board_init(void) |
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{ |
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/* Enable Ctrlc */ |
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console_init_f(); |
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/* arch number of AT91CAP9ADK-Board */ |
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gd->bd->bi_arch_number = MACH_TYPE_AT91CAP9ADK; |
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/* adress of boot parameters */ |
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
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at91cap9_serial_hw_init(); |
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at91cap9_nor_hw_init(); |
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#ifdef CONFIG_CMD_NAND |
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at91cap9_nand_hw_init(); |
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#endif |
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#ifdef CONFIG_HAS_DATAFLASH |
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at91cap9_spi_hw_init(); |
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#endif |
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#ifdef CONFIG_MACB |
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at91cap9_macb_hw_init(); |
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#endif |
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#ifdef CONFIG_USB_OHCI_NEW |
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at91cap9_uhp_hw_init(); |
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#endif |
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return 0; |
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} |
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int dram_init(void) |
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{ |
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gd->bd->bi_dram[0].start = PHYS_SDRAM; |
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; |
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return 0; |
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} |
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#ifdef CONFIG_RESET_PHY_R |
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void reset_phy(void) |
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{ |
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#ifdef CONFIG_MACB |
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/*
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* Initialize ethernet HW addr prior to starting Linux, |
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* needed for nfsroot |
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*/ |
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eth_init(gd->bd); |
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#endif |
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} |
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#endif |
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@ -0,0 +1 @@ |
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TEXT_BASE = 0x73000000
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@ -0,0 +1,80 @@ |
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/*
|
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* (C) Copyright 2007-2008 |
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* Stelian Pop <stelian.pop <at> leadtechdesign.com> |
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* Lead Tech Design <www.leadtechdesign.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
||||
* project. |
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* |
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* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/arch/AT91CAP9.h> |
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#define RED_LED AT91C_PIO_PC29 /* this is the power led */ |
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#define GREEN_LED AT91C_PIO_PA10 /* this is the user1 led */ |
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#define YELLOW_LED AT91C_PIO_PA11 /* this is the user1 led */ |
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void red_LED_on(void) |
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{ |
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AT91C_BASE_PIOC->PIO_SODR = RED_LED; |
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} |
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void red_LED_off(void) |
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{ |
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AT91C_BASE_PIOC->PIO_CODR = RED_LED; |
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} |
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void green_LED_on(void) |
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{ |
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AT91C_BASE_PIOA->PIO_CODR = GREEN_LED; |
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} |
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void green_LED_off(void) |
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{ |
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AT91C_BASE_PIOA->PIO_SODR = GREEN_LED; |
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} |
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|
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void yellow_LED_on(void) |
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{ |
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AT91C_BASE_PIOA->PIO_CODR = YELLOW_LED; |
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} |
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|
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void yellow_LED_off(void) |
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{ |
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AT91C_BASE_PIOA->PIO_SODR = YELLOW_LED; |
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} |
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|
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void coloured_LED_init(void) |
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{ |
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/* Enable clock */ |
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AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCD; |
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|
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/* Disable peripherals on LEDs */ |
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AT91C_BASE_PIOA->PIO_PER = GREEN_LED | YELLOW_LED; |
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/* Enable pins as outputs */ |
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AT91C_BASE_PIOA->PIO_OER = GREEN_LED | YELLOW_LED; |
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/* Turn all LEDs OFF */ |
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AT91C_BASE_PIOA->PIO_SODR = GREEN_LED | YELLOW_LED; |
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|
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/* Disable peripherals on LEDs */ |
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AT91C_BASE_PIOC->PIO_PER = RED_LED; |
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/* Enable pins as outputs */ |
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AT91C_BASE_PIOC->PIO_OER = RED_LED; |
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/* Turn all LEDs OFF */ |
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AT91C_BASE_PIOC->PIO_CODR = RED_LED; |
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} |
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@ -0,0 +1,71 @@ |
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/*
|
||||
* (C) Copyright 2007-2008 |
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* Stelian Pop <stelian.pop <at> leadtechdesign.com> |
||||
* Lead Tech Design <www.leadtechdesign.com> |
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* |
||||
* (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas |
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* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
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|
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#include <common.h> |
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#include <asm/arch/hardware.h> |
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|
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#ifdef CONFIG_CMD_NAND |
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|
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#include <nand.h> |
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|
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/*
|
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* hardware specific access to control-lines |
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*/ |
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#define MASK_ALE (1 << 21) /* our ALE is AD21 */ |
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#define MASK_CLE (1 << 22) /* our CLE is AD22 */ |
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|
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static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd, int cmd) |
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{ |
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struct nand_chip *this = mtd->priv; |
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ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; |
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|
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IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); |
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switch (cmd) { |
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case NAND_CTL_SETCLE: |
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IO_ADDR_W |= MASK_CLE; |
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break; |
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case NAND_CTL_SETALE: |
||||
IO_ADDR_W |= MASK_ALE; |
||||
break; |
||||
case NAND_CTL_CLRNCE: |
||||
AT91C_BASE_PIOD->PIO_SODR = AT91C_PIO_PD15; |
||||
break; |
||||
case NAND_CTL_SETNCE: |
||||
AT91C_BASE_PIOD->PIO_CODR = AT91C_PIO_PD15; |
||||
break; |
||||
} |
||||
this->IO_ADDR_W = (void *) IO_ADDR_W; |
||||
} |
||||
|
||||
int board_nand_init(struct nand_chip *nand) |
||||
{ |
||||
nand->eccmode = NAND_ECC_SOFT; |
||||
nand->hwcontrol = at91cap9adk_nand_hwcontrol; |
||||
nand->chip_delay = 20; |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
@ -0,0 +1,57 @@ |
||||
/* |
||||
* (C) Copyright 2002 |
||||
* Gary Jennejohn, DENX Software Engineering, <gj <at> denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
||||
/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ |
||||
OUTPUT_ARCH(arm) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
|
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
cpu/arm926ejs/start.o (.text) |
||||
*(.text) |
||||
} |
||||
|
||||
. = ALIGN(4); |
||||
.rodata : { *(.rodata) } |
||||
|
||||
. = ALIGN(4); |
||||
.data : { *(.data) } |
||||
|
||||
. = ALIGN(4); |
||||
.got : { *(.got) } |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
. = ALIGN(4); |
||||
__bss_start = .; |
||||
.bss : { *(.bss) } |
||||
_end = .; |
||||
} |
||||
@ -0,0 +1,48 @@ |
||||
#
|
||||
# (C) Copyright 2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS := m501sk.o eeprom.o
|
||||
|
||||
SOBJS := memsetup.o
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS) |
||||
$(AR) crv $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
||||
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
-include .depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1 @@ |
||||
TEXT_BASE = 0x21f00000
|
||||
@ -0,0 +1,102 @@ |
||||
/*
|
||||
* Add by Alan Lu, 07-29-2005 |
||||
* For ATMEL AT24C16 EEPROM |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <i2c.h> |
||||
#ifdef CFG_EEPROM_AT24C16 |
||||
#undef DEBUG |
||||
|
||||
void eeprom_init(void) |
||||
{ |
||||
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) |
||||
i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); |
||||
#endif |
||||
} |
||||
|
||||
int eeprom_read(unsigned dev_addr, unsigned offset, uchar *buffer, |
||||
unsigned cnt) |
||||
{ |
||||
int page, count = 0, i = 0; |
||||
page = offset / 0x100; |
||||
i = offset % 0x100; |
||||
|
||||
while (count < cnt) { |
||||
if (i2c_read(dev_addr|page, i++, 1, buffer+count++, 1) != 0) |
||||
return 1; |
||||
if (i > 0xff) { |
||||
page++; |
||||
i = 0; |
||||
} |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* for CFG_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is |
||||
* 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM. |
||||
* |
||||
* for CFG_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is |
||||
* 0x00000nxx for EEPROM address selectors and page number at n. |
||||
*/ |
||||
int eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, |
||||
unsigned cnt) |
||||
{ |
||||
int page, i = 0, count = 0; |
||||
|
||||
page = offset / 0x100; |
||||
i = offset % 0x100; |
||||
|
||||
while (count < cnt) { |
||||
if (i2c_write(dev_addr|page, i++, 1, buffer+count++, 1) != 0) |
||||
return 1; |
||||
if (i > 0xff) { |
||||
page++; |
||||
i = 0; |
||||
} |
||||
} |
||||
|
||||
#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS) |
||||
udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifndef CONFIG_SPI |
||||
int eeprom_probe(unsigned dev_addr, unsigned offset) |
||||
{ |
||||
unsigned char chip; |
||||
|
||||
/* Probe the chip address */ |
||||
#if CFG_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X) |
||||
chip = offset >> 8; /* block number */ |
||||
#else |
||||
chip = offset >> 16; /* block number */ |
||||
#endif /* CFG_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */ |
||||
|
||||
chip |= dev_addr; /* insert device address */ |
||||
return (i2c_probe(chip)); |
||||
} |
||||
#endif |
||||
#endif |
||||
@ -0,0 +1,194 @@ |
||||
/*
|
||||
* (C) Copyright 2008 |
||||
* Based on modifications by Alan Lu / Artila |
||||
* Author : Timo Tuunainen / Sysart |
||||
Kimmo Leppala / Sysart |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <at91rm9200_net.h> |
||||
#include <dm9161.h> |
||||
#include "m501sk.h" |
||||
#include "net.h" |
||||
|
||||
#ifdef CONFIG_M501SK |
||||
|
||||
void m501sk_gpio_init(void) |
||||
{ |
||||
AT91C_BASE_PIOD->PIO_PER = 1 << (M501SK_DEBUG_LED1 - 96) | |
||||
1 << (M501SK_DEBUG_LED2 - 96) | 1 << (M501SK_DEBUG_LED3 - 96) | |
||||
1 << (M501SK_DEBUG_LED4 - 96) | 1 << (M501SK_READY_LED - 96); |
||||
|
||||
AT91C_BASE_PIOD->PIO_OER = 1 << (M501SK_DEBUG_LED1 - 96) | |
||||
1 << (M501SK_DEBUG_LED2 - 96) | 1 << (M501SK_DEBUG_LED3 - 96) | |
||||
1 << (M501SK_DEBUG_LED4 - 96) | 1 << (M501SK_READY_LED - 96); |
||||
|
||||
AT91C_BASE_PIOD->PIO_SODR = 1 << (M501SK_READY_LED - 96); |
||||
AT91C_BASE_PIOD->PIO_CODR = 1 << (M501SK_DEBUG_LED3 - 96); |
||||
AT91C_BASE_PIOB->PIO_PER = 1 << (M501SK_BUZZER - 32); |
||||
AT91C_BASE_PIOB->PIO_OER = 1 << (M501SK_BUZZER - 32); |
||||
AT91C_BASE_PIOC->PIO_PDR = (1 << 7) | (1 << 8); |
||||
|
||||
/* Power OFF all USART's LEDs */ |
||||
AT91C_BASE_PIOA->PIO_PER = AT91C_PA5_TXD3 | AT91C_PA6_RXD3 | |
||||
AT91C_PA17_TXD0 | AT91C_PA18_RXD0 | AT91C_PA22_RXD2 | \
|
||||
AT91C_PA23_TXD2; |
||||
|
||||
AT91C_BASE_PIOA->PIO_OER = AT91C_PA5_TXD3 | AT91C_PA6_RXD3 | |
||||
AT91C_PA17_TXD0 | AT91C_PA18_RXD0 | AT91C_PA22_RXD2 | \
|
||||
AT91C_PA23_TXD2; |
||||
|
||||
AT91C_BASE_PIOA->PIO_SODR = AT91C_PA5_TXD3 | AT91C_PA6_RXD3 | |
||||
AT91C_PA17_TXD0 | AT91C_PA18_RXD0 | AT91C_PA22_RXD2 | \
|
||||
AT91C_PA23_TXD2; |
||||
|
||||
AT91C_BASE_PIOB->PIO_PER = AT91C_PB20_RXD1 | AT91C_PB21_TXD1; |
||||
AT91C_BASE_PIOB->PIO_OER = AT91C_PB20_RXD1 | AT91C_PB21_TXD1; |
||||
AT91C_BASE_PIOB->PIO_SODR = AT91C_PB20_RXD1 | AT91C_PB21_TXD1; |
||||
} |
||||
|
||||
uchar m501sk_gpio_set(M501SK_PIO io) |
||||
{ |
||||
uchar status = 0xff; |
||||
switch (io) { |
||||
case M501SK_DEBUG_LED1: |
||||
case M501SK_DEBUG_LED2: |
||||
case M501SK_DEBUG_LED3: |
||||
case M501SK_DEBUG_LED4: |
||||
case M501SK_READY_LED: |
||||
AT91C_BASE_PIOD->PIO_SODR = 1 << (io - 96); |
||||
status = AT91C_BASE_PIOD->PIO_ODSR & (1 << (io - 96)); |
||||
break; |
||||
case M501SK_BUZZER: |
||||
AT91C_BASE_PIOB->PIO_SODR = 1 << (io - 32); |
||||
status = AT91C_BASE_PIOB->PIO_ODSR & (1 << (io - 32)); |
||||
break; |
||||
} |
||||
return status; |
||||
} |
||||
|
||||
uchar m501sk_gpio_clear(M501SK_PIO io) |
||||
{ |
||||
uchar status = 0xff; |
||||
switch (io) { |
||||
case M501SK_DEBUG_LED1: |
||||
case M501SK_DEBUG_LED2: |
||||
case M501SK_DEBUG_LED3: |
||||
case M501SK_DEBUG_LED4: |
||||
case M501SK_READY_LED: |
||||
AT91C_BASE_PIOD->PIO_CODR = 1 << (io - 96); |
||||
status = AT91C_BASE_PIOD->PIO_ODSR & (1 << (io - 96)); |
||||
break; |
||||
case M501SK_BUZZER: |
||||
AT91C_BASE_PIOB->PIO_CODR = 1 << (io - 32); |
||||
status = AT91C_BASE_PIOB->PIO_ODSR & (1 << (io - 32)); |
||||
break; |
||||
} |
||||
return status; |
||||
} |
||||
|
||||
void load_sernum_ethaddr(void) |
||||
{ |
||||
return; |
||||
} |
||||
|
||||
/*
|
||||
* Miscelaneous platform dependent initialisations |
||||
*/ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
int board_init(void) |
||||
{ |
||||
/* Enable Ctrlc */ |
||||
console_init_f(); |
||||
|
||||
/* Correct IRDA resistor problem */ |
||||
/* Set PA23_TXD in Output */ |
||||
((AT91PS_PIO)AT91C_BASE_PIOA)->PIO_OER = AT91C_PA23_TXD2; |
||||
|
||||
/* memory and cpu-speed are setup before relocation */ |
||||
/* so we do _nothing_ here */ |
||||
gd->bd->bi_arch_number = MACH_TYPE_M501; |
||||
/* adress of boot parameters */ |
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
||||
m501sk_gpio_init(); |
||||
|
||||
/* Do interrupt init here, because flash needs timers */ |
||||
interrupt_init(); |
||||
flash_init(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
int i = 0; |
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM; |
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; |
||||
|
||||
for (i = 0; i < 500; i++) { |
||||
m501sk_gpio_clear(M501SK_DEBUG_LED3); |
||||
m501sk_gpio_clear(M501SK_BUZZER); |
||||
udelay(250); |
||||
m501sk_gpio_set(M501SK_DEBUG_LED3); |
||||
m501sk_gpio_set(M501SK_BUZZER); |
||||
udelay(80); |
||||
} |
||||
m501sk_gpio_clear(M501SK_BUZZER); |
||||
m501sk_gpio_clear(M501SK_DEBUG_LED3); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_late_init(void) |
||||
{ |
||||
#if defined(CONFIG_CMD_NET) |
||||
eth_init(gd->bd); |
||||
eth_halt(); |
||||
#endif |
||||
|
||||
/* Protect U-Boot, kernel & ramdisk memory addresses */ |
||||
run_command("protect on 10000000 1041ffff", 0); |
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_DRIVER_ETHER |
||||
#if defined(CONFIG_CMD_NET) |
||||
/*
|
||||
* Name: |
||||
* at91rm9200_GetPhyInterface |
||||
* Description: |
||||
* Initialise the interface functions to the PHY |
||||
* Arguments: |
||||
* None |
||||
* Return value: |
||||
* None |
||||
*/ |
||||
void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) |
||||
{ |
||||
p_phyops->Init = dm9161_InitPhy; |
||||
p_phyops->IsPhyConnected = dm9161_IsPhyConnected; |
||||
p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed; |
||||
p_phyops->AutoNegotiate = dm9161_AutoNegotiate; |
||||
} |
||||
#endif /* CONFIG_CMD_NET */ |
||||
#endif /* CONFIG_DRIVER_ETHER */ |
||||
#endif /* CONFIG_M501SK */ |
||||
@ -0,0 +1,167 @@ |
||||
/*
|
||||
* linux/include/asm-arm/arch-at91/hardware.h |
||||
* |
||||
* Copyright (C) 2003 SAN People |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
||||
*/ |
||||
#ifndef __M501SK_H |
||||
#define __M501SK_H |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
#include <asm-arm/arch-at91rm9200/AT91RM9200.h> |
||||
#else |
||||
#include <asm-arm/arch-at91rm9200/AT91RM9200_inc.h> |
||||
#endif |
||||
|
||||
#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) /* Pin Controlled by PA22 */ |
||||
#define AT91C_PA22_RXD2 ((unsigned int) AT91C_PIO_PA22) /* USART 2 RxD */ |
||||
#define AT91C_PA5_TXD3 ((unsigned int) 1 << 5) /* USART 3 TxD */ |
||||
#define AT91C_PA6_RXD3 ((unsigned int) 1 << 6) /* USART 3 RxD */ |
||||
|
||||
/* ========== Register definition for PIOD peripheral ========== */ |
||||
#define AT91C_PIOD_PDSR ((AT91_REG *) 0xFFFFFA3C) /* Pin Data stat Reg */ |
||||
#define AT91C_PIOD_CODR ((AT91_REG *) 0xFFFFFA34) /* Clear Output Data Reg */ |
||||
#define AT91C_PIOD_OWER ((AT91_REG *) 0xFFFFFAA0) /* Output Write Enable Reg */ |
||||
#define AT91C_PIOD_MDER ((AT91_REG *) 0xFFFFFA50) /* Multi-driver Enable Reg */ |
||||
#define AT91C_PIOD_IMR ((AT91_REG *) 0xFFFFFA48) /* Interrupt Mask Reg */ |
||||
#define AT91C_PIOD_IER ((AT91_REG *) 0xFFFFFA40) /* Interrupt Enable Reg */ |
||||
#define AT91C_PIOD_ODSR ((AT91_REG *) 0xFFFFFA38) /* Output Data stat Reg */ |
||||
#define AT91C_PIOD_SODR ((AT91_REG *) 0xFFFFFA30) /* Set Output Data Reg */ |
||||
#define AT91C_PIOD_PER ((AT91_REG *) 0xFFFFFA00) /* PIO Enable Reg */ |
||||
#define AT91C_PIOD_OWDR ((AT91_REG *) 0xFFFFFAA4) /* Output Write Disable Reg */ |
||||
#define AT91C_PIOD_PPUER ((AT91_REG *) 0xFFFFFA64) /* Pull-up Enable Reg */ |
||||
#define AT91C_PIOD_MDDR ((AT91_REG *) 0xFFFFFA54) /* Multi-driver Disable Reg */ |
||||
#define AT91C_PIOD_ISR ((AT91_REG *) 0xFFFFFA4C) /* Interrupt stat Reg */ |
||||
#define AT91C_PIOD_IDR ((AT91_REG *) 0xFFFFFA44) /* Interrupt Disable Reg */ |
||||
#define AT91C_PIOD_PDR ((AT91_REG *) 0xFFFFFA04) /* PIO Disable Reg */ |
||||
#define AT91C_PIOD_ODR ((AT91_REG *) 0xFFFFFA14) /* Output Disable Regr */ |
||||
#define AT91C_PIOD_OWSR ((AT91_REG *) 0xFFFFFAA8) /* Output Write stat Reg */ |
||||
#define AT91C_PIOD_ABSR ((AT91_REG *) 0xFFFFFA78) /* AB Select stat Reg */ |
||||
#define AT91C_PIOD_ASR ((AT91_REG *) 0xFFFFFA70) /* Select A Reg */ |
||||
#define AT91C_PIOD_PPUSR ((AT91_REG *) 0xFFFFFA68) /* Pad Pull-up stat Reg */ |
||||
#define AT91C_PIOD_PPUDR ((AT91_REG *) 0xFFFFFA60) /* Pull-up Disable Reg */ |
||||
#define AT91C_PIOD_MDSR ((AT91_REG *) 0xFFFFFA58) /* Multi-driver stat Reg */ |
||||
#define AT91C_PIOD_PSR ((AT91_REG *) 0xFFFFFA08) /* PIO stat Reg */ |
||||
#define AT91C_PIOD_OER ((AT91_REG *) 0xFFFFFA10) /* Output Enable Reg */ |
||||
#define AT91C_PIOD_OSR ((AT91_REG *) 0xFFFFFA18) /* Output stat Reg */ |
||||
#define AT91C_PIOD_IFER ((AT91_REG *) 0xFFFFFA20) /* Input Filter Enable Reg */ |
||||
#define AT91C_PIOD_BSR ((AT91_REG *) 0xFFFFFA74) /* Select B Reg */ |
||||
#define AT91C_PIOD_IFDR ((AT91_REG *) 0xFFFFFA24) /* Input Filter Disable Reg */ |
||||
#define AT91C_PIOD_IFSR ((AT91_REG *) 0xFFFFFA28) /* Input Filter stat Reg */ |
||||
|
||||
#define AT91C_PIO_PD0 ((unsigned int) 1 << 0) /* Pin Controlled by PD0 */ |
||||
#define AT91C_PD0_ETX0 ((unsigned int) AT91C_PIO_PD0) /* Enet MAC Tx Data 0*/ |
||||
#define AT91C_PIO_PD1 ((unsigned int) 1 << 1) /* Pin Controlled by PD1 */ |
||||
#define AT91C_PD1_ETX1 ((unsigned int) AT91C_PIO_PD1) /* Enet MAC Tx Data 1*/ |
||||
#define AT91C_PIO_PD10 ((unsigned int) 1 << 10) /* Pin Controlled by PD10 */ |
||||
#define AT91C_PD10_PCK3 ((unsigned int) AT91C_PIO_PD10) /* PMC Prog Clk Oput 3*/ |
||||
#define AT91C_PD10_TPS1 ((unsigned int) AT91C_PIO_PD10) /* ETMARM9 pl stat1 */ |
||||
#define AT91C_PIO_PD11 ((unsigned int) 1 << 11) /* Pin Controlled by PD11 */ |
||||
#define AT91C_PD11_ ((unsigned int) AT91C_PIO_PD11) /* */ |
||||
#define AT91C_PD11_TPS2 ((unsigned int) AT91C_PIO_PD11) /* ETMARM9 pl stat2 */ |
||||
#define AT91C_PIO_PD12 ((unsigned int) 1 << 12) /* Pin Controlled by PD12 */ |
||||
#define AT91C_PD12_ ((unsigned int) AT91C_PIO_PD12) /* */ |
||||
#define AT91C_PD12_TPK0 ((unsigned int) AT91C_PIO_PD12) /* ETM Trace Pkt 0 */ |
||||
#define AT91C_PIO_PD13 ((unsigned int) 1 << 13) /* Pin Controlled by PD13 */ |
||||
#define AT91C_PD13_ ((unsigned int) AT91C_PIO_PD13) /* */ |
||||
#define AT91C_PD13_TPK1 ((unsigned int) AT91C_PIO_PD13) /* ETM Trace Pkt 1 */ |
||||
#define AT91C_PIO_PD14 ((unsigned int) 1 << 14) /* Pin Controlled by PD14 */ |
||||
#define AT91C_PD14_ ((unsigned int) AT91C_PIO_PD14) /* */ |
||||
#define AT91C_PD14_TPK2 ((unsigned int) AT91C_PIO_PD14) /* ETM Trace Pkt 2 */ |
||||
#define AT91C_PIO_PD15 ((unsigned int) 1 << 15) /* Pin Controlled by PD15 */ |
||||
#define AT91C_PD15_TD0 ((unsigned int) AT91C_PIO_PD15) /* SSC TxD */ |
||||
#define AT91C_PD15_TPK3 ((unsigned int) AT91C_PIO_PD15) /* ETM Trace Pkt 3 */ |
||||
#define AT91C_PIO_PD16 ((unsigned int) 1 << 16) /* Pin Controlled by PD16 */ |
||||
#define AT91C_PD16_TD1 ((unsigned int) AT91C_PIO_PD16) /* SSC TxD 1 */ |
||||
#define AT91C_PD16_TPK4 ((unsigned int) AT91C_PIO_PD16) /* ETM Trace Pkt 4 */ |
||||
#define AT91C_PIO_PD17 ((unsigned int) 1 << 17) /* Pin Controlled by PD17 */ |
||||
#define AT91C_PD17_TD2 ((unsigned int) AT91C_PIO_PD17) /* SSC TxD 2 */ |
||||
#define AT91C_PD17_TPK5 ((unsigned int) AT91C_PIO_PD17) /* ETM Trace Pkt 5 */ |
||||
#define AT91C_PIO_PD18 ((unsigned int) 1 << 18) /* Pin Controlled by PD18 */ |
||||
#define AT91C_PD18_NPCS1 ((unsigned int) AT91C_PIO_PD18) /* SPI Perip CS 1 */ |
||||
#define AT91C_PD18_TPK6 ((unsigned int) AT91C_PIO_PD18) /* ETM Trace Pkt 6 */ |
||||
#define AT91C_PIO_PD19 ((unsigned int) 1 << 19) /* Pin Controlled by PD19 */ |
||||
#define AT91C_PD19_NPCS2 ((unsigned int) AT91C_PIO_PD19) /* SPI Perip CS 2 */ |
||||
#define AT91C_PD19_TPK7 ((unsigned int) AT91C_PIO_PD19) /* ETM Trace Pkt 7 */ |
||||
#define AT91C_PIO_PD2 ((unsigned int) 1 << 2) /* Pin Controlled by PD2 */ |
||||
#define AT91C_PD2_ETX2 ((unsigned int) AT91C_PIO_PD2) /* Ethernet MAC TxD 2 */ |
||||
#define AT91C_PIO_PD20 ((unsigned int) 1 << 20) /* Pin Controlled by PD20 */ |
||||
#define AT91C_PD20_NPCS3 ((unsigned int) AT91C_PIO_PD20) /* SPI Perip CS 3 */ |
||||
#define AT91C_PD20_TPK8 ((unsigned int) AT91C_PIO_PD20) /* ETM Trace Pkt 8 */ |
||||
#define AT91C_PIO_PD21 ((unsigned int) 1 << 21) /* Pin Controlled by PD21 */ |
||||
#define AT91C_PD21_RTS0 ((unsigned int) AT91C_PIO_PD21) /* Usart 0 RTS */ |
||||
#define AT91C_PD21_TPK9 ((unsigned int) AT91C_PIO_PD21) /* ETM Trace Pkt 9 */ |
||||
#define AT91C_PIO_PD22 ((unsigned int) 1 << 22) /* Pin Controlled by PD22 */ |
||||
#define AT91C_PD22_RTS1 ((unsigned int) AT91C_PIO_PD22) /* Usart 0 RTS */ |
||||
#define AT91C_PD22_TPK10 ((unsigned int) AT91C_PIO_PD22) /* ETM Trace Pkt 10 */ |
||||
#define AT91C_PIO_PD23 ((unsigned int) 1 << 23) /* Pin Controlled by PD23 */ |
||||
#define AT91C_PD23_RTS2 ((unsigned int) AT91C_PIO_PD23) /* USART 2 RTS */ |
||||
#define AT91C_PD23_TPK11 ((unsigned int) AT91C_PIO_PD23) /* ETM Trace Pkt 11 */ |
||||
#define AT91C_PIO_PD24 ((unsigned int) 1 << 24) /* Pin Controlled by PD24 */ |
||||
#define AT91C_PD24_RTS3 ((unsigned int) AT91C_PIO_PD24) /* USART 3 RTS */ |
||||
#define AT91C_PD24_TPK12 ((unsigned int) AT91C_PIO_PD24) /* ETM Trace Pkt 12 */ |
||||
#define AT91C_PIO_PD25 ((unsigned int) 1 << 25) /* Pin Controlled by PD25 */ |
||||
#define AT91C_PD25_DTR1 ((unsigned int) AT91C_PIO_PD25) /* USART 1 DTR */ |
||||
#define AT91C_PD25_TPK13 ((unsigned int) AT91C_PIO_PD25) /* ETM Trace Pkt 13 */ |
||||
#define AT91C_PIO_PD26 ((unsigned int) 1 << 26) /* Pin Controlled by PD26 */ |
||||
#define AT91C_PD26_TPK14 ((unsigned int) AT91C_PIO_PD26) /* ETM Trace Pkt 14 */ |
||||
#define AT91C_PIO_PD27 ((unsigned int) 1 << 27) /* Pin Controlled by PD27 */ |
||||
#define AT91C_PD27_TPK15 ((unsigned int) AT91C_PIO_PD27) /* ETM Trace Pkt 15 */ |
||||
#define AT91C_PIO_PD3 ((unsigned int) 1 << 3) /* Pin Controlled by PD3 */ |
||||
#define AT91C_PD3_ETX3 ((unsigned int) AT91C_PIO_PD3) /* Enet MAC TxD 3 */ |
||||
#define AT91C_PIO_PD4 ((unsigned int) 1 << 4) /* Pin Controlled by PD4 */ |
||||
#define AT91C_PD4_ETXEN ((unsigned int) AT91C_PIO_PD4) /* Enet MAC TxEn */ |
||||
#define AT91C_PIO_PD5 ((unsigned int) 1 << 5) /* Pin Controlled by PD5 */ |
||||
#define AT91C_PD5_ETXER ((unsigned int) AT91C_PIO_PD5) /* Enet MAC TxCE */ |
||||
#define AT91C_PIO_PD6 ((unsigned int) 1 << 6) /* Pin Controlled by PD6 */ |
||||
#define AT91C_PD6_DTXD ((unsigned int) AT91C_PIO_PD6) /* DBGU Debug TxD */ |
||||
#define AT91C_PIO_PD7 ((unsigned int) 1 << 7) /* Pin Controlled by PD7 */ |
||||
#define AT91C_PD7_PCK0 ((unsigned int) AT91C_PIO_PD7) /* PMC Prog Clk Oput 0*/ |
||||
#define AT91C_PD7_TSYNC ((unsigned int) AT91C_PIO_PD7) /* ETM Sync signal */ |
||||
#define AT91C_PIO_PD8 ((unsigned int) 1 << 8) /* Pin Controlled by PD8 */ |
||||
#define AT91C_PD8_PCK1 ((unsigned int) AT91C_PIO_PD8) /* PMC Prog Clk Oput 1*/ |
||||
#define AT91C_PD8_TCLK ((unsigned int) AT91C_PIO_PD8) /* ETM Trace Clk sig */ |
||||
#define AT91C_PIO_PD9 ((unsigned int) 1 << 9) /* Pin Controlled by PD9 */ |
||||
#define AT91C_PD9_PCK2 ((unsigned int) AT91C_PIO_PD9) /* PMC Prog Clk 2 */ |
||||
#define AT91C_PD9_TPS0 ((unsigned int) AT91C_PIO_PD9) /* ETM ARM9 pl stat0 */ |
||||
#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */ |
||||
#define AT91C_PIO_PC5 ((unsigned int) 1 << 5) |
||||
#define AT91C_PIO_PC14 ((unsigned int) 1 << 14) /* Pin Controlled by PC1 */ |
||||
#define AT91C_PIO_PC15 ((unsigned int) 1 << 15) /* Pin Controlled by PC1 */ |
||||
#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) /* Pin Controlled by PC1 */ |
||||
#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) /* Pin Controlled by PC1 */ |
||||
#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) |
||||
#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) |
||||
#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) |
||||
#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) |
||||
#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) |
||||
#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) |
||||
#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) |
||||
|
||||
typedef enum { |
||||
M501SK_BUZZER = 38, |
||||
M501SK_DEBUG_LED1 = 96, |
||||
M501SK_DEBUG_LED2, |
||||
M501SK_DEBUG_LED3, |
||||
M501SK_DEBUG_LED4, |
||||
M501SK_READY_LED = 102, |
||||
} M501SK_PIO; |
||||
|
||||
void m501sk_gpio_init(void); |
||||
uchar m501sk_gpio_set(M501SK_PIO io); |
||||
uchar m501sk_gpio_clear(M501SK_PIO io); |
||||
|
||||
#endif |
||||
@ -0,0 +1,200 @@ |
||||
/* |
||||
* Memory Setup stuff - taken from blob memsetup.S |
||||
* |
||||
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
|
||||
* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
|
||||
* |
||||
* Modified for the at91rm9200dk board by |
||||
* (C) Copyright 2004 |
||||
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <version.h> |
||||
|
||||
#ifdef CONFIG_BOOTBINFUNC |
||||
/* |
||||
* some parameters for the board |
||||
* |
||||
* This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in |
||||
* turn is based on the boot.bin code from ATMEL |
||||
* |
||||
*/ |
||||
|
||||
/* flash */ |
||||
#define MC_PUIA 0xFFFFFF10 |
||||
#define MC_PUIA_VAL 0x00000000 |
||||
#define MC_PUP 0xFFFFFF50 |
||||
#define MC_PUP_VAL 0x00000000 |
||||
#define MC_PUER 0xFFFFFF54 |
||||
#define MC_PUER_VAL 0x00000000 |
||||
#define MC_ASR 0xFFFFFF04 |
||||
#define MC_ASR_VAL 0x00000000 |
||||
#define MC_AASR 0xFFFFFF08 |
||||
#define MC_AASR_VAL 0x00000000 |
||||
#define EBI_CFGR 0xFFFFFF64 |
||||
#define EBI_CFGR_VAL 0x00000000 |
||||
#define SMC2_CSR 0xFFFFFF70 |
||||
#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ |
||||
|
||||
/* clocks */ |
||||
#define PLLAR 0xFFFFFC28 |
||||
#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ |
||||
#define PLLBR 0xFFFFFC2C |
||||
#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ |
||||
#define MCKR 0xFFFFFC30 |
||||
/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ |
||||
#define MCKR_VAL 0x00000202 |
||||
|
||||
/* sdram */ |
||||
#define PIOC_ASR 0xFFFFF870 |
||||
#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as Perip (D16/D31) */ |
||||
#define PIOC_BSR 0xFFFFF874 |
||||
#define PIOC_BSR_VAL 0x00000000 |
||||
#define PIOC_PDR 0xFFFFF804 |
||||
#define PIOC_PDR_VAL 0xFFFF0000 |
||||
#define EBI_CSA 0xFFFFFF60 |
||||
#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ |
||||
#define SDRC_CR 0xFFFFFF98 |
||||
#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */ |
||||
#define SDRAM 0x20000000 /* address of the SDRAM */ |
||||
#define SDRAM1 0x20000080 /* address of the SDRAM */ |
||||
#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ |
||||
#define SDRC_MR 0xFFFFFF90 |
||||
#define SDRC_MR_VAL 0x00000002 /* Precharge All */ |
||||
#define SDRC_MR_VAL1 0x00000004 /* refresh */ |
||||
#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ |
||||
#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ |
||||
#define SDRC_TR 0xFFFFFF94 |
||||
#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ |
||||
|
||||
_TEXT_BASE: |
||||
.word TEXT_BASE
|
||||
|
||||
.globl lowlevelinit
|
||||
lowlevelinit: |
||||
/* memory control configuration */ |
||||
/* this isn't very elegant, but what the heck */ |
||||
ldr r0, =SMRDATA |
||||
ldr r1, _TEXT_BASE |
||||
sub r0, r0, r1 |
||||
add r2, r0, #80 |
||||
0: |
||||
/* the address */ |
||||
ldr r1, [r0], #4 |
||||
/* the value */ |
||||
ldr r3, [r0], #4 |
||||
str r3, [r1] |
||||
cmp r2, r0 |
||||
bne 0b |
||||
/* delay - this is all done by guess */ |
||||
ldr r0, =0x00010000 |
||||
1: |
||||
subs r0, r0, #1 |
||||
bhi 1b |
||||
ldr r0, =SMRDATA1 |
||||
ldr r1, _TEXT_BASE |
||||
sub r0, r0, r1 |
||||
add r2, r0, #176 |
||||
2: |
||||
/* the address */ |
||||
ldr r1, [r0], #4 |
||||
/* the value */ |
||||
ldr r3, [r0], #4 |
||||
str r3, [r1] |
||||
cmp r2, r0 |
||||
bne 2b |
||||
|
||||
/* everything is fine now */ |
||||
mov pc, lr |
||||
|
||||
.ltorg |
||||
|
||||
SMRDATA: |
||||
.word MC_PUIA
|
||||
.word MC_PUIA_VAL
|
||||
.word MC_PUP
|
||||
.word MC_PUP_VAL
|
||||
.word MC_PUER
|
||||
.word MC_PUER_VAL
|
||||
.word MC_ASR
|
||||
.word MC_ASR_VAL
|
||||
.word MC_AASR
|
||||
.word MC_AASR_VAL
|
||||
.word EBI_CFGR
|
||||
.word EBI_CFGR_VAL
|
||||
.word SMC2_CSR
|
||||
.word SMC2_CSR_VAL
|
||||
.word PLLAR
|
||||
.word PLLAR_VAL
|
||||
.word PLLBR
|
||||
.word PLLBR_VAL
|
||||
.word MCKR
|
||||
.word MCKR_VAL
|
||||
/* SMRDATA is 80 bytes long */ |
||||
/* here there's a delay of 100 */ |
||||
SMRDATA1: |
||||
.word PIOC_ASR
|
||||
.word PIOC_ASR_VAL
|
||||
.word PIOC_BSR
|
||||
.word PIOC_BSR_VAL
|
||||
.word PIOC_PDR
|
||||
.word PIOC_PDR_VAL
|
||||
.word EBI_CSA
|
||||
.word EBI_CSA_VAL
|
||||
.word SDRC_CR
|
||||
.word SDRC_CR_VAL
|
||||
.word SDRC_MR
|
||||
.word SDRC_MR_VAL
|
||||
.word SDRAM
|
||||
.word SDRAM_VAL
|
||||
.word SDRC_MR
|
||||
.word SDRC_MR_VAL1
|
||||
.word SDRAM
|
||||
.word SDRAM_VAL
|
||||
.word SDRAM
|
||||
.word SDRAM_VAL
|
||||
.word SDRAM
|
||||
.word SDRAM_VAL
|
||||
.word SDRAM
|
||||
.word SDRAM_VAL
|
||||
.word SDRAM
|
||||
.word SDRAM_VAL
|
||||
.word SDRAM
|
||||
.word SDRAM_VAL
|
||||
.word SDRAM
|
||||
.word SDRAM_VAL
|
||||
.word SDRAM
|
||||
.word SDRAM_VAL
|
||||
.word SDRC_MR
|
||||
.word SDRC_MR_VAL2
|
||||
.word SDRAM1
|
||||
.word SDRAM_VAL
|
||||
.word SDRC_TR
|
||||
.word SDRC_TR_VAL
|
||||
.word SDRAM
|
||||
.word SDRAM_VAL
|
||||
.word SDRC_MR
|
||||
.word SDRC_MR_VAL3
|
||||
.word SDRAM
|
||||
.word SDRAM_VAL
|
||||
/* SMRDATA1 is 176 bytes long */ |
||||
#endif /* CONFIG_BOOTBINFUNC */ |
||||
@ -0,0 +1,55 @@ |
||||
/* |
||||
* (C) Copyright 2002 |
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
||||
OUTPUT_ARCH(arm) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
|
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
cpu/arm920t/start.o (.text) |
||||
*(.text) |
||||
} |
||||
|
||||
. = ALIGN(4); |
||||
.rodata : { *(.rodata) } |
||||
|
||||
. = ALIGN(4); |
||||
.data : { *(.data) } |
||||
|
||||
. = ALIGN(4); |
||||
.got : { *(.got) } |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
. = ALIGN(4); |
||||
__bss_start = .; |
||||
.bss : { *(.bss) } |
||||
_end = .; |
||||
} |
||||
@ -0,0 +1,46 @@ |
||||
#
|
||||
# (C) Copyright 2000-2008
|
||||
# Wolfgang Denk, DENX Software Engineering, wd <at> denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(SOC).a
|
||||
|
||||
COBJS = ether.o timer.o spi.o usb.o
|
||||
SOBJS = lowlevel_init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
|
||||
all: $(obj).depend $(LIB) |
||||
|
||||
$(LIB): $(OBJS) |
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,2 @@ |
||||
PLATFORM_CPPFLAGS += -march=armv5te
|
||||
PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,)
|
||||
@ -0,0 +1,35 @@ |
||||
/*
|
||||
* (C) Copyright 2007-2008 |
||||
* Stelian Pop <stelian.pop <at> leadtechdesign.com> |
||||
* Lead Tech Design <www.leadtechdesign.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/AT91CAP9.h> |
||||
|
||||
extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); |
||||
|
||||
#if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET) |
||||
void at91cap9_eth_initialize(bd_t *bi) |
||||
{ |
||||
macb_eth_initialize(0, (void *)AT91C_BASE_MACB, 0x00); |
||||
} |
||||
#endif |
||||
@ -0,0 +1,43 @@ |
||||
/* |
||||
* AT91CAP9 setup stuff |
||||
* |
||||
* (C) Copyright 2007-2008 |
||||
* Stelian Pop <stelian.pop <at> leadtechdesign.com> |
||||
* Lead Tech Design <www.leadtechdesign.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <version.h> |
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT |
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init: |
||||
|
||||
/* |
||||
* Clocks/SDRAM initialization is handled by at91bootstrap, |
||||
* no need to do it here... |
||||
*/ |
||||
mov pc, lr |
||||
|
||||
.ltorg |
||||
|
||||
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ |
||||
@ -0,0 +1,119 @@ |
||||
/*
|
||||
* Driver for ATMEL DataFlash support |
||||
* Author : Hamid Ikdoumi (Atmel) |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <common.h> |
||||
#include <asm/hardware.h> |
||||
|
||||
#ifdef CONFIG_HAS_DATAFLASH |
||||
#include <dataflash.h> |
||||
|
||||
/* Max Value = 10MHz to be compliant to the Continuous Array Read function */ |
||||
#define AT91C_SPI_CLK 10000000 |
||||
|
||||
/* AC Characteristics: DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ |
||||
#define DATAFLASH_TCSS (0xFA << 16) |
||||
#define DATAFLASH_TCHS (0x8 << 24) |
||||
|
||||
#define AT91C_TIMEOUT_WRDY 200000 |
||||
#define AT91C_SPI_PCS0_DATAFLASH_CARD 0xE /* Chip Select 0: NPCS0%1110 */ |
||||
#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */ |
||||
|
||||
void AT91F_SpiInit(void) |
||||
{ |
||||
/* Reset the SPI */ |
||||
AT91C_BASE_SPI0->SPI_CR = AT91C_SPI_SWRST; |
||||
|
||||
/* Configure SPI in Master Mode with No CS selected !!! */ |
||||
AT91C_BASE_SPI0->SPI_MR = |
||||
AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS; |
||||
|
||||
/* Configure CS0 */ |
||||
AT91C_BASE_SPI0->SPI_CSR[0] = |
||||
AT91C_SPI_CPOL | |
||||
(AT91C_SPI_DLYBS & DATAFLASH_TCSS) | |
||||
(AT91C_SPI_DLYBCT & DATAFLASH_TCHS) | |
||||
((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); |
||||
} |
||||
|
||||
void AT91F_SpiEnable(int cs) |
||||
{ |
||||
switch (cs) { |
||||
case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ |
||||
AT91C_BASE_SPI0->SPI_MR &= 0xFFF0FFFF; |
||||
AT91C_BASE_SPI0->SPI_MR |= |
||||
((AT91C_SPI_PCS0_DATAFLASH_CARD<<16) & AT91C_SPI_PCS); |
||||
break; |
||||
case 3: |
||||
AT91C_BASE_SPI0->SPI_MR &= 0xFFF0FFFF; |
||||
AT91C_BASE_SPI0->SPI_MR |= |
||||
((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS); |
||||
break; |
||||
} |
||||
|
||||
/* SPI_Enable */ |
||||
AT91C_BASE_SPI0->SPI_CR = AT91C_SPI_SPIEN; |
||||
} |
||||
|
||||
unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc) |
||||
{ |
||||
unsigned int timeout; |
||||
|
||||
pDesc->state = BUSY; |
||||
|
||||
AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; |
||||
|
||||
/* Initialize the Transmit and Receive Pointer */ |
||||
AT91C_BASE_SPI0->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt; |
||||
AT91C_BASE_SPI0->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt; |
||||
|
||||
/* Intialize the Transmit and Receive Counters */ |
||||
AT91C_BASE_SPI0->SPI_RCR = pDesc->rx_cmd_size; |
||||
AT91C_BASE_SPI0->SPI_TCR = pDesc->tx_cmd_size; |
||||
|
||||
if (pDesc->tx_data_size != 0) { |
||||
/* Initialize the Next Transmit and Next Receive Pointer */ |
||||
AT91C_BASE_SPI0->SPI_RNPR = (unsigned int)pDesc->rx_data_pt; |
||||
AT91C_BASE_SPI0->SPI_TNPR = (unsigned int)pDesc->tx_data_pt; |
||||
|
||||
/* Intialize the Next Transmit and Next Receive Counters */ |
||||
AT91C_BASE_SPI0->SPI_RNCR = pDesc->rx_data_size; |
||||
AT91C_BASE_SPI0->SPI_TNCR = pDesc->tx_data_size; |
||||
} |
||||
|
||||
/* arm simple, non interrupt dependent timer */ |
||||
reset_timer_masked(); |
||||
timeout = 0; |
||||
|
||||
AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN; |
||||
while (!(AT91C_BASE_SPI0->SPI_SR & AT91C_SPI_RXBUFF) && |
||||
((timeout = get_timer_masked()) < CFG_SPI_WRITE_TOUT)); |
||||
AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; |
||||
pDesc->state = IDLE; |
||||
|
||||
if (timeout >= CFG_SPI_WRITE_TOUT) { |
||||
printf("Error Timeout\n\r"); |
||||
return DATAFLASH_ERROR; |
||||
} |
||||
|
||||
return DATAFLASH_OK; |
||||
} |
||||
#endif |
||||
@ -0,0 +1,149 @@ |
||||
/*
|
||||
* (C) Copyright 2007-2008 |
||||
* Stelian Pop <stelian.pop <at> leadtechdesign.com> |
||||
* Lead Tech Design <www.leadtechdesign.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/hardware.h> |
||||
|
||||
/*
|
||||
* We're using the AT91CAP9 PITC in 32 bit mode, by |
||||
* setting the 20 bit counter period to its maximum (0xfffff). |
||||
*/ |
||||
#define TIMER_LOAD_VAL 0xfffff |
||||
#define READ_RESET_TIMER (AT91C_BASE_PITC->PITC_PIVR) |
||||
#define READ_TIMER (AT91C_BASE_PITC->PITC_PIIR) |
||||
#define TIMER_FREQ (AT91C_MASTER_CLOCK << 4) |
||||
#define TICKS_TO_USEC(ticks) ((ticks) / 6) |
||||
|
||||
ulong get_timer_masked(void); |
||||
ulong resettime; |
||||
|
||||
AT91PS_PITC p_pitc; |
||||
|
||||
/* nothing really to do with interrupts, just starts up a counter. */ |
||||
int interrupt_init(void) |
||||
{ |
||||
/*
|
||||
* Enable PITC Clock |
||||
* The clock is already enabled for system controller in boot |
||||
*/ |
||||
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SYS; |
||||
|
||||
/* Enable PITC */ |
||||
AT91C_BASE_PITC->PITC_PIMR = AT91C_PITC_PITEN; |
||||
|
||||
/* Load PITC_PIMR with the right timer value */ |
||||
AT91C_BASE_PITC->PITC_PIMR |= TIMER_LOAD_VAL; |
||||
|
||||
reset_timer_masked(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* timer without interrupts |
||||
*/ |
||||
|
||||
static inline ulong get_timer_raw(void) |
||||
{ |
||||
ulong now = READ_TIMER; |
||||
if (now >= resettime) |
||||
return now - resettime; |
||||
else |
||||
return 0xFFFFFFFFUL - (resettime - now) ; |
||||
} |
||||
|
||||
void reset_timer_masked(void) |
||||
{ |
||||
resettime = READ_TIMER; |
||||
} |
||||
|
||||
ulong get_timer_masked(void) |
||||
{ |
||||
return TICKS_TO_USEC(get_timer_raw()); |
||||
|
||||
} |
||||
|
||||
void udelay_masked(unsigned long usec) |
||||
{ |
||||
ulong tmp; |
||||
|
||||
tmp = get_timer(0); |
||||
while (get_timer(tmp) < usec) /* our timer works in usecs */ |
||||
; /* NOP */ |
||||
} |
||||
|
||||
void reset_timer(void) |
||||
{ |
||||
reset_timer_masked(); |
||||
} |
||||
|
||||
ulong get_timer(ulong base) |
||||
{ |
||||
ulong now = get_timer_masked(); |
||||
|
||||
if (now >= base) |
||||
return now - base; |
||||
else |
||||
return TICKS_TO_USEC(0xFFFFFFFFUL) - (base - now) ; |
||||
} |
||||
|
||||
void udelay(unsigned long usec) |
||||
{ |
||||
udelay_masked(usec); |
||||
} |
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (read timebase as long long). |
||||
* On ARM it just returns the timer value. |
||||
*/ |
||||
unsigned long long get_ticks(void) |
||||
{ |
||||
return get_timer(0); |
||||
} |
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (timebase clock frequency). |
||||
* On ARM it returns the number of timer ticks per second. |
||||
*/ |
||||
ulong get_tbclk(void) |
||||
{ |
||||
ulong tbclk; |
||||
tbclk = CFG_HZ; |
||||
return tbclk; |
||||
} |
||||
|
||||
/*
|
||||
* Reset the cpu by setting up the watchdog timer and let him time out |
||||
* on the AT91CAP9ADK board |
||||
*/ |
||||
void reset_cpu(ulong ignored) |
||||
{ |
||||
/* this is the way Linux does it */ |
||||
AT91C_BASE_RSTC->RSTC_RCR = (0xA5 << 24) | |
||||
AT91C_RSTC_PROCRST | |
||||
AT91C_RSTC_PERRST; |
||||
|
||||
while (1); |
||||
/* Never reached */ |
||||
} |
||||
@ -0,0 +1,54 @@ |
||||
/*
|
||||
* (C) Copyright 2006 |
||||
* DENX Software Engineering <mk <at> denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) |
||||
#ifdef CONFIG_AT91CAP9 |
||||
|
||||
#include <asm/arch/hardware.h> |
||||
|
||||
int usb_cpu_init(void) |
||||
{ |
||||
/* Enable USB host clock. */ |
||||
AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_UHP; |
||||
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_UHP; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int usb_cpu_stop(void) |
||||
{ |
||||
/* Disable USB host clock. */ |
||||
AT91C_BASE_PMC->PMC_PCDR = 1 << AT91C_ID_UHP; |
||||
AT91C_BASE_PMC->PMC_SCDR = AT91C_PMC_UHP; |
||||
return 0; |
||||
} |
||||
|
||||
int usb_cpu_init_fail(void) |
||||
{ |
||||
return usb_cpu_stop(); |
||||
} |
||||
|
||||
#endif /* CONFIG_AT91CAP9 */ |
||||
#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */ |
||||
@ -0,0 +1,518 @@ |
||||
/*
|
||||
* (C) Copyright 2008 |
||||
* AT91CAP9 definitions |
||||
* Author : ATMEL AT91 application group |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef AT91CAP9_H |
||||
#define AT91CAP9_H |
||||
|
||||
typedef volatile unsigned int AT91_REG; |
||||
|
||||
/* Static Memory Controller */ |
||||
typedef struct _AT91S_SMC { |
||||
AT91_REG SMC_SETUP0; /* Setup Register for CS 0 */ |
||||
AT91_REG SMC_PULSE0; /* Pulse Register for CS 0 */ |
||||
AT91_REG SMC_CYCLE0; /* Cycle Register for CS 0 */ |
||||
AT91_REG SMC_CTRL0; /* Control Register for CS 0 */ |
||||
AT91_REG SMC_SETUP1; /* Setup Register for CS 1 */ |
||||
AT91_REG SMC_PULSE1; /* Pulse Register for CS 1 */ |
||||
AT91_REG SMC_CYCLE1; /* Cycle Register for CS 1 */ |
||||
AT91_REG SMC_CTRL1; /* Control Register for CS 1 */ |
||||
AT91_REG SMC_SETUP2; /* Setup Register for CS 2 */ |
||||
AT91_REG SMC_PULSE2; /* Pulse Register for CS 2 */ |
||||
AT91_REG SMC_CYCLE2; /* Cycle Register for CS 2 */ |
||||
AT91_REG SMC_CTRL2; /* Control Register for CS 2 */ |
||||
AT91_REG SMC_SETUP3; /* Setup Register for CS 3 */ |
||||
AT91_REG SMC_PULSE3; /* Pulse Register for CS 3 */ |
||||
AT91_REG SMC_CYCLE3; /* Cycle Register for CS 3 */ |
||||
AT91_REG SMC_CTRL3; /* Control Register for CS 3 */ |
||||
AT91_REG SMC_SETUP4; /* Setup Register for CS 4 */ |
||||
AT91_REG SMC_PULSE4; /* Pulse Register for CS 4 */ |
||||
AT91_REG SMC_CYCLE4; /* Cycle Register for CS 4 */ |
||||
AT91_REG SMC_CTRL4; /* Control Register for CS 4 */ |
||||
AT91_REG SMC_SETUP5; /* Setup Register for CS 5 */ |
||||
AT91_REG SMC_PULSE5; /* Pulse Register for CS 5 */ |
||||
AT91_REG SMC_CYCLE5; /* Cycle Register for CS 5 */ |
||||
AT91_REG SMC_CTRL5; /* Control Register for CS 5 */ |
||||
AT91_REG SMC_SETUP6; /* Setup Register for CS 6 */ |
||||
AT91_REG SMC_PULSE6; /* Pulse Register for CS 6 */ |
||||
AT91_REG SMC_CYCLE6; /* Cycle Register for CS 6 */ |
||||
AT91_REG SMC_CTRL6; /* Control Register for CS 6 */ |
||||
AT91_REG SMC_SETUP7; /* Setup Register for CS 7 */ |
||||
AT91_REG SMC_PULSE7; /* Pulse Register for CS 7 */ |
||||
AT91_REG SMC_CYCLE7; /* Cycle Register for CS 7 */ |
||||
AT91_REG SMC_CTRL7; /* Control Register for CS 7 */ |
||||
} AT91S_SMC, *AT91PS_SMC; |
||||
|
||||
/* SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x */ |
||||
#define AT91C_SMC_NWESETUP (0x3F << 0) /* NWE Setup Length */ |
||||
#define AT91C_SMC_NCSSETUPWR (0x3F << 8) /* NCS Setup Length for WRite */ |
||||
#define AT91C_SMC_NRDSETUP (0x3F << 16) /* NRD Setup Length */ |
||||
#define AT91C_SMC_NCSSETUPRD (0x3F << 24) /* NCS Setup Length for ReaD */ |
||||
/* SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x */ |
||||
#define AT91C_SMC_NWEPULSE (0x7F << 0) /* NWE Pulse Length */ |
||||
#define AT91C_SMC_NCSPULSEWR (0x7F << 8) /* NCS Pulse Length for WRite */ |
||||
#define AT91C_SMC_NRDPULSE (0x7F << 16) /* NRD Pulse Length */ |
||||
#define AT91C_SMC_NCSPULSERD (0x7F << 24) /* NCS Pulse Length for ReaD */ |
||||
/* SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x */ |
||||
#define AT91C_SMC_NWECYCLE (0x1FF << 0) /* Total Write Cycle Length */ |
||||
#define AT91C_SMC_NRDCYCLE (0x1FF << 16) /* Total Read Cycle Length */ |
||||
/* SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x */ |
||||
#define AT91C_SMC_READMODE (0x1 << 0) /* Read Mode */ |
||||
#define AT91C_SMC_WRITEMODE (0x1 << 1) /* Write Mode */ |
||||
#define AT91C_SMC_NWAITM (0x3 << 5) /* NWAIT Mode */ |
||||
/* External NWAIT disabled */ |
||||
#define AT91C_SMC_NWAITM_NWAIT_DISABLE (0x0 << 5) |
||||
/* External NWAIT enabled in frozen mode */ |
||||
#define AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN (0x2 << 5) |
||||
/* External NWAIT enabled in ready mode */ |
||||
#define AT91C_SMC_NWAITM_NWAIT_ENABLE_READY (0x3 << 5) |
||||
#define AT91C_SMC_BAT (0x1 << 8) /* Byte Access Type */ |
||||
/*
|
||||
* Write controled by ncs, nbs0, nbs1, nbs2, nbs3. |
||||
* Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3. |
||||
*/ |
||||
#define AT91C_SMC_BAT_BYTE_SELECT (0x0 << 8) |
||||
/*
|
||||
* Write controled by ncs, nwe0, nwe1, nwe2, nwe3. |
||||
* Read controled by ncs and nrd. |
||||
*/ |
||||
#define AT91C_SMC_BAT_BYTE_WRITE (0x1 << 8) |
||||
#define AT91C_SMC_DBW (0x3 << 12) /* Data Bus Width */ |
||||
#define AT91C_SMC_DBW_WIDTH_EIGTH_BITS (0x0 << 12) |
||||
#define AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS (0x1 << 12) |
||||
#define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) |
||||
#define AT91C_SMC_TDF (0xF << 16) /* Data Float Time */ |
||||
#define AT91C_SMC_TDFEN (0x1 << 20) /* TDF Enabled */ |
||||
#define AT91C_SMC_PMEN (0x1 << 24) /* Page Mode Enabled */ |
||||
#define AT91C_SMC_PS (0x3 << 28) /* Page Size */ |
||||
#define AT91C_SMC_PS_SIZE_FOUR_BYTES (0x0 << 28) |
||||
#define AT91C_SMC_PS_SIZE_EIGHT_BYTES (0x1 << 28) |
||||
#define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES (0x2 << 28) |
||||
#define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) |
||||
/* SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x */ |
||||
/* SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x */ |
||||
/* SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x */ |
||||
/* SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x */ |
||||
/* SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x */ |
||||
/* SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x */ |
||||
/* SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x */ |
||||
/* SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x */ |
||||
/* SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x */ |
||||
/* SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x */ |
||||
/* SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x */ |
||||
/* SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x */ |
||||
/* SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x */ |
||||
/* SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x */ |
||||
/* SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x */ |
||||
/* SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x */ |
||||
/* SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x */ |
||||
/* SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x */ |
||||
/* SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x */ |
||||
/* SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x */ |
||||
/* SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x */ |
||||
/* SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x */ |
||||
/* SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x */ |
||||
/* SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x */ |
||||
/* SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x */ |
||||
/* SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x */ |
||||
/* SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x */ |
||||
/* SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x */ |
||||
|
||||
/* AHB CCFG */ |
||||
typedef struct _AT91S_CCFG { |
||||
AT91_REG Reserved0[1]; |
||||
AT91_REG CCFG_MPBS0; /* MPB Slave 0 */ |
||||
AT91_REG CCFG_UDPHS; /* AHB Periphs */ |
||||
AT91_REG CCFG_MPBS1; /* MPB Slave 1 */ |
||||
AT91_REG CCFG_EBICSA; /* EBI Chip Select Assignement */ |
||||
AT91_REG Reserved1[2]; |
||||
AT91_REG CCFG_MPBS2; /* MPB Slave 2 */ |
||||
AT91_REG CCFG_MPBS3; /* MPB Slave 3 */ |
||||
AT91_REG CCFG_BRIDGE; /* APB Bridge */ |
||||
AT91_REG Reserved2[49]; |
||||
AT91_REG CCFG_MATRIXVERSION;/* Version */ |
||||
} AT91S_CCFG, *AT91PS_CCFG; |
||||
|
||||
/* CCFG_UDPHS : (CCFG Offset: 0x8) UDPHS Configuration */ |
||||
#define AT91C_CCFG_UDPHS_UDP_SELECT (0x1 << 31) /* UDPHS or UDP */ |
||||
#define AT91C_CCFG_UDPHS_UDP_SELECT_UDPHS (0x0 << 31) |
||||
#define AT91C_CCFG_UDPHS_UDP_SELECT_UDP (0x1 << 31) |
||||
/* CCFG_EBICSA : (CCFG Offset: 0x10) EBI Chip Select Assignement Register */ |
||||
#define AT91C_EBI_CS1A (0x1 << 1) /* CS1 Assignment */ |
||||
#define AT91C_EBI_CS1A_SMC (0x0 << 1) |
||||
#define AT91C_EBI_CS1A_BCRAMC (0x1 << 1) |
||||
#define AT91C_EBI_CS3A (0x1 << 3) /* CS 3 Assignment */ |
||||
#define AT91C_EBI_CS3A_SMC (0x0 << 3) |
||||
#define AT91C_EBI_CS3A_SM (0x1 << 3) |
||||
#define AT91C_EBI_CS4A (0x1 << 4) /* CS4 Assignment */ |
||||
#define AT91C_EBI_CS4A_SMC (0x0 << 4) |
||||
#define AT91C_EBI_CS4A_CF (0x1 << 4) |
||||
#define AT91C_EBI_CS5A (0x1 << 5) /* CS 5 Assignment */ |
||||
#define AT91C_EBI_CS5A_SMC (0x0 << 5) |
||||
#define AT91C_EBI_CS5A_CF (0x1 << 5) |
||||
#define AT91C_EBI_DBPUC (0x1 << 8) /* Data Bus Pull-up */ |
||||
#define AT91C_EBI_DDRPUC (0x1 << 9) /* DDDR DQS Pull-up */ |
||||
#define AT91C_EBI_SUP (0x1 << 16) /* EBI Supply */ |
||||
#define AT91C_EBI_SUP_1V8 (0x0 << 16) |
||||
#define AT91C_EBI_SUP_3V3 (0x1 << 16) |
||||
#define AT91C_EBI_LP (0x1 << 17) /* EBI Low Power */ |
||||
#define AT91C_EBI_LP_LOW_DRIVE (0x0 << 17) |
||||
#define AT91C_EBI_LP_STD_DRIVE (0x1 << 17) |
||||
#define AT91C_CCFG_DDR_SDR_SELECT (0x1 << 31) /* DDR or SDR */ |
||||
#define AT91C_CCFG_DDR_SDR_SELECT_DDR (0x0 << 31) |
||||
#define AT91C_CCFG_DDR_SDR_SELECT_SDR (0x1 << 31) |
||||
/* CCFG_BRIDGE : (CCFG Offset: 0x24) BRIDGE Configuration */ |
||||
#define AT91C_CCFG_AES_TDES_SELECT (0x1 << 31) /* AES or TDES */ |
||||
#define AT91C_CCFG_AES_TDES_SELECT_AES (0x0 << 31) |
||||
#define AT91C_CCFG_AES_TDES_SELECT_TDES (0x1 << 31) |
||||
|
||||
/* PIO controller */ |
||||
typedef struct _AT91S_PIO { |
||||
AT91_REG PIO_PER; /* PIO Enable Register */ |
||||
AT91_REG PIO_PDR; /* PIO Disable Register */ |
||||
AT91_REG PIO_PSR; /* PIO Status Register */ |
||||
AT91_REG Reserved0[1]; |
||||
AT91_REG PIO_OER; /* Output Enable Register */ |
||||
AT91_REG PIO_ODR; /* Output Disable Register */ |
||||
AT91_REG PIO_OSR; /* Output Status Register */ |
||||
AT91_REG Reserved1[1]; |
||||
AT91_REG PIO_IFER; /* Input Filter Enable Register */ |
||||
AT91_REG PIO_IFDR; /* Input Filter Disable Register */ |
||||
AT91_REG PIO_IFSR; /* Input Filter Status Register */ |
||||
AT91_REG Reserved2[1]; |
||||
AT91_REG PIO_SODR; /* Set Output Data Register */ |
||||
AT91_REG PIO_CODR; /* Clear Output Data Register */ |
||||
AT91_REG PIO_ODSR; /* Output Data Status Register */ |
||||
AT91_REG PIO_PDSR; /* Pin Data Status Register */ |
||||
AT91_REG PIO_IER; /* Interrupt Enable Register */ |
||||
AT91_REG PIO_IDR; /* Interrupt Disable Register */ |
||||
AT91_REG PIO_IMR; /* Interrupt Mask Register */ |
||||
AT91_REG PIO_ISR; /* Interrupt Status Register */ |
||||
AT91_REG PIO_MDER; /* Multi-driver Enable Register */ |
||||
AT91_REG PIO_MDDR; /* Multi-driver Disable Register */ |
||||
AT91_REG PIO_MDSR; /* Multi-driver Status Register */ |
||||
AT91_REG Reserved3[1]; |
||||
AT91_REG PIO_PPUDR; /* Pull-up Disable Register */ |
||||
AT91_REG PIO_PPUER; /* Pull-up Enable Register */ |
||||
AT91_REG PIO_PPUSR; /* Pull-up Status Register */ |
||||
AT91_REG Reserved4[1]; |
||||
AT91_REG PIO_ASR; /* Select A Register */ |
||||
AT91_REG PIO_BSR; /* Select B Register */ |
||||
AT91_REG PIO_ABSR; /* AB Select Status Register */ |
||||
AT91_REG Reserved5[9]; |
||||
AT91_REG PIO_OWER; /* Output Write Enable Register */ |
||||
AT91_REG PIO_OWDR; /* Output Write Disable Register */ |
||||
AT91_REG PIO_OWSR; /* Output Write Status Register */ |
||||
} AT91S_PIO, *AT91PS_PIO; |
||||
|
||||
/* Power Management Controller */ |
||||
typedef struct _AT91S_PMC { |
||||
AT91_REG PMC_SCER; /* System Clock Enable Register */ |
||||
AT91_REG PMC_SCDR; /* System Clock Disable Register */ |
||||
AT91_REG PMC_SCSR; /* System Clock Status Register */ |
||||
AT91_REG Reserved0[1]; |
||||
AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ |
||||
AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ |
||||
AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ |
||||
AT91_REG PMC_UCKR; /* UTMI Clock Configuration Register */ |
||||
AT91_REG PMC_MOR; /* Main Oscillator Register */ |
||||
AT91_REG PMC_MCFR; /* Main Clock Frequency Register */ |
||||
AT91_REG PMC_PLLAR; /* PLL A Register */ |
||||
AT91_REG PMC_PLLBR; /* PLL B Register */ |
||||
AT91_REG PMC_MCKR; /* Master Clock Register */ |
||||
AT91_REG Reserved1[3]; |
||||
AT91_REG PMC_PCKR[8]; /* Programmable Clock Register */ |
||||
AT91_REG PMC_IER; /* Interrupt Enable Register */ |
||||
AT91_REG PMC_IDR; /* Interrupt Disable Register */ |
||||
AT91_REG PMC_SR; /* Status Register */ |
||||
AT91_REG PMC_IMR; /* Interrupt Mask Register */ |
||||
} AT91S_PMC, *AT91PS_PMC; |
||||
|
||||
/* PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register */ |
||||
#define AT91C_PMC_PCK (0x1 << 0) /* Processor Clock */ |
||||
#define AT91C_PMC_OTG (0x1 << 5) /* USB OTG Clock */ |
||||
#define AT91C_PMC_UHP (0x1 << 6) /* USB Host Port Clock */ |
||||
#define AT91C_PMC_UDP (0x1 << 7) /* USB Device Port Clock */ |
||||
#define AT91C_PMC_PCK0 (0x1 << 8) /* Programmable Clock Output */ |
||||
#define AT91C_PMC_PCK1 (0x1 << 9) /* Programmable Clock Output */ |
||||
#define AT91C_PMC_PCK2 (0x1 << 10) /* Programmable Clock Output */ |
||||
#define AT91C_PMC_PCK3 (0x1 << 11) /* Programmable Clock Output */ |
||||
/* PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register */ |
||||
/* PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register */ |
||||
/* CKGR_UCKR : (PMC Offset: 0x1c) UTMI Clock Configuration Register */ |
||||
/* CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register */ |
||||
/* CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register */ |
||||
/* CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register */ |
||||
/* CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register */ |
||||
/* PMC_MCKR : (PMC Offset: 0x30) Master Clock Register */ |
||||
#define AT91C_PMC_CSS (0x3 << 0) /* Clock Selection */ |
||||
#define AT91C_PMC_CSS_SLOW_CLK (0x0 << 0) /* Slow Clk */ |
||||
#define AT91C_PMC_CSS_MAIN_CLK (0x1 << 0) /* Main Clk */ |
||||
#define AT91C_PMC_CSS_PLLA_CLK (0x2 << 0) /* PLL A Clk */ |
||||
#define AT91C_PMC_CSS_PLLB_CLK (0x3 << 0) /* PLL B Clk */ |
||||
#define AT91C_PMC_PRES (0x7 << 2) /* Clock Prescaler */ |
||||
#define AT91C_PMC_PRES_CLK (0x0 << 2) |
||||
#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) |
||||
#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) |
||||
#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) |
||||
#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) |
||||
#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) |
||||
#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) |
||||
#define AT91C_PMC_MDIV (0x3 << 8) /* Master Clock Division */ |
||||
#define AT91C_PMC_MDIV_1 (0x0 << 8) |
||||
#define AT91C_PMC_MDIV_2 (0x1 << 8) |
||||
#define AT91C_PMC_MDIV_4 (0x2 << 8) |
||||
/* PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register */ |
||||
/* PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register */ |
||||
#define AT91C_PMC_MOSCS (0x1 << 0) /* MOSC mask */ |
||||
#define AT91C_PMC_LOCKA (0x1 << 1) /* PLL A mask */ |
||||
#define AT91C_PMC_LOCKB (0x1 << 2) /* PLL B mask */ |
||||
#define AT91C_PMC_MCKRDY (0x1 << 3) /* Master mask */ |
||||
#define AT91C_PMC_LOCKU (0x1 << 6) /* PLL UTMI mask */ |
||||
#define AT91C_PMC_PCK0RDY (0x1 << 8) /* PCK0_RDY mask */ |
||||
#define AT91C_PMC_PCK1RDY (0x1 << 9) /* PCK1_RDY mask */ |
||||
#define AT91C_PMC_PCK2RDY (0x1 << 10) /* PCK2_RDY mask */ |
||||
#define AT91C_PMC_PCK3RDY (0x1 << 11) /* PCK3_RDY mask */ |
||||
/* PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register */ |
||||
/* PMC_SR : (PMC Offset: 0x68) PMC Status Register */ |
||||
/* PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register */ |
||||
|
||||
/* Reset controller */ |
||||
typedef struct _AT91S_RSTC { |
||||
AT91_REG RSTC_RCR; /* Reset Control Register */ |
||||
AT91_REG RSTC_RSR; /* Reset Status Register */ |
||||
AT91_REG RSTC_RMR; /* Reset Mode Register */ |
||||
} AT91S_RSTC, *AT91PS_RSTC; |
||||
|
||||
/* RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register */ |
||||
#define AT91C_RSTC_PROCRST (0x1 << 0) /* Processor Reset */ |
||||
#define AT91C_RSTC_ICERST (0x1 << 1) /* ICE Interface Reset */ |
||||
#define AT91C_RSTC_PERRST (0x1 << 2) /* Peripheral Reset */ |
||||
#define AT91C_RSTC_EXTRST (0x1 << 3) /* External Reset */ |
||||
#define AT91C_RSTC_KEY (0xFF << 24) /* Password */ |
||||
/* RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register */ |
||||
#define AT91C_RSTC_URSTS (0x1 << 0) /* User Reset Status */ |
||||
#define AT91C_RSTC_RSTTYP (0x7 << 8) /* Reset Type */ |
||||
#define AT91C_RSTC_RSTTYP_GENERAL (0x0 << 8) |
||||
#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) |
||||
#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) |
||||
#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) |
||||
#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) |
||||
#define AT91C_RSTC_NRSTL (0x1 << 16) /* NRST pin level */ |
||||
#define AT91C_RSTC_SRCMP (0x1 << 17) /* Software Rst in Progress. */ |
||||
/* RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register */ |
||||
#define AT91C_RSTC_URSTEN (0x1 << 0) /* User Reset Enable */ |
||||
#define AT91C_RSTC_URSTIEN (0x1 << 4) /* User Reset Int. Enable */ |
||||
#define AT91C_RSTC_ERSTL (0xF << 8) /* User Reset Enable */ |
||||
|
||||
/* Periodic Timer Controller */ |
||||
typedef struct _AT91S_PITC { |
||||
AT91_REG PITC_PIMR; /* Period Interval Mode Register */ |
||||
AT91_REG PITC_PISR; /* Period Interval Status Register */ |
||||
AT91_REG PITC_PIVR; /* Period Interval Value Register */ |
||||
AT91_REG PITC_PIIR; /* Period Interval Image Register */ |
||||
} AT91S_PITC, *AT91PS_PITC; |
||||
|
||||
/* PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register */ |
||||
#define AT91C_PITC_PIV (0xFFFFF << 0) /* Periodic Interval Value */ |
||||
#define AT91C_PITC_PITEN (0x1 << 24) /* PIT Enable */ |
||||
#define AT91C_PITC_PITIEN (0x1 << 25) /* PIT Interrupt Enable */ |
||||
/* PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register */ |
||||
#define AT91C_PITC_PITS (0x1 << 0) /* PIT Status */ |
||||
/* PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register */ |
||||
#define AT91C_PITC_CPIV (0xFFFFF << 0) /* Current Value */ |
||||
#define AT91C_PITC_PICNT (0xFFF << 20) /* Periodic Interval Counter */ |
||||
/* PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register */ |
||||
|
||||
/* Serial Paraller Interface */ |
||||
typedef struct _AT91S_SPI { |
||||
AT91_REG SPI_CR; /* Control Register */ |
||||
AT91_REG SPI_MR; /* Mode Register */ |
||||
AT91_REG SPI_RDR; /* Receive Data Register */ |
||||
AT91_REG SPI_TDR; /* Transmit Data Register */ |
||||
AT91_REG SPI_SR; /* Status Register */ |
||||
AT91_REG SPI_IER; /* Interrupt Enable Register */ |
||||
AT91_REG SPI_IDR; /* Interrupt Disable Register */ |
||||
AT91_REG SPI_IMR; /* Interrupt Mask Register */ |
||||
AT91_REG Reserved0[4]; |
||||
AT91_REG SPI_CSR[4]; /* Chip Select Register */ |
||||
AT91_REG Reserved1[48]; |
||||
AT91_REG SPI_RPR; /* Receive Pointer Register */ |
||||
AT91_REG SPI_RCR; /* Receive Counter Register */ |
||||
AT91_REG SPI_TPR; /* Transmit Pointer Register */ |
||||
AT91_REG SPI_TCR; /* Transmit Counter Register */ |
||||
AT91_REG SPI_RNPR; /* Receive Next Pointer Register */ |
||||
AT91_REG SPI_RNCR; /* Receive Next Counter Register */ |
||||
AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */ |
||||
AT91_REG SPI_TNCR; /* Transmit Next Counter Register */ |
||||
AT91_REG SPI_PTCR; /* PDC Transfer Control Register */ |
||||
AT91_REG SPI_PTSR; /* PDC Transfer Status Register */ |
||||
} AT91S_SPI, *AT91PS_SPI; |
||||
|
||||
/* SPI_CR : (SPI Offset: 0x0) SPI Control Register */ |
||||
#define AT91C_SPI_SPIEN (0x1 << 0) /* SPI Enable */ |
||||
#define AT91C_SPI_SPIDIS (0x1 << 1) /* SPI Disable */ |
||||
#define AT91C_SPI_SWRST (0x1 << 7) /* SPI Software reset */ |
||||
#define AT91C_SPI_LASTXFER (0x1 << 24) /* SPI Last Transfer */ |
||||
/* SPI_MR : (SPI Offset: 0x4) SPI Mode Register */ |
||||
#define AT91C_SPI_MSTR (0x1 << 0) /* Master/Slave Mode */ |
||||
#define AT91C_SPI_PS (0x1 << 1) /* Peripheral Select */ |
||||
#define AT91C_SPI_PS_FIXED (0x0 << 1) |
||||
#define AT91C_SPI_PS_VARIABLE (0x1 << 1) |
||||
#define AT91C_SPI_PCSDEC (0x1 << 2) /* Chip Select Decode */ |
||||
#define AT91C_SPI_FDIV (0x1 << 3) /* Clock Selection */ |
||||
#define AT91C_SPI_MODFDIS (0x1 << 4) /* Mode Fault Detection */ |
||||
#define AT91C_SPI_LLB (0x1 << 7) /* Clock Selection */ |
||||
#define AT91C_SPI_PCS (0xF << 16) /* Peripheral Chip Select */ |
||||
#define AT91C_SPI_DLYBCS (0xFF << 24) /* Delay Between Chip Selects */ |
||||
/* SPI_RDR : (SPI Offset: 0x8) Receive Data Register */ |
||||
#define AT91C_SPI_RD (0xFFFF << 0) /* Receive Data */ |
||||
#define AT91C_SPI_RPCS (0xF << 16) /* Peripheral CS Status */ |
||||
/* SPI_TDR : (SPI Offset: 0xc) Transmit Data Register */ |
||||
#define AT91C_SPI_TD (0xFFFF << 0) /* Transmit Data */ |
||||
#define AT91C_SPI_TPCS (0xF << 16) /* Peripheral CS Status */ |
||||
/* SPI_SR : (SPI Offset: 0x10) Status Register */ |
||||
#define AT91C_SPI_RDRF (0x1 << 0) /* Receive Data Register Full */ |
||||
#define AT91C_SPI_TDRE (0x1 << 1) /* Trans. Data Register Empty */ |
||||
#define AT91C_SPI_MODF (0x1 << 2) /* Mode Fault Error */ |
||||
#define AT91C_SPI_OVRES (0x1 << 3) /* Overrun Error Status */ |
||||
#define AT91C_SPI_ENDRX (0x1 << 4) /* End of Receiver Transfer */ |
||||
#define AT91C_SPI_ENDTX (0x1 << 5) /* End of Receiver Transfer */ |
||||
#define AT91C_SPI_RXBUFF (0x1 << 6) /* RXBUFF Interrupt */ |
||||
#define AT91C_SPI_TXBUFE (0x1 << 7) /* TXBUFE Interrupt */ |
||||
#define AT91C_SPI_NSSR (0x1 << 8) /* NSSR Interrupt */ |
||||
#define AT91C_SPI_TXEMPTY (0x1 << 9) /* TXEMPTY Interrupt */ |
||||
#define AT91C_SPI_SPIENS (0x1 << 16) /* Enable Status */ |
||||
/* SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register */ |
||||
/* SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register */ |
||||
/* SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register */ |
||||
/* SPI_CSR : (SPI Offset: 0x30) Chip Select Register */ |
||||
#define AT91C_SPI_CPOL (0x1 << 0) /* Clock Polarity */ |
||||
#define AT91C_SPI_NCPHA (0x1 << 1) /* Clock Phase */ |
||||
#define AT91C_SPI_CSAAT (0x1 << 3) /* CS Active After Transfer */ |
||||
#define AT91C_SPI_BITS (0xF << 4) /* Bits Per Transfer */ |
||||
#define AT91C_SPI_BITS_8 (0x0 << 4) /* 8 Bits */ |
||||
#define AT91C_SPI_BITS_9 (0x1 << 4) /* 9 Bits */ |
||||
#define AT91C_SPI_BITS_10 (0x2 << 4) /* 10 Bits */ |
||||
#define AT91C_SPI_BITS_11 (0x3 << 4) /* 11 Bits */ |
||||
#define AT91C_SPI_BITS_12 (0x4 << 4) /* 12 Bits */ |
||||
#define AT91C_SPI_BITS_13 (0x5 << 4) /* 13 Bits */ |
||||
#define AT91C_SPI_BITS_14 (0x6 << 4) /* 14 Bits */ |
||||
#define AT91C_SPI_BITS_15 (0x7 << 4) /* 15 Bits */ |
||||
#define AT91C_SPI_BITS_16 (0x8 << 4) /* 16 Bits */ |
||||
#define AT91C_SPI_SCBR (0xFF << 8) /* Serial Clock Baud Rate */ |
||||
#define AT91C_SPI_DLYBS (0xFF << 16) /* Delay Before SPCK */ |
||||
#define AT91C_SPI_DLYBCT (0xFF << 24) /* Delay Between Transfers */ |
||||
/* SPI_PTCR : PDC Transfer Control Register */ |
||||
#define AT91C_PDC_RXTEN (0x1 << 0) /* Receiver Transfer Enable */ |
||||
#define AT91C_PDC_RXTDIS (0x1 << 1) /* Receiver Transfer Disable */ |
||||
#define AT91C_PDC_TXTEN (0x1 << 8) /* Transm. Transfer Enable */ |
||||
#define AT91C_PDC_TXTDIS (0x1 << 9) /* Transm. Transfer Disable */ |
||||
|
||||
/* PIO definitions */ |
||||
#define AT91C_PIO_PA0 (1 << 0) /* Pin Controlled by PA0 */ |
||||
#define AT91C_PA0_SPI0_MISO AT91C_PIO_PA0 |
||||
#define AT91C_PIO_PA1 (1 << 1) /* Pin Controlled by PA1 */ |
||||
#define AT91C_PA1_SPI0_MOSI AT91C_PIO_PA1 |
||||
#define AT91C_PIO_PA2 (1 << 2) /* Pin Controlled by PA2 */ |
||||
#define AT91C_PA2_SPI0_SPCK AT91C_PIO_PA2 |
||||
#define AT91C_PIO_PA3 (1 << 3) /* Pin Controlled by PA3 */ |
||||
#define AT91C_PA3_SPI0_NPCS1 AT91C_PIO_PA3 |
||||
#define AT91C_PIO_PA4 (1 << 4) /* Pin Controlled by PA4 */ |
||||
#define AT91C_PA4_SPI0_NPCS2A AT91C_PIO_PA4 |
||||
#define AT91C_PIO_PA5 (1 << 5) /* Pin Controlled by PA5 */ |
||||
#define AT91C_PA5_SPI0_NPCS0 AT91C_PIO_PA5 |
||||
#define AT91C_PIO_PA10 (1 << 10) /* Pin Controlled by PA10 */ |
||||
#define AT91C_PIO_PA11 (1 << 11) /* Pin Controlled by PA11 */ |
||||
#define AT91C_PIO_PA22 (1 << 22) /* Pin Controlled by PA22 */ |
||||
#define AT91C_PA22_TXD0 AT91C_PIO_PA22 |
||||
#define AT91C_PIO_PA23 (1 << 23) /* Pin Controlled by PA23 */ |
||||
#define AT91C_PA23_RXD0 AT91C_PIO_PA23 |
||||
#define AT91C_PIO_PA28 (1 << 28) /* Pin Controlled by PA28 */ |
||||
#define AT91C_PA28_SPI0_NPCS3A AT91C_PIO_PA28 |
||||
#define AT91C_PIO_PB21 (1 << 21) /* Pin Controlled by PB21 */ |
||||
#define AT91C_PB21_E_TXCK AT91C_PIO_PB21 |
||||
#define AT91C_PIO_PB22 (1 << 22) /* Pin Controlled by PB22 */ |
||||
#define AT91C_PB22_E_RXDV AT91C_PIO_PB22 |
||||
#define AT91C_PIO_PB23 (1 << 23) /* Pin Controlled by PB23 */ |
||||
#define AT91C_PB23_E_TX0 AT91C_PIO_PB23 |
||||
#define AT91C_PIO_PB24 (1 << 24) /* Pin Controlled by PB24 */ |
||||
#define AT91C_PB24_E_TX1 AT91C_PIO_PB24 |
||||
#define AT91C_PIO_PB25 (1 << 25) /* Pin Controlled by PB25 */ |
||||
#define AT91C_PB25_E_RX0 AT91C_PIO_PB25 |
||||
#define AT91C_PIO_PB26 (1 << 26) /* Pin Controlled by PB26 */ |
||||
#define AT91C_PB26_E_RX1 AT91C_PIO_PB26 |
||||
#define AT91C_PIO_PB27 (1 << 27) /* Pin Controlled by PB27 */ |
||||
#define AT91C_PB27_E_RXER AT91C_PIO_PB27 |
||||
#define AT91C_PIO_PB28 (1 << 28) /* Pin Controlled by PB28 */ |
||||
#define AT91C_PB28_E_TXEN AT91C_PIO_PB28 |
||||
#define AT91C_PIO_PB29 (1 << 29) /* Pin Controlled by PB29 */ |
||||
#define AT91C_PB29_E_MDC AT91C_PIO_PB29 |
||||
#define AT91C_PIO_PB30 (1 << 30) /* Pin Controlled by PB30 */ |
||||
#define AT91C_PB30_E_MDIO AT91C_PIO_PB30 |
||||
#define AT91C_PIO_PB31 (1 << 31) /* Pin Controlled by PB31 */ |
||||
#define AT91C_PIO_PC29 (1 << 29) /* Pin Controlled by PC29 */ |
||||
#define AT91C_PIO_PC30 (1 << 30) /* Pin Controlled by PC30 */ |
||||
#define AT91C_PC30_DRXD AT91C_PIO_PC30 |
||||
#define AT91C_PIO_PC31 (1 << 31) /* Pin Controlled by PC31 */ |
||||
#define AT91C_PC31_DTXD AT91C_PIO_PC31 |
||||
#define AT91C_PIO_PD0 (1 << 0) /* Pin Controlled by PD0 */ |
||||
#define AT91C_PD0_TXD1 AT91C_PIO_PD0 |
||||
#define AT91C_PD0_SPI0_NPCS2D AT91C_PIO_PD0 |
||||
#define AT91C_PIO_PD1 (1 << 1) /* Pin Controlled by PD1 */ |
||||
#define AT91C_PD1_RXD1 AT91C_PIO_PD1 |
||||
#define AT91C_PD1_SPI0_NPCS3D AT91C_PIO_PD1 |
||||
#define AT91C_PIO_PD2 (1 << 2) /* Pin Controlled by PD2 */ |
||||
#define AT91C_PD2_TXD2 AT91C_PIO_PD2 |
||||
#define AT91C_PIO_PD3 (1 << 3) /* Pin Controlled by PD3 */ |
||||
#define AT91C_PD3_RXD2 AT91C_PIO_PD3 |
||||
#define AT91C_PIO_PD15 (1 << 15) /* Pin Controlled by PD15 */ |
||||
|
||||
/* Peripheral ID */ |
||||
#define AT91C_ID_SYS 1 /* System Controller */ |
||||
#define AT91C_ID_PIOABCD 2 /* Parallel IO Controller A, B, C, D */ |
||||
#define AT91C_ID_US0 8 /* USART 0 */ |
||||
#define AT91C_ID_US1 9 /* USART 1 */ |
||||
#define AT91C_ID_US2 10 /* USART 2 */ |
||||
#define AT91C_ID_SPI0 15 /* Serial Peripheral Interface 0 */ |
||||
#define AT91C_ID_EMAC 22 /* Ethernet Mac */ |
||||
#define AT91C_ID_UHP 29 /* USB Host Port */ |
||||
|
||||
/* Base addresses */ |
||||
#define AT91C_BASE_SMC ((AT91PS_SMC) 0xFFFFE800) /* SMC */ |
||||
#define AT91C_BASE_CCFG ((AT91PS_CCFG) 0xFFFFEB10) /* CCFG */ |
||||
#define AT91C_BASE_DBGU ((unsigned long)0xFFFFEE00) /* DBGU */ |
||||
#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF200) /* PIOA */ |
||||
#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF400) /* PIOB */ |
||||
#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF600) /* PIOC */ |
||||
#define AT91C_BASE_PIOD ((AT91PS_PIO) 0xFFFFF800) /* PIOD */ |
||||
#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) /* PMC */ |
||||
#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) /* RSTC */ |
||||
#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) /* PITC */ |
||||
#define AT91C_BASE_US0 ((unsigned long)0xFFF8C000) /* US0 */ |
||||
#define AT91C_BASE_US1 ((unsigned long)0xFFF90000) /* US1 */ |
||||
#define AT91C_BASE_US2 ((unsigned long)0xFFF94000) /* US2 */ |
||||
#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFA4000) /* SPI0 */ |
||||
#define AT91C_BASE_MACB ((unsigned long)0xFFFBC000) /* MACB */ |
||||
|
||||
#endif |
||||
@ -0,0 +1,39 @@ |
||||
/*
|
||||
* (C) Copyright 2007 |
||||
* Stelian Pop <stelian.pop <at> leadtechdesign.com> |
||||
* Lead Tech Design <www.leadtechdesign.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
#ifndef __ASM_ARM_ARCH_CLK_H__ |
||||
#define __ASM_ARM_ARCH_CLK_H__ |
||||
|
||||
#include <asm/arch/hardware.h> |
||||
|
||||
static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) |
||||
{ |
||||
return AT91C_MASTER_CLOCK; |
||||
} |
||||
|
||||
static inline unsigned long get_usart_clk_rate(unsigned int dev_id) |
||||
{ |
||||
return AT91C_MASTER_CLOCK; |
||||
} |
||||
|
||||
#endif /* __ASM_ARM_ARCH_CLK_H__ */ |
||||
@ -0,0 +1,38 @@ |
||||
/*
|
||||
* (C) Copyright 2007 |
||||
* Stelian Pop <stelian.pop <at> leadtechdesign.com> |
||||
* Lead Tech Design <www.leadtechdesign.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
||||
*/ |
||||
#ifndef __ASM_ARCH_HARDWARE_H |
||||
#define __ASM_ARCH_HARDWARE_H |
||||
|
||||
#include <asm/sizes.h> |
||||
|
||||
#include <asm/arch/AT91CAP9.h> |
||||
|
||||
/*
|
||||
* container_of - cast a member of a structure out to the containing structure |
||||
* |
||||
* @ptr: the pointer to the member. |
||||
* @type: the type of the container struct this is embedded in. |
||||
* @member: the name of the member within the struct. |
||||
*/ |
||||
#define container_of(ptr, type, member) ({ \ |
||||
const typeof(((type *)0)->member) *__mptr = (ptr); \
|
||||
(type *)((char *)__mptr - offsetof(type, member)); }) |
||||
|
||||
#endif |
||||
@ -0,0 +1,34 @@ |
||||
/*
|
||||
* (C) Copyright 2007-2008 |
||||
* Stelian Pop <stelian.pop <at> leadtechdesign.com> |
||||
* Lead Tech Design <www.leadtechdesign.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
#ifndef __ASM_ARM_ARCH_MEMORYMAP_H__ |
||||
#define __ASM_ARM_ARCH_MEMORYMAP_H__ |
||||
|
||||
#include <asm/arch/AT91CAP9.h> |
||||
|
||||
#define USART0_BASE AT91C_BASE_US0 |
||||
#define USART1_BASE AT91C_BASE_US1 |
||||
#define USART2_BASE AT91C_BASE_US2 |
||||
#define USART3_BASE AT91C_BASE_DBGU |
||||
|
||||
#endif /* __ASM_ARM_ARCH_MEMORYMAP_H__ */ |
||||
@ -0,0 +1,50 @@ |
||||
/*
|
||||
* (C) Copyright 2007 |
||||
* Stelian Pop <stelian.pop <at> leadtechdesign.com> |
||||
* Lead Tech Design <www.leadtechdesign.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
#ifndef __ASM_ARM_DMA_MAPPING_H |
||||
#define __ASM_ARM_DMA_MAPPING_H |
||||
|
||||
enum dma_data_direction { |
||||
DMA_BIDIRECTIONAL = 0, |
||||
DMA_TO_DEVICE = 1, |
||||
DMA_FROM_DEVICE = 2, |
||||
}; |
||||
|
||||
static void *dma_alloc_coherent(size_t len, unsigned long *handle) |
||||
{ |
||||
*handle = (unsigned long)malloc(len); |
||||
return (void *)*handle; |
||||
} |
||||
|
||||
static inline unsigned long dma_map_single(volatile void *vaddr, size_t len, |
||||
enum dma_data_direction dir) |
||||
{ |
||||
return (unsigned long)vaddr; |
||||
} |
||||
|
||||
static inline void dma_unmap_single(volatile void *vaddr, size_t len, |
||||
unsigned long paddr) |
||||
{ |
||||
} |
||||
|
||||
#endif /* __ASM_ARM_DMA_MAPPING_H */ |
||||
@ -0,0 +1,212 @@ |
||||
/*
|
||||
* (C) Copyright 2007 |
||||
* Stelian Pop <stelian.pop <at> leadtechdesign.com> |
||||
* Lead Tech Design <www.leadtechdesign.com> |
||||
* |
||||
* Configuation settings for the AT91CAP9ADK board. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/* ARM asynchronous clock */ |
||||
#define AT91C_MAIN_CLOCK 200000000 /* from 12 MHz crystal */ |
||||
#define AT91C_MASTER_CLOCK 100000000 /* peripheral = main / 2 */ |
||||
#define CFG_HZ 1000000 /* 1us resolution */ |
||||
|
||||
#define AT91_SLOW_CLOCK 32768 /* slow clock */ |
||||
|
||||
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ |
||||
#define CONFIG_AT91CAP9 1 /* It's an Atmel AT91CAP9 SoC */ |
||||
#define CONFIG_AT91CAP9ADK 1 /* on an AT91CAP9ADK Board */ |
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
||||
#define CONFIG_INITRD_TAG 1 |
||||
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT |
||||
#define CONFIG_SKIP_RELOCATE_UBOOT |
||||
|
||||
#define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) |
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CFG_MALLOC_LEN ROUND(CFG_ENV_SIZE + 128*1024, 0x1000) |
||||
#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
/*
|
||||
* Hardware drivers |
||||
*/ |
||||
|
||||
#define CONFIG_ATMEL_USART 1 |
||||
#undef CONFIG_USART0 |
||||
#undef CONFIG_USART1 |
||||
#undef CONFIG_USART2 |
||||
#define CONFIG_USART3 1 /* USART 3 is DBGU */ |
||||
|
||||
#define CONFIG_BOOTDELAY 3 |
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ |
||||
"root=/dev/mtdblock1 rw rootfstype=jffs2" |
||||
|
||||
/* #define CONFIG_ENV_OVERWRITE 1 */ |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_BOOTFILESIZE 1 |
||||
#define CONFIG_BOOTP_BOOTPATH 1 |
||||
#define CONFIG_BOOTP_GATEWAY 1 |
||||
#define CONFIG_BOOTP_HOSTNAME 1 |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
#undef CONFIG_CMD_BDI |
||||
#undef CONFIG_CMD_IMI |
||||
#undef CONFIG_CMD_AUTOSCRIPT |
||||
#undef CONFIG_CMD_FPGA |
||||
#undef CONFIG_CMD_LOADS |
||||
|
||||
#define CONFIG_CMD_PING 1 |
||||
#define CONFIG_CMD_DHCP 1 |
||||
#define CONFIG_CMD_NAND 1 |
||||
#define CONFIG_CMD_USB 1 |
||||
|
||||
/* SDRAM: Careful: this supposes an AT91CAP-MEM33 expansion card */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM 0x70000000 |
||||
#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ |
||||
|
||||
/* DataFlash */ |
||||
#define CONFIG_HAS_DATAFLASH 1 |
||||
#define CFG_SPI_WRITE_TOUT (5*CFG_HZ) |
||||
#define CFG_MAX_DATAFLASH_BANKS 1 |
||||
#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ |
||||
#define CONFIG_NEW_PARTITION 1 |
||||
|
||||
/* NOR flash */ |
||||
#define CFG_FLASH_CFI 1 |
||||
#define CFG_FLASH_CFI_DRIVER 1 |
||||
#define PHYS_FLASH_1 0x10000000 |
||||
#define CFG_FLASH_BASE PHYS_FLASH_1 |
||||
#define CFG_MAX_FLASH_SECT 256 |
||||
#define CFG_MAX_FLASH_BANKS 1 |
||||
|
||||
#define AT91C_FLASH_NWE_SETUP (4 << 0) |
||||
#define AT91C_FLASH_NCS_WR_SETUP (2 << 8) |
||||
#define AT91C_FLASH_NRD_SETUP (4 << 16) |
||||
#define AT91C_FLASH_NCS_RD_SETUP (2 << 24) |
||||
|
||||
#define AT91C_FLASH_NWE_PULSE (8 << 0) |
||||
#define AT91C_FLASH_NCS_WR_PULSE (10 << 8) |
||||
#define AT91C_FLASH_NRD_PULSE (8 << 16) |
||||
#define AT91C_FLASH_NCS_RD_PULSE (10 << 24) |
||||
|
||||
#define AT91C_FLASH_NWE_CYCLE (16 << 0) |
||||
#define AT91C_FLASH_NRD_CYCLE (16 << 16) |
||||
|
||||
/* NAND flash */ |
||||
#define NAND_MAX_CHIPS 1 |
||||
#define CFG_MAX_NAND_DEVICE 1 |
||||
#define CFG_NAND_BASE 0x40000000 |
||||
|
||||
#define AT91C_SM_NWE_SETUP (2 << 0) |
||||
#define AT91C_SM_NCS_WR_SETUP (1 << 8) |
||||
#define AT91C_SM_NRD_SETUP (2 << 16) |
||||
#define AT91C_SM_NCS_RD_SETUP (1 << 24) |
||||
|
||||
#define AT91C_SM_NWE_PULSE (4 << 0) |
||||
#define AT91C_SM_NCS_WR_PULSE (6 << 8) |
||||
#define AT91C_SM_NRD_PULSE (4 << 16) |
||||
#define AT91C_SM_NCS_RD_PULSE (6 << 24) |
||||
|
||||
#define AT91C_SM_NWE_CYCLE (8 << 0) |
||||
#define AT91C_SM_NRD_CYCLE (8 << 16) |
||||
|
||||
#define AT91C_SM_TDF (1 << 16) |
||||
|
||||
/* Ethernet */ |
||||
#define CONFIG_MACB 1 |
||||
#define CONFIG_RMII 1 |
||||
#define CONFIG_NET_MULTI 1 |
||||
#define CONFIG_NET_RETRY_COUNT 20 |
||||
#define CONFIG_RESET_PHY_R 1 |
||||
|
||||
/* USB */ |
||||
#define CONFIG_USB_OHCI_NEW 1 |
||||
#define LITTLEENDIAN 1 |
||||
#define CONFIG_DOS_PARTITION 1 |
||||
#define CFG_USB_OHCI_CPU_INIT 1 |
||||
#define CFG_USB_OHCI_REGS_BASE 0x00700000 /* AT91C_BASE_UHP */ |
||||
#define CFG_USB_OHCI_SLOT_NAME "at91cap9" |
||||
#define CFG_USB_OHCI_MAX_ROOT_PORTS 2 |
||||
|
||||
|
||||
#define CFG_LOAD_ADDR 0x72000000 /* load address */ |
||||
|
||||
#define CFG_MEMTEST_START PHYS_SDRAM |
||||
#define CFG_MEMTEST_END 0x73000000 |
||||
|
||||
#define CFG_USE_DATAFLASH 1 |
||||
#undef CFG_USE_NORFLASH |
||||
|
||||
#ifdef CFG_USE_DATAFLASH |
||||
|
||||
/* bootstrap + u-boot + env + linux in dataflash */ |
||||
#define CFG_ENV_IS_IN_DATAFLASH 1 |
||||
#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) |
||||
#define CFG_ENV_OFFSET 0x4200 |
||||
#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) |
||||
#define CFG_ENV_SIZE 0x4200 |
||||
#define CONFIG_BOOTCOMMAND "cp.b 0xC003DE00 0x72000000 0x200040; bootm" |
||||
|
||||
#else |
||||
|
||||
/* bootstrap + u-boot + env + linux in norflash */ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_MONITOR_BASE (PHYS_FLASH_1 + 0x8000) |
||||
#define CFG_ENV_OFFSET 0x4000 |
||||
#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_ENV_OFFSET) |
||||
#define CFG_ENV_SIZE 0x4000 |
||||
#define CONFIG_BOOTCOMMAND "cp.b 0x10040000 0x72000000 0x200000; bootm" |
||||
|
||||
#endif |
||||
|
||||
#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } |
||||
|
||||
#define CFG_PROMPT "U-Boot> " |
||||
#define CFG_CBSIZE 256 |
||||
#define CFG_MAXARGS 16 |
||||
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) |
||||
#define CFG_LONGHELP 1 |
||||
#define CONFIG_CMDLINE_EDITING 1 |
||||
|
||||
#define CONFIG_STACKSIZE (32*1024) /* regular stack */ |
||||
|
||||
#ifdef CONFIG_USE_IRQ |
||||
#error CONFIG_USE_IRQ not supported |
||||
#endif |
||||
|
||||
#endif |
||||
@ -0,0 +1,197 @@ |
||||
/*
|
||||
* Based on Modifications by Alan Lu / Artila and |
||||
* Rick Bronson <rick@efn.org> |
||||
* |
||||
* Configuration settings for the Artila M-501 starter kit, |
||||
* with V02 processor card. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/* ARM asynchronous clock */ |
||||
/* from 18.432 MHz crystal (18432000 / 4 * 39) */ |
||||
#define AT91C_MAIN_CLOCK 179712000 |
||||
/* Perip clock (AT91C_MASTER_CLOCK / 3) */ |
||||
#define AT91C_MASTER_CLOCK 59904000 |
||||
#define AT91_SLOW_CLOCK 32768 /* slow clock */ |
||||
|
||||
#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */ |
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
||||
#define CONFIG_INITRD_TAG 1 |
||||
|
||||
#undef CONFIG_AUTOBOOT_PROMPT |
||||
#define CONFIG_MENUPROMPT "." |
||||
|
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) |
||||
#define CFG_GBL_DATA_SIZE 128 /* Bytes reserved for initial data */ |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
/* Hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */ |
||||
#define CFG_AT91C_BRGR_DIVISOR 33 |
||||
|
||||
/*
|
||||
* Hardware drivers |
||||
*/ |
||||
#define CFG_FLASH_CFI 1 |
||||
#define CFG_FLASH_CFI_DRIVER 1 |
||||
#define CFG_ENV_SECT_SIZE 0x20000 |
||||
#define CFG_FLASH_USE_BUFFER_WRITE |
||||
#define CFG_FLASH_PROTECTION /*for Intel P30 Flash*/ |
||||
#define CONFIG_HARD_I2C |
||||
#define CFG_I2C_SPEED 100 |
||||
#define CFG_I2C_SLAVE 0 |
||||
#define CFG_CONSOLE_INFO_QUIET |
||||
#undef CFG_ENV_IS_IN_EEPROM |
||||
#define CFG_I2C_EEPROM_ADDR 0x50 |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 |
||||
#define CFG_EEPROM_AT24C16 |
||||
#define CFG_I2C_RTC_ADDR 0x32 |
||||
#undef CONFIG_RTC_DS1338 |
||||
#define CONFIG_RTC_RS5C372A |
||||
#undef CONFIG_POST |
||||
#define CONFIG_M501SK |
||||
#define CONFIG_CMC_PU2 |
||||
|
||||
/* define one of these to choose the DBGU, USART0 or USART1 as console */ |
||||
#define CONFIG_DBGU |
||||
#undef CONFIG_USART0 |
||||
#undef CONFIG_USART1 |
||||
|
||||
#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ |
||||
#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ |
||||
|
||||
#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200 " \ |
||||
"initrd=0x20800000,8192000 ramdisk_size=15360 " \
|
||||
"root=/dev/ram0 rw mtdparts=phys_mapped_flash:" \
|
||||
"128k(loader)ro,128k(reserved)ro,1408k(linux)" \
|
||||
"ro,2560k(ramdisk)ro,-(userdisk)" |
||||
#define CONFIG_BOOTCOMMAND "bootm 10040000 101a0000" |
||||
#define CONFIG_BOOTDELAY 1 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_IPADDR 192.168.1.100 |
||||
#define CONFIG_SERVERIP 192.168.1.1 |
||||
#define CONFIG_GATEWAYIP 192.168.1.254 |
||||
#define CONFIG_NETMASK 255.255.255.0 |
||||
#define CONFIG_BOOTFILE uImage |
||||
#define CONFIG_ETHADDR 00:13:48:aa:bb:cc |
||||
#define CONFIG_ENV_OVERWRITE 1 |
||||
#define BOARD_LATE_INIT |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"unlock=yes\0" |
||||
|
||||
#define CFG_CMD_JFFS2 |
||||
#undef CONFIG_CMD_EEPROM |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_CMD_RUN |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_MEMORY |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_SDRAM |
||||
#define CONFIG_CMD_DIAG |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_DATE |
||||
#define CONFIG_CMD_POST |
||||
#define CONFIG_CMD_MISC |
||||
#define CONFIG_CMD_LOADS |
||||
#define CONFIG_CMD_IMI |
||||
#define CONFIG_CMD_NFS |
||||
#define CONFIG_CMD_FLASH |
||||
#define CONFIG_CMD_ENV |
||||
|
||||
#define CFG_HUSH_PARSER |
||||
#define CONFIG_AUTO_COMPLETE |
||||
#define CFG_PROMPT_HUSH_PS2 ">>" |
||||
|
||||
#define CFG_MAX_NAND_DEVICE 0 /* Max number of NAND devices */ |
||||
#define SECTORSIZE 512 |
||||
|
||||
#define ADDR_COLUMN 1 |
||||
#define ADDR_PAGE 2 |
||||
#define ADDR_COLUMN_PAGE 3 |
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM 0x20000000 |
||||
#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */ |
||||
|
||||
#define CFG_MEMTEST_START 0x21000000 /* PHYS_SDRAM */ |
||||
/* CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 */ |
||||
#define CFG_MEMTEST_END 0x00100000 |
||||
|
||||
#define CONFIG_DRIVER_ETHER |
||||
#define CONFIG_NET_RETRY_COUNT 20 |
||||
#define CONFIG_AT91C_USE_RMII |
||||
|
||||
#define PHYS_FLASH_1 0x10000000 |
||||
#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */ |
||||
#define CFG_FLASH_BASE PHYS_FLASH_1 |
||||
#define CFG_MAX_FLASH_BANKS 1 |
||||
#define CFG_MAX_FLASH_SECT 256 |
||||
#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ |
||||
#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ |
||||
|
||||
#ifdef CFG_ENV_IS_IN_DATAFLASH |
||||
#define CFG_ENV_OFFSET 0x20000 |
||||
#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
#else |
||||
#define CFG_ENV_IS_IN_FLASH |
||||
#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x00020000) |
||||
#define CFG_ENV_SIZE 2048 |
||||
#endif |
||||
|
||||
#ifdef CFG_ENV_IS_IN_EEPROM |
||||
#define CFG_ENV_OFFSET 1024 |
||||
#define CFG_ENV_SIZE 1024 |
||||
#endif |
||||
|
||||
#define CFG_LOAD_ADDR 0x21000000 /* default load address */ |
||||
|
||||
/* use for protect flash sectors */ |
||||
#define CFG_BOOT_SIZE 0x6000 /* 24 KBytes */ |
||||
#define CFG_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000) |
||||
#define CFG_U_BOOT_SIZE 0x10000 /* 64 KBytes */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 115200 , 19200, 38400, 57600, 9600 } |
||||
|
||||
#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */ |
||||
#define CFG_CBSIZE 512 /* Console I/O Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
/* Print Buffer Size */ |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) |
||||
|
||||
#define CFG_HZ 1000 |
||||
#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 |
||||
|
||||
#define CONFIG_STACKSIZE (32*1024) /* regular stack */ |
||||
|
||||
#ifdef CONFIG_USE_IRQ |
||||
#error CONFIG_USE_IRQ not supported |
||||
#endif |
||||
|
||||
#endif |
||||
Loading…
Reference in new issue