Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Andrea Scian <andrea.scian@dave-tech.it>master
Wolfgang Denk
14 years ago
committed by
Albert ARIBAUD
parent
be28857072
commit
5dcf53696f
@ -1,139 +0,0 @@ |
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/*
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* (C) Copyright 2004 |
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* DAVE Srl |
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* http://www.dave-tech.it
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* http://www.wawnet.biz
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* mailto:info@wawnet.biz |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <netdev.h> |
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#include <asm/hardware.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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/*
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* Miscelaneous platform dependent initialization |
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*/ |
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int board_init (void) |
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{ |
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u32 temp; |
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/* Configuration Port Control Register*/ |
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/* Port A */ |
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PCONA = 0x3ff; |
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/* Port B */ |
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PCONB = 0xff; |
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PDATB = 0xFFFF; |
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/* Port C */ |
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/*
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PCONC = 0xff55ff15; |
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PDATC = 0x0; |
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PUPC = 0xffff; |
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*/ |
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/* Port D */ |
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/*
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PCOND = 0xaaaa; |
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PUPD = 0xff; |
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*/ |
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/* Port E */ |
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PCONE = 0x0001aaa9; |
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PDATE = 0x0; |
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PUPE = 0xff; |
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/* Port F */ |
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PCONF = 0x124955; |
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PDATF = 0xff; /* B2-eth_reset tied high level */ |
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/*
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PUPF = 0x1e3; |
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*/ |
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/* Port G */ |
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PUPG = 0x1; |
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PCONG = 0x3; /*PG0= EINT0= ETH_INT prepared for linux kernel*/ |
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INTMSK = 0x03fffeff; |
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INTCON = 0x05; |
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/*
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Configure chip ethernet interrupt as High level |
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Port G EINT 0-7 EINT0 -> CHIP ETHERNET |
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*/ |
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temp = EXTINT; |
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temp &= ~0x7; |
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temp |= 0x1; /*LEVEL_HIGH*/ |
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EXTINT = temp; |
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/*
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Reset SMSC LAN91C96 chip |
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*/ |
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temp= PCONF; |
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temp |= 0x00000040; |
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PCONF = temp; |
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/* Reset high */ |
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temp = PDATF; |
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temp |= (1 << 3); |
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PDATF = temp; |
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/* Short delay */ |
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for (temp=0;temp<10;temp++) |
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{ |
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/* NOP */ |
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} |
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/* Reset low */ |
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temp = PDATF; |
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temp &= ~(1 << 3); |
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PDATF = temp; |
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/* arch number MACH_TYPE_MBA44B0 */ |
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gd->bd->bi_arch_number = MACH_TYPE_S3C44B0; |
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/* location of boot parameters */ |
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gd->bd->bi_boot_params = 0x0c000100; |
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return 0; |
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} |
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int dram_init (void) |
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{ |
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
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return (0); |
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} |
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#ifdef CONFIG_CMD_NET |
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int board_eth_init(bd_t *bis) |
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{ |
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int rc = 0; |
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#ifdef CONFIG_LAN91C96 |
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rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); |
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#endif |
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return rc; |
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} |
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#endif |
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@ -1,55 +0,0 @@ |
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2002
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# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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# Marius Groeger <mgroeger@sysgo.de>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).o
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COBJS := B2.o flash.o
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SOBJS := lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -1,30 +0,0 @@ |
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#
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# (C) Copyright 2000
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# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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# Marius Groeger <mgroeger@sysgo.de>
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#
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# (C) Copyright 2000-2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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CONFIG_SYS_TEXT_BASE = 0x0C100000
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PLATFORM_CPPFLAGS += -Uarm
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@ -1,76 +0,0 @@ |
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/*
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* (C) Copyright 2001 |
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/hardware.h> |
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/*
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* include common flash code (for esd boards) |
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*/ |
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#include "../common/flash.c" |
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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static ulong flash_get_size (vu_long * addr, flash_info_t * info); |
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static void flash_get_offsets (ulong base, flash_info_t * info); |
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/*-----------------------------------------------------------------------
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*/ |
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unsigned long flash_init (void) |
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{ |
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#ifdef __DEBUG_START_FROM_SRAM__ |
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return CONFIG_SYS_DUMMY_FLASH_SIZE; |
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#else |
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unsigned long size_b0; |
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int i; |
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/* Init: no FLASHes known */ |
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for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { |
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flash_info[i].flash_id = FLASH_UNKNOWN; |
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} |
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/* Static FLASH Bank configuration here - FIXME XXX */ |
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size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); |
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if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", |
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size_b0, size_b0<<20); |
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} |
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/* Setup offsets */ |
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flash_get_offsets (0, &flash_info[0]); |
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/* Monitor protection ON by default */ |
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(void)flash_protect(FLAG_PROTECT_SET, |
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-CONFIG_SYS_MONITOR_LEN, |
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0xffffffff, |
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&flash_info[0]); |
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flash_info[0].size = size_b0; |
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return (size_b0); |
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#endif |
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} |
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@ -1,167 +0,0 @@ |
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/* |
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* (C) Copyright 2004 |
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* DAVE Srl |
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* |
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* http://www.dave-tech.it |
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* http://www.wawnet.biz |
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* mailto:info@wawnet.biz
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* |
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* memsetup-sa1110.S (blob): memory setup for various SA1110 architectures |
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* Modified By MATTO |
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* |
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* Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
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* |
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or
|
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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* |
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*/ |
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/* |
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* Documentation: |
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* Intel Corporation, "Intel StrongARM SA-1110 Microprocessor |
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* Advanced Developer's manual, December 1999 |
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* |
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* Intel has a very hard to find SDRAM configurator on their web site: |
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* http://appzone.intel.com/hcd/sa1110/memory/index.asp |
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* |
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* NOTE: This code assumes that an SA1110 CPU *always* uses SDRAM. This |
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* appears to be true, but it might be possible that somebody designs a |
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* board with mixed EDODRAM/SDRAM memory (which is a bad idea). -- Erik |
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* |
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* 04-10-2001: SELETZ |
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* - separated memory config for multiple platform support |
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* - perform SA1110 Hardware Reset Procedure |
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* |
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*/ |
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.equ B0_Tacs, 0x0 /* 0clk */ |
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.equ B0_Tcos, 0x0 /* 0clk */ |
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.equ B0_Tacc, 0x4 /* 6clk */ |
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.equ B0_Tcoh, 0x0 /* 0clk */ |
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.equ B0_Tah, 0x0 /* 0clk */ |
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.equ B0_Tacp, 0x0 /* 0clk */ |
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.equ B0_PMC, 0x0 /* normal(1data) */ |
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/* Bank 1 parameter */ |
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.equ B1_Tacs, 0x3 /* 4clk */ |
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.equ B1_Tcos, 0x3 /* 4clk */ |
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.equ B1_Tacc, 0x7 /* 14clkv */ |
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.equ B1_Tcoh, 0x3 /* 4clk */ |
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.equ B1_Tah, 0x3 /* 4clk */ |
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.equ B1_Tacp, 0x3 /* 6clk */ |
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.equ B1_PMC, 0x0 /* normal(1data) */ |
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/* Bank 2 parameter - LAN91C96 */ |
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.equ B2_Tacs, 0x3 /* 4clk */ |
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.equ B2_Tcos, 0x3 /* 4clk */ |
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.equ B2_Tacc, 0x7 /* 14clk */ |
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.equ B2_Tcoh, 0x3 /* 4clk */ |
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.equ B2_Tah, 0x3 /* 4clk */ |
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.equ B2_Tacp, 0x3 /* 6clk */ |
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.equ B2_PMC, 0x0 /* normal(1data) */ |
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/* Bank 3 parameter */ |
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.equ B3_Tacs, 0x3 /* 4clk */ |
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.equ B3_Tcos, 0x3 /* 4clk */ |
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.equ B3_Tacc, 0x7 /* 14clk */ |
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.equ B3_Tcoh, 0x3 /* 4clk */ |
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.equ B3_Tah, 0x3 /* 4clk */ |
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.equ B3_Tacp, 0x3 /* 6clk */ |
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.equ B3_PMC, 0x0 /* normal(1data) */ |
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/* Bank 4 parameter */ |
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.equ B4_Tacs, 0x3 /* 4clk */ |
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.equ B4_Tcos, 0x3 /* 4clk */ |
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.equ B4_Tacc, 0x7 /* 14clk */ |
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.equ B4_Tcoh, 0x3 /* 4clk */ |
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.equ B4_Tah, 0x3 /* 4clk */ |
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.equ B4_Tacp, 0x3 /* 6clk */ |
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.equ B4_PMC, 0x0 /* normal(1data) */ |
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/* Bank 5 parameter */ |
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.equ B5_Tacs, 0x3 /* 4clk */ |
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.equ B5_Tcos, 0x3 /* 4clk */ |
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.equ B5_Tacc, 0x7 /* 14clk */ |
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.equ B5_Tcoh, 0x3 /* 4clk */ |
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.equ B5_Tah, 0x3 /* 4clk */ |
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.equ B5_Tacp, 0x3 /* 6clk */ |
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.equ B5_PMC, 0x0 /* normal(1data) */ |
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/* Bank 6(if SROM) parameter */ |
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.equ B6_Tacs, 0x3 /* 4clk */ |
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.equ B6_Tcos, 0x3 /* 4clk */ |
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.equ B6_Tacc, 0x7 /* 14clk */ |
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.equ B6_Tcoh, 0x3 /* 4clk */ |
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.equ B6_Tah, 0x3 /* 4clk */ |
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.equ B6_Tacp, 0x3 /* 6clk */ |
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.equ B6_PMC, 0x0 /* normal(1data) */ |
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/* Bank 7(if SROM) parameter */ |
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.equ B7_Tacs, 0x3 /* 4clk */ |
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.equ B7_Tcos, 0x3 /* 4clk */ |
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.equ B7_Tacc, 0x7 /* 14clk */ |
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.equ B7_Tcoh, 0x3 /* 4clk */ |
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.equ B7_Tah, 0x3 /* 4clk */ |
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.equ B7_Tacp, 0x3 /* 6clk */ |
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.equ B7_PMC, 0x0 /* normal(1data) */ |
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/* Bank 6 parameter */ |
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.equ B6_MT, 0x3 /* SDRAM */ |
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.equ B6_Trcd, 0x0 /* 2clk */ |
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.equ B6_SCAN, 0x0 /* 10bit */ |
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.equ B7_MT, 0x3 /* SDRAM */ |
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.equ B7_Trcd, 0x0 /* 2clk */ |
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.equ B7_SCAN, 0x0 /* 10bit */ |
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/* REFRESH parameter */ |
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.equ REFEN, 0x1 /* Refresh enable */ |
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.equ TREFMD, 0x0 /* CBR(CAS before RAS)/Auto refresh */ |
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.equ Trp, 0x0 /* 2clk */ |
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.equ Trc, 0x3 /* 0x1=5clk 0x3=11clk*/ |
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.equ Tchr, 0x0 /* 0x2=3clk 0x0=0clks */ |
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.equ REFCNT, 879 |
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MEMORY_CONFIG: |
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.long 0x12111900 /* Bank0 = OM[1:0] , Bank1-7 16bit, Bank2=Nowait,UB/LB*/ |
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.word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /*GCS0*/ |
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.word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /*GCS1*/ |
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.word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /*GCS2*/ |
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.word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /*GCS3*/ |
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.word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /*GCS4*/ |
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.word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /*GCS5*/ |
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.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /*GCS6*/ |
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.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /*GCS7*/ |
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.word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) /*REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019*/ |
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.word 0x17 /*SCLK power down mode, BANKSIZE 16M/16M*/ |
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.word 0x20 /*MRSR6 CL=2clk*/ |
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.word 0x20 /*MRSR7*/ |
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.globl lowlevel_init
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lowlevel_init: |
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/* |
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the next instruction fail due memory relocation... |
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we'll find the right MEMORY_CONFIG address with the next 3 lines... |
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*/ |
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/*ldr r0, =MEMORY_CONFIG*/ |
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mov r0, pc |
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ldr r1, =(0x38+4) |
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sub r0, r0, r1 |
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|
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ldmia r0, {r1-r13} |
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ldr r0, =0x01c80000 |
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stmia r0, {r1-r13} |
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mov pc, lr |
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@ -1,216 +0,0 @@ |
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/*
|
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* (C) Copyright 2004 |
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* DAVE Srl |
||||
* |
||||
* http://www.dave-tech.it
|
||||
* http://www.wawnet.biz
|
||||
* mailto:info@wawnet.biz |
||||
* |
||||
* Configuation settings for the B2 board. |
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* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#define CONFIG_ARM7 1 /* This is a ARM7 CPU */ |
||||
#define CONFIG_B2 1 /* on an B2 Board */ |
||||
#define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */ |
||||
#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ |
||||
#define CONFIG_SYS_ICACHE_OFF |
||||
#define CONFIG_SYS_DCACHE_OFF |
||||
#define CONFIG_ARCH_CPU_INIT |
||||
|
||||
#define CONFIG_S3C44B0_CLOCK_SPEED 75 /* we have a 75Mhz S3C44B0*/ |
||||
|
||||
|
||||
#undef CONFIG_USE_IRQ /* don't need them anymore */ |
||||
|
||||
|
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ |
||||
#define CONFIG_ENV_SIZE 1024 /* 1024 bytes may be used for env vars*/ |
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024 ) |
||||
|
||||
/*
|
||||
* Hardware drivers |
||||
*/ |
||||
#define CONFIG_LAN91C96 |
||||
#define CONFIG_LAN91C96_BASE 0x04000300 /* base address */ |
||||
#define CONFIG_SMC_USE_32_BIT |
||||
#undef CONFIG_SHOW_ACTIVITY |
||||
#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ |
||||
|
||||
/*
|
||||
* select serial console configuration |
||||
*/ |
||||
#define CONFIG_S3C44B0_SERIAL |
||||
#define CONFIG_SERIAL1 1 /* we use Serial line 1 */ |
||||
|
||||
#define CONFIG_S3C44B0_I2C |
||||
#define CONFIG_RTC_S3C44B0 |
||||
|
||||
/* allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_SUBNETMASK |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
|
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_DATE |
||||
#define CONFIG_CMD_ELF |
||||
#define CONFIG_CMD_EEPROM |
||||
#define CONFIG_CMD_I2C |
||||
|
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_BOOTDELAY 5 |
||||
#define CONFIG_ETHADDR 00:50:c2:1e:af:fb |
||||
#define CONFIG_BOOTARGS "setenv bootargs root=/dev/ram ip=192.168.0.70:::::eth0:off \ |
||||
ether=25,0,0,0,eth0 ethaddr=00:50:c2:1e:af:fb" |
||||
#define CONFIG_NETMASK 255.255.0.0 |
||||
#define CONFIG_IPADDR 192.168.0.70 |
||||
#define CONFIG_SERVERIP 192.168.0.23 |
||||
#define CONFIG_BOOTFILE "B2-rootfs/usr/B2-zImage.u-boot" |
||||
#define CONFIG_BOOTCOMMAND "bootm 20000 f0000" |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0C400000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x0C800000 /* 4 ... 8 MB in DRAM */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x0c700000 /* default load address */ |
||||
|
||||
#define CONFIG_SYS_HZ 1000 /* 1 kHz */ |
||||
|
||||
/* valid baudrates */ |
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Stack sizes |
||||
* |
||||
* The stack sizes are set up in start.S using the settings below |
||||
*/ |
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
||||
#ifdef CONFIG_USE_IRQ |
||||
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ |
||||
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */ |
||||
#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ |
||||
#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ |
||||
|
||||
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
||||
#define PHYS_FLASH_SIZE 0x00400000 /* 4 MB */ |
||||
|
||||
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
||||
#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ |
||||
#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ |
||||
/*
|
||||
* The following defines are added for buggy IOP480 byte interface. |
||||
* All other boards should use the standard values (CPCI405 etc.) |
||||
*/ |
||||
#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
||||
#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ |
||||
#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ |
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment Variable setup |
||||
*/ |
||||
#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
||||
#define CONFIG_ENV_OFFSET 0x0 /* environment starts at the beginning of the EEPROM */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C EEPROM (STM24C02W6) for environment |
||||
*/ |
||||
#define CONFIG_HARD_I2C /* I2c with hardware support */ |
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CONFIG_SYS_I2C_SLAVE 0xFE |
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0xA8 /* EEPROM STM24C02W6 */ |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
||||
/* mask of address bits that overflow into the "EEPROM chip address" */ |
||||
/*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07*/ |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ |
||||
/* 16 byte page write mode using*/ |
||||
/* last 4 bits of the address */ |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
||||
|
||||
/* Flash banks JFFS2 should use */ |
||||
/*
|
||||
#define CONFIG_SYS_JFFS2_FIRST_BANK 0 |
||||
#define CONFIG_SYS_JFFS2_FIRST_SECTOR 2 |
||||
#define CONFIG_SYS_JFFS2_NUM_BANKS 1 |
||||
*/ |
||||
|
||||
/*
|
||||
Linux TAGs (see arch/arm/lib/armlinux.c) |
||||
*/ |
||||
#define CONFIG_CMDLINE_TAG |
||||
#undef CONFIG_SETUP_MEMORY_TAGS |
||||
#define CONFIG_INITRD_TAG |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue