PPC440EP(x)/PPC440GR(x): In asynchronous PCI mode, the synchronous PCI clock must meet certain requirements. The following equation describes the relationship that must be maintained between the asynchronous PCI clock and synchronous PCI clock. Select an appropriate PCI:PLB ratio to maintain the relationship: AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz This patch now adds a function to check and reconfigure the sync PCI clock to meet this requirement. This is in preparation for some AMCC boards (Sequoia/Rainier and Yosemite/Yellowstone) using this function to not violate the PCI clocking rules. Signed-off-by: Stefan Roese <sr@denx.de>master
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