Wolfgang Denk
15 years ago
commit
5e498dfab8
@ -0,0 +1,63 @@ |
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/*
|
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* Copyright 2009 Freescale Semiconductor, Inc. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#include <common.h> |
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#include <asm/io.h> |
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void cpu_init_f(void) |
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{ |
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ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); |
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/*
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* LCRR - Clock Ratio Register - set up local bus timing |
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* when needed |
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*/ |
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out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8); |
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#if defined(CONFIG_NAND_BR_PRELIM) && defined(CONFIG_NAND_OR_PRELIM) |
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out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM); |
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out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM); |
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#else |
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#error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined |
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#endif |
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#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) |
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ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; |
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char *l2srbar; |
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int i; |
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out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR); |
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/* set MBECCDIS=1, SBECCDIS=1 */ |
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out_be32(&l2cache->l2errdis, |
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(MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC)); |
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|
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/* set L2E=1 & L2SRAM=001 */ |
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out_be32(&l2cache->l2ctl, |
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(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); |
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|
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/* Initialize L2 SRAM to zero */ |
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l2srbar = (char *)CONFIG_SYS_INIT_L2_ADDR; |
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for (i = 0; i < CONFIG_SYS_L2_SIZE; i++) |
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l2srbar[i] = 0; |
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#endif |
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} |
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@ -0,0 +1,67 @@ |
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/* |
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* (C) Copyright 2006 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de |
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* |
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* Copyright 2009 Freescale Semiconductor, Inc. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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OUTPUT_ARCH(powerpc) |
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SECTIONS |
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{ |
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. = 0xfff00000; |
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.text : { |
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*(.text) |
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} |
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_etext = .; |
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.reloc : { |
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_GOT2_TABLE_ = .; |
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*(.got2) |
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_FIXUP_TABLE_ = .; |
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*(.fixup) |
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} |
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__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
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__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
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. = ALIGN(8); |
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.data : { |
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*(.rodata*) |
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*(.data*) |
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*(.sdata*) |
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} |
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_edata = .; |
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. = ALIGN(8); |
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__init_begin = .; |
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__init_end = .; |
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.resetvec ADDR(.text) + 0xffc : { |
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*(.resetvec) |
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} = 0xffff |
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__bss_start = .; |
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.bss : { |
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*(.sbss) |
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*(.bss) |
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} |
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_end = .; |
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} |
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ASSERT(__init_end <= 0xfff00ffc, "NAND bootstrap too big"); |
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@ -1,27 +1,176 @@ |
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Wind River SBC8548 reference board |
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=========================== |
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Intro: |
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====== |
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Copyright 2007, Embedded Specialties, Inc. |
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Copyright 2007 Wind River Systemes, Inc. |
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----------------------------- |
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The SBC8548 is a stand alone single board computer with a 1GHz |
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MPC8548 CPU, 8MB boot flash, 64MB user flash and, 256MB DDR2 400MHz |
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memory. It also has 128MB SDRAM 100MHz LBC memory, with both a PCI-e, |
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and a PCI-X slot, dual mini-DB9 for UART, and dual RJ-45 for eTSEC |
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ethernet connections. |
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|
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1. Building U-Boot |
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------------------ |
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The SBC8548 code is known to build using ELDK 4.1. |
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U-boot Configuration: |
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===================== |
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$ make sbc8548_config |
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Configuring for sbc8548 board... |
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The following possible u-boot configuration targets are available: |
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$ make |
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1) sbc8548_config |
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2) sbc8548_PCI_33_config |
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3) sbc8548_PCI_66_config |
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4) sbc8548_PCI_33_PCIE_config |
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5) sbc8548_PCI_66_PCIE_config |
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|
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Generally speaking, most people should choose to use #5. Details |
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of each choice are listed below. |
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|
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2. Switch and Jumper Settings |
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----------------------------- |
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All Jumpers & Switches are in their default positions. Please refer to |
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the board documentation for details. Some settings control CPU voltages |
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and settings may change with board revisions. |
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Choice #1 does not enable CONFIG_PCI, and assumes that the PCI slot |
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will be left empty (M66EN high), and so the board will operate with |
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a base clock of 66MHz. Note that you need both PCI enabled in u-boot |
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and linux in order to have functional PCI under linux. |
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|
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3. Known limitations |
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-------------------- |
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PCI: |
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The code to support PCI is currently disabled and has not been verified. |
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The second enables PCI support and builds for a 33MHz clock rate. Note |
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that if a 33MHz 32bit card is inserted in the slot, then the whole board |
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will clock down to a 33MHz base clock instead of the default 66MHz. This |
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will change the baud clocks and mess up your serial console output if you |
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were previously running at 66MHz. If you want to use a 33MHz PCI card, |
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then you should build a U-Boot with a _PCI_33_ config and store this |
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to flash prior to powering down the board and inserting the 33MHz PCI |
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card. [The above discussion assumes that the SW2[1-4] has not been changed |
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to reflect a different CCB:SYSCLK ratio] |
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|
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The third option builds PCI support in, and leaves the clocking at the |
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default 66MHz. Options four and five are just repeats of option two |
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and three, but with PCI-e support enabled as well. |
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|
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PCI output listing with an intel e1000 PCI-x and a Syskonnect SK-9Exx |
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is shown below for sbc8548_PCI_66_PCIE_config. (Note that PCI-e with |
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a 33MHz PCI configuration is currently untested.) |
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=> pci 0 |
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Scanning PCI devices on bus 0 |
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BusDevFun VendorId DeviceId Device Class Sub-Class |
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_____________________________________________________________ |
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00.00.00 0x1057 0x0012 Processor 0x20 |
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00.01.00 0x8086 0x1026 Network controller 0x00 |
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=> pci 1 |
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Scanning PCI devices on bus 1 |
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BusDevFun VendorId DeviceId Device Class Sub-Class |
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_____________________________________________________________ |
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01.00.00 0x1957 0x0012 Processor 0x20 |
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=> pci 2 |
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Scanning PCI devices on bus 2 |
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BusDevFun VendorId DeviceId Device Class Sub-Class |
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_____________________________________________________________ |
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02.00.00 0x1148 0x9e00 Network controller 0x00 |
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=> |
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Hardware Reference: |
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=================== |
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The following contains some summary information on hardware settings |
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that are relevant to u-boot, based on the board manual. For the |
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most up to date and complete details of the board, please request the |
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reference manual ERG-00327-001.pdf from www.windriver.com |
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Boot flash: |
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intel V28F640Jx, 8192x8 (one device) at 0xff80_0000 |
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Sodimm flash: |
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intel V28F128Jx, 16384x8 (4 devices) at 0xfb80_0000 |
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Jumpers: |
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Jumper Name ON OFF |
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---------------------------------------------------------------- |
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JP12 CS0/CS6 swap see note[*] see note[*] |
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JP13 SODIMM flash write OK writes disabled |
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write prot. |
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JP14 HRESET/TRST joined isolated |
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JP15 PWR ON when AC pwr use S1 for on/off |
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JP16 Demo LEDs lit not lit |
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JP19 PCI mode PCI PCI-X |
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[*]JP12, when jumpered parallel to the SODIMM, puts the boot flash |
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onto /CS0 and the SODIMM flash on /CS6 (default). When JP12 |
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is jumpered parallel to the LBC-SDRAM, then /CS0 is for the |
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SODIMM flash and /CS6 is for the boot flash. Note that in this |
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alternate setting, you also need to switch SW2.8 to ON. Currently |
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u-boot doesn't support booting off the SODIMM in this alternate |
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setting without manually altering BR0/OR0 and BR6/OR6 in the |
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board config file appropriately. |
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Switches: |
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The defaults are marked with a * |
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Name Desc. ON OFF |
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------------------------------------------------------------------ |
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S1 Pwr toggle n/a n/a |
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SW2.1 CFG_SYS_PLL0 1 0* |
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SW2.2 CFG_SYS_PLL1 1* 0 |
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SW2.3 CFG_SYS_PLL2 1* 0 |
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SW2.4 CFG_SYS_PLL3 1 0* |
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SW2.5 CFG_CORE_PLL0 1* 0 |
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SW2.6 CFG_CORE_PLL1 1 0* |
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SW2.7 CFG_CORE_PLL2 1* 0 |
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SW2.8 CFG_ROM_LOC1 1 0* |
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SW3.1 CFG_HOST_AGT0 1* 0 |
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SW3.2 CFG_HOST_AGT1 1* 0 |
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SW3.3 CFG_HOST_AGT2 1* 0 |
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SW3.4 CFG_IO_PORTS0 1* 0 |
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SW3.5 CFG_IO_PORTS0 1 0* |
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SW3.6 CFG_IO_PORTS0 1 0* |
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SerDes CLK(MHz) SW5.1 SW5.2 |
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---------------------------------------------- |
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25 0 0 |
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100* 1 0 |
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125 0 1 |
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200 1 1 |
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SerDes CLK spread SW5.3 SW5.4 |
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---------------------------------------------- |
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+/- 0.25% 0 0 |
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-0.50% 1 0 |
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-0.75% 0 1 |
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No Spread* 1 1 |
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SW4 settings are readable from the EPLD and are currently not used for |
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any hardware settings (i.e. user configuration switches). |
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LEDs: |
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Name Desc. ON OFF |
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------------------------------------------------------------------ |
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D13 PCI/PCI-X PCI-X PCI |
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D14 3.3V PWR 3.3V no power |
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D15 SYSCLK 66MHz 33MHz |
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Default Memory Map: |
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start end CS<n> width Desc. |
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---------------------------------------------------------------------- |
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0000_0000 0fff_ffff MCS0,1 64 DDR2 (256MB) |
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f000_0000 f7ff_ffff CS3,4 32 LB SDRAM (128MB) |
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f800_0000 f8b0_1fff CS5 - EPLD |
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fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB) |
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ff80_0000 ffff_ffff CS0 8 Boot flash (8MB) |
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The EPLD on CS5 demuxes the following devices at the following offsets: |
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offset size width device |
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-------------------------------------------------------- |
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0 1fff 8 7 segment display LED |
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10_0000 1fff 4 user switches |
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30_0000 1fff 4 HW Rev. register |
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b0_0000 1fff 8 8kB EEPROM |
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