Tom Rini
8 years ago
commit
5ebd27d860
@ -1,156 +0,0 @@ |
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/*
|
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* From Coreboot file of the same name |
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* |
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* Copyright (C) 2012 Chromium OS Authors |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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|
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/* mailbox 0: header */ |
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__packed struct opregion_header { |
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u8 signature[16]; |
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u32 size; |
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u32 version; |
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u8 sbios_version[32]; |
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u8 vbios_version[16]; |
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u8 driver_version[16]; |
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u32 mailboxes; |
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u8 reserved[164]; |
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}; |
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|
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#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" |
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#define IGD_OPREGION_VERSION 2 |
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#define IGD_MBOX1 (1 << 0) |
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#define IGD_MBOX2 (1 << 1) |
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#define IGD_MBOX3 (1 << 2) |
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#define IGD_MBOX4 (1 << 3) |
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#define IGD_MBOX5 (1 << 4) |
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|
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#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \ |
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IGD_MBOX4 | IGD_MBOX5) |
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#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4) |
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|
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#define SBIOS_VERSION_SIZE 32 |
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|
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/* mailbox 1: public acpi methods */ |
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__packed struct opregion_mailbox1 { |
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u32 drdy; |
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u32 csts; |
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u32 cevt; |
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u8 reserved1[20]; |
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u32 didl[8]; |
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u32 cpdl[8]; |
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u32 cadl[8]; |
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u32 nadl[8]; |
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u32 aslp; |
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u32 tidx; |
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u32 chpd; |
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u32 clid; |
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u32 cdck; |
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u32 sxsw; |
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u32 evts; |
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u32 cnot; |
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u32 nrdy; |
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u8 reserved2[60]; |
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}; |
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|
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/* mailbox 2: software sci interface */ |
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__packed struct opregion_mailbox2 { |
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u32 scic; |
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u32 parm; |
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u32 dslp; |
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u8 reserved[244]; |
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}; |
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|
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/* mailbox 3: power conservation */ |
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__packed struct opregion_mailbox3 { |
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u32 ardy; |
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u32 aslc; |
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u32 tche; |
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u32 alsi; |
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u32 bclp; |
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u32 pfit; |
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u32 cblv; |
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u16 bclm[20]; |
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u32 cpfm; |
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u32 epfm; |
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u8 plut[74]; |
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u32 pfmb; |
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u32 ccdv; |
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u32 pcft; |
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u8 reserved[94]; |
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}; |
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|
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#define IGD_BACKLIGHT_BRIGHTNESS 0xff |
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#define IGD_INITIAL_BRIGHTNESS 0x64 |
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|
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#define IGD_FIELD_VALID (1 << 31) |
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#define IGD_WORD_FIELD_VALID (1 << 15) |
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#define IGD_PFIT_STRETCH 6 |
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|
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/* mailbox 4: vbt */ |
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__packed struct { |
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u8 gvd1[7168]; |
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} opregion_vbt_t; |
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|
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/* IGD OpRegion */ |
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__packed struct igd_opregion { |
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opregion_header_t header; |
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opregion_mailbox1_t mailbox1; |
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opregion_mailbox2_t mailbox2; |
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opregion_mailbox3_t mailbox3; |
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opregion_vbt_t vbt; |
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}; |
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|
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/* Intel Video BIOS (Option ROM) */ |
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__packed struct optionrom_header { |
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u16 signature; |
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u8 size; |
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u8 reserved[21]; |
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u16 pcir_offset; |
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u16 vbt_offset; |
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}; |
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|
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#define OPROM_SIGNATURE 0xaa55 |
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|
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__packed struct optionrom_pcir { |
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u32 signature; |
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u16 vendor; |
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u16 device; |
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u16 reserved1; |
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u16 length; |
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u8 revision; |
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u8 classcode[3]; |
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u16 imagelength; |
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u16 coderevision; |
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u8 codetype; |
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u8 indicator; |
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u16 reserved2; |
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}; |
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|
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__packed struct optionrom_vbt { |
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u8 hdr_signature[20]; |
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u16 hdr_version; |
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u16 hdr_size; |
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u16 hdr_vbt_size; |
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u8 hdr_vbt_checksum; |
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u8 hdr_reserved; |
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u32 hdr_vbt_datablock; |
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u32 hdr_aim[4]; |
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u8 datahdr_signature[16]; |
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u16 datahdr_version; |
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u16 datahdr_size; |
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u16 datahdr_datablocksize; |
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u8 coreblock_id; |
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u16 coreblock_size; |
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u16 coreblock_biossize; |
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u8 coreblock_biostype; |
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u8 coreblock_releasestatus; |
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u8 coreblock_hwsupported; |
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u8 coreblock_integratedhw; |
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u8 coreblock_biosbuild[4]; |
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u8 coreblock_biossignon[155]; |
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}; |
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|
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#define VBT_SIGNATURE 0x54425624 |
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@ -0,0 +1,5 @@ |
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/ { |
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coreboot-fb { |
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compatible = "coreboot-fb"; |
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}; |
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}; |
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@ -1,12 +0,0 @@ |
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/*
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* Copyright (C) 2014 Google, Inc |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#ifndef _ASM_ARCH_BD82X6X_H |
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#define _ASM_ARCH_BD82X6X_H |
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int gma_func0_init(struct udevice *dev); |
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#endif |
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@ -0,0 +1,23 @@ |
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------------------------------ |
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U-Boot console UART selection: |
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------------------------------ |
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The U-Boot port for this congatec board currently supports two different |
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configurations (defconfig files). The only difference is the UART that |
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is used as the U-Boot console UART. The default defconfig file: |
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|
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conga-qeval20-qa3-e3845_defconfig |
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|
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provides this console on the UART0 which is provided via a Winbond |
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Super-IO chip connected on the congatec Qseven 2.0 evaluation carrier |
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board (conga-QEVAL). This UART is the one provided with a SubD9 |
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connector on the mainboard (the low one). The 2nd defconfig file: |
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|
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conga-qeval20-qa3-e3845-internal-uart_defconfig |
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provides the U-Boot console on the BayTrail internal legacy UART, |
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which is routed from the QSeven SoM to the X300 connector on the |
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baseboard. Here is called COM2. The baseboard already provides the |
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RS232 level shifters. So a TTL-USB UART adapter does not work in |
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this case. The signals need to get connected directly to the |
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RS232 level signals of the PC UART via some adapter cable. |
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@ -0,0 +1,79 @@ |
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/*
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* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <vbe.h> |
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#include <video.h> |
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#include <asm/arch/sysinfo.h> |
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static int save_vesa_mode(struct cb_framebuffer *fb, |
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struct vesa_mode_info *vesa) |
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{ |
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/*
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* If there is no framebuffer structure, bail out and keep |
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* running on the serial console. |
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*/ |
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if (!fb) |
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return -ENXIO; |
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vesa->x_resolution = fb->x_resolution; |
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vesa->y_resolution = fb->y_resolution; |
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vesa->bits_per_pixel = fb->bits_per_pixel; |
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vesa->bytes_per_scanline = fb->bytes_per_line; |
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vesa->phys_base_ptr = fb->physical_address; |
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vesa->red_mask_size = fb->red_mask_size; |
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vesa->red_mask_pos = fb->red_mask_pos; |
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vesa->green_mask_size = fb->green_mask_size; |
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vesa->green_mask_pos = fb->green_mask_pos; |
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vesa->blue_mask_size = fb->blue_mask_size; |
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vesa->blue_mask_pos = fb->blue_mask_pos; |
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vesa->reserved_mask_size = fb->reserved_mask_size; |
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vesa->reserved_mask_pos = fb->reserved_mask_pos; |
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return 0; |
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} |
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static int coreboot_video_probe(struct udevice *dev) |
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{ |
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struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); |
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struct video_priv *uc_priv = dev_get_uclass_priv(dev); |
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struct cb_framebuffer *fb = lib_sysinfo.framebuffer; |
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struct vesa_mode_info *vesa = &mode_info.vesa; |
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int ret; |
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printf("Video: "); |
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/* Initialize vesa_mode_info structure */ |
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ret = save_vesa_mode(fb, vesa); |
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if (ret) |
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goto err; |
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ret = vbe_setup_video_priv(vesa, uc_priv, plat); |
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if (ret) |
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goto err; |
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printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize, |
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vesa->bits_per_pixel); |
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return 0; |
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err: |
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printf("No video mode configured in coreboot!\n"); |
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return ret; |
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} |
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static const struct udevice_id coreboot_video_ids[] = { |
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{ .compatible = "coreboot-fb" }, |
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{ } |
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}; |
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U_BOOT_DRIVER(coreboot_video) = { |
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.name = "coreboot_video", |
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.id = UCLASS_VIDEO, |
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.of_match = coreboot_video_ids, |
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.probe = coreboot_video_probe, |
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}; |
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@ -1,108 +0,0 @@ |
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/*
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* coreboot Framebuffer driver. |
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* |
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* Copyright (C) 2011 The Chromium OS authors |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/arch/sysinfo.h> |
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#include <vbe.h> |
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#include <video_fb.h> |
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#include "videomodes.h" |
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/*
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* The Graphic Device |
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*/ |
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GraphicDevice ctfb; |
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static void save_vesa_mode(void) |
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{ |
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struct vesa_mode_info *vesa = &mode_info.vesa; |
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struct cb_framebuffer *fb = lib_sysinfo.framebuffer; |
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vesa->x_resolution = fb->x_resolution; |
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vesa->y_resolution = fb->y_resolution; |
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vesa->bits_per_pixel = fb->bits_per_pixel; |
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vesa->bytes_per_scanline = fb->bytes_per_line; |
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vesa->phys_base_ptr = fb->physical_address; |
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vesa->red_mask_size = fb->red_mask_size; |
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vesa->red_mask_pos = fb->red_mask_pos; |
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vesa->green_mask_size = fb->green_mask_size; |
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vesa->green_mask_pos = fb->green_mask_pos; |
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vesa->blue_mask_size = fb->blue_mask_size; |
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vesa->blue_mask_pos = fb->blue_mask_pos; |
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vesa->reserved_mask_size = fb->reserved_mask_size; |
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vesa->reserved_mask_pos = fb->reserved_mask_pos; |
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} |
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static int parse_coreboot_table_fb(GraphicDevice *gdev) |
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{ |
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struct cb_framebuffer *fb = lib_sysinfo.framebuffer; |
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/* If there is no framebuffer structure, bail out and keep
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* running on the serial console. |
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*/ |
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if (!fb) |
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return 0; |
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gdev->winSizeX = fb->x_resolution; |
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gdev->winSizeY = fb->y_resolution; |
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gdev->plnSizeX = fb->x_resolution; |
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gdev->plnSizeY = fb->y_resolution; |
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gdev->gdfBytesPP = fb->bits_per_pixel / 8; |
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switch (fb->bits_per_pixel) { |
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case 24: |
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gdev->gdfIndex = GDF_32BIT_X888RGB; |
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break; |
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case 16: |
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gdev->gdfIndex = GDF_16BIT_565RGB; |
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break; |
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default: |
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gdev->gdfIndex = GDF__8BIT_INDEX; |
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break; |
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} |
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gdev->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS; |
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gdev->pciBase = (unsigned int)fb->physical_address; |
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gdev->frameAdrs = (unsigned int)fb->physical_address; |
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gdev->memSize = fb->bytes_per_line * fb->y_resolution; |
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|
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gdev->vprBase = (unsigned int)fb->physical_address; |
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gdev->cprBase = (unsigned int)fb->physical_address; |
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return 1; |
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} |
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void *video_hw_init(void) |
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{ |
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GraphicDevice *gdev = &ctfb; |
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int bits_per_pixel; |
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printf("Video: "); |
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|
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if (!parse_coreboot_table_fb(gdev)) { |
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printf("No video mode configured in coreboot!\n"); |
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return NULL; |
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} |
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|
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bits_per_pixel = gdev->gdfBytesPP * 8; |
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|
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/* fill in Graphic device struct */ |
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sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY, |
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bits_per_pixel); |
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printf("%s\n", gdev->modeIdent); |
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|
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memset((void *)gdev->pciBase, 0, |
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gdev->winSizeX * gdev->winSizeY * gdev->gdfBytesPP); |
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|
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/* Initialize vesa_mode_info structure */ |
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save_vesa_mode(); |
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return (void *)gdev; |
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} |
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@ -0,0 +1,34 @@ |
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/*
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* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <dm.h> |
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#include <pci.h> |
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#include <vbe.h> |
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|
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static int vesa_video_probe(struct udevice *dev) |
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{ |
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return vbe_setup_video(dev, NULL); |
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} |
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|
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static const struct udevice_id vesa_video_ids[] = { |
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{ .compatible = "vesa-fb" }, |
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{ } |
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}; |
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|
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U_BOOT_DRIVER(vesa_video) = { |
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.name = "vesa_video", |
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.id = UCLASS_VIDEO, |
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.of_match = vesa_video_ids, |
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.probe = vesa_video_probe, |
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}; |
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|
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static struct pci_device_id vesa_video_supported[] = { |
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{ PCI_DEVICE_CLASS(PCI_CLASS_DISPLAY_VGA << 8, ~0) }, |
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{ }, |
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}; |
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|
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U_BOOT_PCI_DEVICE(vesa_video, vesa_video_supported); |
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@ -1,63 +0,0 @@ |
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/*
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* VESA frame buffer driver |
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* |
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* Copyright (C) 2014 Google, Inc |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <pci_rom.h> |
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#include <video_fb.h> |
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#include <vbe.h> |
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|
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/*
|
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* The Graphic Device |
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*/ |
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GraphicDevice ctfb; |
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|
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void *video_hw_init(void) |
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{ |
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GraphicDevice *gdev = &ctfb; |
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struct udevice *dev; |
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int bits_per_pixel; |
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int ret; |
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|
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printf("Video: "); |
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if (!ll_boot_init()) { |
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/*
|
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* If we are running from EFI or coreboot, this driver can't |
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* work. |
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*/ |
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printf("Not available (previous bootloader prevents it)\n"); |
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return NULL; |
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} |
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if (vbe_get_video_info(gdev)) { |
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ret = dm_pci_find_class(PCI_CLASS_DISPLAY_VGA << 8, 0, &dev); |
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if (ret) { |
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printf("no card detected\n"); |
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return NULL; |
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} |
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bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display"); |
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ret = dm_pci_run_vga_bios(dev, NULL, PCI_ROM_USE_NATIVE | |
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PCI_ROM_ALLOW_FALLBACK); |
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bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD); |
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if (ret) { |
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printf("failed to run video BIOS: %d\n", ret); |
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return NULL; |
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} |
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} |
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|
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if (vbe_get_video_info(gdev)) { |
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printf("No video mode configured\n"); |
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return NULL; |
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} |
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|
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bits_per_pixel = gdev->gdfBytesPP * 8; |
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sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY, |
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bits_per_pixel); |
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printf("%s\n", gdev->modeIdent); |
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debug("Frame buffer at %x\n", gdev->pciBase); |
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|
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return (void *)gdev; |
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} |
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Loading…
Reference in new issue