This patch adds ehci driver support for s5p. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>master
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/*
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* SAMSUNG S5P USB HOST EHCI Controller |
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* |
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* Copyright (C) 2012 Samsung Electronics Co.Ltd |
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* Vivek Gautam <gautam.vivek@samsung.com> |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
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* MA 02110-1301 USA |
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*/ |
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#ifndef __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ |
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#define __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ |
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#define CLK_24MHZ 5 |
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#define HOST_CTRL0_PHYSWRSTALL (1 << 31) |
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#define HOST_CTRL0_COMMONON_N (1 << 9) |
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#define HOST_CTRL0_SIDDQ (1 << 6) |
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#define HOST_CTRL0_FORCESLEEP (1 << 5) |
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#define HOST_CTRL0_FORCESUSPEND (1 << 4) |
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#define HOST_CTRL0_WORDINTERFACE (1 << 3) |
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#define HOST_CTRL0_UTMISWRST (1 << 2) |
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#define HOST_CTRL0_LINKSWRST (1 << 1) |
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#define HOST_CTRL0_PHYSWRST (1 << 0) |
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#define HOST_CTRL0_FSEL_MASK (7 << 16) |
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#define EHCICTRL_ENAINCRXALIGN (1 << 29) |
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#define EHCICTRL_ENAINCR4 (1 << 28) |
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#define EHCICTRL_ENAINCR8 (1 << 27) |
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#define EHCICTRL_ENAINCR16 (1 << 26) |
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/* Register map for PHY control */ |
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struct s5p_usb_phy { |
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unsigned int usbphyctrl0; |
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unsigned int usbphytune0; |
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unsigned int reserved1[2]; |
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unsigned int hsicphyctrl1; |
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unsigned int hsicphytune1; |
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unsigned int reserved2[2]; |
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unsigned int hsicphyctrl2; |
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unsigned int hsicphytune2; |
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unsigned int reserved3[2]; |
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unsigned int ehcictrl; |
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unsigned int ohcictrl; |
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unsigned int usbotgsys; |
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unsigned int reserved4; |
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unsigned int usbotgtune; |
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}; |
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/* Switch on the VBUS power. */ |
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int board_usb_vbus_init(void); |
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#endif /* __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ */ |
@ -0,0 +1,110 @@ |
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/*
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* SAMSUNG S5P USB HOST EHCI Controller |
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* |
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* Copyright (C) 2012 Samsung Electronics Co.Ltd |
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* Vivek Gautam <gautam.vivek@samsung.com> |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
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* MA 02110-1301 USA |
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*/ |
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#include <common.h> |
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#include <usb.h> |
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#include <asm/arch/cpu.h> |
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#include <asm/arch/ehci-s5p.h> |
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#include "ehci.h" |
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#include "ehci-core.h" |
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/* Setup the EHCI host controller. */ |
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static void setup_usb_phy(struct s5p_usb_phy *usb) |
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{ |
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clrbits_le32(&usb->usbphyctrl0, |
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HOST_CTRL0_FSEL_MASK | |
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HOST_CTRL0_COMMONON_N | |
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/* HOST Phy setting */ |
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HOST_CTRL0_PHYSWRST | |
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HOST_CTRL0_PHYSWRSTALL | |
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HOST_CTRL0_SIDDQ | |
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HOST_CTRL0_FORCESUSPEND | |
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HOST_CTRL0_FORCESLEEP); |
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setbits_le32(&usb->usbphyctrl0, |
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/* Setting up the ref freq */ |
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(CLK_24MHZ << 16) | |
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/* HOST Phy setting */ |
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HOST_CTRL0_LINKSWRST | |
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HOST_CTRL0_UTMISWRST); |
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udelay(10); |
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clrbits_le32(&usb->usbphyctrl0, |
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HOST_CTRL0_LINKSWRST | |
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HOST_CTRL0_UTMISWRST); |
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udelay(20); |
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/* EHCI Ctrl setting */ |
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setbits_le32(&usb->ehcictrl, |
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EHCICTRL_ENAINCRXALIGN | |
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EHCICTRL_ENAINCR4 | |
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EHCICTRL_ENAINCR8 | |
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EHCICTRL_ENAINCR16); |
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} |
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/* Reset the EHCI host controller. */ |
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static void reset_usb_phy(struct s5p_usb_phy *usb) |
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{ |
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/* HOST_PHY reset */ |
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setbits_le32(&usb->usbphyctrl0, |
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HOST_CTRL0_PHYSWRST | |
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HOST_CTRL0_PHYSWRSTALL | |
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HOST_CTRL0_SIDDQ | |
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HOST_CTRL0_FORCESUSPEND | |
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HOST_CTRL0_FORCESLEEP); |
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} |
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/*
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* EHCI-initialization |
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* Create the appropriate control structures to manage |
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* a new EHCI host controller. |
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*/ |
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int ehci_hcd_init(void) |
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{ |
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struct s5p_usb_phy *usb; |
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usb = (struct s5p_usb_phy *)samsung_get_base_usb_phy(); |
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setup_usb_phy(usb); |
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hccr = (struct ehci_hccr *)(EXYNOS5_USB_HOST_EHCI_BASE); |
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hcor = (struct ehci_hcor *)((uint32_t) hccr |
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+ HC_LENGTH(ehci_readl(&hccr->cr_capbase))); |
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debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n", |
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(uint32_t)hccr, (uint32_t)hcor, |
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(uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); |
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return 0; |
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} |
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/*
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* Destroy the appropriate control structures corresponding |
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* the EHCI host controller. |
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*/ |
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int ehci_hcd_stop() |
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{ |
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struct s5p_usb_phy *usb; |
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usb = (struct s5p_usb_phy *)samsung_get_base_usb_phy(); |
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reset_usb_phy(usb); |
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return 0; |
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} |
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