Add support for the Freescale MPC8360EMDS board. Includes DDR, DUART, Local Bus, PCI.master
Dave Liu
18 years ago
committed by
Kim Phillips
parent
23892e4935
commit
5f8204394e
@ -0,0 +1,50 @@ |
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o pci.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,28 @@ |
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# MPC8360EMDS
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#
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TEXT_BASE = 0xFE000000
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@ -0,0 +1,574 @@ |
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/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc. |
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* |
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* Dave Liu <daveliu@freescale.com> |
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* based on board/mpc8349emds/mpc8349emds.c |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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*/ |
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#include <common.h> |
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#include <ioports.h> |
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#include <mpc83xx.h> |
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#include <i2c.h> |
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#include <spd.h> |
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#include <miiphy.h> |
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#include <command.h> |
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#if defined(CONFIG_PCI) |
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#include <pci.h> |
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#endif |
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#if defined(CONFIG_SPD_EEPROM) |
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#include <spd_sdram.h> |
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#else |
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#include <asm/mmu.h> |
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#endif |
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int board_early_init_f(void) |
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{ |
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volatile u8 *bcsr = (volatile u8 *)CFG_BCSR; |
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/* Enable flash write */ |
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bcsr[0xa] &= ~0x04; |
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return 0; |
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} |
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) |
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extern void ddr_enable_ecc(unsigned int dram_size); |
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#endif |
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int fixed_sdram(void); |
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void sdram_init(void); |
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long int initdram(int board_type) |
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{ |
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volatile immap_t *im = (immap_t *) CFG_IMMRBAR; |
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u32 msize = 0; |
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) |
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return -1; |
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/* DDR SDRAM - Main SODIMM */ |
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im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; |
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#if defined(CONFIG_SPD_EEPROM) |
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msize = spd_sdram(); |
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#else |
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msize = fixed_sdram(); |
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#endif |
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) |
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/*
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* Initialize DDR ECC byte |
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*/ |
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ddr_enable_ecc(msize * 1024 * 1024); |
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#endif |
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/*
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* Initialize SDRAM if it is on local bus. |
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*/ |
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sdram_init(); |
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puts(" DDR RAM: "); |
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/* return total bus SDRAM size(bytes) -- DDR */ |
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return (msize * 1024 * 1024); |
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} |
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#if !defined(CONFIG_SPD_EEPROM) |
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect. |
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************************************************************************/ |
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int fixed_sdram(void) |
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{ |
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volatile immap_t *im = (immap_t *) CFG_IMMRBAR; |
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u32 msize = 0; |
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u32 ddr_size; |
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u32 ddr_size_log2; |
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msize = CFG_DDR_SIZE; |
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for (ddr_size = msize << 20, ddr_size_log2 = 0; |
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(ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { |
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if (ddr_size & 1) { |
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return -1; |
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} |
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} |
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im->sysconf.ddrlaw[0].ar = |
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LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); |
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#if (CFG_DDR_SIZE != 256) |
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#warning Currenly any ddr size other than 256 is not supported |
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#endif |
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im->ddr.csbnds[0].csbnds = 0x00000007; |
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im->ddr.csbnds[1].csbnds = 0x0008000f; |
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im->ddr.cs_config[0] = CFG_DDR_CONFIG; |
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im->ddr.cs_config[1] = CFG_DDR_CONFIG; |
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im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; |
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im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; |
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im->ddr.sdram_cfg = CFG_DDR_CONTROL; |
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im->ddr.sdram_mode = CFG_DDR_MODE; |
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im->ddr.sdram_interval = CFG_DDR_INTERVAL; |
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udelay(200); |
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; |
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return msize; |
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} |
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#endif /*!CFG_SPD_EEPROM */ |
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int checkboard(void) |
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{ |
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puts("Board: Freescale MPC8360EMDS\n"); |
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return 0; |
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} |
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/*
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* if MPC8360EMDS is soldered with SDRAM |
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*/ |
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#if defined(CFG_BR2_PRELIM) \ |
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&& defined(CFG_OR2_PRELIM) \
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&& defined(CFG_LBLAWBAR2_PRELIM) \
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&& defined(CFG_LBLAWAR2_PRELIM) |
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/*
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* Initialize SDRAM memory on the Local Bus. |
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*/ |
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void sdram_init(void) |
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{ |
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volatile immap_t *immap = (immap_t *) CFG_IMMRBAR; |
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volatile lbus83xx_t *lbc = &immap->lbus; |
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uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE; |
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puts("\n SDRAM on Local Bus: "); |
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print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); |
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/*
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* Setup SDRAM Base and Option Registers, already done in cpu_init.c |
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*/ |
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/*setup mtrpt, lsrt and lbcr for LB bus */ |
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lbc->lbcr = CFG_LBC_LBCR; |
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lbc->mrtpr = CFG_LBC_MRTPR; |
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lbc->lsrt = CFG_LBC_LSRT; |
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asm("sync"); |
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/*
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* Configure the SDRAM controller Machine Mode Register. |
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*/ |
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lbc->lsdmr = CFG_LBC_LSDMR_5; /* Normal Operation */ |
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lbc->lsdmr = CFG_LBC_LSDMR_1; /* Precharge All Banks */ |
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asm("sync"); |
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*sdram_addr = 0xff; |
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udelay(100); |
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/*
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* We need do 8 times auto refresh operation. |
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*/ |
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lbc->lsdmr = CFG_LBC_LSDMR_2; |
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asm("sync"); |
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*sdram_addr = 0xff; /* 1 times */ |
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udelay(100); |
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*sdram_addr = 0xff; /* 2 times */ |
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udelay(100); |
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*sdram_addr = 0xff; /* 3 times */ |
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udelay(100); |
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*sdram_addr = 0xff; /* 4 times */ |
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udelay(100); |
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*sdram_addr = 0xff; /* 5 times */ |
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udelay(100); |
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*sdram_addr = 0xff; /* 6 times */ |
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udelay(100); |
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*sdram_addr = 0xff; /* 7 times */ |
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udelay(100); |
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*sdram_addr = 0xff; /* 8 times */ |
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udelay(100); |
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/* Mode register write operation */ |
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lbc->lsdmr = CFG_LBC_LSDMR_4; |
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asm("sync"); |
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*(sdram_addr + 0xcc) = 0xff; |
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udelay(100); |
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/* Normal operation */ |
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lbc->lsdmr = CFG_LBC_LSDMR_5 | 0x40000000; |
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asm("sync"); |
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*sdram_addr = 0xff; |
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udelay(100); |
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} |
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#else |
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void sdram_init(void) |
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{ |
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puts("SDRAM on Local Bus is NOT available!\n"); |
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} |
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#endif |
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#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) |
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/*
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* ECC user commands |
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*/ |
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void ecc_print_status(void) |
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{ |
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volatile immap_t *immap = (immap_t *) CFG_IMMRBAR; |
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volatile ddr83xx_t *ddr = &immap->ddr; |
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printf("\nECC mode: %s\n\n", |
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(ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF"); |
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/* Interrupts */ |
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printf("Memory Error Interrupt Enable:\n"); |
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printf(" Multiple-Bit Error Interrupt Enable: %d\n", |
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(ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0); |
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printf(" Single-Bit Error Interrupt Enable: %d\n", |
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(ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0); |
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printf(" Memory Select Error Interrupt Enable: %d\n\n", |
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(ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0); |
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/* Error disable */ |
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printf("Memory Error Disable:\n"); |
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printf(" Multiple-Bit Error Disable: %d\n", |
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(ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0); |
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printf(" Sinle-Bit Error Disable: %d\n", |
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(ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0); |
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printf(" Memory Select Error Disable: %d\n\n", |
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(ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0); |
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/* Error injection */ |
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printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n", |
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ddr->data_err_inject_hi, ddr->data_err_inject_lo); |
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printf("Memory Data Path Error Injection Mask ECC:\n"); |
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printf(" ECC Mirror Byte: %d\n", |
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(ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0); |
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printf(" ECC Injection Enable: %d\n", |
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(ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0); |
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printf(" ECC Error Injection Mask: 0x%02x\n\n", |
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ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM); |
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/* SBE counter/threshold */ |
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printf("Memory Single-Bit Error Management (0..255):\n"); |
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printf(" Single-Bit Error Threshold: %d\n", |
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(ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT); |
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printf(" Single-Bit Error Counter: %d\n\n", |
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(ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT); |
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/* Error detect */ |
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printf("Memory Error Detect:\n"); |
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printf(" Multiple Memory Errors: %d\n", |
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(ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0); |
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printf(" Multiple-Bit Error: %d\n", |
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(ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0); |
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printf(" Single-Bit Error: %d\n", |
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(ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0); |
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printf(" Memory Select Error: %d\n\n", |
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(ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0); |
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/* Capture data */ |
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printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address); |
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printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n", |
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ddr->capture_data_hi, ddr->capture_data_lo); |
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printf("Memory Data Path Read Capture ECC: 0x%02x\n\n", |
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ddr->capture_ecc & CAPTURE_ECC_ECE); |
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printf("Memory Error Attributes Capture:\n"); |
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printf(" Data Beat Number: %d\n", |
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(ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> |
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ECC_CAPT_ATTR_BNUM_SHIFT); |
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printf(" Transaction Size: %d\n", |
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(ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> |
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ECC_CAPT_ATTR_TSIZ_SHIFT); |
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printf(" Transaction Source: %d\n", |
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(ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> |
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ECC_CAPT_ATTR_TSRC_SHIFT); |
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printf(" Transaction Type: %d\n", |
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(ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> |
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ECC_CAPT_ATTR_TTYP_SHIFT); |
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printf(" Error Information Valid: %d\n\n", |
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ddr->capture_attributes & ECC_CAPT_ATTR_VLD); |
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} |
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int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) |
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{ |
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volatile immap_t *immap = (immap_t *) CFG_IMMRBAR; |
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volatile ddr83xx_t *ddr = &immap->ddr; |
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volatile u32 val; |
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u64 *addr; |
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u32 count; |
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register u64 *i; |
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u32 ret[2]; |
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u32 pattern[2]; |
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u32 writeback[2]; |
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/* The pattern is written into memory to generate error */ |
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pattern[0] = 0xfedcba98UL; |
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pattern[1] = 0x76543210UL; |
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/* After injecting error, re-initialize the memory with the value */ |
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writeback[0] = 0x01234567UL; |
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writeback[1] = 0x89abcdefUL; |
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if (argc > 4) { |
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printf("Usage:\n%s\n", cmdtp->usage); |
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return 1; |
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} |
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if (argc == 2) { |
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if (strcmp(argv[1], "status") == 0) { |
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ecc_print_status(); |
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return 0; |
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} else if (strcmp(argv[1], "captureclear") == 0) { |
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ddr->capture_address = 0; |
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ddr->capture_data_hi = 0; |
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ddr->capture_data_lo = 0; |
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ddr->capture_ecc = 0; |
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ddr->capture_attributes = 0; |
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return 0; |
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} |
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} |
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if (argc == 3) { |
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if (strcmp(argv[1], "sbecnt") == 0) { |
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val = simple_strtoul(argv[2], NULL, 10); |
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if (val > 255) { |
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printf("Incorrect Counter value, " |
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"should be 0..255\n"); |
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return 1; |
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} |
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val = (val << ECC_ERROR_MAN_SBEC_SHIFT); |
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val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET); |
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ddr->err_sbe = val; |
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return 0; |
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} else if (strcmp(argv[1], "sbethr") == 0) { |
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val = simple_strtoul(argv[2], NULL, 10); |
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if (val > 255) { |
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printf("Incorrect Counter value, " |
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"should be 0..255\n"); |
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return 1; |
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} |
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val = (val << ECC_ERROR_MAN_SBET_SHIFT); |
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val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC); |
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ddr->err_sbe = val; |
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return 0; |
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} else if (strcmp(argv[1], "errdisable") == 0) { |
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val = ddr->err_disable; |
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if (strcmp(argv[2], "+sbe") == 0) { |
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val |= ECC_ERROR_DISABLE_SBED; |
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} else if (strcmp(argv[2], "+mbe") == 0) { |
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val |= ECC_ERROR_DISABLE_MBED; |
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} else if (strcmp(argv[2], "+mse") == 0) { |
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val |= ECC_ERROR_DISABLE_MSED; |
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} else if (strcmp(argv[2], "+all") == 0) { |
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val |= (ECC_ERROR_DISABLE_SBED | |
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ECC_ERROR_DISABLE_MBED | |
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ECC_ERROR_DISABLE_MSED); |
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} else if (strcmp(argv[2], "-sbe") == 0) { |
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val &= ~ECC_ERROR_DISABLE_SBED; |
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} else if (strcmp(argv[2], "-mbe") == 0) { |
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val &= ~ECC_ERROR_DISABLE_MBED; |
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} else if (strcmp(argv[2], "-mse") == 0) { |
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val &= ~ECC_ERROR_DISABLE_MSED; |
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} else if (strcmp(argv[2], "-all") == 0) { |
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val &= ~(ECC_ERROR_DISABLE_SBED | |
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ECC_ERROR_DISABLE_MBED | |
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ECC_ERROR_DISABLE_MSED); |
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} else { |
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printf("Incorrect err_disable field\n"); |
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return 1; |
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} |
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ddr->err_disable = val; |
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__asm__ __volatile__("sync"); |
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__asm__ __volatile__("isync"); |
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return 0; |
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} else if (strcmp(argv[1], "errdetectclr") == 0) { |
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val = ddr->err_detect; |
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if (strcmp(argv[2], "mme") == 0) { |
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val |= ECC_ERROR_DETECT_MME; |
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} else if (strcmp(argv[2], "sbe") == 0) { |
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val |= ECC_ERROR_DETECT_SBE; |
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} else if (strcmp(argv[2], "mbe") == 0) { |
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val |= ECC_ERROR_DETECT_MBE; |
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} else if (strcmp(argv[2], "mse") == 0) { |
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val |= ECC_ERROR_DETECT_MSE; |
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} else if (strcmp(argv[2], "all") == 0) { |
||||
val |= (ECC_ERROR_DETECT_MME | |
||||
ECC_ERROR_DETECT_MBE | |
||||
ECC_ERROR_DETECT_SBE | |
||||
ECC_ERROR_DETECT_MSE); |
||||
} else { |
||||
printf("Incorrect err_detect field\n"); |
||||
return 1; |
||||
} |
||||
|
||||
ddr->err_detect = val; |
||||
return 0; |
||||
} else if (strcmp(argv[1], "injectdatahi") == 0) { |
||||
val = simple_strtoul(argv[2], NULL, 16); |
||||
|
||||
ddr->data_err_inject_hi = val; |
||||
return 0; |
||||
} else if (strcmp(argv[1], "injectdatalo") == 0) { |
||||
val = simple_strtoul(argv[2], NULL, 16); |
||||
|
||||
ddr->data_err_inject_lo = val; |
||||
return 0; |
||||
} else if (strcmp(argv[1], "injectecc") == 0) { |
||||
val = simple_strtoul(argv[2], NULL, 16); |
||||
if (val > 0xff) { |
||||
printf("Incorrect ECC inject mask, " |
||||
"should be 0x00..0xff\n"); |
||||
return 1; |
||||
} |
||||
val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM); |
||||
|
||||
ddr->ecc_err_inject = val; |
||||
return 0; |
||||
} else if (strcmp(argv[1], "inject") == 0) { |
||||
val = ddr->ecc_err_inject; |
||||
|
||||
if (strcmp(argv[2], "en") == 0) |
||||
val |= ECC_ERR_INJECT_EIEN; |
||||
else if (strcmp(argv[2], "dis") == 0) |
||||
val &= ~ECC_ERR_INJECT_EIEN; |
||||
else |
||||
printf("Incorrect command\n"); |
||||
|
||||
ddr->ecc_err_inject = val; |
||||
__asm__ __volatile__("sync"); |
||||
__asm__ __volatile__("isync"); |
||||
return 0; |
||||
} else if (strcmp(argv[1], "mirror") == 0) { |
||||
val = ddr->ecc_err_inject; |
||||
|
||||
if (strcmp(argv[2], "en") == 0) |
||||
val |= ECC_ERR_INJECT_EMB; |
||||
else if (strcmp(argv[2], "dis") == 0) |
||||
val &= ~ECC_ERR_INJECT_EMB; |
||||
else |
||||
printf("Incorrect command\n"); |
||||
|
||||
ddr->ecc_err_inject = val; |
||||
return 0; |
||||
} |
||||
} |
||||
if (argc == 4) { |
||||
if (strcmp(argv[1], "testdw") == 0) { |
||||
addr = (u64 *) simple_strtoul(argv[2], NULL, 16); |
||||
count = simple_strtoul(argv[3], NULL, 16); |
||||
|
||||
if ((u32) addr % 8) { |
||||
printf("Address not alligned on " |
||||
"double word boundary\n"); |
||||
return 1; |
||||
} |
||||
disable_interrupts(); |
||||
|
||||
for (i = addr; i < addr + count; i++) { |
||||
|
||||
/* enable injects */ |
||||
ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN; |
||||
__asm__ __volatile__("sync"); |
||||
__asm__ __volatile__("isync"); |
||||
|
||||
/* write memory location injecting errors */ |
||||
ppcDWstore((u32 *) i, pattern); |
||||
|
||||
/* disable injects */ |
||||
ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN; |
||||
__asm__ __volatile__("sync"); |
||||
__asm__ __volatile__("isync"); |
||||
|
||||
/* read data, this generates ECC error */ |
||||
ppcDWload((u32 *) i, ret); |
||||
|
||||
/* re-initialize memory, double word write the location again,
|
||||
* generates new ECC code this time */ |
||||
ppcDWstore((u32 *) i, writeback); |
||||
} |
||||
enable_interrupts(); |
||||
return 0; |
||||
} |
||||
if (strcmp(argv[1], "testword") == 0) { |
||||
addr = (u64 *) simple_strtoul(argv[2], NULL, 16); |
||||
count = simple_strtoul(argv[3], NULL, 16); |
||||
|
||||
if ((u32) addr % 8) { |
||||
printf("Address not alligned on " |
||||
"double word boundary\n"); |
||||
return 1; |
||||
} |
||||
disable_interrupts(); |
||||
|
||||
for (i = addr; i < addr + count; i++) { |
||||
|
||||
/* enable injects */ |
||||
ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN; |
||||
__asm__ __volatile__("sync"); |
||||
__asm__ __volatile__("isync"); |
||||
|
||||
/* write memory location injecting errors */ |
||||
*(u32 *) i = 0xfedcba98UL; |
||||
__asm__ __volatile__("sync"); |
||||
|
||||
/* sub double word write,
|
||||
* bus will read-modify-write, |
||||
* generates ECC error */ |
||||
*((u32 *) i + 1) = 0x76543210UL; |
||||
__asm__ __volatile__("sync"); |
||||
|
||||
/* disable injects */ |
||||
ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN; |
||||
__asm__ __volatile__("sync"); |
||||
__asm__ __volatile__("isync"); |
||||
|
||||
/* re-initialize memory,
|
||||
* double word write the location again, |
||||
* generates new ECC code this time */ |
||||
ppcDWstore((u32 *) i, writeback); |
||||
} |
||||
enable_interrupts(); |
||||
return 0; |
||||
} |
||||
} |
||||
printf("Usage:\n%s\n", cmdtp->usage); |
||||
return 1; |
||||
} |
||||
|
||||
U_BOOT_CMD(ecc, 4, 0, do_ecc, |
||||
"ecc - support for DDR ECC features\n", |
||||
"status - print out status info\n" |
||||
"ecc captureclear - clear capture regs data\n" |
||||
"ecc sbecnt <val> - set Single-Bit Error counter\n" |
||||
"ecc sbethr <val> - set Single-Bit Threshold\n" |
||||
"ecc errdisable <flag> - clear/set disable Memory Error Disable, flag:\n" |
||||
" [-|+]sbe - Single-Bit Error\n" |
||||
" [-|+]mbe - Multiple-Bit Error\n" |
||||
" [-|+]mse - Memory Select Error\n" |
||||
" [-|+]all - all errors\n" |
||||
"ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n" |
||||
" mme - Multiple Memory Errors\n" |
||||
" sbe - Single-Bit Error\n" |
||||
" mbe - Multiple-Bit Error\n" |
||||
" mse - Memory Select Error\n" |
||||
" all - all errors\n" |
||||
"ecc injectdatahi <hi> - set Memory Data Path Error Injection Mask High\n" |
||||
"ecc injectdatalo <lo> - set Memory Data Path Error Injection Mask Low\n" |
||||
"ecc injectecc <ecc> - set ECC Error Injection Mask\n" |
||||
"ecc inject <en|dis> - enable/disable error injection\n" |
||||
"ecc mirror <en|dis> - enable/disable mirror byte\n" |
||||
"ecc testdw <addr> <cnt> - test mem region with double word access:\n" |
||||
" - enables injects\n" |
||||
" - writes pattern injecting errors with double word access\n" |
||||
" - disables injects\n" |
||||
" - reads pattern back with double word access, generates error\n" |
||||
" - re-inits memory\n" |
||||
"ecc testword <addr> <cnt> - test mem region with word access:\n" |
||||
" - enables injects\n" |
||||
" - writes pattern injecting errors with word access\n" |
||||
" - writes pattern with word access, generates error\n" |
||||
" - disables injects\n" " - re-inits memory"); |
||||
#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */ |
||||
@ -0,0 +1,294 @@ |
||||
/*
|
||||
* Copyright (C) 2006 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
*/ |
||||
|
||||
/*
|
||||
* PCI Configuration space access support for MPC83xx PCI Bridge |
||||
*/ |
||||
#include <asm/mmu.h> |
||||
#include <asm/io.h> |
||||
#include <common.h> |
||||
#include <pci.h> |
||||
#include <i2c.h> |
||||
|
||||
#include <asm/i2c.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
#define PCI_FUNCTION_CONFIG 0x44 |
||||
#define PCI_FUNCTION_CFG_LOCK 0x20 |
||||
|
||||
/*
|
||||
* Initialize PCI Devices, report devices found |
||||
*/ |
||||
#ifndef CONFIG_PCI_PNP |
||||
static struct pci_config_table pci_mpc83xxemds_config_table[] = { |
||||
{ |
||||
PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
||||
pci_cfgfunc_config_device, |
||||
{PCI_ENET0_IOADDR, |
||||
PCI_ENET0_MEMADDR, |
||||
PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} |
||||
}, |
||||
{} |
||||
} |
||||
#endif |
||||
static struct pci_controller hose[] = { |
||||
{ |
||||
#ifndef CONFIG_PCI_PNP |
||||
config_table:pci_mpc83xxemds_config_table, |
||||
#endif |
||||
}, |
||||
}; |
||||
|
||||
/**********************************************************************
|
||||
* pci_init_board() |
||||
*********************************************************************/ |
||||
void pci_init_board(void) |
||||
#ifdef CONFIG_PCISLAVE |
||||
{ |
||||
u16 reg16; |
||||
volatile immap_t *immr; |
||||
volatile law83xx_t *pci_law; |
||||
volatile pot83xx_t *pci_pot; |
||||
volatile pcictrl83xx_t *pci_ctrl; |
||||
volatile pciconf83xx_t *pci_conf; |
||||
|
||||
immr = (immap_t *) CFG_IMMRBAR; |
||||
pci_law = immr->sysconf.pcilaw; |
||||
pci_pot = immr->ios.pot; |
||||
pci_ctrl = immr->pci_ctrl; |
||||
pci_conf = immr->pci_conf; |
||||
/*
|
||||
* Configure PCI Inbound Translation Windows |
||||
*/ |
||||
pci_ctrl[0].pitar0 = 0x0; |
||||
pci_ctrl[0].pibar0 = 0x0; |
||||
pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP | |
||||
PIWAR_WTT_SNOOP | PIWAR_IWS_4K; |
||||
|
||||
pci_ctrl[0].pitar1 = 0x0; |
||||
pci_ctrl[0].pibar1 = 0x0; |
||||
pci_ctrl[0].piebar1 = 0x0; |
||||
pci_ctrl[0].piwar1 &= ~PIWAR_EN; |
||||
|
||||
pci_ctrl[0].pitar2 = 0x0; |
||||
pci_ctrl[0].pibar2 = 0x0; |
||||
pci_ctrl[0].piebar2 = 0x0; |
||||
pci_ctrl[0].piwar2 &= ~PIWAR_EN; |
||||
|
||||
hose[0].first_busno = 0; |
||||
hose[0].last_busno = 0xff; |
||||
pci_setup_indirect(&hose[0], |
||||
(CFG_IMMRBAR + 0x8300), (CFG_IMMRBAR + 0x8304)); |
||||
reg16 = 0xff; |
||||
|
||||
pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), |
||||
PCI_COMMAND, ®16); |
||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY; |
||||
pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), |
||||
PCI_COMMAND, reg16); |
||||
|
||||
/*
|
||||
* Clear non-reserved bits in status register. |
||||
*/ |
||||
pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), |
||||
PCI_STATUS, 0xffff); |
||||
pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0), |
||||
PCI_LATENCY_TIMER, 0x80); |
||||
|
||||
/*
|
||||
* Unlock configuration lock in PCI function configuration register. |
||||
*/ |
||||
pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), |
||||
PCI_FUNCTION_CONFIG, ®16); |
||||
reg16 &= ~(PCI_FUNCTION_CFG_LOCK); |
||||
pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), |
||||
PCI_FUNCTION_CONFIG, reg16); |
||||
|
||||
printf("Enabled PCI 32bit Agent Mode\n"); |
||||
} |
||||
#else |
||||
{ |
||||
volatile immap_t *immr; |
||||
volatile clk83xx_t *clk; |
||||
volatile law83xx_t *pci_law; |
||||
volatile pot83xx_t *pci_pot; |
||||
volatile pcictrl83xx_t *pci_ctrl; |
||||
volatile pciconf83xx_t *pci_conf; |
||||
|
||||
u8 val8, orig_i2c_bus; |
||||
u16 reg16; |
||||
u32 val32; |
||||
u32 dev; |
||||
|
||||
immr = (immap_t *) CFG_IMMRBAR; |
||||
clk = (clk83xx_t *) & immr->clk; |
||||
pci_law = immr->sysconf.pcilaw; |
||||
pci_pot = immr->ios.pot; |
||||
pci_ctrl = immr->pci_ctrl; |
||||
pci_conf = immr->pci_conf; |
||||
/*
|
||||
* Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode |
||||
*/ |
||||
val32 = clk->occr; |
||||
udelay(2000); |
||||
#if defined(PCI_66M) |
||||
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; |
||||
printf("PCI clock is 66MHz\n"); |
||||
#elif defined(PCI_33M) |
||||
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 | |
||||
OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR; |
||||
printf("PCI clock is 33MHz\n"); |
||||
#else |
||||
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; |
||||
printf("PCI clock is 66MHz\n"); |
||||
#endif |
||||
udelay(2000); |
||||
|
||||
/*
|
||||
* Configure PCI Local Access Windows |
||||
*/ |
||||
pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR; |
||||
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; |
||||
|
||||
pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR; |
||||
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; |
||||
|
||||
/*
|
||||
* Configure PCI Outbound Translation Windows |
||||
*/ |
||||
|
||||
/* PCI mem space - prefetch */ |
||||
pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; |
||||
pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; |
||||
pci_pot[0].pocmr = |
||||
POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK); |
||||
|
||||
/* PCI mmio - non-prefetch mem space */ |
||||
pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; |
||||
pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; |
||||
pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); |
||||
|
||||
/* PCI IO space */ |
||||
pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK; |
||||
pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; |
||||
pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); |
||||
|
||||
/*
|
||||
* Configure PCI Inbound Translation Windows |
||||
*/ |
||||
pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK; |
||||
pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK; |
||||
pci_ctrl[0].piebar1 = 0x0; |
||||
pci_ctrl[0].piwar1 = |
||||
PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | |
||||
PIWAR_IWS_2G; |
||||
|
||||
/*
|
||||
* Assign PIB PMC slot to desired PCI bus |
||||
*/ |
||||
|
||||
mpc83xx_i2c = (i2c_t *) (CFG_IMMRBAR + CFG_I2C2_OFFSET); |
||||
i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); |
||||
|
||||
val8 = 0; |
||||
i2c_write(0x23, 0x6, 1, &val8, 1); |
||||
i2c_write(0x23, 0x7, 1, &val8, 1); |
||||
val8 = 0xff; |
||||
i2c_write(0x23, 0x2, 1, &val8, 1); |
||||
i2c_write(0x23, 0x3, 1, &val8, 1); |
||||
|
||||
val8 = 0; |
||||
i2c_write(0x26, 0x6, 1, &val8, 1); |
||||
val8 = 0x34; |
||||
i2c_write(0x26, 0x7, 1, &val8, 1); |
||||
|
||||
val8 = 0xf3; /*PMC1, PMC2, PMC3 slot to PCI bus */ |
||||
i2c_write(0x26, 0x2, 1, &val8, 1); |
||||
val8 = 0xff; |
||||
i2c_write(0x26, 0x3, 1, &val8, 1); |
||||
|
||||
val8 = 0; |
||||
i2c_write(0x27, 0x6, 1, &val8, 1); |
||||
i2c_write(0x27, 0x7, 1, &val8, 1); |
||||
val8 = 0xff; |
||||
i2c_write(0x27, 0x2, 1, &val8, 1); |
||||
val8 = 0xef; |
||||
i2c_write(0x27, 0x3, 1, &val8, 1); |
||||
asm("eieio"); |
||||
|
||||
/*
|
||||
* Release PCI RST Output signal |
||||
*/ |
||||
udelay(2000); |
||||
pci_ctrl[0].gcr = 1; |
||||
udelay(2000); |
||||
|
||||
hose[0].first_busno = 0; |
||||
hose[0].last_busno = 0xff; |
||||
|
||||
/* PCI memory prefetch space */ |
||||
pci_set_region(hose[0].regions + 0, |
||||
CFG_PCI_MEM_BASE, |
||||
CFG_PCI_MEM_PHYS, |
||||
CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); |
||||
|
||||
/* PCI memory space */ |
||||
pci_set_region(hose[0].regions + 1, |
||||
CFG_PCI_MMIO_BASE, |
||||
CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM); |
||||
|
||||
/* PCI IO space */ |
||||
pci_set_region(hose[0].regions + 2, |
||||
CFG_PCI_IO_BASE, |
||||
CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO); |
||||
|
||||
/* System memory space */ |
||||
pci_set_region(hose[0].regions + 3, |
||||
CFG_PCI_SLV_MEM_LOCAL, |
||||
CFG_PCI_SLV_MEM_BUS, |
||||
CFG_PCI_SLV_MEM_SIZE, |
||||
PCI_REGION_MEM | PCI_REGION_MEMORY); |
||||
|
||||
hose[0].region_count = 4; |
||||
|
||||
pci_setup_indirect(&hose[0], |
||||
(CFG_IMMRBAR + 0x8300), (CFG_IMMRBAR + 0x8304)); |
||||
|
||||
pci_register_hose(hose); |
||||
|
||||
/*
|
||||
* Write command register |
||||
*/ |
||||
reg16 = 0xff; |
||||
dev = PCI_BDF(0, 0, 0); |
||||
pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, ®16); |
||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
||||
pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16); |
||||
|
||||
/*
|
||||
* Clear non-reserved bits in status register. |
||||
*/ |
||||
pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff); |
||||
pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80); |
||||
pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08); |
||||
|
||||
printf("PCI 32bit bus on PMC1 & PMC2 & PMC3\n"); |
||||
|
||||
/*
|
||||
* Hose scan. |
||||
*/ |
||||
hose->last_busno = pci_hose_scan(hose); |
||||
} |
||||
#endif /* CONFIG_PCISLAVE */ |
||||
#endif /* CONFIG_PCI */ |
||||
@ -0,0 +1,123 @@ |
||||
/* |
||||
* (C) Copyright 2006 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/mpc83xx/start.o (.text) |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
. = ALIGN(16); |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
*(.eh_frame) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
ENTRY(_start) |
||||
@ -0,0 +1,585 @@ |
||||
/*
|
||||
* Copyright (C) 2006 Freescale Semiconductor, Inc. |
||||
* |
||||
* Dave Liu <daveliu@freescale.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#undef DEBUG |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
*/ |
||||
#define CONFIG_E300 1 /* E300 family */ |
||||
#define CONFIG_QE 1 /* Has QE */ |
||||
#define CONFIG_MPC83XX 1 /* MPC83XX family */ |
||||
#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ |
||||
#define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */ |
||||
|
||||
/*
|
||||
* System Clock Setup |
||||
*/ |
||||
#ifdef CONFIG_PCISLAVE |
||||
#define CONFIG_83XX_PCICLK 66000000 /* in HZ */ |
||||
#else |
||||
#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ |
||||
#endif |
||||
|
||||
#ifndef CONFIG_SYS_CLK_FREQ |
||||
#define CONFIG_SYS_CLK_FREQ 66000000 |
||||
#endif |
||||
|
||||
/*
|
||||
* Hardware Reset Configuration Word |
||||
*/ |
||||
#define CFG_HRCW_LOW (\ |
||||
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_DDR_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_CSB_TO_CLKIN_4X1 |\
|
||||
HRCWL_VCO_1X2 |\
|
||||
HRCWL_CE_PLL_VCO_DIV_4 |\
|
||||
HRCWL_CE_PLL_DIV_1X1 |\
|
||||
HRCWL_CE_TO_PLL_1X6 |\
|
||||
HRCWL_CORE_TO_CSB_2X1) |
||||
|
||||
#ifdef CONFIG_PCISLAVE |
||||
#define CFG_HRCW_HIGH (\ |
||||
HRCWH_PCI_AGENT |\
|
||||
HRCWH_PCI1_ARBITER_DISABLE |\
|
||||
HRCWH_PCICKDRV_DISABLE |\
|
||||
HRCWH_CORE_ENABLE |\
|
||||
HRCWH_FROM_0XFFF00100 |\
|
||||
HRCWH_BOOTSEQ_DISABLE |\
|
||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT) |
||||
#else |
||||
#define CFG_HRCW_HIGH (\ |
||||
HRCWH_PCI_HOST |\
|
||||
HRCWH_PCI1_ARBITER_ENABLE |\
|
||||
HRCWH_PCICKDRV_ENABLE |\
|
||||
HRCWH_CORE_ENABLE |\
|
||||
HRCWH_FROM_0X00000100 |\
|
||||
HRCWH_BOOTSEQ_DISABLE |\
|
||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT) |
||||
#endif |
||||
|
||||
/*
|
||||
* System IO Config |
||||
*/ |
||||
#define CFG_SICRH 0x00000000 |
||||
#define CFG_SICRL 0x40000000 |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ |
||||
|
||||
/*
|
||||
* IMMR new address |
||||
*/ |
||||
#define CFG_IMMRBAR 0xE0000000 |
||||
|
||||
/*
|
||||
* DDR Setup |
||||
*/ |
||||
#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ |
||||
#define CFG_SDRAM_BASE CFG_DDR_BASE |
||||
#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE |
||||
|
||||
#undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
||||
#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ |
||||
|
||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
||||
#if defined(CONFIG_SPD_EEPROM) |
||||
/*
|
||||
* Determine DDR configuration from I2C interface. |
||||
*/ |
||||
#define SPD_EEPROM_ADDRESS 0x52 /* DDR SODIMM */ |
||||
#else |
||||
/*
|
||||
* Manually set up DDR parameters |
||||
*/ |
||||
#define CFG_DDR_SIZE 256 /* MB */ |
||||
#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9) |
||||
#define CFG_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */ |
||||
#define CFG_DDR_TIMING_2 0x00000800 /* may need tuning */ |
||||
#define CFG_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */ |
||||
#define CFG_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */ |
||||
#define CFG_DDR_INTERVAL 0x045b0100 /* page mode */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Memory test |
||||
*/ |
||||
#undef CFG_DRAM_TEST /* memory test, takes time */ |
||||
#define CFG_MEMTEST_START 0x00000000 /* memtest region */ |
||||
#define CFG_MEMTEST_END 0x00100000 |
||||
|
||||
/*
|
||||
* The reserved memory |
||||
*/ |
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
||||
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
||||
#define CFG_RAMBOOT |
||||
#else |
||||
#undef CFG_RAMBOOT |
||||
#endif |
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
||||
|
||||
/*
|
||||
* Initial RAM Base Address Setup |
||||
*/ |
||||
#define CFG_INIT_RAM_LOCK 1 |
||||
#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ |
||||
#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ |
||||
#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
|
||||
/*
|
||||
* Local Bus Configuration & Clock Setup |
||||
*/ |
||||
#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) |
||||
#define CFG_LBC_LBCR 0x00000000 |
||||
|
||||
/*
|
||||
* FLASH on the Local Bus |
||||
*/ |
||||
#define CFG_FLASH_CFI /* use the Common Flash Interface */ |
||||
#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ |
||||
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ |
||||
#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */ |
||||
|
||||
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ |
||||
#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ |
||||
|
||||
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ |
||||
(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
|
||||
BR_V) /* valid */ |
||||
#define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */ |
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ |
||||
#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ |
||||
|
||||
#undef CFG_FLASH_CHECKSUM |
||||
|
||||
/*
|
||||
* BCSR on the Local Bus |
||||
*/ |
||||
#define CFG_BCSR 0xF8000000 |
||||
#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ |
||||
#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ |
||||
|
||||
#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */ |
||||
#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ |
||||
|
||||
/*
|
||||
* SDRAM on the Local Bus |
||||
*/ |
||||
#define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ |
||||
#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
||||
|
||||
#define CFG_LB_SDRAM /* if board has SRDAM on local bus */ |
||||
|
||||
#ifdef CFG_LB_SDRAM |
||||
#define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE |
||||
#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */ |
||||
|
||||
/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ |
||||
/*
|
||||
* Base Register 2 and Option Register 2 configure SDRAM. |
||||
* The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. |
||||
* |
||||
* For BR2, need: |
||||
* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 |
||||
* port size = 32-bits = BR2[19:20] = 11 |
||||
* no parity checking = BR2[21:22] = 00 |
||||
* SDRAM for MSEL = BR2[24:26] = 011 |
||||
* Valid = BR[31] = 1 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 |
||||
* |
||||
* CFG_LBC_SDRAM_BASE should be masked and OR'ed into |
||||
* the top 17 bits of BR2. |
||||
*/ |
||||
|
||||
#define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */ |
||||
|
||||
/*
|
||||
* The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. |
||||
* |
||||
* For OR2, need: |
||||
* 64MB mask for AM, OR2[0:7] = 1111 1100 |
||||
* XAM, OR2[17:18] = 11 |
||||
* 9 columns OR2[19-21] = 010 |
||||
* 13 rows OR2[23-25] = 100 |
||||
* EAD set for extra time OR[31] = 1 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 |
||||
*/ |
||||
|
||||
#define CFG_OR2_PRELIM 0xfc006901 |
||||
|
||||
#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ |
||||
#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ |
||||
|
||||
/*
|
||||
* LSDMR masks |
||||
*/ |
||||
#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) |
||||
|
||||
#define CFG_LBC_LSDMR_COMMON 0x0063b723 |
||||
|
||||
/*
|
||||
* SDRAM Controller configuration sequence. |
||||
*/ |
||||
#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_PCHALL) |
||||
#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_ARFRSH) |
||||
#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_ARFRSH) |
||||
#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_MRW) |
||||
#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_NORMAL) |
||||
|
||||
#endif |
||||
|
||||
/*
|
||||
* Windows to access PIB via local bus |
||||
*/ |
||||
#define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */ |
||||
#define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */ |
||||
|
||||
/*
|
||||
* CS4 on Local Bus, to PIB |
||||
*/ |
||||
#define CFG_BR4_PRELIM 0xf8008801 /* CS4 base address at 0xf8008000 */ |
||||
#define CFG_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ |
||||
|
||||
/*
|
||||
* CS5 on Local Bus, to PIB |
||||
*/ |
||||
#define CFG_BR5_PRELIM 0xf8010801 /* CS5 base address at 0xf8010000 */ |
||||
#define CFG_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ |
||||
|
||||
/*
|
||||
* Serial Port |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||
#define CFG_NS16550 |
||||
#define CFG_NS16550_SERIAL |
||||
#define CFG_NS16550_REG_SIZE 1 |
||||
#define CFG_NS16550_CLK get_bus_freq(0) |
||||
|
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
||||
|
||||
#define CFG_NS16550_COM1 (CFG_IMMRBAR+0x4500) |
||||
#define CFG_NS16550_COM2 (CFG_IMMRBAR+0x4600) |
||||
|
||||
/* Use the HUSH parser */ |
||||
#define CFG_HUSH_PARSER |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 0x3F /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
#define CFG_I2C_NOPROBES {0x52} /* Don't probe these addrs */ |
||||
#define CFG_I2C_OFFSET 0x3000 |
||||
#define CFG_I2C2_OFFSET 0x3100 |
||||
|
||||
/*
|
||||
* Config on-board RTC |
||||
*/ |
||||
#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ |
||||
#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
||||
|
||||
/*
|
||||
* General PCI |
||||
* Addresses are mapped 1-1. |
||||
*/ |
||||
#define CFG_PCI_MEM_BASE 0x80000000 |
||||
#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE |
||||
#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ |
||||
#define CFG_PCI_MMIO_BASE 0x90000000 |
||||
#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE |
||||
#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ |
||||
#define CFG_PCI_IO_BASE 0xE0300000 |
||||
#define CFG_PCI_IO_PHYS 0xE0300000 |
||||
#define CFG_PCI_IO_SIZE 0x100000 /* 1M */ |
||||
|
||||
#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE |
||||
#define CFG_PCI_SLV_MEM_BUS 0x00000000 |
||||
#define CFG_PCI_SLV_MEM_SIZE 0x80000000 |
||||
|
||||
|
||||
#ifdef CONFIG_PCI |
||||
|
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
|
||||
#undef CONFIG_EEPRO100 |
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
||||
|
||||
#endif /* CONFIG_PCI */ |
||||
|
||||
|
||||
#ifndef CONFIG_NET_MULTI |
||||
#define CONFIG_NET_MULTI 1 |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
|
||||
#ifndef CFG_RAMBOOT |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) |
||||
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
#else |
||||
#define CFG_NO_FLASH 1 /* Flash is not usable now */ |
||||
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
#endif |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#if defined(CFG_RAMBOOT) |
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ |
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_ASKENV \
|
||||
| CFG_CMD_PCI \
|
||||
| CFG_CMD_I2C) \
|
||||
& \
|
||||
~(CFG_CMD_ENV \
|
||||
| CFG_CMD_LOADS)) |
||||
#else |
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ |
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_ASKENV \
|
||||
| CFG_CMD_I2C) \
|
||||
& \
|
||||
~(CFG_CMD_ENV \
|
||||
| CFG_CMD_LOADS)) |
||||
#endif |
||||
#else |
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ |
||||
| CFG_CMD_PCI \
|
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_ASKENV \
|
||||
| CFG_CMD_I2C) |
||||
#else |
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ |
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_ASKENV \
|
||||
| CFG_CMD_I2C ) |
||||
#endif |
||||
#endif |
||||
|
||||
#include <cmd_confdefs.h> |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_LOAD_ADDR 0x2000000 /* default load address */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*
|
||||
* Core HID Setup |
||||
*/ |
||||
#define CFG_HID0_INIT 0x000000000 |
||||
#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK |
||||
#define CFG_HID2 HID2_HBE |
||||
|
||||
/*
|
||||
* Cache Config |
||||
*/ |
||||
#define CFG_DCACHE_SIZE 32768 |
||||
#define CFG_CACHELINE_SIZE 32 |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*
|
||||
* MMU Setup |
||||
*/ |
||||
|
||||
/* DDR: cache cacheable */ |
||||
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT0L CFG_IBAT0L |
||||
#define CFG_DBAT0U CFG_IBAT0U |
||||
|
||||
/* IMMRBAR & PCI IO: cache-inhibit and guarded */ |
||||
#define CFG_IBAT1L (CFG_IMMRBAR | BATL_PP_10 | \ |
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_IBAT1U (CFG_IMMRBAR | BATU_BL_4M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT1L CFG_IBAT1L |
||||
#define CFG_DBAT1U CFG_IBAT1U |
||||
|
||||
/* BCSR: cache-inhibit and guarded */ |
||||
#define CFG_IBAT2L (CFG_BCSR | BATL_PP_10 | \ |
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_IBAT2U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT2L CFG_IBAT2L |
||||
#define CFG_DBAT2U CFG_IBAT2U |
||||
|
||||
/* FLASH: icache cacheable, but dcache-inhibit and guarded */ |
||||
#define CFG_IBAT3L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT3U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT3L (CFG_FLASH_BASE | BATL_PP_10 | \ |
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_DBAT3U CFG_IBAT3U |
||||
|
||||
/* Local bus SDRAM: cacheable */ |
||||
#define CFG_IBAT4L (CFG_LBC_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT4U (CFG_LBC_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT4L CFG_IBAT4L |
||||
#define CFG_DBAT4U CFG_IBAT4U |
||||
|
||||
/* Stack in dcache: cacheable, no memory coherence */ |
||||
#define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10) |
||||
#define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT5L CFG_IBAT5L |
||||
#define CFG_DBAT5U CFG_IBAT5U |
||||
|
||||
#ifdef CONFIG_PCI |
||||
/* PCI MEM space: cacheable */ |
||||
#define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT6L CFG_IBAT6L |
||||
#define CFG_DBAT6U CFG_IBAT6U |
||||
/* PCI MMIO space: cache-inhibit and guarded */ |
||||
#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \ |
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT7L CFG_IBAT7L |
||||
#define CFG_DBAT7U CFG_IBAT7U |
||||
#else |
||||
#define CFG_IBAT6L (0) |
||||
#define CFG_IBAT6U (0) |
||||
#define CFG_IBAT7L (0) |
||||
#define CFG_IBAT7U (0) |
||||
#define CFG_DBAT6L CFG_IBAT6L |
||||
#define CFG_DBAT6U CFG_IBAT6U |
||||
#define CFG_DBAT7L CFG_IBAT7L |
||||
#define CFG_DBAT7U CFG_IBAT7U |
||||
#endif |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
|
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#if defined(CONFIG_UEC_ETH) |
||||
#define CONFIG_ETHADDR 00:04:9f:ef:01:01 |
||||
#define CONFIG_HAS_ETH1 |
||||
#define CONFIG_ETH1ADDR 00:04:9f:ef:01:02 |
||||
#endif |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ |
||||
|
||||
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ |
||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=400000\0" \
|
||||
"ramdiskfile=ramfs.83xx\0" \
|
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"bootm $loadaddr" |
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr" |
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue