This patch provides support for MPC8308RDB development board from Freescale with a minimal set of features: Dual UART is supported NOR flash is supported Both TSEC Ethernet controllers are supported PCI Express initialization is supported The following features are enabled in configuration but not fully tested: I2C (used to get the board revision) I2C-connected RTC VSC7385 switch There is one (hopefully) minor issue: on soft reset the board sometimes resets twice. I've not managed to find the fix for this problem yet. As a workaround instruction cache can be disabled. Signed-off-by: Ilya Yanok <yanok@emcraft.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>master
Ilya Yanok
15 years ago
committed by
Kim Phillips
parent
7c619ddcee
commit
5fb17030d5
@ -0,0 +1,52 @@ |
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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# (C) Copyright 2010
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# Ilya Yanok, Emcraft Systems, yanok@emcraft.com
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o sdram.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1 @@ |
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TEXT_BASE = 0xFE000000
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@ -0,0 +1,160 @@ |
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/*
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* Copyright (C) 2010 Freescale Semiconductor, Inc. |
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* Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <hwconfig.h> |
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#include <i2c.h> |
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#include <libfdt.h> |
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#include <fdt_support.h> |
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#include <pci.h> |
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#include <mpc83xx.h> |
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#include <vsc7385.h> |
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#include <netdev.h> |
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#include <asm/io.h> |
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#include <asm/fsl_serdes.h> |
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#include <asm/fsl_mpc83xx_serdes.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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int board_early_init_f(void) |
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{ |
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
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if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF) |
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gd->flags |= GD_FLG_SILENT; |
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return 0; |
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} |
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static u8 read_board_info(void) |
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{ |
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u8 val8; |
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i2c_set_bus_num(0); |
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if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0) |
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return val8; |
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else |
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return 0; |
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} |
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int checkboard(void) |
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{ |
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static const char * const rev_str[] = { |
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"1.0", |
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"<reserved>", |
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"<reserved>", |
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"<reserved>", |
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"<unknown>", |
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}; |
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u8 info; |
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int i; |
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info = read_board_info(); |
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i = (!info) ? 4 : info & 0x03; |
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printf("Board: Freescale MPC8308RDB Rev %s\n", rev_str[i]); |
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return 0; |
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} |
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static struct pci_region pcie_regions_0[] = { |
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{ |
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.bus_start = CONFIG_SYS_PCIE1_MEM_BASE, |
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.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, |
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.size = CONFIG_SYS_PCIE1_MEM_SIZE, |
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.flags = PCI_REGION_MEM, |
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}, |
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{ |
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.bus_start = CONFIG_SYS_PCIE1_IO_BASE, |
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.phys_start = CONFIG_SYS_PCIE1_IO_PHYS, |
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.size = CONFIG_SYS_PCIE1_IO_SIZE, |
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.flags = PCI_REGION_IO, |
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}, |
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}; |
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void pci_init_board(void) |
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{ |
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immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; |
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sysconf83xx_t *sysconf = &immr->sysconf; |
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clk83xx_t *clk = (clk83xx_t *)&immr->clk; |
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law83xx_t *pcie_law = sysconf->pcielaw; |
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struct pci_region *pcie_reg[] = { pcie_regions_0 }; |
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, |
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); |
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clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM , |
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SCCR_PCIEXP1CM_1); |
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/* Deassert the resets in the control register */ |
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out_be32(&sysconf->pecr1, 0xE0008000); |
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udelay(2000); |
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/* Configure PCI Express Local Access Windows */ |
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out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); |
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out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); |
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mpc83xx_pcie_init(1, pcie_reg, 0); |
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} |
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/*
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* Miscellaneous late-boot configurations |
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* |
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* If a VSC7385 microcode image is present, then upload it. |
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*/ |
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int misc_init_r(void) |
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{ |
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#ifdef CONFIG_VSC7385_IMAGE |
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if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, |
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CONFIG_VSC7385_IMAGE_SIZE)) { |
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puts("Failure uploading VSC7385 microcode.\n"); |
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return 1; |
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} |
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#endif |
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return 0; |
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} |
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#if defined(CONFIG_OF_BOARD_SETUP) |
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void ft_board_setup(void *blob, bd_t *bd) |
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{ |
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ft_cpu_setup(blob, bd); |
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fdt_fixup_dr_usb(blob, bd); |
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} |
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#endif |
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int board_eth_init(bd_t *bis) |
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{ |
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int rv, num_if = 0; |
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/* Initialize TSECs first */ |
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if ((rv = cpu_eth_init(bis)) >= 0) |
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num_if += rv; |
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else |
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printf("ERROR: failed to initialize TSECs.\n"); |
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if ((rv = pci_eth_init(bis)) >= 0) |
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num_if += rv; |
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else |
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printf("ERROR: failed to initialize PCI Ethernet.\n"); |
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return num_if; |
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} |
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@ -0,0 +1,126 @@ |
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/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc. |
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* Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com |
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* |
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* Authors: Nick.Spence@freescale.com |
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* Wilson.Lo@freescale.com |
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* scottwood@freescale.com |
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* |
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* This files is mostly identical to the original from |
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* board\freescale\mpc8315erdb\sdram.c |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <mpc83xx.h> |
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#include <asm/bitops.h> |
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#include <asm/io.h> |
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#include <asm/processor.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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static void resume_from_sleep(void) |
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{ |
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u32 magic = *(u32 *)0; |
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typedef void (*func_t)(void); |
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func_t resume = *(func_t *)4; |
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if (magic == 0xf5153ae5) |
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resume(); |
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gd->flags &= ~GD_FLG_SILENT; |
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puts("\nResume from sleep failed: bad magic word\n"); |
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} |
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/* Fixed sdram init -- doesn't use serial presence detect.
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* |
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* This is useful for faster booting in configs where the RAM is unlikely |
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* to be changed, or for things like NAND booting where space is tight. |
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*/ |
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static long fixed_sdram(void) |
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{ |
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
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u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; |
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u32 msize_log2 = __ilog2(msize); |
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out_be32(&im->sysconf.ddrlaw[0].bar, |
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CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000); |
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out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); |
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out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); |
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/*
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* Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], |
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* or the DDR2 controller may fail to initialize correctly. |
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*/ |
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udelay(50000); |
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out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); |
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out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); |
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/* Currently we use only one CS, so disable the other bank. */ |
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out_be32(&im->ddr.cs_config[1], 0); |
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out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); |
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out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); |
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out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); |
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out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); |
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out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); |
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if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF) { |
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out_be32(&im->ddr.sdram_cfg, |
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CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI); |
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} else { |
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out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); |
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} |
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out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); |
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out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); |
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out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); |
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out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); |
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sync(); |
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/* enable DDR controller */ |
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setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); |
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sync(); |
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return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); |
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} |
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phys_size_t initdram(int board_type) |
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{ |
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
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u32 msize; |
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if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) |
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return -1; |
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/* DDR SDRAM */ |
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msize = fixed_sdram(); |
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if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF) |
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resume_from_sleep(); |
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/* return total bus SDRAM size(bytes) -- DDR */ |
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return msize; |
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} |
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@ -0,0 +1,560 @@ |
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/*
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* Copyright (C) 2009-2010 Freescale Semiconductor, Inc. |
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* Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com |
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* |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/*
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* High Level Configuration Options |
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*/ |
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#define CONFIG_E300 1 /* E300 family */ |
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#define CONFIG_MPC83xx 1 /* MPC83xx family */ |
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#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ |
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#define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */ |
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#define CONFIG_MISC_INIT_R |
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/*
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* On-board devices |
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* |
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* TSEC1 is SoC TSEC |
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* TSEC2 is VSC switch |
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*/ |
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#define CONFIG_TSEC1 |
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#define CONFIG_VSC7385_ENET |
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/*
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* System Clock Setup |
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*/ |
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#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ |
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#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN |
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|
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/*
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* Hardware Reset Configuration Word |
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* if CLKIN is 66.66MHz, then |
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* CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz |
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* We choose the A type silicon as default, so the core is 400Mhz. |
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*/ |
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#define CONFIG_SYS_HRCW_LOW (\ |
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HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
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HRCWL_DDR_TO_SCB_CLK_2X1 |\
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HRCWL_SVCOD_DIV_2 |\
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HRCWL_CSB_TO_CLKIN_4X1 |\
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HRCWL_CORE_TO_CSB_3X1) |
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/*
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* There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits |
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* in 8308's HRCWH according to the manual, but original Freescale's |
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* code has them and I've expirienced some problems using the board |
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* with BDI3000 attached when I've tried to set these bits to zero |
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* (UART doesn't work after the 'reset run' command). |
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*/ |
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#define CONFIG_SYS_HRCW_HIGH (\ |
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HRCWH_PCI_HOST |\
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HRCWH_PCI1_ARBITER_ENABLE |\
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HRCWH_CORE_ENABLE |\
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HRCWH_FROM_0X00000100 |\
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HRCWH_BOOTSEQ_DISABLE |\
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HRCWH_SW_WATCHDOG_DISABLE |\
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HRCWH_ROM_LOC_LOCAL_16BIT |\
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HRCWH_RL_EXT_LEGACY |\
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HRCWH_TSEC1M_IN_RGMII |\
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HRCWH_TSEC2M_IN_RGMII |\
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HRCWH_BIG_ENDIAN) |
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/*
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* System IO Config |
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*/ |
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#define CONFIG_SYS_SICRH 0x01b7d103 |
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#define CONFIG_SYS_SICRL 0x00000040 /* 3.3V, no delay */ |
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#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ |
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/*
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* IMMR new address |
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*/ |
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#define CONFIG_SYS_IMMR 0xE0000000 |
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|
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/*
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* SERDES |
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*/ |
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#define CONFIG_FSL_SERDES |
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#define CONFIG_FSL_SERDES1 0xe3000 |
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/*
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* Arbiter Setup |
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*/ |
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ |
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ |
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#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ |
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/*
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* DDR Setup |
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*/ |
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#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ |
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE |
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE |
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 |
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#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ |
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| DDRCDR_PZ_LOZ \
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| DDRCDR_NZ_LOZ \
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| DDRCDR_ODT \
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| DDRCDR_Q_DRN) |
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/* 0x7b880001 */ |
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/*
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* Manually set up DDR parameters |
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* consist of two chips HY5PS12621BFP-C4 from HYNIX |
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*/ |
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|
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#define CONFIG_SYS_DDR_SIZE 128 /* MB */ |
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|
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#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 |
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#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ |
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| 0x00010000 /* ODT_WR to CSn */ \
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| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) |
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/* 0x80010102 */ |
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#define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
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#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ |
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| (0 << TIMING_CFG0_WRT_SHIFT) \
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| (0 << TIMING_CFG0_RRT_SHIFT) \
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| (0 << TIMING_CFG0_WWT_SHIFT) \
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| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
|
||||
| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
|
||||
| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
|
||||
| (2 << TIMING_CFG0_MRS_CYC_SHIFT)) |
||||
/* 0x00220802 */ |
||||
#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ |
||||
| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
|
||||
| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
|
||||
| (5 << TIMING_CFG1_CASLAT_SHIFT) \
|
||||
| (6 << TIMING_CFG1_REFREC_SHIFT) \
|
||||
| (2 << TIMING_CFG1_WRREC_SHIFT) \
|
||||
| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
|
||||
| (2 << TIMING_CFG1_WRTORD_SHIFT)) |
||||
/* 0x27256222 */ |
||||
#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ |
||||
| (4 << TIMING_CFG2_CPO_SHIFT) \
|
||||
| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
|
||||
| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
|
||||
| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
|
||||
| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
|
||||
| (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) |
||||
/* 0x121048c5 */ |
||||
#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ |
||||
| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) |
||||
/* 0x03600100 */ |
||||
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ |
||||
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
|
||||
| SDRAM_CFG_32_BE) |
||||
/* 0x43080000 */ |
||||
|
||||
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ |
||||
#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ |
||||
| (0x0232 << SDRAM_MODE_SD_SHIFT)) |
||||
/* ODT 150ohm CL=3, AL=1 on SDRAM */ |
||||
#define CONFIG_SYS_DDR_MODE2 0x00000000 |
||||
|
||||
/*
|
||||
* Memory test |
||||
*/ |
||||
#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x07f00000 |
||||
|
||||
/*
|
||||
* The reserved memory |
||||
*/ |
||||
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
||||
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ |
||||
|
||||
/*
|
||||
* Initial RAM Base Address Setup |
||||
*/ |
||||
#define CONFIG_SYS_INIT_RAM_LOCK 1 |
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ |
||||
#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */ |
||||
#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) |
||||
|
||||
/*
|
||||
* Local Bus Configuration & Clock Setup |
||||
*/ |
||||
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
||||
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 |
||||
#define CONFIG_SYS_LBC_LBCR 0x00040000 |
||||
|
||||
/*
|
||||
* FLASH on the Local Bus |
||||
*/ |
||||
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
||||
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
||||
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
||||
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ |
||||
#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ |
||||
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ |
||||
|
||||
/* Window base at flash base */ |
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE |
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */ |
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM (\ |
||||
CONFIG_SYS_FLASH_BASE /* Flash Base address */ |\
|
||||
(2 << BR_PS_SHIFT) /* 16 bit port size */ |\
|
||||
BR_V) /* valid */ |
||||
#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ |
||||
| OR_UPM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV2 \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX \
|
||||
| OR_GPCM_EHTR \
|
||||
| OR_GPCM_EAD) |
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
||||
/* 127 64KB sectors and 8 8KB top sectors per device */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 135 |
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
||||
|
||||
/*
|
||||
* NAND Flash on the Local Bus |
||||
*/ |
||||
#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ |
||||
#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \ |
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V ) /* valid */ |
||||
#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ |
||||
| OR_FCM_CSCT \
|
||||
| OR_FCM_CST \
|
||||
| OR_FCM_CHT \
|
||||
| OR_FCM_SCY_1 \
|
||||
| OR_FCM_TRLX \
|
||||
| OR_FCM_EHTR ) |
||||
/* 0xFFFF8396 */ |
||||
|
||||
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE |
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ |
||||
|
||||
#ifdef CONFIG_VSC7385_ENET |
||||
#define CONFIG_TSEC2 |
||||
#define CONFIG_SYS_VSC7385_BASE 0xF0000000 |
||||
#define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */ |
||||
#define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/ |
||||
/* Access window base at VSC7385 base */ |
||||
#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE |
||||
/* Access window size 128K */ |
||||
#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 |
||||
/* The flash address and size of the VSC7385 firmware image */ |
||||
#define CONFIG_VSC7385_IMAGE 0xFE7FE000 |
||||
#define CONFIG_VSC7385_IMAGE_SIZE 8192 |
||||
#endif |
||||
/*
|
||||
* Serial Port |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1 |
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) |
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) |
||||
|
||||
/* Use the HUSH parser */ |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
|
||||
/* Pass open firmware flat tree */ |
||||
#define CONFIG_OF_LIBFDT 1 |
||||
#define CONFIG_OF_BOARD_SETUP 1 |
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */ |
||||
#define CONFIG_FSL_I2C |
||||
#define CONFIG_I2C_MULTI_BUS |
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F |
||||
#define CONFIG_SYS_I2C_NOPROBES {{0x51}} /* Don't probe these addrs */ |
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000 |
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100 |
||||
|
||||
|
||||
/*
|
||||
* Board info - revision and where boot from |
||||
*/ |
||||
#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 |
||||
|
||||
/*
|
||||
* Config on-board RTC |
||||
*/ |
||||
#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ |
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
||||
|
||||
/*
|
||||
* General PCI |
||||
* Addresses are mapped 1-1. |
||||
*/ |
||||
#define CONFIG_SYS_PCIE1_BASE 0xA0000000 |
||||
#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 |
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 |
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 |
||||
#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 |
||||
#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 |
||||
#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 |
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 |
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 |
||||
|
||||
/*
|
||||
* Fake PCIE2 definitions: there is no PCIE2 on this board but the code |
||||
* in arch/powerpc/cpu/mpc83xx/pcie.c doesn't compile without this |
||||
*/ |
||||
#define CONFIG_SYS_PCIE2_BASE 0xC0000000 |
||||
#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000 |
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000 |
||||
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 |
||||
#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000 |
||||
#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000 |
||||
#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 |
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000 |
||||
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 |
||||
|
||||
#define CONFIG_PCI |
||||
#define CONFIG_PCIE |
||||
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
||||
#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 |
||||
|
||||
/*
|
||||
* TSEC |
||||
*/ |
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_TSEC_ENET /* TSEC ethernet support */ |
||||
#define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
||||
#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) |
||||
#define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
||||
#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) |
||||
|
||||
/*
|
||||
* TSEC ethernet configuration |
||||
*/ |
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_TSEC1_NAME "eTSEC0" |
||||
#define CONFIG_TSEC2_NAME "eTSEC1" |
||||
#define TSEC1_PHY_ADDR 2 |
||||
#define TSEC2_PHY_ADDR 1 |
||||
#define TSEC1_PHYIDX 0 |
||||
#define TSEC2_PHYIDX 0 |
||||
#define TSEC1_FLAGS TSEC_GIGABIT |
||||
#define TSEC2_FLAGS TSEC_GIGABIT |
||||
|
||||
/* Options are: eTSEC[0-1] */ |
||||
#define CONFIG_ETHPRIME "eTSEC0" |
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ |
||||
CONFIG_SYS_MONITOR_LEN) |
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_DATE |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_CMD_PCI |
||||
#define CONFIG_CMD_PING |
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
||||
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
|
||||
/* Print Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
/* Boot Argument Buffer Size */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*
|
||||
* Core HID Setup |
||||
*/ |
||||
#define CONFIG_SYS_HID0_INIT 0x000000000 |
||||
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ |
||||
HID0_ENABLE_INSTRUCTION_CACHE | \
|
||||
HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) |
||||
#define CONFIG_SYS_HID2 HID2_HBE |
||||
|
||||
/*
|
||||
* MMU Setup |
||||
*/ |
||||
|
||||
/* DDR: cache cacheable */ |
||||
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ |
||||
BATL_MEMCOHERENCE) |
||||
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ |
||||
BATU_VS | BATU_VP) |
||||
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
||||
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U |
||||
|
||||
/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ |
||||
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ |
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ |
||||
BATU_VP) |
||||
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
||||
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U |
||||
|
||||
/* FLASH: icache cacheable, but dcache-inhibit and guarded */ |
||||
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ |
||||
BATL_MEMCOHERENCE) |
||||
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ |
||||
BATU_VS | BATU_VP) |
||||
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ |
||||
BATL_CACHEINHIBIT | \
|
||||
BATL_GUARDEDSTORAGE) |
||||
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U |
||||
|
||||
/* Stack in dcache: cacheable, no memory coherence */ |
||||
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) |
||||
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ |
||||
BATU_VS | BATU_VP) |
||||
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L |
||||
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
|
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#if defined(CONFIG_TSEC_ENET) |
||||
#define CONFIG_HAS_ETH0 |
||||
#define CONFIG_HAS_ETH1 |
||||
#endif |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ |
||||
|
||||
#define xstr(s) str(s) |
||||
#define str(s) #s |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs}" \
|
||||
" console=${consoledev},${baudrate}\0" \
|
||||
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
|
||||
"addmisc=setenv bootargs ${bootargs}\0" \
|
||||
"kernel_addr=FE080000\0" \
|
||||
"fdt_addr=FE280000\0" \
|
||||
"ramdisk_addr=FE290000\0" \
|
||||
"u-boot=mpc8308rdb/u-boot.bin\0" \
|
||||
"kernel_addr_r=1000000\0" \
|
||||
"fdt_addr_r=C00000\0" \
|
||||
"hostname=mpc8308rdb\0" \
|
||||
"bootfile=mpc8308rdb/uImage\0" \
|
||||
"fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \
|
||||
"rootpath=/opt/eldk-4.2/ppc_6xx\0" \
|
||||
"flash_self=run ramargs addip addtty addmtd addmisc;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
|
||||
"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
|
||||
"bootm ${kernel_addr} - ${fdt_addr}\0" \
|
||||
"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
|
||||
"tftp ${fdt_addr_r} ${fdtfile};" \
|
||||
"run nfsargs addip addtty addmtd addmisc;" \
|
||||
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
|
||||
"bootcmd=run flash_self\0" \
|
||||
"load=tftp ${loadaddr} ${u-boot}\0" \
|
||||
"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \
|
||||
" +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \
|
||||
" +${filesize};cp.b ${fileaddr} " \
|
||||
xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
|
||||
"upd=run load update\0" \
|
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue