Add header files for RISC-V. Cache, ptregs, data type and other definitions are included. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com>master
Rick Chen
6 years ago
committed by
Tom Rini
parent
039ed7c572
commit
6020faf62c
@ -0,0 +1,172 @@ |
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/*
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* Copyright 1995, Russell King. |
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* Various bits and pieces copyrights include: |
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* Linus Torvalds (test_bit). |
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* |
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* Copyright (C) 2017 Andes Technology Corporation |
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* Rick Chen, Andes Technology Corporation <rick@andestech.com> |
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* |
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* bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). |
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* |
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* Please note that the code in this file should never be included |
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* from user space. Many of these are not implemented in assembler |
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* since they would be too costly. Also, they require priviledged |
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* instructions (which are not available from user mode) to ensure |
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* that they are atomic. |
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*/ |
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#ifndef __ASM_RISCV_BITOPS_H |
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#define __ASM_RISCV_BITOPS_H |
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#ifdef __KERNEL__ |
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#include <asm/system.h> |
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#include <asm-generic/bitops/fls.h> |
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#include <asm-generic/bitops/__fls.h> |
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#include <asm-generic/bitops/fls64.h> |
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#include <asm-generic/bitops/__ffs.h> |
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#define smp_mb__before_clear_bit() do { } while (0) |
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#define smp_mb__after_clear_bit() do { } while (0) |
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/*
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* Function prototypes to keep gcc -Wall happy. |
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*/ |
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static inline void __set_bit(int nr, void *addr) |
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{ |
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int *a = (int *)addr; |
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int mask; |
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a += nr >> 5; |
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mask = 1 << (nr & 0x1f); |
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*a |= mask; |
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} |
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static inline void __clear_bit(int nr, void *addr) |
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{ |
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int *a = (int *)addr; |
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int mask; |
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a += nr >> 5; |
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mask = 1 << (nr & 0x1f); |
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*a &= ~mask; |
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} |
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static inline void __change_bit(int nr, void *addr) |
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{ |
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int mask; |
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unsigned long *ADDR = (unsigned long *)addr; |
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ADDR += nr >> 5; |
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mask = 1 << (nr & 31); |
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*ADDR ^= mask; |
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} |
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static inline int __test_and_set_bit(int nr, void *addr) |
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{ |
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int mask, retval; |
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unsigned int *a = (unsigned int *)addr; |
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a += nr >> 5; |
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mask = 1 << (nr & 0x1f); |
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retval = (mask & *a) != 0; |
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*a |= mask; |
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return retval; |
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} |
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static inline int __test_and_clear_bit(int nr, void *addr) |
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{ |
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int mask, retval; |
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unsigned int *a = (unsigned int *)addr; |
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a += nr >> 5; |
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mask = 1 << (nr & 0x1f); |
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retval = (mask & *a) != 0; |
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*a &= ~mask; |
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return retval; |
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} |
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static inline int __test_and_change_bit(int nr, void *addr) |
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{ |
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int mask, retval; |
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unsigned int *a = (unsigned int *)addr; |
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a += nr >> 5; |
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mask = 1 << (nr & 0x1f); |
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retval = (mask & *a) != 0; |
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*a ^= mask; |
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return retval; |
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} |
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/*
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* This routine doesn't need to be atomic. |
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*/ |
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static inline int test_bit(int nr, const void *addr) |
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{ |
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return ((unsigned char *)addr)[nr >> 3] & (1U << (nr & 7)); |
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} |
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/*
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* ffz = Find First Zero in word. Undefined if no zero exists, |
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* so code should check against ~0UL first.. |
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*/ |
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static inline unsigned long ffz(unsigned long word) |
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{ |
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int k; |
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word = ~word; |
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k = 31; |
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if (word & 0x0000ffff) { |
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k -= 16; word <<= 16; |
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} |
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if (word & 0x00ff0000) { |
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k -= 8; word <<= 8; |
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} |
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if (word & 0x0f000000) { |
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k -= 4; word <<= 4; |
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} |
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if (word & 0x30000000) { |
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k -= 2; word <<= 2; |
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} |
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if (word & 0x40000000) |
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k -= 1; |
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return k; |
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} |
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/*
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* ffs: find first bit set. This is defined the same way as |
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* the libc and compiler builtin ffs routines, therefore |
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* differs in spirit from the above ffz (man ffs). |
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*/ |
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/*
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* redefined in include/linux/bitops.h |
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* #define ffs(x) generic_ffs(x) |
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*/ |
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/*
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* hweightN: returns the hamming weight (i.e. the number |
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* of bits set) of a N-bit word |
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*/ |
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#define hweight32(x) generic_hweight32(x) |
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#define hweight16(x) generic_hweight16(x) |
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#define hweight8(x) generic_hweight8(x) |
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#define ext2_set_bit test_and_set_bit |
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#define ext2_clear_bit test_and_clear_bit |
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#define ext2_test_bit test_bit |
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#define ext2_find_first_zero_bit find_first_zero_bit |
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#define ext2_find_next_zero_bit find_next_zero_bit |
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/* Bitmap functions for the minix filesystem. */ |
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#define minix_test_and_set_bit(nr, addr) test_and_set_bit(nr, addr) |
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#define minix_set_bit(nr, addr) set_bit(nr, addr) |
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#define minix_test_and_clear_bit(nr, addr) test_and_clear_bit(nr, addr) |
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#define minix_test_bit(nr, addr) test_bit(nr, addr) |
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#define minix_find_first_zero_bit(addr, size) find_first_zero_bit(addr, size) |
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#endif /* __KERNEL__ */ |
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#endif /* __ASM_RISCV_BITOPS_H */ |
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@ -0,0 +1,65 @@ |
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/*
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* Copyright (c) 2013, Google Inc. |
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* |
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* Copyright (C) 2011 |
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* Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef NDS32_BOOTM_H |
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#define NDS32_BOOTM_H |
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#include <asm/setup.h> |
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#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ |
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defined(CONFIG_CMDLINE_TAG) || \
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defined(CONFIG_INITRD_TAG) || \
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defined(CONFIG_SERIAL_TAG) || \
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defined(CONFIG_REVISION_TAG) |
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# define BOOTM_ENABLE_TAGS 1 |
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#else |
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# define BOOTM_ENABLE_TAGS 0 |
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#endif |
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#ifdef CONFIG_SETUP_MEMORY_TAGS |
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# define BOOTM_ENABLE_MEMORY_TAGS 1 |
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#else |
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# define BOOTM_ENABLE_MEMORY_TAGS 0 |
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#endif |
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#ifdef CONFIG_CMDLINE_TAG |
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#define BOOTM_ENABLE_CMDLINE_TAG 1 |
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#else |
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#define BOOTM_ENABLE_CMDLINE_TAG 0 |
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#endif |
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#ifdef CONFIG_INITRD_TAG |
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#define BOOTM_ENABLE_INITRD_TAG 1 |
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#else |
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#define BOOTM_ENABLE_INITRD_TAG 0 |
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#endif |
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#ifdef CONFIG_SERIAL_TAG |
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#define BOOTM_ENABLE_SERIAL_TAG 1 |
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void get_board_serial(struct tag_serialnr *serialnr); |
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#else |
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#define BOOTM_ENABLE_SERIAL_TAG 0 |
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static inline void get_board_serial(struct tag_serialnr *serialnr) |
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{ |
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} |
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#endif |
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#ifdef CONFIG_REVISION_TAG |
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#define BOOTM_ENABLE_REVISION_TAG 1 |
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u32 get_board_rev(void); |
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#else |
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#define BOOTM_ENABLE_REVISION_TAG 0 |
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static inline u32 get_board_rev(void) |
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{ |
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return 0; |
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} |
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#endif |
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#endif |
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@ -0,0 +1,35 @@ |
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/*
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* linux/include/asm-arm/byteorder.h |
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* |
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* Copyright (C) 2017 Andes Technology Corporation |
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* Rick Chen, Andes Technology Corporation <rick@andestech.com> |
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* |
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* ARM Endian-ness. In little endian mode, the data bus is connected such |
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* that byte accesses appear as: |
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* 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31 |
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* and word accesses (data or instruction) appear as: |
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* d0...d31 |
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* |
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* When in big endian mode, byte accesses appear as: |
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* 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7 |
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* and word accesses (data or instruction) appear as: |
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* d0...d31 |
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*/ |
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#ifndef __ASM_RISCV_BYTEORDER_H |
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#define __ASM_RISCV_BYTEORDER_H |
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#include <asm/types.h> |
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#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) |
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# define __BYTEORDER_HAS_U64__ |
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# define __SWAB_64_THRU_32__ |
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#endif |
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#ifdef __RISCVEB__ |
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#include <linux/byteorder/big_endian.h> |
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#else |
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#include <linux/byteorder/little_endian.h> |
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#endif |
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#endif |
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@ -0,0 +1,22 @@ |
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/*
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* Copyright (C) 2017 Andes Technology Corporation |
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* Rick Chen, Andes Technology Corporation <rick@andestech.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _ASM_RISCV_CACHE_H |
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#define _ASM_RISCV_CACHE_H |
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/*
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* The current upper bound for RISCV L1 data cache line sizes is 32 bytes. |
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* We use that value for aligning DMA buffers unless the board config has |
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* specified an alternate cache line size. |
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*/ |
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#ifdef CONFIG_SYS_CACHELINE_SIZE |
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#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE |
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#else |
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#define ARCH_DMA_MINALIGN 32 |
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#endif |
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#endif /* _ASM_RISCV_CACHE_H */ |
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@ -0,0 +1,13 @@ |
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/*
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* Copyright (C) 2017 Andes Technology Corporation |
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* Rick Chen, Andes Technology Corporation <rick@andestech.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _ASM_CONFIG_H_ |
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#define _ASM_CONFIG_H_ |
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#define CONFIG_LMB |
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#endif |
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@ -0,0 +1,188 @@ |
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/*
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* Copyright (c) 2017 Microsemi Corporation. |
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* Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef RISCV_CSR_ENCODING_H |
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#define RISCV_CSR_ENCODING_H |
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#define MSTATUS_UIE 0x00000001 |
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#define MSTATUS_SIE 0x00000002 |
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#define MSTATUS_HIE 0x00000004 |
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#define MSTATUS_MIE 0x00000008 |
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#define MSTATUS_UPIE 0x00000010 |
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#define MSTATUS_SPIE 0x00000020 |
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#define MSTATUS_HPIE 0x00000040 |
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#define MSTATUS_MPIE 0x00000080 |
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#define MSTATUS_SPP 0x00000100 |
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#define MSTATUS_HPP 0x00000600 |
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#define MSTATUS_MPP 0x00001800 |
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#define MSTATUS_FS 0x00006000 |
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#define MSTATUS_XS 0x00018000 |
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#define MSTATUS_MPRV 0x00020000 |
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#define MSTATUS_PUM 0x00040000 |
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#define MSTATUS_VM 0x1F000000 |
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#define MSTATUS32_SD 0x80000000 |
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#define MSTATUS64_SD 0x8000000000000000 |
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#define MCAUSE32_CAUSE 0x7FFFFFFF |
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#define MCAUSE64_CAUSE 0x7FFFFFFFFFFFFFFF |
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#define MCAUSE32_INT 0x80000000 |
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#define MCAUSE64_INT 0x8000000000000000 |
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#define SSTATUS_UIE 0x00000001 |
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#define SSTATUS_SIE 0x00000002 |
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#define SSTATUS_UPIE 0x00000010 |
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#define SSTATUS_SPIE 0x00000020 |
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#define SSTATUS_SPP 0x00000100 |
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#define SSTATUS_FS 0x00006000 |
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#define SSTATUS_XS 0x00018000 |
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#define SSTATUS_PUM 0x00040000 |
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#define SSTATUS32_SD 0x80000000 |
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#define SSTATUS64_SD 0x8000000000000000 |
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#define MIP_SSIP BIT(IRQ_S_SOFT) |
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#define MIP_HSIP BIT(IRQ_H_SOFT) |
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#define MIP_MSIP BIT(IRQ_M_SOFT) |
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#define MIP_STIP BIT(IRQ_S_TIMER) |
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#define MIP_HTIP BIT(IRQ_H_TIMER) |
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#define MIP_MTIP BIT(IRQ_M_TIMER) |
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#define MIP_SEIP BIT(IRQ_S_EXT) |
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#define MIP_HEIP BIT(IRQ_H_EXT) |
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#define MIP_MEIP BIT(IRQ_M_EXT) |
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#define SIP_SSIP MIP_SSIP |
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#define SIP_STIP MIP_STIP |
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#define PRV_U 0 |
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#define PRV_S 1 |
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#define PRV_H 2 |
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#define PRV_M 3 |
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#define VM_MBARE 0 |
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#define VM_MBB 1 |
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#define VM_MBBID 2 |
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#define VM_SV32 8 |
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#define VM_SV39 9 |
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#define VM_SV48 10 |
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#define IRQ_S_SOFT 1 |
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#define IRQ_H_SOFT 2 |
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#define IRQ_M_SOFT 3 |
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#define IRQ_S_TIMER 5 |
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#define IRQ_H_TIMER 6 |
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#define IRQ_M_TIMER 7 |
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#define IRQ_S_EXT 9 |
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#define IRQ_H_EXT 10 |
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#define IRQ_M_EXT 11 |
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#define IRQ_COP 12 |
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#define IRQ_HOST 13 |
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#define DEFAULT_RSTVEC 0x00001000 |
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#define DEFAULT_NMIVEC 0x00001004 |
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#define DEFAULT_MTVEC 0x00001010 |
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#define CONFIG_STRING_ADDR 0x0000100C |
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#define EXT_IO_BASE 0x40000000 |
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#define DRAM_BASE 0x80000000 |
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// page table entry (PTE) fields
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#define PTE_V 0x001 // Valid
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#define PTE_TYPE 0x01E // Type
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#define PTE_R 0x020 // Referenced
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#define PTE_D 0x040 // Dirty
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#define PTE_SOFT 0x380 // Reserved for Software
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#define PTE_TYPE_TABLE 0x00 |
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#define PTE_TYPE_TABLE_GLOBAL 0x02 |
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#define PTE_TYPE_URX_SR 0x04 |
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#define PTE_TYPE_URWX_SRW 0x06 |
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#define PTE_TYPE_UR_SR 0x08 |
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#define PTE_TYPE_URW_SRW 0x0A |
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#define PTE_TYPE_URX_SRX 0x0C |
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#define PTE_TYPE_URWX_SRWX0x0E |
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#define PTE_TYPE_SR 0x10 |
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#define PTE_TYPE_SRW 0x12 |
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#define PTE_TYPE_SRX 0x14 |
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#define PTE_TYPE_SRWX 0x16 |
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#define PTE_TYPE_SR_GLOBAL 0x18 |
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#define PTE_TYPE_SRW_GLOBAL 0x1A |
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#define PTE_TYPE_SRX_GLOBAL 0x1C |
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#define PTE_TYPE_SRWX_GLOBAL 0x1E |
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#define PTE_PPN_SHIFT 10 |
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#define PTE_TABLE(PTE) ((0x0000000AU >> ((PTE) & 0x1F)) & 1) |
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#define PTE_UR(PTE) ((0x0000AAA0U >> ((PTE) & 0x1F)) & 1) |
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#define PTE_UW(PTE) ((0x00008880U >> ((PTE) & 0x1F)) & 1) |
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#define PTE_UX(PTE) ((0x0000A0A0U >> ((PTE) & 0x1F)) & 1) |
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#define PTE_SR(PTE) ((0xAAAAAAA0U >> ((PTE) & 0x1F)) & 1) |
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#define PTE_SW(PTE) ((0x88888880U >> ((PTE) & 0x1F)) & 1) |
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#define PTE_SX(PTE) ((0xA0A0A000U >> ((PTE) & 0x1F)) & 1) |
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#define PTE_CHECK_PERM(PTE, SUPERVISOR, STORE, FETCH) \ |
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((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \
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(FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \
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((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE))) |
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#ifdef __riscv |
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#ifdef CONFIG_64BIT |
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# define MSTATUS_SD MSTATUS64_SD |
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# define SSTATUS_SD SSTATUS64_SD |
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# define MCAUSE_INT MCAUSE64_INT |
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# define MCAUSE_CAUSE MCAUSE64_CAUSE |
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# define RISCV_PGLEVEL_BITS 9 |
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#else |
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# define MSTATUS_SD MSTATUS32_SD |
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# define SSTATUS_SD SSTATUS32_SD |
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# define RISCV_PGLEVEL_BITS 10 |
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# define MCAUSE_INT MCAUSE32_INT |
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# define MCAUSE_CAUSE MCAUSE32_CAUSE |
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#endif |
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#define RISCV_PGSHIFT 12 |
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#define RISCV_PGSIZE BIT(RISCV_PGSHIFT) |
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#ifndef __ASSEMBLER__ |
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#ifdef __GNUC__ |
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#define read_csr(reg) ({ unsigned long __tmp; \ |
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asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
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__tmp; }) |
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#define write_csr(reg, val) ({ \ |
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if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
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asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
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else \
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asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) |
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#define swap_csr(reg, val) ({ unsigned long __tmp; \ |
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if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
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asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
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else \
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asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
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__tmp; }) |
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#define set_csr(reg, bit) ({ unsigned long __tmp; \ |
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if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
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asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
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else \
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asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
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__tmp; }) |
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#define clear_csr(reg, bit) ({ unsigned long __tmp; \ |
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if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
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asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
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else \
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asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
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__tmp; }) |
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#define rdtime() read_csr(time) |
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#define rdcycle() read_csr(cycle) |
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#define rdinstret() read_csr(instret) |
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#endif |
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#endif |
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#endif |
||||
#endif |
||||
@ -0,0 +1,22 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* Copyright (c) 2017 Microsemi Corporation. |
||||
* Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __ASM_GBL_DATA_H |
||||
#define __ASM_GBL_DATA_H |
||||
|
||||
/* Architecture-specific global data */ |
||||
struct arch_global_data { |
||||
}; |
||||
|
||||
#include <asm-generic/global_data.h> |
||||
|
||||
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("gp") |
||||
|
||||
#endif /* __ASM_GBL_DATA_H */ |
||||
@ -0,0 +1,494 @@ |
||||
/*
|
||||
* Copyright (C) 2017 Andes Technology Corporation |
||||
* Rick Chen, Andes Technology Corporation <rick@andestech.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
* |
||||
*/ |
||||
#ifndef __ASM_RISCV_IO_H |
||||
#define __ASM_RISCV_IO_H |
||||
|
||||
#ifdef __KERNEL__ |
||||
|
||||
#include <linux/types.h> |
||||
#include <asm/byteorder.h> |
||||
|
||||
static inline void sync(void) |
||||
{ |
||||
} |
||||
|
||||
/*
|
||||
* Given a physical address and a length, return a virtual address |
||||
* that can be used to access the memory range with the caching |
||||
* properties specified by "flags". |
||||
*/ |
||||
#define MAP_NOCACHE (0) |
||||
#define MAP_WRCOMBINE (0) |
||||
#define MAP_WRBACK (0) |
||||
#define MAP_WRTHROUGH (0) |
||||
|
||||
#ifdef CONFIG_ARCH_MAP_SYSMEM |
||||
static inline void *map_sysmem(phys_addr_t paddr, unsigned long len) |
||||
{ |
||||
if (paddr < PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE) |
||||
paddr = paddr | 0x40000000; |
||||
return (void *)(uintptr_t)paddr; |
||||
} |
||||
|
||||
static inline void *unmap_sysmem(const void *vaddr) |
||||
{ |
||||
phys_addr_t paddr = (phys_addr_t)vaddr; |
||||
|
||||
paddr = paddr & ~0x40000000; |
||||
return (void *)(uintptr_t)paddr; |
||||
} |
||||
|
||||
static inline phys_addr_t map_to_sysmem(const void *ptr) |
||||
{ |
||||
return (phys_addr_t)(uintptr_t)ptr; |
||||
} |
||||
#endif |
||||
|
||||
static inline void * |
||||
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) |
||||
{ |
||||
return (void *)paddr; |
||||
} |
||||
|
||||
/*
|
||||
* Take down a mapping set up by map_physmem(). |
||||
*/ |
||||
static inline void unmap_physmem(void *vaddr, unsigned long flags) |
||||
{ |
||||
} |
||||
|
||||
static inline phys_addr_t virt_to_phys(void *vaddr) |
||||
{ |
||||
return (phys_addr_t)(vaddr); |
||||
} |
||||
|
||||
/*
|
||||
* Generic virtual read/write. Note that we don't support half-word |
||||
* read/writes. We define __arch_*[bl] here, and leave __arch_*w |
||||
* to the architecture specific code. |
||||
*/ |
||||
#define __arch_getb(a) (*(unsigned char *)(a)) |
||||
#define __arch_getw(a) (*(unsigned short *)(a)) |
||||
#define __arch_getl(a) (*(unsigned int *)(a)) |
||||
#define __arch_getq(a) (*(unsigned long *)(a)) |
||||
|
||||
#define __arch_putb(v, a) (*(unsigned char *)(a) = (v)) |
||||
#define __arch_putw(v, a) (*(unsigned short *)(a) = (v)) |
||||
#define __arch_putl(v, a) (*(unsigned int *)(a) = (v)) |
||||
#define __arch_putq(v, a) (*(unsigned long *)(a) = (v)) |
||||
|
||||
#define __raw_writeb(v, a) __arch_putb(v, a) |
||||
#define __raw_writew(v, a) __arch_putw(v, a) |
||||
#define __raw_writel(v, a) __arch_putl(v, a) |
||||
#define __raw_writeq(v, a) __arch_putq(v, a) |
||||
|
||||
#define __raw_readb(a) __arch_getb(a) |
||||
#define __raw_readw(a) __arch_getw(a) |
||||
#define __raw_readl(a) __arch_getl(a) |
||||
#define __raw_readq(a) __arch_getq(a) |
||||
|
||||
/*
|
||||
* TODO: The kernel offers some more advanced versions of barriers, it might |
||||
* have some advantages to use them instead of the simple one here. |
||||
*/ |
||||
#define dmb() __asm__ __volatile__ ("" : : : "memory") |
||||
#define __iormb() dmb() |
||||
#define __iowmb() dmb() |
||||
|
||||
static inline void writeb(u8 val, volatile void __iomem *addr) |
||||
{ |
||||
__iowmb(); |
||||
__arch_putb(val, addr); |
||||
} |
||||
|
||||
static inline void writew(u16 val, volatile void __iomem *addr) |
||||
{ |
||||
__iowmb(); |
||||
__arch_putw(val, addr); |
||||
} |
||||
|
||||
static inline void writel(u32 val, volatile void __iomem *addr) |
||||
{ |
||||
__iowmb(); |
||||
__arch_putl(val, addr); |
||||
} |
||||
|
||||
static inline void writeq(u64 val, volatile void __iomem *addr) |
||||
{ |
||||
__iowmb(); |
||||
__arch_putq(val, addr); |
||||
} |
||||
|
||||
static inline u8 readb(const volatile void __iomem *addr) |
||||
{ |
||||
u8 val; |
||||
|
||||
val = __arch_getb(addr); |
||||
__iormb(); |
||||
return val; |
||||
} |
||||
|
||||
static inline u16 readw(const volatile void __iomem *addr) |
||||
{ |
||||
u16 val; |
||||
|
||||
val = __arch_getw(addr); |
||||
__iormb(); |
||||
return val; |
||||
} |
||||
|
||||
static inline u32 readl(const volatile void __iomem *addr) |
||||
{ |
||||
u32 val; |
||||
|
||||
val = __arch_getl(addr); |
||||
__iormb(); |
||||
return val; |
||||
} |
||||
|
||||
static inline u64 readq(const volatile void __iomem *addr) |
||||
{ |
||||
u32 val; |
||||
|
||||
val = __arch_getq(addr); |
||||
__iormb(); |
||||
return val; |
||||
} |
||||
|
||||
/*
|
||||
* The compiler seems to be incapable of optimising constants |
||||
* properly. Spell it out to the compiler in some cases. |
||||
* These are only valid for small values of "off" (< 1<<12) |
||||
*/ |
||||
#define __raw_base_writeb(val, base, off) __arch_base_putb(val, base, off) |
||||
#define __raw_base_writew(val, base, off) __arch_base_putw(val, base, off) |
||||
#define __raw_base_writel(val, base, off) __arch_base_putl(val, base, off) |
||||
|
||||
#define __raw_base_readb(base, off) __arch_base_getb(base, off) |
||||
#define __raw_base_readw(base, off) __arch_base_getw(base, off) |
||||
#define __raw_base_readl(base, off) __arch_base_getl(base, off) |
||||
|
||||
#define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a) |
||||
#define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a)) |
||||
|
||||
#define out_le32(a, v) out_arch(l, le32, a, v) |
||||
#define out_le16(a, v) out_arch(w, le16, a, v) |
||||
|
||||
#define in_le32(a) in_arch(l, le32, a) |
||||
#define in_le16(a) in_arch(w, le16, a) |
||||
|
||||
#define out_be32(a, v) out_arch(l, be32, a, v) |
||||
#define out_be16(a, v) out_arch(w, be16, a, v) |
||||
|
||||
#define in_be32(a) in_arch(l, be32, a) |
||||
#define in_be16(a) in_arch(w, be16, a) |
||||
|
||||
#define out_8(a, v) __raw_writeb(v, a) |
||||
#define in_8(a) __raw_readb(a) |
||||
|
||||
/*
|
||||
* Clear and set bits in one shot. These macros can be used to clear and |
||||
* set multiple bits in a register using a single call. These macros can |
||||
* also be used to set a multiple-bit bit pattern using a mask, by |
||||
* specifying the mask in the 'clear' parameter and the new bit pattern |
||||
* in the 'set' parameter. |
||||
*/ |
||||
|
||||
#define clrbits(type, addr, clear) \ |
||||
out_##type((addr), in_##type(addr) & ~(clear)) |
||||
|
||||
#define setbits(type, addr, set) \ |
||||
out_##type((addr), in_##type(addr) | (set)) |
||||
|
||||
#define clrsetbits(type, addr, clear, set) \ |
||||
out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) |
||||
|
||||
#define clrbits_be32(addr, clear) clrbits(be32, addr, clear) |
||||
#define setbits_be32(addr, set) setbits(be32, addr, set) |
||||
#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) |
||||
|
||||
#define clrbits_le32(addr, clear) clrbits(le32, addr, clear) |
||||
#define setbits_le32(addr, set) setbits(le32, addr, set) |
||||
#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) |
||||
|
||||
#define clrbits_be16(addr, clear) clrbits(be16, addr, clear) |
||||
#define setbits_be16(addr, set) setbits(be16, addr, set) |
||||
#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) |
||||
|
||||
#define clrbits_le16(addr, clear) clrbits(le16, addr, clear) |
||||
#define setbits_le16(addr, set) setbits(le16, addr, set) |
||||
#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) |
||||
|
||||
#define clrbits_8(addr, clear) clrbits(8, addr, clear) |
||||
#define setbits_8(addr, set) setbits(8, addr, set) |
||||
#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) |
||||
|
||||
/*
|
||||
* Now, pick up the machine-defined IO definitions |
||||
* #include <asm/arch/io.h> |
||||
*/ |
||||
|
||||
/*
|
||||
* IO port access primitives |
||||
* ------------------------- |
||||
* |
||||
* The NDS32 doesn't have special IO access instructions just like ARM; |
||||
* all IO is memory mapped. |
||||
* Note that these are defined to perform little endian accesses |
||||
* only. Their primary purpose is to access PCI and ISA peripherals. |
||||
* |
||||
* Note that for a big endian machine, this implies that the following |
||||
* big endian mode connectivity is in place, as described by numerious |
||||
* ARM documents: |
||||
* |
||||
* PCI: D0-D7 D8-D15 D16-D23 D24-D31 |
||||
* ARM: D24-D31 D16-D23 D8-D15 D0-D7 |
||||
* |
||||
* The machine specific io.h include defines __io to translate an "IO" |
||||
* address to a memory address. |
||||
* |
||||
* Note that we prevent GCC re-ordering or caching values in expressions |
||||
* by introducing sequence points into the in*() definitions. Note that |
||||
* __raw_* do not guarantee this behaviour. |
||||
* |
||||
* The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. |
||||
*/ |
||||
#ifdef __io |
||||
#define outb(v, p) __raw_writeb(v, __io(p)) |
||||
#define outw(v, p) __raw_writew(cpu_to_le16(v), __io(p)) |
||||
#define outl(v, p) __raw_writel(cpu_to_le32(v), __io(p)) |
||||
|
||||
#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) |
||||
#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; }) |
||||
#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; }) |
||||
|
||||
#define outsb(p, d, l) writesb(__io(p), d, l) |
||||
#define outsw(p, d, l) writesw(__io(p), d, l) |
||||
#define outsl(p, d, l) writesl(__io(p), d, l) |
||||
|
||||
#define insb(p, d, l) readsb(__io(p), d, l) |
||||
#define insw(p, d, l) readsw(__io(p), d, l) |
||||
#define insl(p, d, l) readsl(__io(p), d, l) |
||||
|
||||
static inline void readsb(unsigned int *addr, void *data, int bytelen) |
||||
{ |
||||
unsigned char *ptr; |
||||
unsigned char *ptr2; |
||||
|
||||
ptr = (unsigned char *)addr; |
||||
ptr2 = (unsigned char *)data; |
||||
|
||||
while (bytelen) { |
||||
*ptr2 = *ptr; |
||||
ptr2++; |
||||
bytelen--; |
||||
} |
||||
} |
||||
|
||||
static inline void readsw(unsigned int *addr, void *data, int wordlen) |
||||
{ |
||||
unsigned short *ptr; |
||||
unsigned short *ptr2; |
||||
|
||||
ptr = (unsigned short *)addr; |
||||
ptr2 = (unsigned short *)data; |
||||
|
||||
while (wordlen) { |
||||
*ptr2 = *ptr; |
||||
ptr2++; |
||||
wordlen--; |
||||
} |
||||
} |
||||
|
||||
static inline void readsl(unsigned int *addr, void *data, int longlen) |
||||
{ |
||||
unsigned int *ptr; |
||||
unsigned int *ptr2; |
||||
|
||||
ptr = (unsigned int *)addr; |
||||
ptr2 = (unsigned int *)data; |
||||
|
||||
while (longlen) { |
||||
*ptr2 = *ptr; |
||||
ptr2++; |
||||
longlen--; |
||||
} |
||||
} |
||||
|
||||
static inline void writesb(unsigned int *addr, const void *data, int bytelen) |
||||
{ |
||||
unsigned char *ptr; |
||||
unsigned char *ptr2; |
||||
|
||||
ptr = (unsigned char *)addr; |
||||
ptr2 = (unsigned char *)data; |
||||
|
||||
while (bytelen) { |
||||
*ptr = *ptr2; |
||||
ptr2++; |
||||
bytelen--; |
||||
} |
||||
} |
||||
|
||||
static inline void writesw(unsigned int *addr, const void *data, int wordlen) |
||||
{ |
||||
unsigned short *ptr; |
||||
unsigned short *ptr2; |
||||
|
||||
ptr = (unsigned short *)addr; |
||||
ptr2 = (unsigned short *)data; |
||||
|
||||
while (wordlen) { |
||||
*ptr = *ptr2; |
||||
ptr2++; |
||||
wordlen--; |
||||
} |
||||
} |
||||
|
||||
static inline void writesl(unsigned int *addr, const void *data, int longlen) |
||||
{ |
||||
unsigned int *ptr; |
||||
unsigned int *ptr2; |
||||
|
||||
ptr = (unsigned int *)addr; |
||||
ptr2 = (unsigned int *)data; |
||||
|
||||
while (longlen) { |
||||
*ptr = *ptr2; |
||||
ptr2++; |
||||
longlen--; |
||||
} |
||||
} |
||||
#endif |
||||
|
||||
#define outb_p(val, port) outb((val), (port)) |
||||
#define outw_p(val, port) outw((val), (port)) |
||||
#define outl_p(val, port) outl((val), (port)) |
||||
#define inb_p(port) inb((port)) |
||||
#define inw_p(port) inw((port)) |
||||
#define inl_p(port) inl((port)) |
||||
|
||||
#define outsb_p(port, from, len) outsb(port, from, len) |
||||
#define outsw_p(port, from, len) outsw(port, from, len) |
||||
#define outsl_p(port, from, len) outsl(port, from, len) |
||||
#define insb_p(port, to, len) insb(port, to, len) |
||||
#define insw_p(port, to, len) insw(port, to, len) |
||||
#define insl_p(port, to, len) insl(port, to, len) |
||||
|
||||
/*
|
||||
* DMA-consistent mapping functions. These allocate/free a region of |
||||
* uncached, unwrite-buffered mapped memory space for use with DMA |
||||
* devices. This is the "generic" version. The PCI specific version |
||||
* is in pci.h |
||||
*/ |
||||
|
||||
/*
|
||||
* String version of IO memory access ops: |
||||
*/ |
||||
|
||||
/*
|
||||
* If this architecture has PCI memory IO, then define the read/write |
||||
* macros. These should only be used with the cookie passed from |
||||
* ioremap. |
||||
*/ |
||||
#ifdef __mem_pci |
||||
|
||||
#define readb(c) ({ unsigned int __v = \ |
||||
__raw_readb(__mem_pci(c)); __v; }) |
||||
#define readw(c) ({ unsigned int __v = \ |
||||
le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) |
||||
#define readl(c) ({ unsigned int __v = \ |
||||
le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) |
||||
|
||||
#define writeb(v, c) __raw_writeb(v, __mem_pci(c)) |
||||
#define writew(v, c) __raw_writew(cpu_to_le16(v), __mem_pci(c)) |
||||
#define writel(v, c) __raw_writel(cpu_to_le32(v), __mem_pci(c)) |
||||
|
||||
#define memset_io(c, v, l) _memset_io(__mem_pci(c), (v), (l)) |
||||
#define memcpy_fromio(a, c, l) _memcpy_fromio((a), __mem_pci(c), (l)) |
||||
#define memcpy_toio(c, a, l) _memcpy_toio(__mem_pci(c), (a), (l)) |
||||
|
||||
#define eth_io_copy_and_sum(s, c, l, b) \ |
||||
eth_copy_and_sum((s), __mem_pci(c), (l), (b)) |
||||
|
||||
static inline int |
||||
check_signature(unsigned long io_addr, const unsigned char *signature, |
||||
int length) |
||||
{ |
||||
int retval = 0; |
||||
|
||||
do { |
||||
if (readb(io_addr) != *signature) |
||||
goto out; |
||||
io_addr++; |
||||
signature++; |
||||
length--; |
||||
} while (length); |
||||
retval = 1; |
||||
out: |
||||
return retval; |
||||
} |
||||
#endif /* __mem_pci */ |
||||
|
||||
/*
|
||||
* If this architecture has ISA IO, then define the isa_read/isa_write |
||||
* macros. |
||||
*/ |
||||
#ifdef __mem_isa |
||||
|
||||
#define isa_readb(addr) __raw_readb(__mem_isa(addr)) |
||||
#define isa_readw(addr) __raw_readw(__mem_isa(addr)) |
||||
#define isa_readl(addr) __raw_readl(__mem_isa(addr)) |
||||
#define isa_writeb(val, addr) __raw_writeb(val, __mem_isa(addr)) |
||||
#define isa_writew(val, addr) __raw_writew(val, __mem_isa(addr)) |
||||
#define isa_writel(val, addr) __raw_writel(val, __mem_isa(addr)) |
||||
#define isa_memset_io(a, b, c) _memset_io(__mem_isa(a), (b), (c)) |
||||
#define isa_memcpy_fromio(a, b, c) _memcpy_fromio((a), __mem_isa(b), (c)) |
||||
#define isa_memcpy_toio(a, b, c) _memcpy_toio(__mem_isa((a)), (b), (c)) |
||||
|
||||
#define isa_eth_io_copy_and_sum(a, b, c, d) \ |
||||
eth_copy_and_sum((a), __mem_isa(b), (c), (d)) |
||||
|
||||
static inline int |
||||
isa_check_signature(unsigned long io_addr, const unsigned char *signature, |
||||
int length) |
||||
{ |
||||
int retval = 0; |
||||
|
||||
do { |
||||
if (isa_readb(io_addr) != *signature) |
||||
goto out; |
||||
io_addr++; |
||||
signature++; |
||||
length--; |
||||
} while (length); |
||||
retval = 1; |
||||
out: |
||||
return retval; |
||||
} |
||||
|
||||
#else /* __mem_isa */ |
||||
|
||||
#define isa_readb(addr) (__readwrite_bug("isa_readb"), 0) |
||||
#define isa_readw(addr) (__readwrite_bug("isa_readw"), 0) |
||||
#define isa_readl(addr) (__readwrite_bug("isa_readl"), 0) |
||||
#define isa_writeb(val, addr) __readwrite_bug("isa_writeb") |
||||
#define isa_writew(val, addr) __readwrite_bug("isa_writew") |
||||
#define isa_writel(val, addr) __readwrite_bug("isa_writel") |
||||
#define isa_memset_io(a, b, c) __readwrite_bug("isa_memset_io") |
||||
#define isa_memcpy_fromio(a, b, c) __readwrite_bug("isa_memcpy_fromio") |
||||
#define isa_memcpy_toio(a, b, c) __readwrite_bug("isa_memcpy_toio") |
||||
|
||||
#define isa_eth_io_copy_and_sum(a, b, c, d) \ |
||||
__readwrite_bug("isa_eth_io_copy_and_sum") |
||||
|
||||
#define isa_check_signature(io, sig, len) (0) |
||||
|
||||
#endif /* __mem_isa */ |
||||
#endif /* __KERNEL__ */ |
||||
#endif /* __ASM_RISCV_IO_H */ |
||||
@ -0,0 +1,12 @@ |
||||
/*
|
||||
* U-Boot - linkage.h |
||||
* |
||||
* Copyright (c) 2005-2007 Analog Devices Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __ASM_LINKAGE_H |
||||
#define __ASM_LINKAGE_H |
||||
|
||||
#endif |
||||
@ -0,0 +1,30 @@ |
||||
/*
|
||||
* Copyright (C) 2017 Andes Technology Corporation |
||||
* Rick Chen, Andes Technology Corporation <rick@andestech.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __ASM_RISCV_MACH_TYPE_H |
||||
#define __ASM_RISCV_MACH_TYPE_H |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
/* The type of machine we're running on */ |
||||
extern unsigned int __machine_arch_type; |
||||
#endif |
||||
|
||||
#define MACH_TYPE_AE250 1 |
||||
|
||||
#ifdef CONFIG_ARCH_AE250 |
||||
# ifdef machine_arch_type |
||||
# undef machine_arch_type |
||||
# define machine_arch_type __machine_arch_type |
||||
# else |
||||
# define machine_arch_type MACH_TYPE_AE250 |
||||
# endif |
||||
# define machine_is_ae250() (machine_arch_type == MACH_TYPE_AE250) |
||||
#else |
||||
# define machine_is_ae250() (1) |
||||
#endif |
||||
|
||||
#endif /* __ASM_RISCV_MACH_TYPE_H */ |
||||
@ -0,0 +1,89 @@ |
||||
/*
|
||||
* linux/include/asm-arm/posix_types.h |
||||
* |
||||
* Copyright (C) 1996-1998 Russell King. |
||||
* |
||||
* Copyright (C) 2011 Andes Technology Corporation |
||||
* Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com) |
||||
* Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com) |
||||
* Copyright (C) 2017 Rick Chen (rick@andestech.com) |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
* |
||||
* Changelog: |
||||
* 27-06-1996 RMK Created |
||||
* 25-10-2017 Modified for arch RISCV |
||||
*/ |
||||
#ifndef __ARCH_RISCV_POSIX_TYPES_H |
||||
#define __ARCH_RISCV_POSIX_TYPES_H |
||||
|
||||
/*
|
||||
* This file is generally used by user-level software, so you need to |
||||
* be a little careful about namespace pollution etc. Also, we cannot |
||||
* assume GCC is being used. |
||||
*/ |
||||
|
||||
typedef unsigned short __kernel_dev_t; |
||||
typedef unsigned long __kernel_ino_t; |
||||
typedef unsigned short __kernel_mode_t; |
||||
typedef unsigned short __kernel_nlink_t; |
||||
typedef long __kernel_off_t; |
||||
typedef int __kernel_pid_t; |
||||
typedef unsigned short __kernel_ipc_pid_t; |
||||
typedef unsigned short __kernel_uid_t; |
||||
typedef unsigned short __kernel_gid_t; |
||||
#ifdef __GNUC__ |
||||
typedef __SIZE_TYPE__ __kernel_size_t; |
||||
#else |
||||
typedef unsigned int __kernel_size_t; |
||||
#endif |
||||
typedef int __kernel_ssize_t; |
||||
typedef int __kernel_ptrdiff_t; |
||||
typedef long __kernel_time_t; |
||||
typedef long __kernel_suseconds_t; |
||||
typedef long __kernel_clock_t; |
||||
typedef int __kernel_daddr_t; |
||||
typedef char *__kernel_caddr_t; |
||||
typedef unsigned short __kernel_uid16_t; |
||||
typedef unsigned short __kernel_gid16_t; |
||||
typedef unsigned int __kernel_uid32_t; |
||||
typedef unsigned int __kernel_gid32_t; |
||||
|
||||
typedef unsigned short __kernel_old_uid_t; |
||||
typedef unsigned short __kernel_old_gid_t; |
||||
|
||||
#ifdef __GNUC__ |
||||
typedef long long __kernel_loff_t; |
||||
#endif |
||||
|
||||
typedef struct { |
||||
#if defined(__KERNEL__) || defined(__USE_ALL) |
||||
int val[2]; |
||||
#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ |
||||
int __val[2]; |
||||
#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ |
||||
} __kernel_fsid_t; |
||||
|
||||
#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) |
||||
|
||||
#undef __FD_SET |
||||
#define __FD_SET(fd, fdsetp) \ |
||||
(((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1 << (fd & 31))) |
||||
|
||||
#undef __FD_CLR |
||||
#define __FD_CLR(fd, fdsetp) \ |
||||
(((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1 << (fd & 31))) |
||||
|
||||
#undef __FD_ISSET |
||||
#define __FD_ISSET(fd, fdsetp) \ |
||||
((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1 << (fd & 31))) != 0) |
||||
|
||||
#undef __FD_ZERO |
||||
#define __FD_ZERO(fdsetp) \ |
||||
(memset(fdsetp, 0, sizeof(*(fd_set *)fdsetp))) |
||||
|
||||
#endif |
||||
|
||||
#endif /* __ARCH_RISCV_POSIX_TYPES_H */ |
||||
@ -0,0 +1,26 @@ |
||||
/*
|
||||
* linux/include/asm-arm/processor.h |
||||
* |
||||
* Copyright (C) 1995-2002 Russell King |
||||
* |
||||
* Copyright (C) 2011 Andes Technology Corporation |
||||
* Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com) |
||||
* Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com) |
||||
* Copyright (C) 2017 Rick Chen (rick@andestech.com) |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
#ifndef __ASM_RISCV_PROCESSOR_H |
||||
#define __ASM_RISCV_PROCESSOR_H |
||||
|
||||
/**************************************************************
|
||||
* CAUTION: |
||||
* - do not implement for RISCV Arch yet. |
||||
* - so far some files include /asm/processor.h, but |
||||
* no one uses the macros defined in this head file. |
||||
**************************************************************/ |
||||
|
||||
#endif /* __ASM_RISCV_PROCESSOR_H */ |
||||
@ -0,0 +1,106 @@ |
||||
/*
|
||||
* Copyright (c) 2017 Microsemi Corporation. |
||||
* Copyright (c) 2017 Padmarao Begari <Padmarao.Begari@microsemi.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
#ifndef __ASM_RISCV_PTRACE_H |
||||
#define __ASM_RISCV_PTRACE_H |
||||
|
||||
struct pt_regs { |
||||
unsigned long sepc; |
||||
unsigned long ra; |
||||
unsigned long sp; |
||||
unsigned long gp; |
||||
unsigned long tp; |
||||
unsigned long t0; |
||||
unsigned long t1; |
||||
unsigned long t2; |
||||
unsigned long s0; |
||||
unsigned long s1; |
||||
unsigned long a0; |
||||
unsigned long a1; |
||||
unsigned long a2; |
||||
unsigned long a3; |
||||
unsigned long a4; |
||||
unsigned long a5; |
||||
unsigned long a6; |
||||
unsigned long a7; |
||||
unsigned long s2; |
||||
unsigned long s3; |
||||
unsigned long s4; |
||||
unsigned long s5; |
||||
unsigned long s6; |
||||
unsigned long s7; |
||||
unsigned long s8; |
||||
unsigned long s9; |
||||
unsigned long s10; |
||||
unsigned long s11; |
||||
unsigned long t3; |
||||
unsigned long t4; |
||||
unsigned long t5; |
||||
unsigned long t6; |
||||
/* Supervisor CSRs */ |
||||
unsigned long sstatus; |
||||
unsigned long sbadaddr; |
||||
unsigned long scause; |
||||
}; |
||||
|
||||
#ifdef CONFIG_64BIT |
||||
#define REG_FMT "%016lx" |
||||
#else |
||||
#define REG_FMT "%08lx" |
||||
#endif |
||||
|
||||
#define user_mode(regs) (((regs)->sstatus & SR_PS) == 0) |
||||
|
||||
/* Helpers for working with the instruction pointer */ |
||||
#define GET_IP(regs) ((regs)->sepc) |
||||
#define SET_IP(regs, val) (GET_IP(regs) = (val)) |
||||
|
||||
static inline unsigned long instruction_pointer(struct pt_regs *regs) |
||||
{ |
||||
return GET_IP(regs); |
||||
} |
||||
|
||||
static inline void instruction_pointer_set(struct pt_regs *regs, |
||||
unsigned long val) |
||||
{ |
||||
SET_IP(regs, val); |
||||
} |
||||
|
||||
#define profile_pc(regs) instruction_pointer(regs) |
||||
|
||||
/* Helpers for working with the user stack pointer */ |
||||
#define GET_USP(regs) ((regs)->sp) |
||||
#define SET_USP(regs, val) (GET_USP(regs) = (val)) |
||||
|
||||
static inline unsigned long user_stack_pointer(struct pt_regs *regs) |
||||
{ |
||||
return GET_USP(regs); |
||||
} |
||||
|
||||
static inline void user_stack_pointer_set(struct pt_regs *regs, |
||||
unsigned long val) |
||||
{ |
||||
SET_USP(regs, val); |
||||
} |
||||
|
||||
/* Helpers for working with the frame pointer */ |
||||
#define GET_FP(regs) ((regs)->s0) |
||||
#define SET_FP(regs, val) (GET_FP(regs) = (val)) |
||||
|
||||
static inline unsigned long frame_pointer(struct pt_regs *regs) |
||||
{ |
||||
return GET_FP(regs); |
||||
} |
||||
|
||||
static inline void frame_pointer_set(struct pt_regs *regs, |
||||
unsigned long val) |
||||
{ |
||||
SET_FP(regs, val); |
||||
} |
||||
|
||||
#endif /* __ASM_RISCV_PTRACE_H */ |
||||
@ -0,0 +1,11 @@ |
||||
/*
|
||||
* Copyright (c) 2012 The Chromium OS Authors. |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __ASM_RISCV_SECTIONS_H |
||||
#define __ASM_RISCV_SECTIONS_H |
||||
|
||||
#include <asm-generic/sections.h> |
||||
|
||||
#endif |
||||
@ -0,0 +1,191 @@ |
||||
/*
|
||||
* linux/arch/nds32/include/asm/setup.h |
||||
* |
||||
* Copyright (C) 1997-1999 Russell King |
||||
* Copyright (C) 2008 Andes Technology Corporation |
||||
* Copyright (C) 2013 Ken Kuo (ken_kuo@andestech.com) |
||||
* Copyright (C) 2017 Rick Chen (rick@andestech.com) |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
* |
||||
* Structure passed to kernel to tell it about the |
||||
* hardware it's running on. See Documentation/arm/Setup |
||||
* for more info. |
||||
*/ |
||||
#ifndef __RISCV_SETUP_H |
||||
#define __RISCV_SETUP_H |
||||
|
||||
#define COMMAND_LINE_SIZE 256 |
||||
|
||||
/* The list ends with an ATAG_NONE node. */ |
||||
#define ATAG_NONE 0x00000000 |
||||
|
||||
struct tag_header { |
||||
u32 size; |
||||
u32 tag; |
||||
}; |
||||
|
||||
/* The list must start with an ATAG_CORE node */ |
||||
#define ATAG_CORE 0x54410001 |
||||
|
||||
struct tag_core { |
||||
u32 flags; /* bit 0 = read-only */ |
||||
u32 pagesize; |
||||
u32 rootdev; |
||||
}; |
||||
|
||||
/* it is allowed to have multiple ATAG_MEM nodes */ |
||||
#define ATAG_MEM 0x54410002 |
||||
|
||||
struct tag_mem32 { |
||||
u32 size; |
||||
u32 start; /* physical start address */ |
||||
}; |
||||
|
||||
/* VGA text type displays */ |
||||
#define ATAG_VIDEOTEXT 0x54410003 |
||||
|
||||
struct tag_videotext { |
||||
u8 x; |
||||
u8 y; |
||||
u16 video_page; |
||||
u8 video_mode; |
||||
u8 video_cols; |
||||
u16 video_ega_bx; |
||||
u8 video_lines; |
||||
u8 video_isvga; |
||||
u16 video_points; |
||||
}; |
||||
|
||||
/* describes how the ramdisk will be used in kernel */ |
||||
#define ATAG_RAMDISK 0x54410004 |
||||
|
||||
struct tag_ramdisk { |
||||
u32 flags; /* bit 0 = load, bit 1 = prompt */ |
||||
u32 size; /* decompressed ramdisk size in _kilo_ bytes */ |
||||
u32 start; /* starting block of floppy-based RAM disk image */ |
||||
}; |
||||
|
||||
/*
|
||||
* this one accidentally used virtual addresses - as such, |
||||
* it's deprecated. |
||||
* describes where the compressed ramdisk image lives (virtual address) |
||||
*/ |
||||
#define ATAG_INITRD 0x54410005 |
||||
|
||||
/* describes where the compressed ramdisk image lives (physical address) */ |
||||
#define ATAG_INITRD2 0x54420005 |
||||
|
||||
struct tag_initrd { |
||||
u32 start; /* physical start address */ |
||||
u32 size; /* size of compressed ramdisk image in bytes */ |
||||
}; |
||||
|
||||
/* board serial number. "64 bits should be enough for everybody" */ |
||||
#define ATAG_SERIAL 0x54410006 |
||||
|
||||
struct tag_serialnr { |
||||
u32 low; |
||||
u32 high; |
||||
}; |
||||
|
||||
/* board revision */ |
||||
#define ATAG_REVISION 0x54410007 |
||||
|
||||
struct tag_revision { |
||||
u32 rev; |
||||
}; |
||||
|
||||
/* initial values for vesafb-type framebuffers. see struct screen_info
|
||||
* in include/linux/tty.h |
||||
*/ |
||||
#define ATAG_VIDEOLFB 0x54410008 |
||||
|
||||
struct tag_videolfb { |
||||
u16 lfb_width; |
||||
u16 lfb_height; |
||||
u16 lfb_depth; |
||||
u16 lfb_linelength; |
||||
u32 lfb_base; |
||||
u32 lfb_size; |
||||
u8 red_size; |
||||
u8 red_pos; |
||||
u8 green_size; |
||||
u8 green_pos; |
||||
u8 blue_size; |
||||
u8 blue_pos; |
||||
u8 rsvd_size; |
||||
u8 rsvd_pos; |
||||
}; |
||||
|
||||
/* command line: \0 terminated string */ |
||||
#define ATAG_CMDLINE 0x54410009 |
||||
|
||||
struct tag_cmdline { |
||||
char cmdline[COMMAND_LINE_SIZE]; |
||||
}; |
||||
|
||||
struct tag { |
||||
struct tag_header hdr; |
||||
union { |
||||
struct tag_core core; |
||||
struct tag_mem32 mem; |
||||
struct tag_videotext videotext; |
||||
struct tag_ramdisk ramdisk; |
||||
struct tag_initrd initrd; |
||||
struct tag_serialnr serialnr; |
||||
struct tag_revision revision; |
||||
struct tag_videolfb videolfb; |
||||
struct tag_cmdline cmdline; |
||||
} u; |
||||
}; |
||||
|
||||
struct tagtable { |
||||
u32 tag; |
||||
int (*parse)(const struct tag *); |
||||
}; |
||||
|
||||
#define tag_member_present(tag, member) \ |
||||
((unsigned long)(&((struct tag *)0L)->member + 1) \
|
||||
<= (tag)->hdr.size * 4) |
||||
|
||||
#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size)) |
||||
#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) |
||||
|
||||
#define for_each_tag(t, base) \ |
||||
for (t = base; t->hdr.size; t = tag_next(t)) |
||||
|
||||
#ifdef __KERNEL__ |
||||
|
||||
#define __tag __used __attribute__((__section__(".taglist"))) |
||||
#define __tagtable(tag, fn) \ |
||||
static struct tagtable __tagtable_##fn __tag = { tag, fn } |
||||
|
||||
/*
|
||||
* Memory map description |
||||
*/ |
||||
#define NR_BANKS 8 |
||||
|
||||
struct meminfo { |
||||
int nr_banks; |
||||
struct { |
||||
unsigned long start; |
||||
unsigned long size; |
||||
int node; |
||||
} bank[NR_BANKS]; |
||||
}; |
||||
|
||||
/*
|
||||
* Early command line parameters. |
||||
*/ |
||||
struct early_params { |
||||
const char *arg; |
||||
void (*fn)(char **p); |
||||
}; |
||||
|
||||
#define __early_param(name, fn) \ |
||||
static struct early_params __early_##fn __used \
|
||||
__attribute__((__section__("__early_param"))) = { name, fn } |
||||
|
||||
#endif |
||||
#endif |
||||
@ -0,0 +1,43 @@ |
||||
/*
|
||||
* Copyright (C) 2011 Andes Technology Corporation |
||||
* Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com) |
||||
* Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com) |
||||
* Copyright (C) 2017 Rick Chen (rick@andestech.com) |
||||
* |
||||
* This file is subject to the terms and conditions of the GNU General Public |
||||
* License. See the file "COPYING" in the main directory of this archive |
||||
* for more details. |
||||
*/ |
||||
|
||||
#ifndef __ASM_RISCV_STRING_H |
||||
#define __ASM_RISCV_STRING_H |
||||
|
||||
/*
|
||||
* We don't do inline string functions, since the |
||||
* optimised inline asm versions are not small. |
||||
*/ |
||||
|
||||
#undef __HAVE_ARCH_STRRCHR |
||||
#undef __HAVE_ARCH_STRCHR |
||||
#undef __HAVE_ARCH_MEMCPY |
||||
#undef __HAVE_ARCH_MEMMOVE |
||||
#undef __HAVE_ARCH_MEMCHR |
||||
#undef __HAVE_ARCH_MEMZERO |
||||
#undef __HAVE_ARCH_MEMSET |
||||
|
||||
#ifdef CONFIG_MARCO_MEMSET |
||||
#define memset(p, v, n) \ |
||||
({ \
|
||||
if ((n) != 0) { \
|
||||
if (__builtin_constant_p((v)) && (v) == 0) \
|
||||
__memzero((p), (n)); \
|
||||
else \
|
||||
memset((p), (v), (n)); \
|
||||
} \
|
||||
(p); \
|
||||
}) |
||||
|
||||
#define memzero(p, n) ({ if ((n) != 0) __memzero((p), (n)); (p); }) |
||||
#endif |
||||
|
||||
#endif /* __ASM_RISCV_STRING_H */ |
||||
@ -0,0 +1,18 @@ |
||||
/*
|
||||
* Copyright (C) 2017 Andes Technology Corporation |
||||
* Rick Chen, Andes Technology Corporation <rick@andestech.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __ASM_RISCV_SYSTEM_H |
||||
#define __ASM_RISCV_SYSTEM_H |
||||
|
||||
/*
|
||||
* Interrupt configuring macros. |
||||
* |
||||
* TODO |
||||
* |
||||
*/ |
||||
|
||||
#endif /* __ASM_RISCV_SYSTEM_H */ |
||||
@ -0,0 +1,64 @@ |
||||
/*
|
||||
* Copyright (C) 2011 Andes Technology Corporation |
||||
* Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com) |
||||
* Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com) |
||||
* Copyright (C) 2017 Rick Chen (rick@andestech.com) |
||||
* |
||||
* This file is subject to the terms and conditions of the GNU General Public |
||||
* License. See the file "COPYING" in the main directory of this archive |
||||
* for more details. |
||||
*/ |
||||
|
||||
#ifndef __ASM_RISCV_TYPES_H |
||||
#define __ASM_RISCV_TYPES_H |
||||
|
||||
typedef unsigned short umode_t; |
||||
|
||||
/*
|
||||
* __xx is ok: it doesn't pollute the POSIX namespace. Use these in the |
||||
* header files exported to user space |
||||
*/ |
||||
|
||||
typedef __signed__ char __s8; |
||||
typedef unsigned char __u8; |
||||
|
||||
typedef __signed__ short __s16; |
||||
typedef unsigned short __u16; |
||||
|
||||
typedef __signed__ int __s32; |
||||
typedef unsigned int __u32; |
||||
|
||||
#if defined(__GNUC__) && !defined(__STRICT_ANSI__) |
||||
typedef __signed__ long long __s64; |
||||
typedef unsigned long long __u64; |
||||
#endif |
||||
|
||||
/*
|
||||
* These aren't exported outside the kernel to avoid name space clashes |
||||
*/ |
||||
#ifdef __KERNEL__ |
||||
|
||||
typedef signed char s8; |
||||
typedef unsigned char u8; |
||||
|
||||
typedef signed short s16; |
||||
typedef unsigned short u16; |
||||
|
||||
typedef signed int s32; |
||||
typedef unsigned int u32; |
||||
|
||||
typedef signed long long s64; |
||||
typedef unsigned long long u64; |
||||
|
||||
#define BITS_PER_LONG 32 |
||||
|
||||
#include <stddef.h> |
||||
|
||||
typedef u32 dma_addr_t; |
||||
|
||||
typedef unsigned long phys_addr_t; |
||||
typedef unsigned long phys_size_t; |
||||
|
||||
#endif /* __KERNEL__ */ |
||||
|
||||
#endif |
||||
@ -0,0 +1,21 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* Copyright (C) 2017 Andes Technology Corporation |
||||
* Rick Chen, Andes Technology Corporation <rick@andestech.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _U_BOOT_RISCV_H_ |
||||
#define _U_BOOT_RISCV_H_ 1 |
||||
|
||||
/* cpu/.../cpu.c */ |
||||
int cleanup_before_linux(void); |
||||
|
||||
/* board/.../... */ |
||||
int board_init(void); |
||||
|
||||
#endif /* _U_BOOT_RISCV_H_ */ |
||||
@ -0,0 +1,46 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* Copyright (C) 2017 Andes Technology Corporation |
||||
* Rick Chen, Andes Technology Corporation <rick@andestech.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
* |
||||
******************************************************************** |
||||
* NOTE: This header file defines an interface to U-Boot. Including |
||||
* this (unmodified) header file in another file is considered normal |
||||
* use of U-Boot, and does *not* fall under the heading of "derived |
||||
* work". |
||||
******************************************************************** |
||||
*/ |
||||
|
||||
#ifndef _U_BOOT_H_ |
||||
#define _U_BOOT_H_ 1 |
||||
|
||||
#include <asm/u-boot-riscv.h> |
||||
|
||||
#include <environment.h> |
||||
|
||||
typedef struct bd_info { |
||||
unsigned long bi_arch_number; /* unique id for this board */ |
||||
unsigned long bi_boot_params; /* where this board expects params */ |
||||
unsigned long bi_memstart; /* start of DRAM memory */ |
||||
unsigned long bi_memsize; /* size of DRAM memory in bytes */ |
||||
unsigned long bi_flashstart; /* start of FLASH memory */ |
||||
unsigned long bi_flashsize; /* size of FLASH memory */ |
||||
unsigned long bi_flashoffset; /* reserved area for startup monitor */ |
||||
unsigned char bi_enetaddr[6]; |
||||
|
||||
struct /* RAM configuration */ |
||||
{ |
||||
unsigned long start; |
||||
unsigned long size; |
||||
} bi_dram[CONFIG_NR_DRAM_BANKS]; |
||||
} bd_t; |
||||
|
||||
/* For image.h:image_check_target_arch() */ |
||||
#define IH_ARCH_DEFAULT IH_ARCH_RISCV |
||||
|
||||
#endif /* _U_BOOT_H_ */ |
||||
@ -0,0 +1 @@ |
||||
#include <asm-generic/unaligned.h> |
||||
Loading…
Reference in new issue