* Patch by Erwin Rol, 27 Feb 2003: Add support for RTEMS * Add image information to README * Fix dual PCMCIA slot support (when running with just one slot populated) * Add VFD type detection to trab board * extend drivers/cs8900.c driver to synchronize ethaddr environment variable with value in the EEPROM * Start adding MIPS support filesmaster
wdenk
22 years ago
parent
2a9e02ead3
commit
6069ff2653
@ -0,0 +1,70 @@ |
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/*
|
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Copyright (C) 1996 by Ralf Baechle |
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* Copyright (C) 2000 by Maciej W. Rozycki |
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* |
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* Defitions for the address spaces of the MIPS CPUs. |
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*/ |
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#ifndef __ASM_MIPS_ADDRSPACE_H |
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#define __ASM_MIPS_ADDRSPACE_H |
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|
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/*
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* Memory segments (32bit kernel mode addresses) |
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*/ |
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#define KUSEG 0x00000000 |
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#define KSEG0 0x80000000 |
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#define KSEG1 0xa0000000 |
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#define KSEG2 0xc0000000 |
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#define KSEG3 0xe0000000 |
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|
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#define K0BASE KSEG0 |
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|
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/*
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* Returns the kernel segment base of a given address |
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*/ |
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#ifndef __ASSEMBLY__ |
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#define KSEGX(a) (((unsigned long)(a)) & 0xe0000000) |
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#else |
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#define KSEGX(a) ((a) & 0xe0000000) |
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#endif |
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|
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/*
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* Returns the physical address of a KSEG0/KSEG1 address |
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*/ |
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#ifndef __ASSEMBLY__ |
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#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff) |
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#else |
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#define PHYSADDR(a) ((a) & 0x1fffffff) |
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#endif |
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|
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/*
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* Map an address to a certain kernel segment |
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*/ |
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#ifndef __ASSEMBLY__ |
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#define KSEG0ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG0)) |
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#define KSEG1ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG1)) |
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#define KSEG2ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG2)) |
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#define KSEG3ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG3)) |
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#else |
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#define KSEG0ADDR(a) (((a) & 0x1fffffff) | KSEG0) |
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#define KSEG1ADDR(a) (((a) & 0x1fffffff) | KSEG1) |
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#define KSEG2ADDR(a) (((a) & 0x1fffffff) | KSEG2) |
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#define KSEG3ADDR(a) (((a) & 0x1fffffff) | KSEG3) |
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#endif |
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|
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/*
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* Memory segments (64bit kernel mode addresses) |
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*/ |
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#define XKUSEG 0x0000000000000000 |
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#define XKSSEG 0x4000000000000000 |
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#define XKPHYS 0x8000000000000000 |
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#define XKSEG 0xc000000000000000 |
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#define CKSEG0 0xffffffff80000000 |
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#define CKSEG1 0xffffffffa0000000 |
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#define CKSSEG 0xffffffffc0000000 |
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#define CKSEG3 0xffffffffe0000000 |
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#endif /* __ASM_MIPS_ADDRSPACE_H */ |
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@ -0,0 +1,912 @@ |
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/*
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Copyright (c) 1994 - 1997, 1999, 2000 Ralf Baechle (ralf@gnu.org) |
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* Copyright (c) 2000 Silicon Graphics, Inc. |
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*/ |
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#ifndef _ASM_BITOPS_H |
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#define _ASM_BITOPS_H |
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#include <linux/types.h> |
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#include <asm/byteorder.h> /* sigh ... */ |
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#ifdef __KERNEL__ |
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#include <asm/sgidefs.h> |
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#include <asm/system.h> |
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#include <linux/config.h> |
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|
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/*
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* clear_bit() doesn't provide any barrier for the compiler. |
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*/ |
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#define smp_mb__before_clear_bit() barrier() |
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#define smp_mb__after_clear_bit() barrier() |
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|
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/*
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* Only disable interrupt for kernel mode stuff to keep usermode stuff |
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* that dares to use kernel include files alive. |
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*/ |
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#define __bi_flags unsigned long flags |
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#define __bi_cli() __cli() |
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#define __bi_save_flags(x) __save_flags(x) |
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#define __bi_save_and_cli(x) __save_and_cli(x) |
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#define __bi_restore_flags(x) __restore_flags(x) |
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#else |
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#define __bi_flags |
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#define __bi_cli() |
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#define __bi_save_flags(x) |
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#define __bi_save_and_cli(x) |
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#define __bi_restore_flags(x) |
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#endif /* __KERNEL__ */ |
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#ifdef CONFIG_CPU_HAS_LLSC |
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#include <asm/mipsregs.h> |
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/*
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* These functions for MIPS ISA > 1 are interrupt and SMP proof and |
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* interrupt friendly |
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*/ |
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/*
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* set_bit - Atomically set a bit in memory |
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* @nr: the bit to set |
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* @addr: the address to start counting from |
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* |
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* This function is atomic and may not be reordered. See __set_bit() |
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* if you do not require the atomic guarantees. |
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* Note that @nr may be almost arbitrarily large; this function is not |
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* restricted to acting on a single-word quantity. |
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*/ |
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extern __inline__ void |
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set_bit(int nr, volatile void *addr) |
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{ |
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unsigned long *m = ((unsigned long *) addr) + (nr >> 5); |
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unsigned long temp; |
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__asm__ __volatile__( |
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"1:\tll\t%0, %1\t\t# set_bit\n\t" |
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"or\t%0, %2\n\t" |
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"sc\t%0, %1\n\t" |
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"beqz\t%0, 1b" |
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: "=&r" (temp), "=m" (*m) |
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: "ir" (1UL << (nr & 0x1f)), "m" (*m)); |
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} |
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|
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/*
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* __set_bit - Set a bit in memory |
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* @nr: the bit to set |
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* @addr: the address to start counting from |
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* |
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* Unlike set_bit(), this function is non-atomic and may be reordered. |
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* If it's called on the same region of memory simultaneously, the effect |
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* may be that only one operation succeeds. |
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*/ |
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extern __inline__ void __set_bit(int nr, volatile void * addr) |
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{ |
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unsigned long * m = ((unsigned long *) addr) + (nr >> 5); |
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*m |= 1UL << (nr & 31); |
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} |
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|
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/*
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* clear_bit - Clears a bit in memory |
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* @nr: Bit to clear |
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* @addr: Address to start counting from |
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* |
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* clear_bit() is atomic and may not be reordered. However, it does |
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* not contain a memory barrier, so if it is used for locking purposes, |
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* you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() |
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* in order to ensure changes are visible on other processors. |
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*/ |
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extern __inline__ void |
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clear_bit(int nr, volatile void *addr) |
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{ |
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unsigned long *m = ((unsigned long *) addr) + (nr >> 5); |
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unsigned long temp; |
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__asm__ __volatile__( |
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"1:\tll\t%0, %1\t\t# clear_bit\n\t" |
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"and\t%0, %2\n\t" |
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"sc\t%0, %1\n\t" |
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"beqz\t%0, 1b\n\t" |
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: "=&r" (temp), "=m" (*m) |
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: "ir" (~(1UL << (nr & 0x1f))), "m" (*m)); |
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} |
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|
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/*
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* change_bit - Toggle a bit in memory |
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* @nr: Bit to clear |
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* @addr: Address to start counting from |
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* |
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* change_bit() is atomic and may not be reordered. |
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* Note that @nr may be almost arbitrarily large; this function is not |
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* restricted to acting on a single-word quantity. |
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*/ |
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extern __inline__ void |
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change_bit(int nr, volatile void *addr) |
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{ |
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unsigned long *m = ((unsigned long *) addr) + (nr >> 5); |
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unsigned long temp; |
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__asm__ __volatile__( |
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"1:\tll\t%0, %1\t\t# change_bit\n\t" |
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"xor\t%0, %2\n\t" |
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"sc\t%0, %1\n\t" |
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"beqz\t%0, 1b" |
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: "=&r" (temp), "=m" (*m) |
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: "ir" (1UL << (nr & 0x1f)), "m" (*m)); |
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} |
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|
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/*
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* __change_bit - Toggle a bit in memory |
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* @nr: the bit to set |
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* @addr: the address to start counting from |
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* |
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* Unlike change_bit(), this function is non-atomic and may be reordered. |
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* If it's called on the same region of memory simultaneously, the effect |
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* may be that only one operation succeeds. |
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*/ |
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extern __inline__ void __change_bit(int nr, volatile void * addr) |
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{ |
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unsigned long * m = ((unsigned long *) addr) + (nr >> 5); |
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*m ^= 1UL << (nr & 31); |
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} |
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|
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/*
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* test_and_set_bit - Set a bit and return its old value |
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* @nr: Bit to set |
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* @addr: Address to count from |
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* |
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier. |
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*/ |
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extern __inline__ int |
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test_and_set_bit(int nr, volatile void *addr) |
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{ |
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unsigned long *m = ((unsigned long *) addr) + (nr >> 5); |
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unsigned long temp, res; |
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__asm__ __volatile__( |
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".set\tnoreorder\t\t# test_and_set_bit\n" |
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"1:\tll\t%0, %1\n\t" |
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"or\t%2, %0, %3\n\t" |
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"sc\t%2, %1\n\t" |
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"beqz\t%2, 1b\n\t" |
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" and\t%2, %0, %3\n\t" |
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".set\treorder" |
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: "=&r" (temp), "=m" (*m), "=&r" (res) |
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: "r" (1UL << (nr & 0x1f)), "m" (*m) |
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: "memory"); |
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return res != 0; |
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} |
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|
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/*
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* __test_and_set_bit - Set a bit and return its old value |
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* @nr: Bit to set |
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* @addr: Address to count from |
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* |
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* This operation is non-atomic and can be reordered.
|
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* If two examples of this operation race, one can appear to succeed |
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* but actually fail. You must protect multiple accesses with a lock. |
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*/ |
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extern __inline__ int __test_and_set_bit(int nr, volatile void * addr) |
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{ |
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int mask, retval; |
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volatile int *a = addr; |
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a += nr >> 5; |
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mask = 1 << (nr & 0x1f); |
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retval = (mask & *a) != 0; |
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*a |= mask; |
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return retval; |
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} |
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|
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/*
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* test_and_clear_bit - Clear a bit and return its old value |
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* @nr: Bit to set |
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* @addr: Address to count from |
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* |
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier. |
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*/ |
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extern __inline__ int |
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test_and_clear_bit(int nr, volatile void *addr) |
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{ |
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unsigned long *m = ((unsigned long *) addr) + (nr >> 5); |
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unsigned long temp, res; |
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__asm__ __volatile__( |
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".set\tnoreorder\t\t# test_and_clear_bit\n" |
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"1:\tll\t%0, %1\n\t" |
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"or\t%2, %0, %3\n\t" |
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"xor\t%2, %3\n\t" |
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"sc\t%2, %1\n\t" |
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"beqz\t%2, 1b\n\t" |
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" and\t%2, %0, %3\n\t" |
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".set\treorder" |
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: "=&r" (temp), "=m" (*m), "=&r" (res) |
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: "r" (1UL << (nr & 0x1f)), "m" (*m) |
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: "memory"); |
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return res != 0; |
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} |
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|
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/*
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* __test_and_clear_bit - Clear a bit and return its old value |
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* @nr: Bit to set |
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* @addr: Address to count from |
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* |
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* This operation is non-atomic and can be reordered.
|
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* If two examples of this operation race, one can appear to succeed |
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* but actually fail. You must protect multiple accesses with a lock. |
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*/ |
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extern __inline__ int __test_and_clear_bit(int nr, volatile void * addr) |
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{ |
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int mask, retval; |
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volatile int *a = addr; |
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a += nr >> 5; |
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mask = 1 << (nr & 0x1f); |
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retval = (mask & *a) != 0; |
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*a &= ~mask; |
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return retval; |
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} |
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|
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/*
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* test_and_change_bit - Change a bit and return its new value |
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* @nr: Bit to set |
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* @addr: Address to count from |
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* |
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* This operation is atomic and cannot be reordered.
|
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* It also implies a memory barrier. |
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*/ |
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extern __inline__ int |
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test_and_change_bit(int nr, volatile void *addr) |
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{ |
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unsigned long *m = ((unsigned long *) addr) + (nr >> 5); |
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unsigned long temp, res; |
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|
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__asm__ __volatile__( |
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".set\tnoreorder\t\t# test_and_change_bit\n" |
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"1:\tll\t%0, %1\n\t" |
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"xor\t%2, %0, %3\n\t" |
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"sc\t%2, %1\n\t" |
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"beqz\t%2, 1b\n\t" |
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" and\t%2, %0, %3\n\t" |
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".set\treorder" |
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: "=&r" (temp), "=m" (*m), "=&r" (res) |
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: "r" (1UL << (nr & 0x1f)), "m" (*m) |
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: "memory"); |
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|
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return res != 0; |
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} |
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|
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/*
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* __test_and_change_bit - Change a bit and return its old value |
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* @nr: Bit to set |
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* @addr: Address to count from |
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* |
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* This operation is non-atomic and can be reordered.
|
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* If two examples of this operation race, one can appear to succeed |
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* but actually fail. You must protect multiple accesses with a lock. |
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*/ |
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extern __inline__ int __test_and_change_bit(int nr, volatile void * addr) |
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{ |
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int mask, retval; |
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volatile int *a = addr; |
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|
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a += nr >> 5; |
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mask = 1 << (nr & 0x1f); |
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retval = (mask & *a) != 0; |
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*a ^= mask; |
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return retval; |
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} |
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|
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#else /* MIPS I */ |
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|
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/*
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* set_bit - Atomically set a bit in memory |
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* @nr: the bit to set |
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* @addr: the address to start counting from |
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* |
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* This function is atomic and may not be reordered. See __set_bit() |
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* if you do not require the atomic guarantees. |
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* Note that @nr may be almost arbitrarily large; this function is not |
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* restricted to acting on a single-word quantity. |
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*/ |
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extern __inline__ void set_bit(int nr, volatile void * addr) |
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{ |
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int mask; |
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volatile int *a = addr; |
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__bi_flags; |
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|
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a += nr >> 5; |
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mask = 1 << (nr & 0x1f); |
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__bi_save_and_cli(flags); |
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*a |= mask; |
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__bi_restore_flags(flags); |
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} |
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|
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/*
|
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* __set_bit - Set a bit in memory |
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* @nr: the bit to set |
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* @addr: the address to start counting from |
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* |
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* Unlike set_bit(), this function is non-atomic and may be reordered. |
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* If it's called on the same region of memory simultaneously, the effect |
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* may be that only one operation succeeds. |
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*/ |
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extern __inline__ void __set_bit(int nr, volatile void * addr) |
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{ |
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int mask; |
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volatile int *a = addr; |
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|
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a += nr >> 5; |
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mask = 1 << (nr & 0x1f); |
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*a |= mask; |
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} |
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|
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/*
|
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* clear_bit - Clears a bit in memory |
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* @nr: Bit to clear |
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* @addr: Address to start counting from |
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* |
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* clear_bit() is atomic and may not be reordered. However, it does |
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* not contain a memory barrier, so if it is used for locking purposes, |
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* you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() |
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* in order to ensure changes are visible on other processors. |
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*/ |
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extern __inline__ void clear_bit(int nr, volatile void * addr) |
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{ |
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int mask; |
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volatile int *a = addr; |
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__bi_flags; |
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|
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a += nr >> 5; |
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mask = 1 << (nr & 0x1f); |
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__bi_save_and_cli(flags); |
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*a &= ~mask; |
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__bi_restore_flags(flags); |
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} |
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|
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/*
|
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* change_bit - Toggle a bit in memory |
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* @nr: Bit to clear |
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* @addr: Address to start counting from |
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* |
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* change_bit() is atomic and may not be reordered. |
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* Note that @nr may be almost arbitrarily large; this function is not |
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* restricted to acting on a single-word quantity. |
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*/ |
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extern __inline__ void change_bit(int nr, volatile void * addr) |
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{ |
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int mask; |
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volatile int *a = addr; |
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__bi_flags; |
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|
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a += nr >> 5; |
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mask = 1 << (nr & 0x1f); |
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__bi_save_and_cli(flags); |
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*a ^= mask; |
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__bi_restore_flags(flags); |
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} |
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|
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/*
|
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* __change_bit - Toggle a bit in memory |
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* @nr: the bit to set |
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* @addr: the address to start counting from |
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* |
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* Unlike change_bit(), this function is non-atomic and may be reordered. |
||||
* If it's called on the same region of memory simultaneously, the effect |
||||
* may be that only one operation succeeds. |
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*/ |
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extern __inline__ void __change_bit(int nr, volatile void * addr) |
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{ |
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unsigned long * m = ((unsigned long *) addr) + (nr >> 5); |
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|
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*m ^= 1UL << (nr & 31); |
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} |
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|
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/*
|
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* test_and_set_bit - Set a bit and return its old value |
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* @nr: Bit to set |
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* @addr: Address to count from |
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* |
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* This operation is atomic and cannot be reordered.
|
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* It also implies a memory barrier. |
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*/ |
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extern __inline__ int test_and_set_bit(int nr, volatile void * addr) |
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{ |
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int mask, retval; |
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volatile int *a = addr; |
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__bi_flags; |
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|
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a += nr >> 5; |
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mask = 1 << (nr & 0x1f); |
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__bi_save_and_cli(flags); |
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retval = (mask & *a) != 0; |
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*a |= mask; |
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__bi_restore_flags(flags); |
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|
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return retval; |
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} |
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|
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/*
|
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* __test_and_set_bit - Set a bit and return its old value |
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* @nr: Bit to set |
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* @addr: Address to count from |
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* |
||||
* This operation is non-atomic and can be reordered.
|
||||
* If two examples of this operation race, one can appear to succeed |
||||
* but actually fail. You must protect multiple accesses with a lock. |
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*/ |
||||
extern __inline__ int __test_and_set_bit(int nr, volatile void * addr) |
||||
{ |
||||
int mask, retval; |
||||
volatile int *a = addr; |
||||
|
||||
a += nr >> 5; |
||||
mask = 1 << (nr & 0x1f); |
||||
retval = (mask & *a) != 0; |
||||
*a |= mask; |
||||
|
||||
return retval; |
||||
} |
||||
|
||||
/*
|
||||
* test_and_clear_bit - Clear a bit and return its old value |
||||
* @nr: Bit to set |
||||
* @addr: Address to count from |
||||
* |
||||
* This operation is atomic and cannot be reordered.
|
||||
* It also implies a memory barrier. |
||||
*/ |
||||
extern __inline__ int test_and_clear_bit(int nr, volatile void * addr) |
||||
{ |
||||
int mask, retval; |
||||
volatile int *a = addr; |
||||
__bi_flags; |
||||
|
||||
a += nr >> 5; |
||||
mask = 1 << (nr & 0x1f); |
||||
__bi_save_and_cli(flags); |
||||
retval = (mask & *a) != 0; |
||||
*a &= ~mask; |
||||
__bi_restore_flags(flags); |
||||
|
||||
return retval; |
||||
} |
||||
|
||||
/*
|
||||
* __test_and_clear_bit - Clear a bit and return its old value |
||||
* @nr: Bit to set |
||||
* @addr: Address to count from |
||||
* |
||||
* This operation is non-atomic and can be reordered.
|
||||
* If two examples of this operation race, one can appear to succeed |
||||
* but actually fail. You must protect multiple accesses with a lock. |
||||
*/ |
||||
extern __inline__ int __test_and_clear_bit(int nr, volatile void * addr) |
||||
{ |
||||
int mask, retval; |
||||
volatile int *a = addr; |
||||
|
||||
a += nr >> 5; |
||||
mask = 1 << (nr & 0x1f); |
||||
retval = (mask & *a) != 0; |
||||
*a &= ~mask; |
||||
|
||||
return retval; |
||||
} |
||||
|
||||
/*
|
||||
* test_and_change_bit - Change a bit and return its new value |
||||
* @nr: Bit to set |
||||
* @addr: Address to count from |
||||
* |
||||
* This operation is atomic and cannot be reordered.
|
||||
* It also implies a memory barrier. |
||||
*/ |
||||
extern __inline__ int test_and_change_bit(int nr, volatile void * addr) |
||||
{ |
||||
int mask, retval; |
||||
volatile int *a = addr; |
||||
__bi_flags; |
||||
|
||||
a += nr >> 5; |
||||
mask = 1 << (nr & 0x1f); |
||||
__bi_save_and_cli(flags); |
||||
retval = (mask & *a) != 0; |
||||
*a ^= mask; |
||||
__bi_restore_flags(flags); |
||||
|
||||
return retval; |
||||
} |
||||
|
||||
/*
|
||||
* __test_and_change_bit - Change a bit and return its old value |
||||
* @nr: Bit to set |
||||
* @addr: Address to count from |
||||
* |
||||
* This operation is non-atomic and can be reordered.
|
||||
* If two examples of this operation race, one can appear to succeed |
||||
* but actually fail. You must protect multiple accesses with a lock. |
||||
*/ |
||||
extern __inline__ int __test_and_change_bit(int nr, volatile void * addr) |
||||
{ |
||||
int mask, retval; |
||||
volatile int *a = addr; |
||||
|
||||
a += nr >> 5; |
||||
mask = 1 << (nr & 0x1f); |
||||
retval = (mask & *a) != 0; |
||||
*a ^= mask; |
||||
|
||||
return retval; |
||||
} |
||||
|
||||
#undef __bi_flags |
||||
#undef __bi_cli |
||||
#undef __bi_save_flags |
||||
#undef __bi_restore_flags |
||||
|
||||
#endif /* MIPS I */ |
||||
|
||||
/*
|
||||
* test_bit - Determine whether a bit is set |
||||
* @nr: bit number to test |
||||
* @addr: Address to start counting from |
||||
*/ |
||||
extern __inline__ int test_bit(int nr, volatile void *addr) |
||||
{ |
||||
return ((1UL << (nr & 31)) & (((const unsigned int *) addr)[nr >> 5])) != 0; |
||||
} |
||||
|
||||
#ifndef __MIPSEB__ |
||||
|
||||
/* Little endian versions. */ |
||||
|
||||
/*
|
||||
* find_first_zero_bit - find the first zero bit in a memory region |
||||
* @addr: The address to start the search at |
||||
* @size: The maximum size to search |
||||
* |
||||
* Returns the bit-number of the first zero bit, not the number of the byte |
||||
* containing a bit. |
||||
*/ |
||||
extern __inline__ int find_first_zero_bit (void *addr, unsigned size) |
||||
{ |
||||
unsigned long dummy; |
||||
int res; |
||||
|
||||
if (!size) |
||||
return 0; |
||||
|
||||
__asm__ (".set\tnoreorder\n\t" |
||||
".set\tnoat\n" |
||||
"1:\tsubu\t$1,%6,%0\n\t" |
||||
"blez\t$1,2f\n\t" |
||||
"lw\t$1,(%5)\n\t" |
||||
"addiu\t%5,4\n\t" |
||||
#if (_MIPS_ISA == _MIPS_ISA_MIPS2 ) || (_MIPS_ISA == _MIPS_ISA_MIPS3 ) || \ |
||||
(_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5 ) || \
|
||||
(_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64) |
||||
"beql\t%1,$1,1b\n\t" |
||||
"addiu\t%0,32\n\t" |
||||
#else |
||||
"addiu\t%0,32\n\t" |
||||
"beq\t%1,$1,1b\n\t" |
||||
"nop\n\t" |
||||
"subu\t%0,32\n\t" |
||||
#endif |
||||
#ifdef __MIPSEB__ |
||||
#error "Fix this for big endian" |
||||
#endif /* __MIPSEB__ */ |
||||
"li\t%1,1\n" |
||||
"1:\tand\t%2,$1,%1\n\t" |
||||
"beqz\t%2,2f\n\t" |
||||
"sll\t%1,%1,1\n\t" |
||||
"bnez\t%1,1b\n\t" |
||||
"add\t%0,%0,1\n\t" |
||||
".set\tat\n\t" |
||||
".set\treorder\n" |
||||
"2:" |
||||
: "=r" (res), "=r" (dummy), "=r" (addr) |
||||
: "0" ((signed int) 0), "1" ((unsigned int) 0xffffffff), |
||||
"2" (addr), "r" (size) |
||||
: "$1"); |
||||
|
||||
return res; |
||||
} |
||||
|
||||
/*
|
||||
* find_next_zero_bit - find the first zero bit in a memory region |
||||
* @addr: The address to base the search on |
||||
* @offset: The bitnumber to start searching at |
||||
* @size: The maximum size to search |
||||
*/ |
||||
extern __inline__ int find_next_zero_bit (void * addr, int size, int offset) |
||||
{ |
||||
unsigned int *p = ((unsigned int *) addr) + (offset >> 5); |
||||
int set = 0, bit = offset & 31, res; |
||||
unsigned long dummy; |
||||
|
||||
if (bit) { |
||||
/*
|
||||
* Look for zero in first byte |
||||
*/ |
||||
#ifdef __MIPSEB__ |
||||
#error "Fix this for big endian byte order" |
||||
#endif |
||||
__asm__(".set\tnoreorder\n\t" |
||||
".set\tnoat\n" |
||||
"1:\tand\t$1,%4,%1\n\t" |
||||
"beqz\t$1,1f\n\t" |
||||
"sll\t%1,%1,1\n\t" |
||||
"bnez\t%1,1b\n\t" |
||||
"addiu\t%0,1\n\t" |
||||
".set\tat\n\t" |
||||
".set\treorder\n" |
||||
"1:" |
||||
: "=r" (set), "=r" (dummy) |
||||
: "0" (0), "1" (1 << bit), "r" (*p) |
||||
: "$1"); |
||||
if (set < (32 - bit)) |
||||
return set + offset; |
||||
set = 32 - bit; |
||||
p++; |
||||
} |
||||
/*
|
||||
* No zero yet, search remaining full bytes for a zero |
||||
*/ |
||||
res = find_first_zero_bit(p, size - 32 * (p - (unsigned int *) addr)); |
||||
return offset + set + res; |
||||
} |
||||
|
||||
#endif /* !(__MIPSEB__) */ |
||||
|
||||
/*
|
||||
* ffz - find first zero in word. |
||||
* @word: The word to search |
||||
* |
||||
* Undefined if no zero exists, so code should check against ~0UL first. |
||||
*/ |
||||
extern __inline__ unsigned long ffz(unsigned long word) |
||||
{ |
||||
unsigned int __res; |
||||
unsigned int mask = 1; |
||||
|
||||
__asm__ ( |
||||
".set\tnoreorder\n\t" |
||||
".set\tnoat\n\t" |
||||
"move\t%0,$0\n" |
||||
"1:\tand\t$1,%2,%1\n\t" |
||||
"beqz\t$1,2f\n\t" |
||||
"sll\t%1,1\n\t" |
||||
"bnez\t%1,1b\n\t" |
||||
"addiu\t%0,1\n\t" |
||||
".set\tat\n\t" |
||||
".set\treorder\n" |
||||
"2:\n\t" |
||||
: "=&r" (__res), "=r" (mask) |
||||
: "r" (word), "1" (mask) |
||||
: "$1"); |
||||
|
||||
return __res; |
||||
} |
||||
|
||||
#ifdef __KERNEL__ |
||||
|
||||
/**
|
||||
* ffs - find first bit set |
||||
* @x: the word to search |
||||
* |
||||
* This is defined the same way as |
||||
* the libc and compiler builtin ffs routines, therefore |
||||
* differs in spirit from the above ffz (man ffs). |
||||
*/ |
||||
|
||||
#define ffs(x) generic_ffs(x) |
||||
|
||||
/*
|
||||
* hweightN - returns the hamming weight of a N-bit word |
||||
* @x: the word to weigh |
||||
* |
||||
* The Hamming Weight of a number is the total number of bits set in it. |
||||
*/ |
||||
|
||||
#define hweight32(x) generic_hweight32(x) |
||||
#define hweight16(x) generic_hweight16(x) |
||||
#define hweight8(x) generic_hweight8(x) |
||||
|
||||
#endif /* __KERNEL__ */ |
||||
|
||||
#ifdef __MIPSEB__ |
||||
/*
|
||||
* find_next_zero_bit - find the first zero bit in a memory region |
||||
* @addr: The address to base the search on |
||||
* @offset: The bitnumber to start searching at |
||||
* @size: The maximum size to search |
||||
*/ |
||||
extern __inline__ int find_next_zero_bit(void *addr, int size, int offset) |
||||
{ |
||||
unsigned long *p = ((unsigned long *) addr) + (offset >> 5); |
||||
unsigned long result = offset & ~31UL; |
||||
unsigned long tmp; |
||||
|
||||
if (offset >= size) |
||||
return size; |
||||
size -= result; |
||||
offset &= 31UL; |
||||
if (offset) { |
||||
tmp = *(p++); |
||||
tmp |= ~0UL >> (32-offset); |
||||
if (size < 32) |
||||
goto found_first; |
||||
if (~tmp) |
||||
goto found_middle; |
||||
size -= 32; |
||||
result += 32; |
||||
} |
||||
while (size & ~31UL) { |
||||
if (~(tmp = *(p++))) |
||||
goto found_middle; |
||||
result += 32; |
||||
size -= 32; |
||||
} |
||||
if (!size) |
||||
return result; |
||||
tmp = *p; |
||||
|
||||
found_first: |
||||
tmp |= ~0UL << size; |
||||
found_middle: |
||||
return result + ffz(tmp); |
||||
} |
||||
|
||||
/* Linus sez that gcc can optimize the following correctly, we'll see if this
|
||||
* holds on the Sparc as it does for the ALPHA. |
||||
*/ |
||||
|
||||
#if 0 /* Fool kernel-doc since it doesn't do macros yet */
|
||||
/*
|
||||
* find_first_zero_bit - find the first zero bit in a memory region |
||||
* @addr: The address to start the search at |
||||
* @size: The maximum size to search |
||||
* |
||||
* Returns the bit-number of the first zero bit, not the number of the byte |
||||
* containing a bit. |
||||
*/ |
||||
extern int find_first_zero_bit (void *addr, unsigned size); |
||||
#endif |
||||
|
||||
#define find_first_zero_bit(addr, size) \ |
||||
find_next_zero_bit((addr), (size), 0) |
||||
|
||||
#endif /* (__MIPSEB__) */ |
||||
|
||||
/* Now for the ext2 filesystem bit operations and helper routines. */ |
||||
|
||||
#ifdef __MIPSEB__ |
||||
extern __inline__ int ext2_set_bit(int nr, void * addr) |
||||
{ |
||||
int mask, retval, flags; |
||||
unsigned char *ADDR = (unsigned char *) addr; |
||||
|
||||
ADDR += nr >> 3; |
||||
mask = 1 << (nr & 0x07); |
||||
save_and_cli(flags); |
||||
retval = (mask & *ADDR) != 0; |
||||
*ADDR |= mask; |
||||
restore_flags(flags); |
||||
return retval; |
||||
} |
||||
|
||||
extern __inline__ int ext2_clear_bit(int nr, void * addr) |
||||
{ |
||||
int mask, retval, flags; |
||||
unsigned char *ADDR = (unsigned char *) addr; |
||||
|
||||
ADDR += nr >> 3; |
||||
mask = 1 << (nr & 0x07); |
||||
save_and_cli(flags); |
||||
retval = (mask & *ADDR) != 0; |
||||
*ADDR &= ~mask; |
||||
restore_flags(flags); |
||||
return retval; |
||||
} |
||||
|
||||
extern __inline__ int ext2_test_bit(int nr, const void * addr) |
||||
{ |
||||
int mask; |
||||
const unsigned char *ADDR = (const unsigned char *) addr; |
||||
|
||||
ADDR += nr >> 3; |
||||
mask = 1 << (nr & 0x07); |
||||
return ((mask & *ADDR) != 0); |
||||
} |
||||
|
||||
#define ext2_find_first_zero_bit(addr, size) \ |
||||
ext2_find_next_zero_bit((addr), (size), 0) |
||||
|
||||
extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset) |
||||
{ |
||||
unsigned long *p = ((unsigned long *) addr) + (offset >> 5); |
||||
unsigned long result = offset & ~31UL; |
||||
unsigned long tmp; |
||||
|
||||
if (offset >= size) |
||||
return size; |
||||
size -= result; |
||||
offset &= 31UL; |
||||
if(offset) { |
||||
/* We hold the little endian value in tmp, but then the
|
||||
* shift is illegal. So we could keep a big endian value |
||||
* in tmp, like this: |
||||
* |
||||
* tmp = __swab32(*(p++)); |
||||
* tmp |= ~0UL >> (32-offset); |
||||
* |
||||
* but this would decrease preformance, so we change the |
||||
* shift: |
||||
*/ |
||||
tmp = *(p++); |
||||
tmp |= __swab32(~0UL >> (32-offset)); |
||||
if(size < 32) |
||||
goto found_first; |
||||
if(~tmp) |
||||
goto found_middle; |
||||
size -= 32; |
||||
result += 32; |
||||
} |
||||
while(size & ~31UL) { |
||||
if(~(tmp = *(p++))) |
||||
goto found_middle; |
||||
result += 32; |
||||
size -= 32; |
||||
} |
||||
if(!size) |
||||
return result; |
||||
tmp = *p; |
||||
|
||||
found_first: |
||||
/* tmp is little endian, so we would have to swab the shift,
|
||||
* see above. But then we have to swab tmp below for ffz, so |
||||
* we might as well do this here. |
||||
*/ |
||||
return result + ffz(__swab32(tmp) | (~0UL << size)); |
||||
found_middle: |
||||
return result + ffz(__swab32(tmp)); |
||||
} |
||||
#else /* !(__MIPSEB__) */ |
||||
|
||||
/* Native ext2 byte ordering, just collapse using defines. */ |
||||
#define ext2_set_bit(nr, addr) test_and_set_bit((nr), (addr)) |
||||
#define ext2_clear_bit(nr, addr) test_and_clear_bit((nr), (addr)) |
||||
#define ext2_test_bit(nr, addr) test_bit((nr), (addr)) |
||||
#define ext2_find_first_zero_bit(addr, size) find_first_zero_bit((addr), (size)) |
||||
#define ext2_find_next_zero_bit(addr, size, offset) \ |
||||
find_next_zero_bit((addr), (size), (offset)) |
||||
|
||||
#endif /* !(__MIPSEB__) */ |
||||
|
||||
/*
|
||||
* Bitmap functions for the minix filesystem. |
||||
* FIXME: These assume that Minix uses the native byte/bitorder. |
||||
* This limits the Minix filesystem's value for data exchange very much. |
||||
*/ |
||||
#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr) |
||||
#define minix_set_bit(nr,addr) set_bit(nr,addr) |
||||
#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr) |
||||
#define minix_test_bit(nr,addr) test_bit(nr,addr) |
||||
#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) |
||||
|
||||
#endif /* _ASM_BITOPS_H */ |
||||
@ -0,0 +1,31 @@ |
||||
/* $Id: byteorder.h,v 1.8 1998/11/02 09:29:32 ralf Exp $
|
||||
* |
||||
* This file is subject to the terms and conditions of the GNU General Public |
||||
* License. See the file "COPYING" in the main directory of this archive |
||||
* for more details. |
||||
* |
||||
* Copyright (C) by Ralf Baechle |
||||
*/ |
||||
#ifndef _MIPS_BYTEORDER_H |
||||
#define _MIPS_BYTEORDER_H |
||||
|
||||
#include <asm/types.h> |
||||
|
||||
#ifdef __GNUC__ |
||||
|
||||
#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) |
||||
# define __BYTEORDER_HAS_U64__ |
||||
# define __SWAB_64_THRU_32__ |
||||
#endif |
||||
|
||||
#endif /* __GNUC__ */ |
||||
|
||||
#if defined (__MIPSEB__) |
||||
# include <linux/byteorder/big_endian.h> |
||||
#elif defined (__MIPSEL__) |
||||
# include <linux/byteorder/little_endian.h> |
||||
#else |
||||
# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" |
||||
#endif |
||||
|
||||
#endif /* _MIPS_BYTEORDER_H */ |
||||
@ -0,0 +1,24 @@ |
||||
/*
|
||||
* cachectl.h -- defines for MIPS cache control system calls |
||||
* |
||||
* Copyright (C) 1994, 1995, 1996 by Ralf Baechle |
||||
*/ |
||||
#ifndef __ASM_MIPS_CACHECTL |
||||
#define __ASM_MIPS_CACHECTL |
||||
|
||||
/*
|
||||
* Options for cacheflush system call |
||||
*/ |
||||
#define ICACHE (1<<0) /* flush instruction cache */ |
||||
#define DCACHE (1<<1) /* writeback and flush data cache */ |
||||
#define BCACHE (ICACHE|DCACHE) /* flush both caches */ |
||||
|
||||
/*
|
||||
* Caching modes for the cachectl(2) call |
||||
* |
||||
* cachectl(2) is currently not supported and returns ENOSYS. |
||||
*/ |
||||
#define CACHEABLE 0 /* make pages cacheable */ |
||||
#define UNCACHEABLE 1 /* make pages uncacheable */ |
||||
|
||||
#endif /* __ASM_MIPS_CACHECTL */ |
||||
@ -0,0 +1,47 @@ |
||||
/*
|
||||
* Cache operations for the cache instruction. |
||||
* |
||||
* This file is subject to the terms and conditions of the GNU General Public |
||||
* License. See the file "COPYING" in the main directory of this archive |
||||
* for more details. |
||||
* |
||||
* (C) Copyright 1996, 1997 by Ralf Baechle |
||||
*/ |
||||
#ifndef __ASM_MIPS_CACHEOPS_H |
||||
#define __ASM_MIPS_CACHEOPS_H |
||||
|
||||
/*
|
||||
* Cache Operations |
||||
*/ |
||||
#define Index_Invalidate_I 0x00 |
||||
#define Index_Writeback_Inv_D 0x01 |
||||
#define Index_Invalidate_SI 0x02 |
||||
#define Index_Writeback_Inv_SD 0x03 |
||||
#define Index_Load_Tag_I 0x04 |
||||
#define Index_Load_Tag_D 0x05 |
||||
#define Index_Load_Tag_SI 0x06 |
||||
#define Index_Load_Tag_SD 0x07 |
||||
#define Index_Store_Tag_I 0x08 |
||||
#define Index_Store_Tag_D 0x09 |
||||
#define Index_Store_Tag_SI 0x0A |
||||
#define Index_Store_Tag_SD 0x0B |
||||
#define Create_Dirty_Excl_D 0x0d |
||||
#define Create_Dirty_Excl_SD 0x0f |
||||
#define Hit_Invalidate_I 0x10 |
||||
#define Hit_Invalidate_D 0x11 |
||||
#define Hit_Invalidate_SI 0x12 |
||||
#define Hit_Invalidate_SD 0x13 |
||||
#define Fill 0x14 |
||||
#define Hit_Writeback_Inv_D 0x15 |
||||
/* 0x16 is unused */ |
||||
#define Hit_Writeback_Inv_SD 0x17 |
||||
#define Hit_Writeback_I 0x18 |
||||
#define Hit_Writeback_D 0x19 |
||||
/* 0x1a is unused */ |
||||
#define Hit_Writeback_SD 0x1b |
||||
/* 0x1c is unused */ |
||||
/* 0x1e is unused */ |
||||
#define Hit_Set_Virtual_SI 0x1e |
||||
#define Hit_Set_Virtual_SD 0x1f |
||||
|
||||
#endif /* __ASM_MIPS_CACHEOPS_H */ |
||||
@ -0,0 +1,58 @@ |
||||
/*
|
||||
* (C) Copyright 2002-2003 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __ASM_GBL_DATA_H |
||||
#define __ASM_GBL_DATA_H |
||||
|
||||
#include <asm/regdef.h> |
||||
|
||||
/*
|
||||
* The following data structure is placed in some memory wich is |
||||
* available very early after boot (like DPRAM on MPC8xx/MPC82xx, or |
||||
* some locked parts of the data cache) to allow for a minimum set of |
||||
* global variables during system initialization (until we have set |
||||
* up the memory controller so that we can use RAM). |
||||
* |
||||
* Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t) |
||||
*/ |
||||
|
||||
typedef struct global_data { |
||||
bd_t *bd; |
||||
unsigned long flags; |
||||
unsigned long baudrate; |
||||
unsigned long have_console; /* serial_init() was called */ |
||||
unsigned long ram_size; /* RAM size */ |
||||
unsigned long reloc_off; /* Relocation Offset */ |
||||
unsigned long env_addr; /* Address of Environment struct */ |
||||
unsigned long env_valid; /* Checksum of Environment valid? */ |
||||
} gd_t; |
||||
|
||||
/*
|
||||
* Global Data Flags |
||||
*/ |
||||
#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ |
||||
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ |
||||
|
||||
#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("k0") |
||||
|
||||
#endif /* __ASM_GBL_DATA_H */ |
||||
@ -0,0 +1,450 @@ |
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public |
||||
* License. See the file "COPYING" in the main directory of this archive |
||||
* for more details. |
||||
* |
||||
* Copyright (C) 1994, 1995 Waldorf GmbH |
||||
* Copyright (C) 1994 - 2000 Ralf Baechle |
||||
* Copyright (C) 1999, 2000 Silicon Graphics, Inc. |
||||
* Copyright (C) 2000 FSMLabs, Inc. |
||||
*/ |
||||
#ifndef _ASM_IO_H |
||||
#define _ASM_IO_H |
||||
|
||||
#include <linux/config.h> |
||||
#if 0 |
||||
#include <linux/pagemap.h> |
||||
#endif |
||||
#include <asm/addrspace.h> |
||||
#include <asm/byteorder.h> |
||||
|
||||
/*
|
||||
* Slowdown I/O port space accesses for antique hardware. |
||||
*/ |
||||
#undef CONF_SLOWDOWN_IO |
||||
|
||||
/*
|
||||
* Sane hardware offers swapping of I/O space accesses in hardware; less |
||||
* sane hardware forces software to fiddle with this ... |
||||
*/ |
||||
#if defined(CONFIG_SWAP_IO_SPACE) && defined(__MIPSEB__) |
||||
|
||||
#define __ioswab8(x) (x) |
||||
#define __ioswab16(x) swab16(x) |
||||
#define __ioswab32(x) swab32(x) |
||||
|
||||
#else |
||||
|
||||
#define __ioswab8(x) (x) |
||||
#define __ioswab16(x) (x) |
||||
#define __ioswab32(x) (x) |
||||
|
||||
#endif |
||||
|
||||
/*
|
||||
* This file contains the definitions for the MIPS counterpart of the |
||||
* x86 in/out instructions. This heap of macros and C results in much |
||||
* better code than the approach of doing it in plain C. The macros |
||||
* result in code that is to fast for certain hardware. On the other |
||||
* side the performance of the string functions should be improved for |
||||
* sake of certain devices like EIDE disks that do highspeed polled I/O. |
||||
* |
||||
* Ralf |
||||
* |
||||
* This file contains the definitions for the x86 IO instructions |
||||
* inb/inw/inl/outb/outw/outl and the "string versions" of the same |
||||
* (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" |
||||
* versions of the single-IO instructions (inb_p/inw_p/..). |
||||
* |
||||
* This file is not meant to be obfuscating: it's just complicated |
||||
* to (a) handle it all in a way that makes gcc able to optimize it |
||||
* as well as possible and (b) trying to avoid writing the same thing |
||||
* over and over again with slight variations and possibly making a |
||||
* mistake somewhere. |
||||
*/ |
||||
|
||||
/*
|
||||
* On MIPS I/O ports are memory mapped, so we access them using normal |
||||
* load/store instructions. mips_io_port_base is the virtual address to |
||||
* which all ports are being mapped. For sake of efficiency some code |
||||
* assumes that this is an address that can be loaded with a single lui |
||||
* instruction, so the lower 16 bits must be zero. Should be true on |
||||
* on any sane architecture; generic code does not use this assumption. |
||||
*/ |
||||
extern unsigned long mips_io_port_base; |
||||
|
||||
/*
|
||||
* Thanks to James van Artsdalen for a better timing-fix than |
||||
* the two short jumps: using outb's to a nonexistent port seems |
||||
* to guarantee better timings even on fast machines. |
||||
* |
||||
* On the other hand, I'd like to be sure of a non-existent port: |
||||
* I feel a bit unsafe about using 0x80 (should be safe, though) |
||||
* |
||||
* Linus |
||||
* |
||||
*/ |
||||
|
||||
#define __SLOW_DOWN_IO \ |
||||
__asm__ __volatile__( \
|
||||
"sb\t$0,0x80(%0)" \
|
||||
: : "r" (mips_io_port_base)); |
||||
|
||||
#ifdef CONF_SLOWDOWN_IO |
||||
#ifdef REALLY_SLOW_IO |
||||
#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; } |
||||
#else |
||||
#define SLOW_DOWN_IO __SLOW_DOWN_IO |
||||
#endif |
||||
#else |
||||
#define SLOW_DOWN_IO |
||||
#endif |
||||
|
||||
/*
|
||||
* Change virtual addresses to physical addresses and vv. |
||||
* These are trivial on the 1:1 Linux/MIPS mapping |
||||
*/ |
||||
extern inline unsigned long virt_to_phys(volatile void * address) |
||||
{ |
||||
return PHYSADDR(address); |
||||
} |
||||
|
||||
extern inline void * phys_to_virt(unsigned long address) |
||||
{ |
||||
return (void *)KSEG0ADDR(address); |
||||
} |
||||
|
||||
/*
|
||||
* IO bus memory addresses are also 1:1 with the physical address |
||||
*/ |
||||
extern inline unsigned long virt_to_bus(volatile void * address) |
||||
{ |
||||
return PHYSADDR(address); |
||||
} |
||||
|
||||
extern inline void * bus_to_virt(unsigned long address) |
||||
{ |
||||
return (void *)KSEG0ADDR(address); |
||||
} |
||||
|
||||
/*
|
||||
* isa_slot_offset is the address where E(ISA) busaddress 0 is mapped |
||||
* for the processor. |
||||
*/ |
||||
extern unsigned long isa_slot_offset; |
||||
|
||||
extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags); |
||||
|
||||
#if 0 |
||||
extern inline void *ioremap(unsigned long offset, unsigned long size) |
||||
{ |
||||
return __ioremap(offset, size, _CACHE_UNCACHED); |
||||
} |
||||
|
||||
extern inline void *ioremap_nocache(unsigned long offset, unsigned long size) |
||||
{ |
||||
return __ioremap(offset, size, _CACHE_UNCACHED); |
||||
} |
||||
|
||||
extern void iounmap(void *addr); |
||||
#endif |
||||
|
||||
/*
|
||||
* XXX We need system specific versions of these to handle EISA address bits |
||||
* 24-31 on SNI. |
||||
* XXX more SNI hacks. |
||||
*/ |
||||
#define readb(addr) (*(volatile unsigned char *)(addr)) |
||||
#define readw(addr) __ioswab16((*(volatile unsigned short *)(addr))) |
||||
#define readl(addr) __ioswab32((*(volatile unsigned int *)(addr))) |
||||
#define __raw_readb readb |
||||
#define __raw_readw readw |
||||
#define __raw_readl readl |
||||
|
||||
#define writeb(b,addr) (*(volatile unsigned char *)(addr)) = (b) |
||||
#define writew(b,addr) (*(volatile unsigned short *)(addr)) = (__ioswab16(b)) |
||||
#define writel(b,addr) (*(volatile unsigned int *)(addr)) = (__ioswab32(b)) |
||||
#define __raw_writeb writeb |
||||
#define __raw_writew writew |
||||
#define __raw_writel writel |
||||
|
||||
#define memset_io(a,b,c) memset((void *)(a),(b),(c)) |
||||
#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) |
||||
#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) |
||||
|
||||
/* END SNI HACKS ... */ |
||||
|
||||
/*
|
||||
* ISA space is 'always mapped' on currently supported MIPS systems, no need |
||||
* to explicitly ioremap() it. The fact that the ISA IO space is mapped |
||||
* to PAGE_OFFSET is pure coincidence - it does not mean ISA values |
||||
* are physical addresses. The following constant pointer can be |
||||
* used as the IO-area pointer (it can be iounmapped as well, so the |
||||
* analogy with PCI is quite large): |
||||
*/ |
||||
#define __ISA_IO_base ((char *)(PAGE_OFFSET)) |
||||
|
||||
#define isa_readb(a) readb(a) |
||||
#define isa_readw(a) readw(a) |
||||
#define isa_readl(a) readl(a) |
||||
#define isa_writeb(b,a) writeb(b,a) |
||||
#define isa_writew(w,a) writew(w,a) |
||||
#define isa_writel(l,a) writel(l,a) |
||||
|
||||
#define isa_memset_io(a,b,c) memset_io((a),(b),(c)) |
||||
#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),(b),(c)) |
||||
#define isa_memcpy_toio(a,b,c) memcpy_toio((a),(b),(c)) |
||||
|
||||
/*
|
||||
* We don't have csum_partial_copy_fromio() yet, so we cheat here and |
||||
* just copy it. The net code will then do the checksum later. |
||||
*/ |
||||
#define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len)) |
||||
#define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d)) |
||||
|
||||
static inline int check_signature(unsigned long io_addr, |
||||
const unsigned char *signature, int length) |
||||
{ |
||||
int retval = 0; |
||||
do { |
||||
if (readb(io_addr) != *signature) |
||||
goto out; |
||||
io_addr++; |
||||
signature++; |
||||
length--; |
||||
} while (length); |
||||
retval = 1; |
||||
out: |
||||
return retval; |
||||
} |
||||
#define isa_check_signature(io, s, l) check_signature(i,s,l) |
||||
|
||||
/*
|
||||
* Talk about misusing macros.. |
||||
*/ |
||||
|
||||
#define __OUT1(s) \ |
||||
extern inline void __out##s(unsigned int value, unsigned int port) { |
||||
|
||||
#define __OUT2(m) \ |
||||
__asm__ __volatile__ ("s" #m "\t%0,%1(%2)" |
||||
|
||||
#define __OUT(m,s,w) \ |
||||
__OUT1(s) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); } \
|
||||
__OUT1(s##c) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); } \
|
||||
__OUT1(s##_p) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); \
|
||||
SLOW_DOWN_IO; } \
|
||||
__OUT1(s##c_p) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); \
|
||||
SLOW_DOWN_IO; } |
||||
|
||||
#define __IN1(t,s) \ |
||||
extern __inline__ t __in##s(unsigned int port) { t _v; |
||||
|
||||
/*
|
||||
* Required nops will be inserted by the assembler |
||||
*/ |
||||
#define __IN2(m) \ |
||||
__asm__ __volatile__ ("l" #m "\t%0,%1(%2)" |
||||
|
||||
#define __IN(t,m,s,w) \ |
||||
__IN1(t,s) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); return __ioswab##w(_v); } \
|
||||
__IN1(t,s##c) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); return __ioswab##w(_v); } \
|
||||
__IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); SLOW_DOWN_IO; return __ioswab##w(_v); } \
|
||||
__IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); SLOW_DOWN_IO; return __ioswab##w(_v); } |
||||
|
||||
#define __INS1(s) \ |
||||
extern inline void __ins##s(unsigned int port, void * addr, unsigned long count) { |
||||
|
||||
#define __INS2(m) \ |
||||
if (count) \
|
||||
__asm__ __volatile__ ( \
|
||||
".set\tnoreorder\n\t" \
|
||||
".set\tnoat\n" \
|
||||
"1:\tl" #m "\t$1,%4(%5)\n\t" \
|
||||
"subu\t%1,1\n\t" \
|
||||
"s" #m "\t$1,(%0)\n\t" \
|
||||
"bne\t$0,%1,1b\n\t" \
|
||||
"addiu\t%0,%6\n\t" \
|
||||
".set\tat\n\t" \
|
||||
".set\treorder" |
||||
|
||||
#define __INS(m,s,i) \ |
||||
__INS1(s) __INS2(m) \
|
||||
: "=r" (addr), "=r" (count) \
|
||||
: "0" (addr), "1" (count), "i" (0), \
|
||||
"r" (mips_io_port_base+port), "I" (i) \
|
||||
: "$1");} \
|
||||
__INS1(s##c) __INS2(m) \
|
||||
: "=r" (addr), "=r" (count) \
|
||||
: "0" (addr), "1" (count), "ir" (port), \
|
||||
"r" (mips_io_port_base), "I" (i) \
|
||||
: "$1");} |
||||
|
||||
#define __OUTS1(s) \ |
||||
extern inline void __outs##s(unsigned int port, const void * addr, unsigned long count) { |
||||
|
||||
#define __OUTS2(m) \ |
||||
if (count) \
|
||||
__asm__ __volatile__ ( \
|
||||
".set\tnoreorder\n\t" \
|
||||
".set\tnoat\n" \
|
||||
"1:\tl" #m "\t$1,(%0)\n\t" \
|
||||
"subu\t%1,1\n\t" \
|
||||
"s" #m "\t$1,%4(%5)\n\t" \
|
||||
"bne\t$0,%1,1b\n\t" \
|
||||
"addiu\t%0,%6\n\t" \
|
||||
".set\tat\n\t" \
|
||||
".set\treorder" |
||||
|
||||
#define __OUTS(m,s,i) \ |
||||
__OUTS1(s) __OUTS2(m) \
|
||||
: "=r" (addr), "=r" (count) \
|
||||
: "0" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), "I" (i) \
|
||||
: "$1");} \
|
||||
__OUTS1(s##c) __OUTS2(m) \
|
||||
: "=r" (addr), "=r" (count) \
|
||||
: "0" (addr), "1" (count), "ir" (port), "r" (mips_io_port_base), "I" (i) \
|
||||
: "$1");} |
||||
|
||||
__IN(unsigned char,b,b,8) |
||||
__IN(unsigned short,h,w,16) |
||||
__IN(unsigned int,w,l,32) |
||||
|
||||
__OUT(b,b,8) |
||||
__OUT(h,w,16) |
||||
__OUT(w,l,32) |
||||
|
||||
__INS(b,b,1) |
||||
__INS(h,w,2) |
||||
__INS(w,l,4) |
||||
|
||||
__OUTS(b,b,1) |
||||
__OUTS(h,w,2) |
||||
__OUTS(w,l,4) |
||||
|
||||
|
||||
/*
|
||||
* Note that due to the way __builtin_constant_p() works, you |
||||
* - can't use it inside an inline function (it will never be true) |
||||
* - you don't have to worry about side effects within the __builtin.. |
||||
*/ |
||||
#define outb(val,port) \ |
||||
((__builtin_constant_p((port)) && (port) < 32768) ? \
|
||||
__outbc((val),(port)) : \
|
||||
__outb((val),(port))) |
||||
|
||||
#define inb(port) \ |
||||
((__builtin_constant_p((port)) && (port) < 32768) ? \
|
||||
__inbc(port) : \
|
||||
__inb(port)) |
||||
|
||||
#define outb_p(val,port) \ |
||||
((__builtin_constant_p((port)) && (port) < 32768) ? \
|
||||
__outbc_p((val),(port)) : \
|
||||
__outb_p((val),(port))) |
||||
|
||||
#define inb_p(port) \ |
||||
((__builtin_constant_p((port)) && (port) < 32768) ? \
|
||||
__inbc_p(port) : \
|
||||
__inb_p(port)) |
||||
|
||||
#define outw(val,port) \ |
||||
((__builtin_constant_p((port)) && (port) < 32768) ? \
|
||||
__outwc((val),(port)) : \
|
||||
__outw((val),(port))) |
||||
|
||||
#define inw(port) \ |
||||
((__builtin_constant_p((port)) && (port) < 32768) ? \
|
||||
__inwc(port) : \
|
||||
__inw(port)) |
||||
|
||||
#define outw_p(val,port) \ |
||||
((__builtin_constant_p((port)) && (port) < 32768) ? \
|
||||
__outwc_p((val),(port)) : \
|
||||
__outw_p((val),(port))) |
||||
|
||||
#define inw_p(port) \ |
||||
((__builtin_constant_p((port)) && (port) < 32768) ? \
|
||||
__inwc_p(port) : \
|
||||
__inw_p(port)) |
||||
|
||||
#define outl(val,port) \ |
||||
((__builtin_constant_p((port)) && (port) < 32768) ? \
|
||||
__outlc((val),(port)) : \
|
||||
__outl((val),(port))) |
||||
|
||||
#define inl(port) \ |
||||
((__builtin_constant_p((port)) && (port) < 32768) ? \
|
||||
__inlc(port) : \
|
||||
__inl(port)) |
||||
|
||||
#define outl_p(val,port) \ |
||||
((__builtin_constant_p((port)) && (port) < 32768) ? \
|
||||
__outlc_p((val),(port)) : \
|
||||
__outl_p((val),(port))) |
||||
|
||||
#define inl_p(port) \ |
||||
((__builtin_constant_p((port)) && (port) < 32768) ? \
|
||||
__inlc_p(port) : \
|
||||
__inl_p(port)) |
||||
|
||||
|
||||
#define outsb(port,addr,count) \ |
||||
((__builtin_constant_p((port)) && (port) < 32768) ? \
|
||||
__outsbc((port),(addr),(count)) : \
|
||||
__outsb ((port),(addr),(count))) |
||||
|
||||
#define insb(port,addr,count) \ |
||||
((__builtin_constant_p((port)) && (port) < 32768) ? \
|
||||
__insbc((port),(addr),(count)) : \
|
||||
__insb((port),(addr),(count))) |
||||
|
||||
#define outsw(port,addr,count) \ |
||||
((__builtin_constant_p((port)) && (port) < 32768) ? \
|
||||
__outswc((port),(addr),(count)) : \
|
||||
__outsw ((port),(addr),(count))) |
||||
|
||||
#define insw(port,addr,count) \ |
||||
((__builtin_constant_p((port)) && (port) < 32768) ? \
|
||||
__inswc((port),(addr),(count)) : \
|
||||
__insw((port),(addr),(count))) |
||||
|
||||
#define outsl(port,addr,count) \ |
||||
((__builtin_constant_p((port)) && (port) < 32768) ? \
|
||||
__outslc((port),(addr),(count)) : \
|
||||
__outsl ((port),(addr),(count))) |
||||
|
||||
#define insl(port,addr,count) \ |
||||
((__builtin_constant_p((port)) && (port) < 32768) ? \
|
||||
__inslc((port),(addr),(count)) : \
|
||||
__insl((port),(addr),(count))) |
||||
|
||||
#define IO_SPACE_LIMIT 0xffff |
||||
|
||||
/*
|
||||
* The caches on some architectures aren't dma-coherent and have need to |
||||
* handle this in software. There are three types of operations that |
||||
* can be applied to dma buffers. |
||||
* |
||||
* - dma_cache_wback_inv(start, size) makes caches and coherent by |
||||
* writing the content of the caches back to memory, if necessary. |
||||
* The function also invalidates the affected part of the caches as |
||||
* necessary before DMA transfers from outside to memory. |
||||
* - dma_cache_wback(start, size) makes caches and coherent by |
||||
* writing the content of the caches back to memory, if necessary. |
||||
* The function also invalidates the affected part of the caches as |
||||
* necessary before DMA transfers from outside to memory. |
||||
* - dma_cache_inv(start, size) invalidates the affected parts of the |
||||
* caches. Dirty lines of the caches may be written back or simply |
||||
* be discarded. This operation is necessary before dma operations |
||||
* to the memory. |
||||
*/ |
||||
extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); |
||||
extern void (*_dma_cache_wback)(unsigned long start, unsigned long size); |
||||
extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); |
||||
|
||||
#define dma_cache_wback_inv(start,size) _dma_cache_wback_inv(start,size) |
||||
#define dma_cache_wback(start,size) _dma_cache_wback(start,size) |
||||
#define dma_cache_inv(start,size) _dma_cache_inv(start,size) |
||||
|
||||
#endif /* _ASM_IO_H */ |
||||
@ -0,0 +1,35 @@ |
||||
/*
|
||||
* Various ISA level dependant constants. |
||||
* Most of the following constants reflect the different layout |
||||
* of Coprocessor 0 registers. |
||||
* |
||||
* Copyright (c) 1998 Harald Koerfgen |
||||
*/ |
||||
#include <linux/config.h> |
||||
|
||||
#ifndef __ASM_ISADEP_H |
||||
#define __ASM_ISADEP_H |
||||
|
||||
#if defined(CONFIG_CPU_R3000) |
||||
/*
|
||||
* R2000 or R3000 |
||||
*/ |
||||
|
||||
/*
|
||||
* kernel or user mode? (CP0_STATUS) |
||||
*/ |
||||
#define KU_MASK 0x08 |
||||
#define KU_USER 0x08 |
||||
#define KU_KERN 0x00 |
||||
|
||||
#else |
||||
/*
|
||||
* kernel or user mode? |
||||
*/ |
||||
#define KU_MASK 0x18 |
||||
#define KU_USER 0x10 |
||||
#define KU_KERN 0x00 |
||||
|
||||
#endif |
||||
|
||||
#endif /* __ASM_ISADEP_H */ |
||||
@ -0,0 +1,540 @@ |
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public |
||||
* License. See the file "COPYING" in the main directory of this archive |
||||
* for more details. |
||||
* |
||||
* Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle |
||||
* Copyright (C) 2000 Silicon Graphics, Inc. |
||||
* Modified for further R[236]000 support by Paul M. Antoine, 1996. |
||||
* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com |
||||
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. |
||||
*/ |
||||
#ifndef _ASM_MIPSREGS_H |
||||
#define _ASM_MIPSREGS_H |
||||
|
||||
#if 0 |
||||
#include <linux/linkage.h> |
||||
#endif |
||||
|
||||
/*
|
||||
* The following macros are especially useful for __asm__ |
||||
* inline assembler. |
||||
*/ |
||||
#ifndef __STR |
||||
#define __STR(x) #x |
||||
#endif |
||||
#ifndef STR |
||||
#define STR(x) __STR(x) |
||||
#endif |
||||
|
||||
/*
|
||||
* Coprocessor 0 register names |
||||
*/ |
||||
#define CP0_INDEX $0 |
||||
#define CP0_RANDOM $1 |
||||
#define CP0_ENTRYLO0 $2 |
||||
#define CP0_ENTRYLO1 $3 |
||||
#define CP0_CONF $3 |
||||
#define CP0_CONTEXT $4 |
||||
#define CP0_PAGEMASK $5 |
||||
#define CP0_WIRED $6 |
||||
#define CP0_INFO $7 |
||||
#define CP0_BADVADDR $8 |
||||
#define CP0_COUNT $9 |
||||
#define CP0_ENTRYHI $10 |
||||
#define CP0_COMPARE $11 |
||||
#define CP0_STATUS $12 |
||||
#define CP0_CAUSE $13 |
||||
#define CP0_EPC $14 |
||||
#define CP0_PRID $15 |
||||
#define CP0_CONFIG $16 |
||||
#define CP0_LLADDR $17 |
||||
#define CP0_WATCHLO $18 |
||||
#define CP0_WATCHHI $19 |
||||
#define CP0_XCONTEXT $20 |
||||
#define CP0_FRAMEMASK $21 |
||||
#define CP0_DIAGNOSTIC $22 |
||||
#define CP0_PERFORMANCE $25 |
||||
#define CP0_ECC $26 |
||||
#define CP0_CACHEERR $27 |
||||
#define CP0_TAGLO $28 |
||||
#define CP0_TAGHI $29 |
||||
#define CP0_ERROREPC $30 |
||||
|
||||
/*
|
||||
* R4640/R4650 cp0 register names. These registers are listed |
||||
* here only for completeness; without MMU these CPUs are not useable |
||||
* by Linux. A future ELKS port might take make Linux run on them |
||||
* though ... |
||||
*/ |
||||
#define CP0_IBASE $0 |
||||
#define CP0_IBOUND $1 |
||||
#define CP0_DBASE $2 |
||||
#define CP0_DBOUND $3 |
||||
#define CP0_CALG $17 |
||||
#define CP0_IWATCH $18 |
||||
#define CP0_DWATCH $19 |
||||
|
||||
/*
|
||||
* Coprocessor 0 Set 1 register names |
||||
*/ |
||||
#define CP0_S1_DERRADDR0 $26 |
||||
#define CP0_S1_DERRADDR1 $27 |
||||
#define CP0_S1_INTCONTROL $20 |
||||
/*
|
||||
* Coprocessor 1 (FPU) register names |
||||
*/ |
||||
#define CP1_REVISION $0 |
||||
#define CP1_STATUS $31 |
||||
|
||||
/*
|
||||
* FPU Status Register Values |
||||
*/ |
||||
/*
|
||||
* Status Register Values |
||||
*/ |
||||
|
||||
#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ |
||||
#define FPU_CSR_COND 0x00800000 /* $fcc0 */ |
||||
#define FPU_CSR_COND0 0x00800000 /* $fcc0 */ |
||||
#define FPU_CSR_COND1 0x02000000 /* $fcc1 */ |
||||
#define FPU_CSR_COND2 0x04000000 /* $fcc2 */ |
||||
#define FPU_CSR_COND3 0x08000000 /* $fcc3 */ |
||||
#define FPU_CSR_COND4 0x10000000 /* $fcc4 */ |
||||
#define FPU_CSR_COND5 0x20000000 /* $fcc5 */ |
||||
#define FPU_CSR_COND6 0x40000000 /* $fcc6 */ |
||||
#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ |
||||
|
||||
/*
|
||||
* X the exception cause indicator |
||||
* E the exception enable |
||||
* S the sticky/flag bit |
||||
*/ |
||||
#define FPU_CSR_ALL_X 0x0003f000 |
||||
#define FPU_CSR_UNI_X 0x00020000 |
||||
#define FPU_CSR_INV_X 0x00010000 |
||||
#define FPU_CSR_DIV_X 0x00008000 |
||||
#define FPU_CSR_OVF_X 0x00004000 |
||||
#define FPU_CSR_UDF_X 0x00002000 |
||||
#define FPU_CSR_INE_X 0x00001000 |
||||
|
||||
#define FPU_CSR_ALL_E 0x00000f80 |
||||
#define FPU_CSR_INV_E 0x00000800 |
||||
#define FPU_CSR_DIV_E 0x00000400 |
||||
#define FPU_CSR_OVF_E 0x00000200 |
||||
#define FPU_CSR_UDF_E 0x00000100 |
||||
#define FPU_CSR_INE_E 0x00000080 |
||||
|
||||
#define FPU_CSR_ALL_S 0x0000007c |
||||
#define FPU_CSR_INV_S 0x00000040 |
||||
#define FPU_CSR_DIV_S 0x00000020 |
||||
#define FPU_CSR_OVF_S 0x00000010 |
||||
#define FPU_CSR_UDF_S 0x00000008 |
||||
#define FPU_CSR_INE_S 0x00000004 |
||||
|
||||
/* rounding mode */ |
||||
#define FPU_CSR_RN 0x0 /* nearest */ |
||||
#define FPU_CSR_RZ 0x1 /* towards zero */ |
||||
#define FPU_CSR_RU 0x2 /* towards +Infinity */ |
||||
#define FPU_CSR_RD 0x3 /* towards -Infinity */ |
||||
|
||||
|
||||
/*
|
||||
* Values for PageMask register |
||||
*/ |
||||
#include <linux/config.h> |
||||
#ifdef CONFIG_CPU_VR41XX |
||||
#define PM_1K 0x00000000 |
||||
#define PM_4K 0x00001800 |
||||
#define PM_16K 0x00007800 |
||||
#define PM_64K 0x0001f800 |
||||
#define PM_256K 0x0007f800 |
||||
#else |
||||
#define PM_4K 0x00000000 |
||||
#define PM_16K 0x00006000 |
||||
#define PM_64K 0x0001e000 |
||||
#define PM_256K 0x0007e000 |
||||
#define PM_1M 0x001fe000 |
||||
#define PM_4M 0x007fe000 |
||||
#define PM_16M 0x01ffe000 |
||||
#endif |
||||
|
||||
/*
|
||||
* Values used for computation of new tlb entries |
||||
*/ |
||||
#define PL_4K 12 |
||||
#define PL_16K 14 |
||||
#define PL_64K 16 |
||||
#define PL_256K 18 |
||||
#define PL_1M 20 |
||||
#define PL_4M 22 |
||||
#define PL_16M 24 |
||||
|
||||
/*
|
||||
* Macros to access the system control coprocessor |
||||
*/ |
||||
#define read_32bit_cp0_register(source) \ |
||||
({ int __res; \
|
||||
__asm__ __volatile__( \
|
||||
".set\tpush\n\t" \
|
||||
".set\treorder\n\t" \
|
||||
"mfc0\t%0,"STR(source)"\n\t" \
|
||||
".set\tpop" \
|
||||
: "=r" (__res)); \
|
||||
__res;}) |
||||
|
||||
#define read_32bit_cp0_set1_register(source) \ |
||||
({ int __res; \
|
||||
__asm__ __volatile__( \
|
||||
".set\tpush\n\t" \
|
||||
".set\treorder\n\t" \
|
||||
"cfc0\t%0,"STR(source)"\n\t" \
|
||||
".set\tpop" \
|
||||
: "=r" (__res)); \
|
||||
__res;}) |
||||
|
||||
/*
|
||||
* For now use this only with interrupts disabled! |
||||
*/ |
||||
#define read_64bit_cp0_register(source) \ |
||||
({ int __res; \
|
||||
__asm__ __volatile__( \
|
||||
".set\tmips3\n\t" \
|
||||
"dmfc0\t%0,"STR(source)"\n\t" \
|
||||
".set\tmips0" \
|
||||
: "=r" (__res)); \
|
||||
__res;}) |
||||
|
||||
#define write_32bit_cp0_register(register,value) \ |
||||
__asm__ __volatile__( \
|
||||
"mtc0\t%0,"STR(register)"\n\t" \
|
||||
"nop" \
|
||||
: : "r" (value)); |
||||
|
||||
#define write_32bit_cp0_set1_register(register,value) \ |
||||
__asm__ __volatile__( \
|
||||
"ctc0\t%0,"STR(register)"\n\t" \
|
||||
"nop" \
|
||||
: : "r" (value)); |
||||
|
||||
#define write_64bit_cp0_register(register,value) \ |
||||
__asm__ __volatile__( \
|
||||
".set\tmips3\n\t" \
|
||||
"dmtc0\t%0,"STR(register)"\n\t" \
|
||||
".set\tmips0" \
|
||||
: : "r" (value)) |
||||
|
||||
/*
|
||||
* This should be changed when we get a compiler that support the MIPS32 ISA.
|
||||
*/ |
||||
#define read_mips32_cp0_config1() \ |
||||
({ int __res; \
|
||||
__asm__ __volatile__( \
|
||||
".set\tnoreorder\n\t" \
|
||||
".set\tnoat\n\t" \
|
||||
".word\t0x40018001\n\t" \
|
||||
"move\t%0,$1\n\t" \
|
||||
".set\tat\n\t" \
|
||||
".set\treorder" \
|
||||
:"=r" (__res)); \
|
||||
__res;}) |
||||
|
||||
/*
|
||||
* R4x00 interrupt enable / cause bits |
||||
*/ |
||||
#define IE_SW0 (1<< 8) |
||||
#define IE_SW1 (1<< 9) |
||||
#define IE_IRQ0 (1<<10) |
||||
#define IE_IRQ1 (1<<11) |
||||
#define IE_IRQ2 (1<<12) |
||||
#define IE_IRQ3 (1<<13) |
||||
#define IE_IRQ4 (1<<14) |
||||
#define IE_IRQ5 (1<<15) |
||||
|
||||
/*
|
||||
* R4x00 interrupt cause bits |
||||
*/ |
||||
#define C_SW0 (1<< 8) |
||||
#define C_SW1 (1<< 9) |
||||
#define C_IRQ0 (1<<10) |
||||
#define C_IRQ1 (1<<11) |
||||
#define C_IRQ2 (1<<12) |
||||
#define C_IRQ3 (1<<13) |
||||
#define C_IRQ4 (1<<14) |
||||
#define C_IRQ5 (1<<15) |
||||
|
||||
#ifndef _LANGUAGE_ASSEMBLY |
||||
/*
|
||||
* Manipulate the status register. |
||||
* Mostly used to access the interrupt bits. |
||||
*/ |
||||
#define __BUILD_SET_CP0(name,register) \ |
||||
extern __inline__ unsigned int \
|
||||
set_cp0_##name(unsigned int set) \
|
||||
{ \
|
||||
unsigned int res; \
|
||||
\
|
||||
res = read_32bit_cp0_register(register); \
|
||||
res |= set; \
|
||||
write_32bit_cp0_register(register, res); \
|
||||
\
|
||||
return res; \
|
||||
} \
|
||||
\
|
||||
extern __inline__ unsigned int \
|
||||
clear_cp0_##name(unsigned int clear) \
|
||||
{ \
|
||||
unsigned int res; \
|
||||
\
|
||||
res = read_32bit_cp0_register(register); \
|
||||
res &= ~clear; \
|
||||
write_32bit_cp0_register(register, res); \
|
||||
\
|
||||
return res; \
|
||||
} \
|
||||
\
|
||||
extern __inline__ unsigned int \
|
||||
change_cp0_##name(unsigned int change, unsigned int new) \
|
||||
{ \
|
||||
unsigned int res; \
|
||||
\
|
||||
res = read_32bit_cp0_register(register); \
|
||||
res &= ~change; \
|
||||
res |= (new & change); \
|
||||
if(change) \
|
||||
write_32bit_cp0_register(register, res); \
|
||||
\
|
||||
return res; \
|
||||
} |
||||
|
||||
__BUILD_SET_CP0(status,CP0_STATUS) |
||||
__BUILD_SET_CP0(cause,CP0_CAUSE) |
||||
__BUILD_SET_CP0(config,CP0_CONFIG) |
||||
|
||||
#endif /* defined (_LANGUAGE_ASSEMBLY) */ |
||||
|
||||
/*
|
||||
* Bitfields in the R4xx0 cp0 status register |
||||
*/ |
||||
#define ST0_IE 0x00000001 |
||||
#define ST0_EXL 0x00000002 |
||||
#define ST0_ERL 0x00000004 |
||||
#define ST0_KSU 0x00000018 |
||||
# define KSU_USER 0x00000010 |
||||
# define KSU_SUPERVISOR 0x00000008 |
||||
# define KSU_KERNEL 0x00000000 |
||||
#define ST0_UX 0x00000020 |
||||
#define ST0_SX 0x00000040 |
||||
#define ST0_KX 0x00000080 |
||||
#define ST0_DE 0x00010000 |
||||
#define ST0_CE 0x00020000 |
||||
|
||||
/*
|
||||
* Bitfields in the R[23]000 cp0 status register. |
||||
*/ |
||||
#define ST0_IEC 0x00000001 |
||||
#define ST0_KUC 0x00000002 |
||||
#define ST0_IEP 0x00000004 |
||||
#define ST0_KUP 0x00000008 |
||||
#define ST0_IEO 0x00000010 |
||||
#define ST0_KUO 0x00000020 |
||||
/* bits 6 & 7 are reserved on R[23]000 */ |
||||
#define ST0_ISC 0x00010000 |
||||
#define ST0_SWC 0x00020000 |
||||
#define ST0_CM 0x00080000 |
||||
|
||||
/*
|
||||
* Bits specific to the R4640/R4650 |
||||
*/ |
||||
#define ST0_UM (1 << 4) |
||||
#define ST0_IL (1 << 23) |
||||
#define ST0_DL (1 << 24) |
||||
|
||||
/*
|
||||
* Bitfields in the TX39 family CP0 Configuration Register 3 |
||||
*/ |
||||
#define TX39_CONF_ICS_SHIFT 19 |
||||
#define TX39_CONF_ICS_MASK 0x00380000 |
||||
#define TX39_CONF_ICS_1KB 0x00000000 |
||||
#define TX39_CONF_ICS_2KB 0x00080000 |
||||
#define TX39_CONF_ICS_4KB 0x00100000 |
||||
#define TX39_CONF_ICS_8KB 0x00180000 |
||||
#define TX39_CONF_ICS_16KB 0x00200000 |
||||
|
||||
#define TX39_CONF_DCS_SHIFT 16 |
||||
#define TX39_CONF_DCS_MASK 0x00070000 |
||||
#define TX39_CONF_DCS_1KB 0x00000000 |
||||
#define TX39_CONF_DCS_2KB 0x00010000 |
||||
#define TX39_CONF_DCS_4KB 0x00020000 |
||||
#define TX39_CONF_DCS_8KB 0x00030000 |
||||
#define TX39_CONF_DCS_16KB 0x00040000 |
||||
|
||||
#define TX39_CONF_CWFON 0x00004000 |
||||
#define TX39_CONF_WBON 0x00002000 |
||||
#define TX39_CONF_RF_SHIFT 10 |
||||
#define TX39_CONF_RF_MASK 0x00000c00 |
||||
#define TX39_CONF_DOZE 0x00000200 |
||||
#define TX39_CONF_HALT 0x00000100 |
||||
#define TX39_CONF_LOCK 0x00000080 |
||||
#define TX39_CONF_ICE 0x00000020 |
||||
#define TX39_CONF_DCE 0x00000010 |
||||
#define TX39_CONF_IRSIZE_SHIFT 2 |
||||
#define TX39_CONF_IRSIZE_MASK 0x0000000c |
||||
#define TX39_CONF_DRSIZE_SHIFT 0 |
||||
#define TX39_CONF_DRSIZE_MASK 0x00000003 |
||||
|
||||
/*
|
||||
* Status register bits available in all MIPS CPUs. |
||||
*/ |
||||
#define ST0_IM 0x0000ff00 |
||||
#define STATUSB_IP0 8 |
||||
#define STATUSF_IP0 (1 << 8) |
||||
#define STATUSB_IP1 9 |
||||
#define STATUSF_IP1 (1 << 9) |
||||
#define STATUSB_IP2 10 |
||||
#define STATUSF_IP2 (1 << 10) |
||||
#define STATUSB_IP3 11 |
||||
#define STATUSF_IP3 (1 << 11) |
||||
#define STATUSB_IP4 12 |
||||
#define STATUSF_IP4 (1 << 12) |
||||
#define STATUSB_IP5 13 |
||||
#define STATUSF_IP5 (1 << 13) |
||||
#define STATUSB_IP6 14 |
||||
#define STATUSF_IP6 (1 << 14) |
||||
#define STATUSB_IP7 15 |
||||
#define STATUSF_IP7 (1 << 15) |
||||
#define STATUSB_IP8 0 |
||||
#define STATUSF_IP8 (1 << 0) |
||||
#define STATUSB_IP9 1 |
||||
#define STATUSF_IP9 (1 << 1) |
||||
#define STATUSB_IP10 2 |
||||
#define STATUSF_IP10 (1 << 2) |
||||
#define STATUSB_IP11 3 |
||||
#define STATUSF_IP11 (1 << 3) |
||||
#define STATUSB_IP12 4 |
||||
#define STATUSF_IP12 (1 << 4) |
||||
#define STATUSB_IP13 5 |
||||
#define STATUSF_IP13 (1 << 5) |
||||
#define STATUSB_IP14 6 |
||||
#define STATUSF_IP14 (1 << 6) |
||||
#define STATUSB_IP15 7 |
||||
#define STATUSF_IP15 (1 << 7) |
||||
#define ST0_CH 0x00040000 |
||||
#define ST0_SR 0x00100000 |
||||
#define ST0_BEV 0x00400000 |
||||
#define ST0_RE 0x02000000 |
||||
#define ST0_FR 0x04000000 |
||||
#define ST0_CU 0xf0000000 |
||||
#define ST0_CU0 0x10000000 |
||||
#define ST0_CU1 0x20000000 |
||||
#define ST0_CU2 0x40000000 |
||||
#define ST0_CU3 0x80000000 |
||||
#define ST0_XX 0x80000000 /* MIPS IV naming */ |
||||
|
||||
/*
|
||||
* Bitfields and bit numbers in the coprocessor 0 cause register. |
||||
* |
||||
* Refer to your MIPS R4xx0 manual, chapter 5 for explanation. |
||||
*/ |
||||
#define CAUSEB_EXCCODE 2 |
||||
#define CAUSEF_EXCCODE (31 << 2) |
||||
#define CAUSEB_IP 8 |
||||
#define CAUSEF_IP (255 << 8) |
||||
#define CAUSEB_IP0 8 |
||||
#define CAUSEF_IP0 (1 << 8) |
||||
#define CAUSEB_IP1 9 |
||||
#define CAUSEF_IP1 (1 << 9) |
||||
#define CAUSEB_IP2 10 |
||||
#define CAUSEF_IP2 (1 << 10) |
||||
#define CAUSEB_IP3 11 |
||||
#define CAUSEF_IP3 (1 << 11) |
||||
#define CAUSEB_IP4 12 |
||||
#define CAUSEF_IP4 (1 << 12) |
||||
#define CAUSEB_IP5 13 |
||||
#define CAUSEF_IP5 (1 << 13) |
||||
#define CAUSEB_IP6 14 |
||||
#define CAUSEF_IP6 (1 << 14) |
||||
#define CAUSEB_IP7 15 |
||||
#define CAUSEF_IP7 (1 << 15) |
||||
#define CAUSEB_IV 23 |
||||
#define CAUSEF_IV (1 << 23) |
||||
#define CAUSEB_CE 28 |
||||
#define CAUSEF_CE (3 << 28) |
||||
#define CAUSEB_BD 31 |
||||
#define CAUSEF_BD (1 << 31) |
||||
|
||||
/*
|
||||
* Bits in the coprozessor 0 config register. |
||||
*/ |
||||
#define CONF_CM_CACHABLE_NO_WA 0 |
||||
#define CONF_CM_CACHABLE_WA 1 |
||||
#define CONF_CM_UNCACHED 2 |
||||
#define CONF_CM_CACHABLE_NONCOHERENT 3 |
||||
#define CONF_CM_CACHABLE_CE 4 |
||||
#define CONF_CM_CACHABLE_COW 5 |
||||
#define CONF_CM_CACHABLE_CUW 6 |
||||
#define CONF_CM_CACHABLE_ACCELERATED 7 |
||||
#define CONF_CM_CMASK 7 |
||||
#define CONF_DB (1 << 4) |
||||
#define CONF_IB (1 << 5) |
||||
#define CONF_SC (1 << 17) |
||||
#define CONF_AC (1 << 23) |
||||
#define CONF_HALT (1 << 25) |
||||
|
||||
/*
|
||||
* R10000 performance counter definitions. |
||||
* |
||||
* FIXME: The R10000 performance counter opens a nice way to implement CPU |
||||
* time accounting with a precission of one cycle. I don't have |
||||
* R10000 silicon but just a manual, so ... |
||||
*/ |
||||
|
||||
/*
|
||||
* Events counted by counter #0 |
||||
*/ |
||||
#define CE0_CYCLES 0 |
||||
#define CE0_INSN_ISSUED 1 |
||||
#define CE0_LPSC_ISSUED 2 |
||||
#define CE0_S_ISSUED 3 |
||||
#define CE0_SC_ISSUED 4 |
||||
#define CE0_SC_FAILED 5 |
||||
#define CE0_BRANCH_DECODED 6 |
||||
#define CE0_QW_WB_SECONDARY 7 |
||||
#define CE0_CORRECTED_ECC_ERRORS 8 |
||||
#define CE0_ICACHE_MISSES 9 |
||||
#define CE0_SCACHE_I_MISSES 10 |
||||
#define CE0_SCACHE_I_WAY_MISSPREDICTED 11 |
||||
#define CE0_EXT_INTERVENTIONS_REQ 12 |
||||
#define CE0_EXT_INVALIDATE_REQ 13 |
||||
#define CE0_VIRTUAL_COHERENCY_COND 14 |
||||
#define CE0_INSN_GRADUATED 15 |
||||
|
||||
/*
|
||||
* Events counted by counter #1 |
||||
*/ |
||||
#define CE1_CYCLES 0 |
||||
#define CE1_INSN_GRADUATED 1 |
||||
#define CE1_LPSC_GRADUATED 2 |
||||
#define CE1_S_GRADUATED 3 |
||||
#define CE1_SC_GRADUATED 4 |
||||
#define CE1_FP_INSN_GRADUATED 5 |
||||
#define CE1_QW_WB_PRIMARY 6 |
||||
#define CE1_TLB_REFILL 7 |
||||
#define CE1_BRANCH_MISSPREDICTED 8 |
||||
#define CE1_DCACHE_MISS 9 |
||||
#define CE1_SCACHE_D_MISSES 10 |
||||
#define CE1_SCACHE_D_WAY_MISSPREDICTED 11 |
||||
#define CE1_EXT_INTERVENTION_HITS 12 |
||||
#define CE1_EXT_INVALIDATE_REQ 13 |
||||
#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 |
||||
#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 |
||||
|
||||
/*
|
||||
* These flags define in which priviledge mode the counters count events |
||||
*/ |
||||
#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ |
||||
#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ |
||||
#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ |
||||
#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ |
||||
|
||||
#endif /* _ASM_MIPSREGS_H */ |
||||
@ -0,0 +1,123 @@ |
||||
/* $Id: posix_types.h,v 1.6 2000/02/04 23:32:54 ralf Exp $
|
||||
* |
||||
* This file is subject to the terms and conditions of the GNU General Public |
||||
* License. See the file "COPYING" in the main directory of this archive |
||||
* for more details. |
||||
* |
||||
* Copyright (C) 1996, 1997, 1998, 2000 by Ralf Baechle |
||||
*/ |
||||
#ifndef _ASM_POSIX_TYPES_H |
||||
#define _ASM_POSIX_TYPES_H |
||||
|
||||
/*
|
||||
* This file is generally used by user-level software, so you need to |
||||
* be a little careful about namespace pollution etc. Also, we cannot |
||||
* assume GCC is being used. |
||||
*/ |
||||
|
||||
typedef unsigned int __kernel_dev_t; |
||||
typedef unsigned long __kernel_ino_t; |
||||
typedef unsigned int __kernel_mode_t; |
||||
typedef int __kernel_nlink_t; |
||||
typedef long __kernel_off_t; |
||||
typedef int __kernel_pid_t; |
||||
typedef int __kernel_ipc_pid_t; |
||||
typedef int __kernel_uid_t; |
||||
typedef int __kernel_gid_t; |
||||
typedef unsigned int __kernel_size_t; |
||||
typedef int __kernel_ssize_t; |
||||
typedef int __kernel_ptrdiff_t; |
||||
typedef long __kernel_time_t; |
||||
typedef long __kernel_suseconds_t; |
||||
typedef long __kernel_clock_t; |
||||
typedef long __kernel_daddr_t; |
||||
typedef char * __kernel_caddr_t; |
||||
|
||||
typedef unsigned short __kernel_uid16_t; |
||||
typedef unsigned short __kernel_gid16_t; |
||||
typedef int __kernel_uid32_t; |
||||
typedef int __kernel_gid32_t; |
||||
typedef __kernel_uid_t __kernel_old_uid_t; |
||||
typedef __kernel_gid_t __kernel_old_gid_t; |
||||
|
||||
#ifdef __GNUC__ |
||||
typedef long long __kernel_loff_t; |
||||
#endif |
||||
|
||||
typedef struct { |
||||
long val[2]; |
||||
} __kernel_fsid_t; |
||||
|
||||
#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) |
||||
|
||||
#undef __FD_SET |
||||
static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp) |
||||
{ |
||||
unsigned long __tmp = __fd / __NFDBITS; |
||||
unsigned long __rem = __fd % __NFDBITS; |
||||
__fdsetp->fds_bits[__tmp] |= (1UL<<__rem); |
||||
} |
||||
|
||||
#undef __FD_CLR |
||||
static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp) |
||||
{ |
||||
unsigned long __tmp = __fd / __NFDBITS; |
||||
unsigned long __rem = __fd % __NFDBITS; |
||||
__fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem); |
||||
} |
||||
|
||||
#undef __FD_ISSET |
||||
static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p) |
||||
{
|
||||
unsigned long __tmp = __fd / __NFDBITS; |
||||
unsigned long __rem = __fd % __NFDBITS; |
||||
return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0; |
||||
} |
||||
|
||||
/*
|
||||
* This will unroll the loop for the normal constant case (8 ints, |
||||
* for a 256-bit fd_set) |
||||
*/ |
||||
#undef __FD_ZERO |
||||
static __inline__ void __FD_ZERO(__kernel_fd_set *__p) |
||||
{ |
||||
unsigned long *__tmp = __p->fds_bits; |
||||
int __i; |
||||
|
||||
if (__builtin_constant_p(__FDSET_LONGS)) { |
||||
switch (__FDSET_LONGS) { |
||||
case 16: |
||||
__tmp[ 0] = 0; __tmp[ 1] = 0; |
||||
__tmp[ 2] = 0; __tmp[ 3] = 0; |
||||
__tmp[ 4] = 0; __tmp[ 5] = 0; |
||||
__tmp[ 6] = 0; __tmp[ 7] = 0; |
||||
__tmp[ 8] = 0; __tmp[ 9] = 0; |
||||
__tmp[10] = 0; __tmp[11] = 0; |
||||
__tmp[12] = 0; __tmp[13] = 0; |
||||
__tmp[14] = 0; __tmp[15] = 0; |
||||
return; |
||||
|
||||
case 8: |
||||
__tmp[ 0] = 0; __tmp[ 1] = 0; |
||||
__tmp[ 2] = 0; __tmp[ 3] = 0; |
||||
__tmp[ 4] = 0; __tmp[ 5] = 0; |
||||
__tmp[ 6] = 0; __tmp[ 7] = 0; |
||||
return; |
||||
|
||||
case 4: |
||||
__tmp[ 0] = 0; __tmp[ 1] = 0; |
||||
__tmp[ 2] = 0; __tmp[ 3] = 0; |
||||
return; |
||||
} |
||||
} |
||||
__i = __FDSET_LONGS; |
||||
while (__i) { |
||||
__i--; |
||||
*__tmp = 0; |
||||
__tmp++; |
||||
} |
||||
} |
||||
|
||||
#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ |
||||
|
||||
#endif /* _ASM_POSIX_TYPES_H */ |
||||
@ -0,0 +1,283 @@ |
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public |
||||
* License. See the file "COPYING" in the main directory of this archive |
||||
* for more details. |
||||
* |
||||
* Copyright (C) 1994 Waldorf GMBH |
||||
* Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001 Ralf Baechle |
||||
* Copyright (C) 1996 Paul M. Antoine |
||||
* Copyright (C) 1999 Silicon Graphics, Inc. |
||||
*/ |
||||
#ifndef _ASM_PROCESSOR_H |
||||
#define _ASM_PROCESSOR_H |
||||
|
||||
#include <linux/config.h> |
||||
|
||||
#include <asm/isadep.h> |
||||
|
||||
/*
|
||||
* Default implementation of macro that returns current |
||||
* instruction pointer ("program counter"). |
||||
*/ |
||||
#define current_text_addr() ({ __label__ _l; _l: &&_l;}) |
||||
|
||||
#if !defined (_LANGUAGE_ASSEMBLY) |
||||
#if 0 |
||||
#include <linux/threads.h> |
||||
#endif |
||||
#include <asm/cachectl.h> |
||||
#include <asm/mipsregs.h> |
||||
#include <asm/reg.h> |
||||
#include <asm/system.h> |
||||
|
||||
struct mips_cpuinfo { |
||||
unsigned long udelay_val; |
||||
unsigned long *pgd_quick; |
||||
unsigned long *pte_quick; |
||||
unsigned long pgtable_cache_sz; |
||||
}; |
||||
|
||||
/*
|
||||
* System setup and hardware flags.. |
||||
* XXX: Should go into mips_cpuinfo. |
||||
*/ |
||||
extern void (*cpu_wait)(void); /* only available on R4[26]00 and R3081 */ |
||||
extern void r3081_wait(void); |
||||
extern void r4k_wait(void); |
||||
extern char cyclecounter_available; /* only available from R4000 upwards. */ |
||||
|
||||
extern struct mips_cpuinfo boot_cpu_data; |
||||
extern unsigned int vced_count, vcei_count; |
||||
|
||||
#ifdef CONFIG_SMP |
||||
extern struct mips_cpuinfo cpu_data[]; |
||||
#define current_cpu_data cpu_data[smp_processor_id()] |
||||
#else |
||||
#define cpu_data &boot_cpu_data |
||||
#define current_cpu_data boot_cpu_data |
||||
#endif |
||||
|
||||
/*
|
||||
* Bus types (default is ISA, but people can check others with these..) |
||||
* MCA_bus hardcoded to 0 for now. |
||||
* |
||||
* This needs to be extended since MIPS systems are being delivered with |
||||
* numerous different types of bus systems. |
||||
*/ |
||||
extern int EISA_bus; |
||||
#define MCA_bus 0 |
||||
#define MCA_bus__is_a_macro /* for versions in ksyms.c */ |
||||
|
||||
/*
|
||||
* MIPS has no problems with write protection |
||||
*/ |
||||
#define wp_works_ok 1 |
||||
#define wp_works_ok__is_a_macro /* for versions in ksyms.c */ |
||||
|
||||
/* Lazy FPU handling on uni-processor */ |
||||
extern struct task_struct *last_task_used_math; |
||||
|
||||
/*
|
||||
* User space process size: 2GB. This is hardcoded into a few places, |
||||
* so don't change it unless you know what you are doing. TASK_SIZE |
||||
* for a 64 bit kernel expandable to 8192EB, of which the current MIPS |
||||
* implementations will "only" be able to use 1TB ... |
||||
*/ |
||||
#define TASK_SIZE (0x7fff8000UL) |
||||
|
||||
/* This decides where the kernel will search for a free chunk of vm
|
||||
* space during mmap's. |
||||
*/ |
||||
#define TASK_UNMAPPED_BASE (TASK_SIZE / 3) |
||||
|
||||
/*
|
||||
* Size of io_bitmap in longwords: 32 is ports 0-0x3ff. |
||||
*/ |
||||
#define IO_BITMAP_SIZE 32 |
||||
|
||||
#define NUM_FPU_REGS 32 |
||||
|
||||
struct mips_fpu_hard_struct { |
||||
double fp_regs[NUM_FPU_REGS]; |
||||
unsigned int control; |
||||
}; |
||||
|
||||
/*
|
||||
* It would be nice to add some more fields for emulator statistics, but there |
||||
* are a number of fixed offsets in offset.h and elsewhere that would have to |
||||
* be recalculated by hand. So the additional information will be private to |
||||
* the FPU emulator for now. See asm-mips/fpu_emulator.h. |
||||
*/ |
||||
typedef u64 fpureg_t; |
||||
struct mips_fpu_soft_struct { |
||||
fpureg_t regs[NUM_FPU_REGS]; |
||||
unsigned int sr; |
||||
}; |
||||
|
||||
union mips_fpu_union { |
||||
struct mips_fpu_hard_struct hard; |
||||
struct mips_fpu_soft_struct soft; |
||||
}; |
||||
|
||||
#define INIT_FPU { \ |
||||
{{0,},} \
|
||||
} |
||||
|
||||
typedef struct { |
||||
unsigned long seg; |
||||
} mm_segment_t; |
||||
|
||||
/*
|
||||
* If you change thread_struct remember to change the #defines below too! |
||||
*/ |
||||
struct thread_struct { |
||||
/* Saved main processor registers. */ |
||||
unsigned long reg16; |
||||
unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23; |
||||
unsigned long reg29, reg30, reg31; |
||||
|
||||
/* Saved cp0 stuff. */ |
||||
unsigned long cp0_status; |
||||
|
||||
/* Saved fpu/fpu emulator stuff. */ |
||||
union mips_fpu_union fpu; |
||||
|
||||
/* Other stuff associated with the thread. */ |
||||
unsigned long cp0_badvaddr; /* Last user fault */ |
||||
unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ |
||||
unsigned long error_code; |
||||
unsigned long trap_no; |
||||
#define MF_FIXADE 1 /* Fix address errors in software */ |
||||
#define MF_LOGADE 2 /* Log address errors to syslog */ |
||||
unsigned long mflags; |
||||
mm_segment_t current_ds; |
||||
unsigned long irix_trampoline; /* Wheee... */ |
||||
unsigned long irix_oldctx; |
||||
|
||||
/*
|
||||
* These are really only needed if the full FPU emulator is configured. |
||||
* Would be made conditional on MIPS_FPU_EMULATOR if it weren't for the |
||||
* fact that having offset.h rebuilt differently for different config |
||||
* options would be asking for trouble. |
||||
* |
||||
* Saved EPC during delay-slot emulation (see math-emu/cp1emu.c) |
||||
*/ |
||||
unsigned long dsemul_epc; |
||||
|
||||
/*
|
||||
* Pointer to instruction used to induce address error |
||||
*/ |
||||
unsigned long dsemul_aerpc; |
||||
}; |
||||
|
||||
#endif /* !defined (_LANGUAGE_ASSEMBLY) */ |
||||
|
||||
#define INIT_THREAD { \ |
||||
/* \
|
||||
* saved main processor registers \
|
||||
*/ \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, \
|
||||
/* \
|
||||
* saved cp0 stuff \
|
||||
*/ \
|
||||
0, \
|
||||
/* \
|
||||
* saved fpu/fpu emulator stuff \
|
||||
*/ \
|
||||
INIT_FPU, \
|
||||
/* \
|
||||
* Other stuff associated with the process \
|
||||
*/ \
|
||||
0, 0, 0, 0, \
|
||||
/* \
|
||||
* For now the default is to fix address errors \
|
||||
*/ \
|
||||
MF_FIXADE, { 0 }, 0, 0, \
|
||||
/* \
|
||||
* dsemul_epc and dsemul_aerpc should never be used uninitialized, \
|
||||
* but... \
|
||||
*/ \
|
||||
0 ,0 \
|
||||
} |
||||
|
||||
#ifdef __KERNEL__ |
||||
|
||||
#define KERNEL_STACK_SIZE 8192 |
||||
|
||||
#if !defined (_LANGUAGE_ASSEMBLY) |
||||
|
||||
/* Free all resources held by a thread. */ |
||||
#define release_thread(thread) do { } while(0) |
||||
|
||||
extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); |
||||
|
||||
/* Copy and release all segment info associated with a VM */ |
||||
#define copy_segments(p, mm) do { } while(0) |
||||
#define release_segments(mm) do { } while(0) |
||||
|
||||
/*
|
||||
* Return saved PC of a blocked thread. |
||||
*/ |
||||
extern inline unsigned long thread_saved_pc(struct thread_struct *t) |
||||
{ |
||||
extern void ret_from_fork(void); |
||||
|
||||
/* New born processes are a special case */ |
||||
if (t->reg31 == (unsigned long) ret_from_fork) |
||||
return t->reg31; |
||||
|
||||
return ((unsigned long *)t->reg29)[10]; |
||||
} |
||||
|
||||
/*
|
||||
* Do necessary setup to start up a newly executed thread. |
||||
*/ |
||||
#define start_thread(regs, new_pc, new_sp) do { \ |
||||
/* New thread looses kernel privileges. */ \
|
||||
regs->cp0_status = (regs->cp0_status & ~(ST0_CU0|ST0_KSU)) | KU_USER;\
|
||||
regs->cp0_epc = new_pc; \
|
||||
regs->regs[29] = new_sp; \
|
||||
current->thread.current_ds = USER_DS; \
|
||||
} while (0) |
||||
|
||||
unsigned long get_wchan(struct task_struct *p); |
||||
|
||||
#define __PT_REG(reg) ((long)&((struct pt_regs *)0)->reg - sizeof(struct pt_regs)) |
||||
#define __KSTK_TOS(tsk) ((unsigned long)(tsk) + KERNEL_STACK_SIZE - 32) |
||||
#define KSTK_EIP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(cp0_epc))) |
||||
#define KSTK_ESP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(regs[29]))) |
||||
|
||||
/* Allocation and freeing of basic task resources. */ |
||||
/*
|
||||
* NOTE! The task struct and the stack go together |
||||
*/ |
||||
#define THREAD_SIZE (2*PAGE_SIZE) |
||||
#define alloc_task_struct() \ |
||||
((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) |
||||
#define free_task_struct(p) free_pages((unsigned long)(p),1) |
||||
#define get_task_struct(tsk) atomic_inc(&virt_to_page(tsk)->count) |
||||
|
||||
#define init_task (init_task_union.task) |
||||
#define init_stack (init_task_union.stack) |
||||
|
||||
#define cpu_relax() do { } while (0) |
||||
|
||||
#endif /* !defined (_LANGUAGE_ASSEMBLY) */ |
||||
#endif /* __KERNEL__ */ |
||||
|
||||
/*
|
||||
* Return_address is a replacement for __builtin_return_address(count) |
||||
* which on certain architectures cannot reasonably be implemented in GCC |
||||
* (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386). |
||||
* Note that __builtin_return_address(x>=1) is forbidden because GCC |
||||
* aborts compilation on some CPUs. It's simply not possible to unwind |
||||
* some CPU's stackframes. |
||||
* |
||||
* __builtin_return_address works only for non-leaf functions. We avoid the |
||||
* overhead of a function call by forcing the compiler to save the return |
||||
* address register on the stack. |
||||
*/ |
||||
#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);}) |
||||
|
||||
#endif /* _ASM_PROCESSOR_H */ |
||||
@ -0,0 +1,86 @@ |
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public |
||||
* License. See the file "COPYING" in the main directory of this archive |
||||
* for more details. |
||||
* |
||||
* Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000 by Ralf Baechle |
||||
* |
||||
* Machine dependent structs and defines to help the user use |
||||
* the ptrace system call. |
||||
*/ |
||||
#ifndef _ASM_PTRACE_H |
||||
#define _ASM_PTRACE_H |
||||
|
||||
#include <asm/isadep.h> |
||||
#include <linux/types.h> |
||||
|
||||
/* 0 - 31 are integer registers, 32 - 63 are fp registers. */ |
||||
#define FPR_BASE 32 |
||||
#define PC 64 |
||||
#define CAUSE 65 |
||||
#define BADVADDR 66 |
||||
#define MMHI 67 |
||||
#define MMLO 68 |
||||
#define FPC_CSR 69 |
||||
#define FPC_EIR 70 |
||||
|
||||
#ifndef _LANGUAGE_ASSEMBLY |
||||
/*
|
||||
* This struct defines the way the registers are stored on the stack during a |
||||
* system call/exception. As usual the registers k0/k1 aren't being saved. |
||||
*/ |
||||
struct pt_regs { |
||||
/* Pad bytes for argument save space on the stack. */ |
||||
unsigned long pad0[6]; |
||||
|
||||
/* Saved main processor registers. */ |
||||
unsigned long regs[32]; |
||||
|
||||
/* Other saved registers. */ |
||||
unsigned long lo; |
||||
unsigned long hi; |
||||
|
||||
/*
|
||||
* saved cp0 registers |
||||
*/ |
||||
unsigned long cp0_epc; |
||||
unsigned long cp0_badvaddr; |
||||
unsigned long cp0_status; |
||||
unsigned long cp0_cause; |
||||
}; |
||||
|
||||
#endif /* !(_LANGUAGE_ASSEMBLY) */ |
||||
|
||||
/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ |
||||
/* #define PTRACE_GETREGS 12 */ |
||||
/* #define PTRACE_SETREGS 13 */ |
||||
/* #define PTRACE_GETFPREGS 14 */ |
||||
/* #define PTRACE_SETFPREGS 15 */ |
||||
/* #define PTRACE_GETFPXREGS 18 */ |
||||
/* #define PTRACE_SETFPXREGS 19 */ |
||||
|
||||
#define PTRACE_SETOPTIONS 21 |
||||
|
||||
/* options set using PTRACE_SETOPTIONS */ |
||||
#define PTRACE_O_TRACESYSGOOD 0x00000001 |
||||
|
||||
#if 0 /* def _LANGUAGE_ASSEMBLY */
|
||||
#include <asm/offset.h> |
||||
#endif |
||||
|
||||
#ifdef __KERNEL__ |
||||
|
||||
#ifndef _LANGUAGE_ASSEMBLY |
||||
/*
|
||||
* Does the process account for user or for system time? |
||||
*/ |
||||
#define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER) |
||||
|
||||
#define instruction_pointer(regs) ((regs)->cp0_epc) |
||||
|
||||
extern void show_regs(struct pt_regs *); |
||||
#endif /* !(_LANGUAGE_ASSEMBLY) */ |
||||
|
||||
#endif |
||||
|
||||
#endif /* _ASM_PTRACE_H */ |
||||
@ -0,0 +1,66 @@ |
||||
/*
|
||||
* Various register offset definitions for debuggers, core file |
||||
* examiners and whatnot. |
||||
* |
||||
* This file is subject to the terms and conditions of the GNU General Public |
||||
* License. See the file "COPYING" in the main directory of this archive |
||||
* for more details. |
||||
* |
||||
* Copyright (C) 1995, 1999 by Ralf Baechle |
||||
*/ |
||||
#ifndef __ASM_MIPS_REG_H |
||||
#define __ASM_MIPS_REG_H |
||||
|
||||
/*
|
||||
* This defines/structures correspond to the register layout on stack - |
||||
* if the order here is changed, it needs to be updated in |
||||
* include/asm-mips/stackframe.h |
||||
*/ |
||||
#define EF_REG0 6 |
||||
#define EF_REG1 7 |
||||
#define EF_REG2 8 |
||||
#define EF_REG3 9 |
||||
#define EF_REG4 10 |
||||
#define EF_REG5 11 |
||||
#define EF_REG6 12 |
||||
#define EF_REG7 13 |
||||
#define EF_REG8 14 |
||||
#define EF_REG9 15 |
||||
#define EF_REG10 16 |
||||
#define EF_REG11 17 |
||||
#define EF_REG12 18 |
||||
#define EF_REG13 19 |
||||
#define EF_REG14 20 |
||||
#define EF_REG15 21 |
||||
#define EF_REG16 22 |
||||
#define EF_REG17 23 |
||||
#define EF_REG18 24 |
||||
#define EF_REG19 25 |
||||
#define EF_REG20 26 |
||||
#define EF_REG21 27 |
||||
#define EF_REG22 28 |
||||
#define EF_REG23 29 |
||||
#define EF_REG24 30 |
||||
#define EF_REG25 31 |
||||
/*
|
||||
* k0/k1 unsaved |
||||
*/ |
||||
#define EF_REG28 34 |
||||
#define EF_REG29 35 |
||||
#define EF_REG30 36 |
||||
#define EF_REG31 37 |
||||
|
||||
/*
|
||||
* Saved special registers |
||||
*/ |
||||
#define EF_LO 38 |
||||
#define EF_HI 39 |
||||
|
||||
#define EF_CP0_EPC 40 |
||||
#define EF_CP0_BADVADDR 41 |
||||
#define EF_CP0_STATUS 42 |
||||
#define EF_CP0_CAUSE 44 |
||||
|
||||
#define EF_SIZE 180 /* size in bytes */ |
||||
|
||||
#endif /* __ASM_MIPS_REG_H */ |
||||
@ -0,0 +1,52 @@ |
||||
/*
|
||||
* include/asm-mips/regdefs.h |
||||
* |
||||
* This file is subject to the terms and conditions of the GNU General Public |
||||
* License. See the file "COPYING" in the main directory of this archive |
||||
* for more details. |
||||
* |
||||
* Copyright (C) 1994, 1995 by Ralf Baechle |
||||
*/ |
||||
|
||||
#ifndef __ASM_MIPS_REGDEF_H |
||||
#define __ASM_MIPS_REGDEF_H |
||||
|
||||
/*
|
||||
* Symbolic register names for 32 bit ABI |
||||
*/ |
||||
#define zero $0 /* wired zero */ |
||||
#define AT $1 /* assembler temp - uppercase because of ".set at" */ |
||||
#define v0 $2 /* return value */ |
||||
#define v1 $3 |
||||
#define a0 $4 /* argument registers */ |
||||
#define a1 $5 |
||||
#define a2 $6 |
||||
#define a3 $7 |
||||
#define t0 $8 /* caller saved */ |
||||
#define t1 $9 |
||||
#define t2 $10 |
||||
#define t3 $11 |
||||
#define t4 $12 |
||||
#define t5 $13 |
||||
#define t6 $14 |
||||
#define t7 $15 |
||||
#define s0 $16 /* callee saved */ |
||||
#define s1 $17 |
||||
#define s2 $18 |
||||
#define s3 $19 |
||||
#define s4 $20 |
||||
#define s5 $21 |
||||
#define s6 $22 |
||||
#define s7 $23 |
||||
#define t8 $24 /* caller saved */ |
||||
#define t9 $25 |
||||
#define jp $25 /* PIC jump register */ |
||||
#define k0 $26 /* kernel scratch */ |
||||
#define k1 $27 |
||||
#define gp $28 /* global pointer */ |
||||
#define sp $29 /* stack pointer */ |
||||
#define fp $30 /* frame pointer */ |
||||
#define s8 $30 /* same like fp! */ |
||||
#define ra $31 /* return address */ |
||||
|
||||
#endif /* __ASM_MIPS_REGDEF_H */ |
||||
@ -0,0 +1,44 @@ |
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public |
||||
* License. See the file "COPYING" in the main directory of this archive |
||||
* for more details. |
||||
* |
||||
* Copyright (C) 1996, 1999, 2001 Ralf Baechle |
||||
* Copyright (C) 1999 Silicon Graphics, Inc. |
||||
* Copyright (C) 2001 MIPS Technologies, Inc. |
||||
*/ |
||||
#ifndef __ASM_SGIDEFS_H |
||||
#define __ASM_SGIDEFS_H |
||||
|
||||
/*
|
||||
* Using a Linux compiler for building Linux seems logic but not to |
||||
* everybody. |
||||
*/ |
||||
#if 0 /* ndef __linux__ */
|
||||
#error Use a Linux compiler or give up. |
||||
#endif |
||||
|
||||
/*
|
||||
* Definitions for the ISA levels |
||||
* |
||||
* With the introduction of MIPS32 / MIPS64 instruction sets definitions |
||||
* MIPS ISAs are no longer subsets of each other. Therefore comparisons |
||||
* on these symbols except with == may result in unexpected results and |
||||
* are forbidden! |
||||
*/ |
||||
#define _MIPS_ISA_MIPS1 1 |
||||
#define _MIPS_ISA_MIPS2 2 |
||||
#define _MIPS_ISA_MIPS3 3 |
||||
#define _MIPS_ISA_MIPS4 4 |
||||
#define _MIPS_ISA_MIPS5 5 |
||||
#define _MIPS_ISA_MIPS32 6 |
||||
#define _MIPS_ISA_MIPS64 7 |
||||
|
||||
/*
|
||||
* Subprogram calling convention |
||||
*/ |
||||
#define _MIPS_SIM_ABI32 1 |
||||
#define _MIPS_SIM_NABI32 2 |
||||
#define _MIPS_SIM_ABI64 3 |
||||
|
||||
#endif /* __ASM_SGIDEFS_H */ |
||||
@ -0,0 +1,157 @@ |
||||
/* $Id: string.h,v 1.13 2000/02/19 14:12:14 harald Exp $
|
||||
* |
||||
* This file is subject to the terms and conditions of the GNU General Public |
||||
* License. See the file "COPYING" in the main directory of this archive |
||||
* for more details. |
||||
* |
||||
* Copyright (c) 1994, 1995, 1996, 1997, 1998 by Ralf Baechle |
||||
*/ |
||||
#ifndef __ASM_MIPS_STRING_H |
||||
#define __ASM_MIPS_STRING_H |
||||
|
||||
#include <linux/config.h> |
||||
|
||||
#define __HAVE_ARCH_STRCPY |
||||
extern __inline__ char *strcpy(char *__dest, __const__ char *__src) |
||||
{ |
||||
char *__xdest = __dest; |
||||
|
||||
__asm__ __volatile__( |
||||
".set\tnoreorder\n\t" |
||||
".set\tnoat\n" |
||||
"1:\tlbu\t$1,(%1)\n\t" |
||||
"addiu\t%1,1\n\t" |
||||
"sb\t$1,(%0)\n\t" |
||||
"bnez\t$1,1b\n\t" |
||||
"addiu\t%0,1\n\t" |
||||
".set\tat\n\t" |
||||
".set\treorder" |
||||
: "=r" (__dest), "=r" (__src) |
||||
: "0" (__dest), "1" (__src) |
||||
: "$1","memory"); |
||||
|
||||
return __xdest; |
||||
} |
||||
|
||||
#define __HAVE_ARCH_STRNCPY |
||||
extern __inline__ char *strncpy(char *__dest, __const__ char *__src, size_t __n) |
||||
{ |
||||
char *__xdest = __dest; |
||||
|
||||
if (__n == 0) |
||||
return __xdest; |
||||
|
||||
__asm__ __volatile__( |
||||
".set\tnoreorder\n\t" |
||||
".set\tnoat\n" |
||||
"1:\tlbu\t$1,(%1)\n\t" |
||||
"subu\t%2,1\n\t" |
||||
"sb\t$1,(%0)\n\t" |
||||
"beqz\t$1,2f\n\t" |
||||
"addiu\t%0,1\n\t" |
||||
"bnez\t%2,1b\n\t" |
||||
"addiu\t%1,1\n" |
||||
"2:\n\t" |
||||
".set\tat\n\t" |
||||
".set\treorder" |
||||
: "=r" (__dest), "=r" (__src), "=r" (__n) |
||||
: "0" (__dest), "1" (__src), "2" (__n) |
||||
: "$1","memory"); |
||||
|
||||
return __dest; |
||||
} |
||||
|
||||
#define __HAVE_ARCH_STRCMP |
||||
extern __inline__ int strcmp(__const__ char *__cs, __const__ char *__ct) |
||||
{ |
||||
int __res; |
||||
|
||||
__asm__ __volatile__( |
||||
".set\tnoreorder\n\t" |
||||
".set\tnoat\n\t" |
||||
"lbu\t%2,(%0)\n" |
||||
"1:\tlbu\t$1,(%1)\n\t" |
||||
"addiu\t%0,1\n\t" |
||||
"bne\t$1,%2,2f\n\t" |
||||
"addiu\t%1,1\n\t" |
||||
"bnez\t%2,1b\n\t" |
||||
"lbu\t%2,(%0)\n\t" |
||||
#if defined(CONFIG_CPU_R3000) |
||||
"nop\n\t" |
||||
#endif |
||||
"move\t%2,$1\n" |
||||
"2:\tsubu\t%2,$1\n" |
||||
"3:\t.set\tat\n\t" |
||||
".set\treorder" |
||||
: "=r" (__cs), "=r" (__ct), "=r" (__res) |
||||
: "0" (__cs), "1" (__ct) |
||||
: "$1"); |
||||
|
||||
return __res; |
||||
} |
||||
|
||||
#define __HAVE_ARCH_STRNCMP |
||||
extern __inline__ int |
||||
strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count) |
||||
{ |
||||
int __res; |
||||
|
||||
__asm__ __volatile__( |
||||
".set\tnoreorder\n\t" |
||||
".set\tnoat\n" |
||||
"1:\tlbu\t%3,(%0)\n\t" |
||||
"beqz\t%2,2f\n\t" |
||||
"lbu\t$1,(%1)\n\t" |
||||
"subu\t%2,1\n\t" |
||||
"bne\t$1,%3,3f\n\t" |
||||
"addiu\t%0,1\n\t" |
||||
"bnez\t%3,1b\n\t" |
||||
"addiu\t%1,1\n" |
||||
"2:\n\t" |
||||
#if defined(CONFIG_CPU_R3000) |
||||
"nop\n\t" |
||||
#endif |
||||
"move\t%3,$1\n" |
||||
"3:\tsubu\t%3,$1\n\t" |
||||
".set\tat\n\t" |
||||
".set\treorder" |
||||
: "=r" (__cs), "=r" (__ct), "=r" (__count), "=r" (__res) |
||||
: "0" (__cs), "1" (__ct), "2" (__count) |
||||
: "$1"); |
||||
|
||||
return __res; |
||||
} |
||||
|
||||
#undef __HAVE_ARCH_MEMSET |
||||
extern void *memset(void *__s, int __c, size_t __count); |
||||
|
||||
#undef __HAVE_ARCH_MEMCPY |
||||
extern void *memcpy(void *__to, __const__ void *__from, size_t __n); |
||||
|
||||
#undef __HAVE_ARCH_MEMMOVE |
||||
extern void *memmove(void *__dest, __const__ void *__src, size_t __n); |
||||
|
||||
/* Don't build bcopy at all ... */ |
||||
#define __HAVE_ARCH_BCOPY |
||||
|
||||
#define __HAVE_ARCH_MEMSCAN |
||||
extern __inline__ void *memscan(void *__addr, int __c, size_t __size) |
||||
{ |
||||
char *__end = (char *)__addr + __size; |
||||
|
||||
__asm__(".set\tpush\n\t" |
||||
".set\tnoat\n\t" |
||||
".set\treorder\n\t" |
||||
"1:\tbeq\t%0,%1,2f\n\t" |
||||
"addiu\t%0,1\n\t" |
||||
"lb\t$1,-1(%0)\n\t" |
||||
"bne\t$1,%4,1b\n" |
||||
"2:\t.set\tpop" |
||||
: "=r" (__addr), "=r" (__end) |
||||
: "0" (__addr), "1" (__end), "r" (__c) |
||||
: "$1"); |
||||
|
||||
return __addr; |
||||
} |
||||
|
||||
#endif /* __ASM_MIPS_STRING_H */ |
||||
@ -0,0 +1,268 @@ |
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public |
||||
* License. See the file "COPYING" in the main directory of this archive |
||||
* for more details. |
||||
* |
||||
* Copyright (C) 1994 - 1999 by Ralf Baechle |
||||
* Copyright (C) 1996 by Paul M. Antoine |
||||
* Copyright (C) 1994 - 1999 by Ralf Baechle |
||||
* |
||||
* Changed set_except_vector declaration to allow return of previous |
||||
* vector address value - necessary for "borrowing" vectors.
|
||||
* |
||||
* Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com |
||||
* Copyright (C) 2000 MIPS Technologies, Inc. |
||||
*/ |
||||
#ifndef _ASM_SYSTEM_H |
||||
#define _ASM_SYSTEM_H |
||||
|
||||
#include <linux/config.h> |
||||
#include <asm/sgidefs.h> |
||||
#include <asm/ptrace.h> |
||||
#if 0 |
||||
#include <linux/kernel.h> |
||||
#endif |
||||
|
||||
extern __inline__ void |
||||
__sti(void) |
||||
{ |
||||
__asm__ __volatile__( |
||||
".set\tpush\n\t" |
||||
".set\treorder\n\t" |
||||
".set\tnoat\n\t" |
||||
"mfc0\t$1,$12\n\t" |
||||
"ori\t$1,0x1f\n\t" |
||||
"xori\t$1,0x1e\n\t" |
||||
"mtc0\t$1,$12\n\t" |
||||
".set\tpop\n\t" |
||||
: /* no outputs */ |
||||
: /* no inputs */ |
||||
: "$1", "memory"); |
||||
} |
||||
|
||||
/*
|
||||
* For cli() we have to insert nops to make shure that the new value |
||||
* has actually arrived in the status register before the end of this |
||||
* macro. |
||||
* R4000/R4400 need three nops, the R4600 two nops and the R10000 needs |
||||
* no nops at all. |
||||
*/ |
||||
extern __inline__ void |
||||
__cli(void) |
||||
{ |
||||
__asm__ __volatile__( |
||||
".set\tpush\n\t" |
||||
".set\treorder\n\t" |
||||
".set\tnoat\n\t" |
||||
"mfc0\t$1,$12\n\t" |
||||
"ori\t$1,1\n\t" |
||||
"xori\t$1,1\n\t" |
||||
".set\tnoreorder\n\t" |
||||
"mtc0\t$1,$12\n\t" |
||||
"nop\n\t" |
||||
"nop\n\t" |
||||
"nop\n\t" |
||||
".set\tpop\n\t" |
||||
: /* no outputs */ |
||||
: /* no inputs */ |
||||
: "$1", "memory"); |
||||
} |
||||
|
||||
#define __save_flags(x) \ |
||||
__asm__ __volatile__( \
|
||||
".set\tpush\n\t" \
|
||||
".set\treorder\n\t" \
|
||||
"mfc0\t%0,$12\n\t" \
|
||||
".set\tpop\n\t" \
|
||||
: "=r" (x)) |
||||
|
||||
#define __save_and_cli(x) \ |
||||
__asm__ __volatile__( \
|
||||
".set\tpush\n\t" \
|
||||
".set\treorder\n\t" \
|
||||
".set\tnoat\n\t" \
|
||||
"mfc0\t%0,$12\n\t" \
|
||||
"ori\t$1,%0,1\n\t" \
|
||||
"xori\t$1,1\n\t" \
|
||||
".set\tnoreorder\n\t" \
|
||||
"mtc0\t$1,$12\n\t" \
|
||||
"nop\n\t" \
|
||||
"nop\n\t" \
|
||||
"nop\n\t" \
|
||||
".set\tpop\n\t" \
|
||||
: "=r" (x) \
|
||||
: /* no inputs */ \
|
||||
: "$1", "memory") |
||||
|
||||
#define __restore_flags(flags) \ |
||||
do { \
|
||||
unsigned long __tmp1; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
".set\tnoreorder\t\t\t# __restore_flags\n\t" \
|
||||
".set\tnoat\n\t" \
|
||||
"mfc0\t$1, $12\n\t" \
|
||||
"andi\t%0, 1\n\t" \
|
||||
"ori\t$1, 1\n\t" \
|
||||
"xori\t$1, 1\n\t" \
|
||||
"or\t%0, $1\n\t" \
|
||||
"mtc0\t%0, $12\n\t" \
|
||||
"nop\n\t" \
|
||||
"nop\n\t" \
|
||||
"nop\n\t" \
|
||||
".set\tat\n\t" \
|
||||
".set\treorder" \
|
||||
: "=r" (__tmp1) \
|
||||
: "0" (flags) \
|
||||
: "$1", "memory"); \
|
||||
} while(0) |
||||
|
||||
#ifdef CONFIG_SMP |
||||
|
||||
extern void __global_sti(void); |
||||
extern void __global_cli(void); |
||||
extern unsigned long __global_save_flags(void); |
||||
extern void __global_restore_flags(unsigned long); |
||||
# define sti() __global_sti() |
||||
# define cli() __global_cli() |
||||
# define save_flags(x) do { x = __global_save_flags(); } while (0) |
||||
# define restore_flags(x) __global_restore_flags(x) |
||||
# define save_and_cli(x) do { save_flags(x); cli(); } while(0) |
||||
|
||||
#else /* Single processor */ |
||||
|
||||
# define sti() __sti() |
||||
# define cli() __cli() |
||||
# define save_flags(x) __save_flags(x) |
||||
# define save_and_cli(x) __save_and_cli(x) |
||||
# define restore_flags(x) __restore_flags(x) |
||||
|
||||
#endif /* SMP */ |
||||
|
||||
/* For spinlocks etc */ |
||||
#define local_irq_save(x) __save_and_cli(x); |
||||
#define local_irq_restore(x) __restore_flags(x); |
||||
#define local_irq_disable() __cli(); |
||||
#define local_irq_enable() __sti(); |
||||
|
||||
/*
|
||||
* These are probably defined overly paranoid ... |
||||
*/ |
||||
#ifdef CONFIG_CPU_HAS_WB |
||||
|
||||
#include <asm/wbflush.h> |
||||
#define rmb() do { } while(0) |
||||
#define wmb() wbflush() |
||||
#define mb() wbflush() |
||||
|
||||
#else /* CONFIG_CPU_HAS_WB */ |
||||
|
||||
#define mb() \ |
||||
__asm__ __volatile__( \
|
||||
"# prevent instructions being moved around\n\t" \
|
||||
".set\tnoreorder\n\t" \
|
||||
"# 8 nops to fool the R4400 pipeline\n\t" \
|
||||
"nop;nop;nop;nop;nop;nop;nop;nop\n\t" \
|
||||
".set\treorder" \
|
||||
: /* no output */ \
|
||||
: /* no input */ \
|
||||
: "memory") |
||||
#define rmb() mb() |
||||
#define wmb() mb() |
||||
|
||||
#endif /* CONFIG_CPU_HAS_WB */ |
||||
|
||||
#ifdef CONFIG_SMP |
||||
#define smp_mb() mb() |
||||
#define smp_rmb() rmb() |
||||
#define smp_wmb() wmb() |
||||
#else |
||||
#define smp_mb() barrier() |
||||
#define smp_rmb() barrier() |
||||
#define smp_wmb() barrier() |
||||
#endif |
||||
|
||||
#define set_mb(var, value) \ |
||||
do { var = value; mb(); } while (0) |
||||
|
||||
#define set_wmb(var, value) \ |
||||
do { var = value; wmb(); } while (0) |
||||
|
||||
#if !defined (_LANGUAGE_ASSEMBLY) |
||||
/*
|
||||
* switch_to(n) should switch tasks to task nr n, first |
||||
* checking that n isn't the current task, in which case it does nothing. |
||||
*/ |
||||
#if 0 |
||||
extern asmlinkage void *resume(void *last, void *next); |
||||
#endif |
||||
#endif /* !defined (_LANGUAGE_ASSEMBLY) */ |
||||
|
||||
#define prepare_to_switch() do { } while(0) |
||||
#define switch_to(prev,next,last) \ |
||||
do { \
|
||||
(last) = resume(prev, next); \
|
||||
} while(0) |
||||
|
||||
/*
|
||||
* For 32 and 64 bit operands we can take advantage of ll and sc. |
||||
* FIXME: This doesn't work for R3000 machines. |
||||
*/ |
||||
extern __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val) |
||||
{ |
||||
#ifdef CONFIG_CPU_HAS_LLSC |
||||
unsigned long dummy; |
||||
|
||||
__asm__ __volatile__( |
||||
".set\tnoreorder\t\t\t# xchg_u32\n\t" |
||||
".set\tnoat\n\t" |
||||
"ll\t%0, %3\n" |
||||
"1:\tmove\t$1, %2\n\t" |
||||
"sc\t$1, %1\n\t" |
||||
"beqzl\t$1, 1b\n\t" |
||||
" ll\t%0, %3\n\t" |
||||
".set\tat\n\t" |
||||
".set\treorder" |
||||
: "=r" (val), "=o" (*m), "=r" (dummy) |
||||
: "o" (*m), "2" (val) |
||||
: "memory"); |
||||
|
||||
return val; |
||||
#else |
||||
unsigned long flags, retval; |
||||
|
||||
save_flags(flags); |
||||
cli(); |
||||
retval = *m; |
||||
*m = val; |
||||
restore_flags(flags); |
||||
return retval; |
||||
#endif /* Processor-dependent optimization */ |
||||
} |
||||
|
||||
#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) |
||||
#define tas(ptr) (xchg((ptr),1)) |
||||
|
||||
static __inline__ unsigned long |
||||
__xchg(unsigned long x, volatile void * ptr, int size) |
||||
{ |
||||
switch (size) { |
||||
case 4: |
||||
return xchg_u32(ptr, x); |
||||
} |
||||
return x; |
||||
} |
||||
|
||||
extern void *set_except_vector(int n, void *addr); |
||||
|
||||
extern void __die(const char *, struct pt_regs *, const char *where, |
||||
unsigned long line) __attribute__((noreturn)); |
||||
extern void __die_if_kernel(const char *, struct pt_regs *, const char *where, |
||||
unsigned long line); |
||||
|
||||
#define die(msg, regs) \ |
||||
__die(msg, regs, __FILE__ ":"__FUNCTION__, __LINE__) |
||||
#define die_if_kernel(msg, regs) \ |
||||
__die_if_kernel(msg, regs, __FILE__ ":"__FUNCTION__, __LINE__) |
||||
|
||||
#endif /* _ASM_SYSTEM_H */ |
||||
@ -0,0 +1,77 @@ |
||||
/* $Id: types.h,v 1.3 1999/08/18 23:37:50 ralf Exp $
|
||||
* |
||||
* This file is subject to the terms and conditions of the GNU General Public |
||||
* License. See the file "COPYING" in the main directory of this archive |
||||
* for more details. |
||||
* |
||||
* Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle |
||||
* Copyright (C) 1999 Silicon Graphics, Inc. |
||||
*/ |
||||
#ifndef _ASM_TYPES_H |
||||
#define _ASM_TYPES_H |
||||
|
||||
typedef unsigned short umode_t; |
||||
|
||||
/*
|
||||
* __xx is ok: it doesn't pollute the POSIX namespace. Use these in the |
||||
* header files exported to user space |
||||
*/ |
||||
|
||||
typedef __signed__ char __s8; |
||||
typedef unsigned char __u8; |
||||
|
||||
typedef __signed__ short __s16; |
||||
typedef unsigned short __u16; |
||||
|
||||
typedef __signed__ int __s32; |
||||
typedef unsigned int __u32; |
||||
|
||||
#if (_MIPS_SZLONG == 64) |
||||
|
||||
typedef __signed__ long __s64; |
||||
typedef unsigned long __u64; |
||||
|
||||
#else |
||||
|
||||
#if defined(__GNUC__) && !defined(__STRICT_ANSI__) |
||||
typedef __signed__ long long __s64; |
||||
typedef unsigned long long __u64; |
||||
#endif |
||||
|
||||
#endif |
||||
|
||||
/*
|
||||
* These aren't exported outside the kernel to avoid name space clashes |
||||
*/ |
||||
#ifdef __KERNEL__ |
||||
|
||||
typedef __signed char s8; |
||||
typedef unsigned char u8; |
||||
|
||||
typedef __signed short s16; |
||||
typedef unsigned short u16; |
||||
|
||||
typedef __signed int s32; |
||||
typedef unsigned int u32; |
||||
|
||||
#if (_MIPS_SZLONG == 64) |
||||
|
||||
typedef __signed__ long s64; |
||||
typedef unsigned long u64; |
||||
|
||||
#else |
||||
|
||||
#if defined(__GNUC__) && !defined(__STRICT_ANSI__) |
||||
typedef __signed__ long long s64; |
||||
typedef unsigned long long u64; |
||||
#endif |
||||
|
||||
#endif |
||||
|
||||
#define BITS_PER_LONG _MIPS_SZLONG |
||||
|
||||
typedef unsigned long dma_addr_t; |
||||
|
||||
#endif /* __KERNEL__ */ |
||||
|
||||
#endif /* _ASM_TYPES_H */ |
||||
@ -0,0 +1,44 @@ |
||||
/*
|
||||
* (C) Copyright 2003 |
||||
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef _U_BOOT_H_ |
||||
#define _U_BOOT_H_ 1 |
||||
|
||||
typedef struct bd_info { |
||||
int bi_baudrate; /* serial console baudrate */ |
||||
unsigned long bi_ip_addr; /* IP Address */ |
||||
unsigned char bi_enetaddr[6]; /* Ethernet adress */ |
||||
struct environment_s *bi_env; |
||||
ulong bi_arch_number; /* unique id for this board */ |
||||
ulong bi_boot_params; /* where this board expects params */ |
||||
struct /* RAM configuration */ |
||||
{ |
||||
ulong start; |
||||
ulong size; |
||||
} bi_dram[CONFIG_NR_DRAM_BANKS]; |
||||
} bd_t; |
||||
|
||||
#define bi_env_data bi_env->data |
||||
#define bi_env_crc bi_env->crc |
||||
|
||||
#endif /* _U_BOOT_H_ */ |
||||
@ -0,0 +1,24 @@ |
||||
#
|
||||
# (C) Copyright 2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__
|
||||
Loading…
Reference in new issue