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@ -1425,9 +1425,6 @@ |
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/*----------------------------------------------------------------------------+
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| Clock / Power-on-reset DCR's. |
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+----------------------------------------------------------------------------*/ |
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#define CPR0_CFGADDR 0x00C |
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#define CPR0_CFGDATA 0x00D |
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#define CPR0_CLKUPD 0x20 |
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#define CPR0_CLKUPD_BSY_MASK 0x80000000 |
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#define CPR0_CLKUPD_BSY_COMPLETED 0x00000000 |
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@ -3314,6 +3311,23 @@ |
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#define mtsdr(reg, data) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0) |
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#define mfsdr(reg, data) do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0) |
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/*
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* All 44x except 440GP have CPR registers (indirect DCR) |
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*/ |
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#if !defined(CONFIG_440GP) |
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#define CPR0_CFGADDR 0x00C |
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#define CPR0_CFGDATA 0x00D |
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#define mtcpr(reg, data) do { \ |
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mtdcr(CPR0_CFGADDR, reg); \
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mtdcr(CPR0_CFGDATA, data); \
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} while (0) |
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#define mfcpr(reg, data) do { \ |
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mtdcr(CPR0_CFGADDR, reg); \
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data = mfdcr(CPR0_CFGDATA); \
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} while (0) |
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#endif |
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#ifndef __ASSEMBLY__ |
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