@ -1,7 +1,6 @@
/ *
* Copyright 2 0 0 4 F r e e s c a l e S e m i c o n d u c t o r .
* Copyright 2 0 0 4 , 2 0 0 7 F r e e s c a l e S e m i c o n d u c t o r .
* Copyright ( C ) 2 0 0 3 M o t o r o l a ,I n c .
* Xianghua X i a o < X . X i a o @motorola.com>
*
* See f i l e C R E D I T S f o r l i s t o f p e o p l e w h o c o n t r i b u t e d t o t h i s
* project.
@ -46,7 +45,7 @@
# endif
# undef M S R _ K E R N E L
# define M S R _ K E R N E L ( M S R _ M E ) / * M a c h i n e C h e c k * /
# define M S R _ K E R N E L ( M S R _ M E ) / * M a c h i n e C h e c k * /
/ *
* Set u p G O T : G l o b a l O f f s e t T a b l e
@ -80,110 +79,37 @@
*
* /
.section .bootpg , " ax"
.globl _start_e500
.section .bootpg , " ax"
.globl _start_e500
_start_e500 :
mfspr r0 , P V R
lis r1 , P V R _ 8 5 x x _ R E V 1 @h
ori r1 , r1 , P V R _ 8 5 x x _ R E V 1 @l
cmpw r0 , r1
bne 1 f
/* Semi-bogus errata fixup for Rev 1 */
li r0 ,0 x20 0 0
mtspr 9 7 7 ,r0
/* clear registers/arrays not reset by hardware */
/ *
* Before i n v a l i d a t i n g M M U L 1 / L 2 , r e a d T L B 1 E n t r y 0 a n d t h e n
* write i t b a c k i m m e d i a t e l y t o f i x u p a R e v 1 b u g ( E r r a t a C P U 4 )
* for t h i s i n i t i a l T L B 1 e n t r y 0 , o t h e r w i s e t h e T L B 1 e n t r y 0
* will b e i n v a l i d a t e d ( i n c o r r e c t l y ) .
* /
lis r2 ,0 x10 0 0
mtspr M A S 0 ,r2
tlbre
tlbwe
isync
1 :
/ *
* Clear a n d s e t u p s o m e r e g i s t e r s .
* Note : Some r e g i s t e r s n e e d s t r i c t s y n c h r o n i z a t i o n b y
* sync/ m b a r / m s y n c / i s y n c w h e n b e i n g " m t s p r " .
* BookE : isync b e f o r e P I D ,t l b i v a x ,t l b w e
* BookE : isync a f t e r M S R ,P I D ; msync_isync after tlbivax & tlbwe
* E500 : msync,i s y n c b e f o r e L 1 C S R 0
* E500 : isync a f t e r B B E A R ,B B T A R ,B U C S R ,D B C R 0 ,D B C R 1 ,H I D 0 ,H I D 1 ,
* L1 C S R 0 , L 1 C S R 1 , M A S [ 0 ,1 ,2 ,3 ,4 ,6 ] ,M M U C S R 0 , P I D [ 0 ,1 ,2 ] ,
* SPEFCSR
* /
/* invalidate d-cache */
mfspr r0 ,L 1 C S R 0
ori r0 ,r0 ,0 x00 0 2
msync
isync
mtspr L 1 C S R 0 ,r0
isync
/* disable d-cache */
li r0 ,0 x0
mtspr L 1 C S R 0 ,r0
/* invalidate i-cache */
mfspr r0 ,L 1 C S R 1
ori r0 ,r0 ,0 x00 0 2
mtspr L 1 C S R 1 ,r0
isync
/* disable i-cache */
li r0 ,0 x0
mtspr L 1 C S R 1 ,r0
isync
/* clear registers */
li r0 ,0
mtspr S R R 0 ,r0
mtspr S R R 1 ,r0
mtspr C S R R 0 ,r0
mtspr C S R R 1 ,r0
mtspr M C S R R 0 ,r0
mtspr M C S R R 1 ,r0
mtspr E S R ,r0
mtspr M C S R ,r0
mtspr D E A R ,r0
/* not needed and conflicts with some debuggers */
/* mtspr DBCR0,r0 */
mtspr D B C R 1 ,r0
mtspr D B C R 2 ,r0
/* not needed and conflicts with some debuggers */
/* mtspr IAC1,r0 */
/* mtspr IAC2,r0 */
mtspr D A C 1 ,r0
mtspr D A C 2 ,r0
/* L1 */
li r0 ,2
mtspr L 1 C S R 0 ,r0 / * i n v a l i d a t e d - c a c h e * /
mtspr L 1 C S R 1 ,r0 / * i n v a l i d a t e i - c a c h e * /
mfspr r1 ,D B S R
mtspr D B S R ,r1 / * C l e a r a l l v a l i d b i t s * /
mtspr P I D 0 ,r0
mtspr P I D 1 ,r0
mtspr P I D 2 ,r0
mtspr T C R ,r0
/ *
* Enable L 1 C a c h e s e a r l y
*
* /
mtspr B U C S R ,r0 / * d i s a b l e b r a n c h p r e d i c t i o n * /
mtspr M A S 4 ,r0
mtspr M A S 6 ,r0
# if d e f i n e d ( C O N F I G _ E N A B L E _ 3 6 B I T _ P H Y S )
mtspr M A S 7 ,r0
# endif
lis r2 ,L 1 C S R 0 _ C P E @H /* enable parity */
ori r2 ,r2 ,L 1 C S R 0 _ D C E
mtspr L 1 C S R 0 ,r2 / * e n a b l e L 1 D c a c h e * /
isync
mtspr L 1 C S R 1 ,r2 / * e n a b l e L 1 I c a c h e * /
isync
msync
/* Setup interrupt vectors */
lis r1 ,T E X T _ B A S E @h
mtspr I V P R , r1
mtspr I V P R ,r1
li r1 ,0 x01 0 0
mtspr I V O R 0 ,r1 / * 0 : C r i t i c a l i n p u t * /
@ -217,26 +143,6 @@ _start_e500:
li r1 ,0 x0 f00
mtspr I V O R 1 5 ,r1 / * 1 5 : D e b u g * /
/ *
* Invalidate M M U L 1 / L 2
*
* Note : There i s a f i x u p e a r l i e r f o r E r r a t a C P U 4 o n
* Rev 1 p a r t s t h a t m u s t p r e c e d e t h i s M M U i n v a l i d a t i o n .
* /
li r2 , 0 x00 1 e
mtspr M M U C S R 0 , r2
isync
/ *
* Invalidate a l l T L B 0 e n t r i e s .
* /
li r3 ,4
li r4 ,0
tlbivax r4 ,r3
/ *
* To a v o i d R E V 1 E r r a t a C P U 6 i s s u e s , m a k e s u r e
* the i n s t r u c t i o n f o l l o w i n g t l b i v a x i s n o t a s t o r e .
* /
/ *
* After r e s e t , C C S R B A R i s l o c a t e d a t C F G _ C C S R B A R _ D E F A U L T , i . e .
@ -254,14 +160,14 @@ _start_e500:
lwzu r4 ,0 ( r5 ) / * h o w m a n y T L B 1 e n t r i e s w e a c t u a l l y u s e * /
mtctr r4
0 : lwzu r0 ,4 ( r5 )
lwzu r1 ,4 ( r5 )
lwzu r2 ,4 ( r5 )
lwzu r3 ,4 ( r5 )
mtspr M A S 0 ,r0
mtspr M A S 1 ,r1
mtspr M A S 2 ,r2
mtspr M A S 3 ,r3
0 : lwzu r6 ,4 ( r5 )
lwzu r7 ,4 ( r5 )
lwzu r8 ,4 ( r5 )
lwzu r9 ,4 ( r5 )
mtspr M A S 0 ,r6
mtspr M A S 1 ,r7
mtspr M A S 2 ,r8
mtspr M A S 3 ,r9
isync
msync
tlbwe
@ -271,22 +177,22 @@ _start_e500:
1 :
# if ( C F G _ C C S R B A R _ D E F A U L T ! = C F G _ C C S R B A R )
/* Special sequence needed to update CCSRBAR itself */
lis r4 , C F G _ C C S R B A R _ D E F A U L T @h
ori r4 , r4 , C F G _ C C S R B A R _ D E F A U L T @l
lis r4 ,C F G _ C C S R B A R _ D E F A U L T @h
ori r4 ,r4 ,C F G _ C C S R B A R _ D E F A U L T @l
lis r5 , C F G _ C C S R B A R @h
ori r5 , r5 , C F G _ C C S R B A R @l
lis r5 ,C F G _ C C S R B A R @h
ori r5 ,r5 ,C F G _ C C S R B A R @l
srwi r6 ,r5 ,1 2
stw r6 , 0 ( r4 )
stw r6 ,0 ( r4 )
isync
lis r5 , 0 x f f f f
lis r5 ,0 x f f f f
ori r5 ,r5 ,0 x f00 0
lwz r5 , 0 ( r5 )
lwz r5 ,0 ( r5 )
isync
lis r3 , C F G _ C C S R B A R @h
lwz r5 , C F G _ C C S R B A R @l(r3)
lis r3 ,C F G _ C C S R B A R @h
lwz r5 ,C F G _ C C S R B A R @l(r3)
isync
# endif
@ -300,8 +206,8 @@ _start_e500:
lwzu r5 ,0 ( r6 ) / * h o w m a n y w i n d o w s w e a c t u a l l y u s e * /
mtctr r5
li r2 ,0 x0 c28 / * t h e f i r s t p a i r i s r e s e r v e d f o r b o o t - o v e r - r i o - o r - p c i * /
li r1 ,0 x0 c30
li r2 ,0 x0 c28 / * t h e f i r s t p a i r i s r e s e r v e d f o r * /
li r1 ,0 x0 c30 / * b o o t - o v e r - r i o - o r - p c i * /
0 : lwzu r4 ,4 ( r6 )
lwzu r3 ,4 ( r6 )
@ -311,31 +217,6 @@ _start_e500:
addi r1 ,r1 ,0 x00 2 0
bdnz 0 b
/* Jump out the last 4K page and continue to 'normal' start */
1 : bl 3 f
b _ s t a r t
3 : li r0 ,0
mtspr S R R 1 ,r0 / * K e e p t h i n g s d i s a b l e d f o r n o w * /
mflr r1
mtspr S R R 0 ,r1
rfi
/ *
* r3 - 1 s t a r g t o b o a r d _ i n i t ( ) : I M M P p o i n t e r
* r4 - 2 n d a r g t o b o a r d _ i n i t ( ) : b o o t f l a g
* /
.text
.long 0x27051956 /* U-BOOT Magic Number */
.globl version_string
version_string :
.ascii U_BOOT_VERSION
.ascii " ( " , _ _ DATE_ _ , " - " , _ _ T I M E _ _ , " ) "
.ascii CONFIG_ I D E N T _ S T R I N G , " \ 0 "
. = EXC_ O F F _ S Y S _ R E S E T
.globl _start
_start :
/* Clear and set up some registers. */
li r0 ,0 x00 0 0
lis r1 ,0 x f f f f
@ -354,17 +235,14 @@ _start:
/* Enable Time Base and Select Time Base Clock */
lis r0 ,H I D 0 _ E M C P @h /* Enable machine check */
ori r0 ,r0 ,0 x40 0 0 / * t i m e b a s e i s p r o c e s s o r c l o c k * /
# if d e f i n e d ( C O N F I G _ E N A B L E _ 3 6 B I T _ P H Y S )
ori r0 ,r0 ,0 x00 8 0 / * e n a b l e M A S 7 u p d a t e s * /
ori r0 ,r0 ,( H I D 0 _ T B E N | H I D 0 _ E N M A S 7 ) @l /* Enable Timebase & MAS7 */
# else
ori r0 ,r0 ,H I D 0 _ T B E N @l /* enable Timebase */
# endif
mtspr H I D 0 ,r0
# if d e f i n e d ( C O N F I G _ A D D R _ S T R E A M I N G )
li r0 ,0 x30 0 0
# else
li r0 ,0 x10 0 0
# endif
li r0 ,( H I D 1 _ A S T M E | H I D 1 _ A B E ) @l /* Addr streaming & broadcast */
mtspr H I D 1 ,r0
/* Enable Branch Prediction */
@ -382,35 +260,56 @@ _start:
mtspr D B C R 0 ,r0
# endif
/* L1 DCache is used for initial RAM */
mfspr r2 , L 1 C S R 0
ori r2 , r2 , 0 x00 0 3
oris r2 , r2 , 0 x00 0 1
mtspr L 1 C S R 0 , r2 / * e n a b l e / i n v a l i d a t e L 1 D c a c h e * /
/* Jump out the last 4K page and continue to 'normal' start */
bl 3 f
b _ s t a r t _ c o n t
3 : li r0 ,0
mtspr S R R 1 ,r0 / * K e e p t h i n g s d i s a b l e d f o r n o w * /
mflr r1
mtspr S R R 0 ,r1
rfi
isync
.text
.globl _start
_start :
.long 0x27051956 /* U-BOOT Magic Number */
.globl version_string
version_string :
.ascii U_BOOT_VERSION
.ascii " ( " , _ _ DATE_ _ , " - " , _ _ T I M E _ _ , " ) "
.ascii CONFIG_ I D E N T _ S T R I N G , " \ 0 "
.align 4
.globl _start_cont
_start_cont :
/* L1 DCache is used for initial RAM */
/ * Allocate I n i t i a l R A M i n d a t a c a c h e .
* /
lis r3 , C F G _ I N I T _ R A M _ A D D R @h
ori r3 , r3 , C F G _ I N I T _ R A M _ A D D R @l
li r2 , 5 1 2 / * 5 1 2 * 3 2 =16K * /
lis r3 ,C F G _ I N I T _ R A M _ A D D R @h
ori r3 ,r3 ,C F G _ I N I T _ R A M _ A D D R @l
li r2 ,5 1 2 / * 5 1 2 * 3 2 =16K * /
mtctr r2
li r0 , 0
li r0 ,0
1 :
dcbz r0 , r3
dcbtls 0 ,r0 , r3
addi r3 , r3 , 3 2
dcbz r0 ,r3
dcbtls 0 ,r0 ,r3
addi r3 ,r3 ,3 2
bdnz 1 b
# ifndef C F G _ R A M B O O T
/* Calculate absolute address in FLASH and jump there */
/*--------------------------------------------------------------*/
lis r3 , C F G _ M O N I T O R _ B A S E @h
ori r3 , r3 , C F G _ M O N I T O R _ B A S E @l
addi r3 , r3 , i n _ f l a s h - _ s t a r t + E X C _ O F F _ S Y S _ R E S E T
lis r3 ,C F G _ M O N I T O R _ B A S E @h
ori r3 ,r3 ,C F G _ M O N I T O R _ B A S E @l
addi r3 ,r3 ,i n _ f l a s h - _ s t a r t + _ S T A R T _ O F F S E T
mtlr r3
blr
.global in_flash
in_flash :
# endif / * C F G _ R A M B O O T * /
@ -424,26 +323,24 @@ in_flash:
stwu r1 ,- 8 ( r1 ) / * S a v e b a c k c h a i n a n d m o v e S P * /
lis r0 ,R E S E T _ V E C T O R @h /* Address of reset vector */
ori r0 ,r0 , R E S E T _ V E C T O R @l
ori r0 ,r0 ,R E S E T _ V E C T O R @l
stwu r1 ,- 8 ( r1 ) / * S a v e b a c k c h a i n a n d m o v e S P * /
stw r0 ,+ 1 2 ( r1 ) / * S a v e r e t u r n a d d r ( u n d e r f l o w v e c t ) * /
GET_ G O T
bl c p u _ i n i t _ f
bl i c a c h e _ e n a b l e
bl b o a r d _ i n i t _ f
isync
/* --FIXME-- machine check with MCSRRn and rfmci */
. = EXC_ O F F _ S Y S _ R E S E T
.globl _start_of_vectors
_start_of_vectors :
# if 0
/* Critical input. */
CRIT_ E X C E P T I O N ( 0 x01 0 0 , C r i t c a l I n p u t , C r i t c a l I n p u t E x c e p t i o n )
# endif
/* Machine check --FIXME-- Should be MACH_EXCEPTION */
CRIT _ E X C E P T I O N ( 0 x0 2 0 0 , M a c h i n e C h e c k , M a c h i n e C h e c k E x c e p t i o n )
CRIT_ E X C E P T I O N ( 0 x01 0 0 , C r i t i c a l I n p u t , C r i t c a l I n p u t E x c e p t i o n )
/* Machine check */
MCK _ E X C E P T I O N ( 0 x20 0 , M a c h i n e C h e c k , M a c h i n e C h e c k E x c e p t i o n )
/* Data Storage exception. */
STD_ E X C E P T I O N ( 0 x03 0 0 , D a t a S t o r a g e , U n k n o w n E x c e p t i o n )
@ -452,7 +349,7 @@ _start_of_vectors:
STD_ E X C E P T I O N ( 0 x04 0 0 , I n s t S t o r a g e , U n k n o w n E x c e p t i o n )
/* External Interrupt exception. */
STD_ E X C E P T I O N ( 0 x05 0 0 , E x t I n t e r r u p t , U n k n o w n E x c e p t i o n )
STD_ E X C E P T I O N ( 0 x05 0 0 , E x t I n t e r r u p t , E x t I n t E x c e p t i o n )
/* Alignment exception. */
. = 0 x0 6 0 0
@ -469,8 +366,8 @@ Alignment:
mtlr r6
blrl
.L_Alignment :
.long AlignmentException - _ start + E X C _ O F F _ S Y S _ R E S E T
.long int_return - _ start + E X C _ O F F _ S Y S _ R E S E T
.long AlignmentException - _ start + _ S T A R T _ O F F S E T
.long int_return - _ start + _ S T A R T _ O F F S E T
/* Program check exception */
. = 0 x0 7 0 0
@ -483,8 +380,8 @@ ProgramCheck:
mtlr r6
blrl
.L_ProgramCheck :
.long ProgramCheckException - _ start + E X C _ O F F _ S Y S _ R E S E T
.long int_return - _ start + E X C _ O F F _ S Y S _ R E S E T
.long ProgramCheckException - _ start + _ S T A R T _ O F F S E T
.long int_return - _ start + _ S T A R T _ O F F S E T
/ * No F P U o n M P C 8 5 x x . T h i s e x c e p t i o n i s n o t s u p p o s e d t o h a p p e n .
* /
@ -496,23 +393,23 @@ ProgramCheck:
* r3 - . . . a r g u m e n t s
* /
SystemCall :
addis r11 ,r0 ,0 / * g e t f u n c t i o n s t a b l e a d d r * /
ori r11 ,r11 ,0 / * N o t e : t h i s c o d e i s p a t c h e d i n t r a p _ i n i t * /
addis r12 ,r0 ,0 / * g e t n u m b e r o f f u n c t i o n s * /
addis r11 ,r0 ,0 / * g e t f u n c t i o n s t a b l e a d d r * /
ori r11 ,r11 ,0 / * N o t e : t h i s c o d e i s p a t c h e d i n t r a p _ i n i t * /
addis r12 ,r0 ,0 / * g e t n u m b e r o f f u n c t i o n s * /
ori r12 ,r12 ,0
cmplw 0 , r0 , r12
cmplw 0 ,r0 ,r12
bge 1 f
rlwinm r0 ,r0 ,2 ,0 ,3 1 / * f n _ a d d r = f n _ t b l [ r0 ] * /
rlwinm r0 ,r0 ,2 ,0 ,3 1 / * f n _ a d d r = f n _ t b l [ r0 ] * /
add r11 ,r11 ,r0
lwz r11 ,0 ( r11 )
li r20 ,0 x d00 - 4 / * G e t s t a c k p o i n t e r * /
li r20 ,0 x d00 - 4 / * G e t s t a c k p o i n t e r * /
lwz r12 ,0 ( r20 )
subi r12 ,r12 ,1 2 / * A d j u s t s t a c k p o i n t e r * /
subi r12 ,r12 ,1 2 / * A d j u s t s t a c k p o i n t e r * /
li r0 ,0 x c00 + _ e n d _ b a c k - S y s t e m C a l l
cmplw 0 , r0 , r12 / * C h e c k s t a c k o v e r f l o w * /
cmplw 0 ,r0 ,r12 / * C h e c k s t a c k o v e r f l o w * /
bgt 1 f
stw r12 ,0 ( r20 )
@ -570,7 +467,7 @@ _end_back:
_end_of_vectors :
. = 0 x2 1 0 0
. = . + ( 0 x1 0 0 - ( . & 0 x f f ) ) / * a l i g n f o r d e b u g * /
/ *
* This c o d e f i n i s h e s s a v i n g t h e r e g i s t e r s t o t h e e x c e p t i o n f r a m e
@ -655,26 +552,58 @@ crit_return:
REST_ G P R ( 3 1 , r1 )
lwz r2 ,_ N I P ( r1 ) / * R e s t o r e e n v i r o n m e n t * /
lwz r0 ,_ M S R ( r1 )
mtspr 9 9 0 ,r2 / * S R R 2 * /
mtspr 9 9 1 ,r0 / * S R R 3 * /
mtspr S P R N _ C S R R 0 ,r2
mtspr S P R N _ C S R R 1 ,r0
lwz r0 ,G P R 0 ( r1 )
lwz r2 ,G P R 2 ( r1 )
lwz r1 ,G P R 1 ( r1 )
SYNC
rfci
mck_return :
mfmsr r28 / * D i s a b l e i n t e r r u p t s * /
li r4 ,0
ori r4 ,r4 ,M S R _ E E
andc r28 ,r28 ,r4
SYNC / * S o m e c h i p r e v s n e e d t h i s . . . * /
mtmsr r28
SYNC
lwz r2 ,_ C T R ( r1 )
lwz r0 ,_ L I N K ( r1 )
mtctr r2
mtlr r0
lwz r2 ,_ X E R ( r1 )
lwz r0 ,_ C C R ( r1 )
mtspr X E R ,r2
mtcrf 0 x F F ,r0
REST_ 1 0 G P R S ( 3 , r1 )
REST_ 1 0 G P R S ( 1 3 , r1 )
REST_ 8 G P R S ( 2 3 , r1 )
REST_ G P R ( 3 1 , r1 )
lwz r2 ,_ N I P ( r1 ) / * R e s t o r e e n v i r o n m e n t * /
lwz r0 ,_ M S R ( r1 )
mtspr S P R N _ M C S R R 0 ,r2
mtspr S P R N _ M C S R R 1 ,r0
lwz r0 ,G P R 0 ( r1 )
lwz r2 ,G P R 2 ( r1 )
lwz r1 ,G P R 1 ( r1 )
SYNC
rfmci
/ * Cache f u n c t i o n s .
* /
invalidate_icache :
mfspr r0 ,L 1 C S R 1
ori r0 ,r0 ,0 x00 0 2
ori r0 ,r0 ,L 1 C S R 1 _ I C F I
msync
isync
mtspr L 1 C S R 1 ,r0
isync
blr / * e n t i r e I c a c h e * /
blr / * e n t i r e I c a c h e * /
invalidate_dcache :
mfspr r0 ,L 1 C S R 0
ori r0 ,r0 ,0 x00 0 2
ori r0 ,r0 ,L 1 C S R 0 _ D C F I
msync
isync
mtspr L 1 C S R 0 ,r0
@ -697,9 +626,9 @@ icache_enable:
.globl icache_disable
icache_disable :
mfspr r0 ,L 1 C S R 1
lis r1 ,0 x f f f f f f f e @h
ori r1 ,r1 ,0 x f f f f f f f e @l
and r0 ,r0 ,r1
lis r3 ,0
ori r3 ,r3 ,L 1 C S R 1 _ I C E
andc r0 ,r0 ,r3
mtspr L 1 C S R 1 ,r0
isync
blr
@ -707,7 +636,7 @@ icache_disable:
.globl icache_status
icache_status :
mfspr r3 ,L 1 C S R 1
andi. r3 ,r3 ,1
andi. r3 ,r3 ,L 1 C S R 1 _ I C E
blr
.globl dcache_enable
@ -727,12 +656,10 @@ dcache_enable:
.globl dcache_disable
dcache_disable :
mfspr r0 ,L 1 C S R 0
lis r1 ,0 x f f f f f f f e @h
ori r1 ,r1 ,0 x f f f f f f f e @l
and r0 ,r0 ,r1
msync
isync
mfspr r3 ,L 1 C S R 0
lis r4 ,0
ori r4 ,r4 ,L 1 C S R 0 _ D C E
andc r3 ,r3 ,r4
mtspr L 1 C S R 0 ,r0
isync
blr
@ -740,27 +667,27 @@ dcache_disable:
.globl dcache_status
dcache_status :
mfspr r3 ,L 1 C S R 0
andi. r3 ,r3 ,1
andi. r3 ,r3 ,L 1 C S R 0 _ D C E
blr
.globl get_pir
get_pir :
mfspr r3 , P I R
mfspr r3 ,P I R
blr
.globl get_pvr
get_pvr :
mfspr r3 , P V R
mfspr r3 ,P V R
blr
.globl get_svr
get_svr :
mfspr r3 , S V R
mfspr r3 ,S V R
blr
.globl wr_tcr
wr_tcr :
mtspr T C R , r3
mtspr T C R ,r3
blr
/*------------------------------------------------------------------------------- */
@ -913,16 +840,16 @@ ppcSync:
* /
.globl relocate_code
relocate_code :
mr r1 , r3 / * S e t n e w s t a c k p o i n t e r * /
mr r9 , r4 / * S a v e c o p y o f I n i t D a t a p o i n t e r * /
mr r10 , r5 / * S a v e c o p y o f D e s t i n a t i o n A d d r e s s * /
mr r1 ,r3 / * S e t n e w s t a c k p o i n t e r * /
mr r9 ,r4 / * S a v e c o p y o f I n i t D a t a p o i n t e r * /
mr r10 ,r5 / * S a v e c o p y o f D e s t i n a t i o n A d d r e s s * /
mr r3 , r5 / * D e s t i n a t i o n A d d r e s s * /
lis r4 , C F G _ M O N I T O R _ B A S E @h /* Source Address */
ori r4 , r4 , C F G _ M O N I T O R _ B A S E @l
mr r3 ,r5 / * D e s t i n a t i o n A d d r e s s * /
lis r4 ,C F G _ M O N I T O R _ B A S E @h /* Source Address */
ori r4 ,r4 ,C F G _ M O N I T O R _ B A S E @l
lwz r5 ,G O T ( _ _ i n i t _ e n d )
sub r5 ,r5 ,r4
li r6 , C F G _ C A C H E L I N E _ S I Z E / * C a c h e L i n e S i z e * /
li r6 ,C F G _ C A C H E L I N E _ S I Z E / * C a c h e L i n e S i z e * /
/ *
* Fix G O T p o i n t e r :
@ -931,12 +858,12 @@ relocate_code:
*
* Offset :
* /
sub r15 , r10 , r4
sub r15 ,r10 ,r4
/* First our own GOT */
add r14 , r14 , r15
add r14 ,r14 ,r15
/* the the one used by the C code */
add r30 , r30 , r15
add r30 ,r30 ,r15
/ *
* Now r e l o c a t e c o d e
@ -997,10 +924,10 @@ relocate_code:
* initialization, n o w r u n n i n g f r o m R A M .
* /
addi r0 , r10 , i n _ r a m - _ s t a r t + E X C _ O F F _ S Y S _ R E S E T
addi r0 ,r10 ,i n _ r a m - _ s t a r t + _ S T A R T _ O F F S E T
mtlr r0
blr / * N E V E R R E T U R N S ! * /
.globl in_ram
in_ram :
/ *
@ -1044,19 +971,19 @@ clear_bss:
lwz r3 ,G O T ( _ _ b s s _ s t a r t )
lwz r4 ,G O T ( _ e n d )
cmplw 0 , r3 , r4
cmplw 0 ,r3 ,r4
beq 6 f
li r0 , 0
li r0 ,0
5 :
stw r0 , 0 ( r3 )
addi r3 , r3 , 4
cmplw 0 , r3 , r4
stw r0 ,0 ( r3 )
addi r3 ,r3 ,4
cmplw 0 ,r3 ,r4
bne 5 b
6 :
mr r3 , r9 / * I n i t D a t a p o i n t e r * /
mr r4 , r10 / * D e s t i n a t i o n A d d r e s s * /
mr r3 ,r9 / * I n i t D a t a p o i n t e r * /
mr r4 ,r10 / * D e s t i n a t i o n A d d r e s s * /
bl b o a r d _ i n i t _ r
/ *
@ -1067,52 +994,54 @@ clear_bss:
* /
.globl trap_init
trap_init :
lwz r7 , G O T ( _ s t a r t )
lwz r8 , G O T ( _ e n d _ o f _ v e c t o r s )
lwz r7 ,G O T ( _ s t a r t _ o f _ v e c t o r s )
lwz r8 ,G O T ( _ e n d _ o f _ v e c t o r s )
li r9 , 0 x10 0 / * r e s e t v e c t o r a l w a y s a t 0 x10 0 * /
li r9 ,0 x10 0 / * r e s e t v e c t o r a l w a y s a t 0 x10 0 * /
cmplw 0 , r7 , r8
cmplw 0 ,r7 ,r8
bgelr / * r e t u r n i f r7 > =r8 - j u s t i n c a s e * /
mflr r4 / * s a v e l i n k r e g i s t e r * /
1 :
lwz r0 , 0 ( r7 )
stw r0 , 0 ( r9 )
addi r7 , r7 , 4
addi r9 , r9 , 4
cmplw 0 , r7 , r8
lwz r0 ,0 ( r7 )
stw r0 ,0 ( r9 )
addi r7 ,r7 ,4
addi r9 ,r9 ,4
cmplw 0 ,r7 ,r8
bne 1 b
/ *
* relocate ` h d l r ' a n d ` i n t _ r e t u r n ' e n t r i e s
* /
li r7 , . L _ M a c h i n e C h e c k - _ s t a r t + E X C _ O F F _ S Y S _ R E S E T
li r7 ,. L _ C r i t i c a l I n p u t - _ s t a r t + _ S T A R T _ O F F S E T
bl t r a p _ r e l o c
li r7 , . L _ D a t a S t o r a g e - _ s t a r t + E X C _ O F F _ S Y S _ R E S E T
li r7 ,. L _ M a c h i n e C h e c k - _ s t a r t + _ S T A R T _ O F F S E T
bl t r a p _ r e l o c
li r7 , . L _ I n s t S t o r a g e - _ s t a r t + E X C _ O F F _ S Y S _ R E S E T
li r7 ,. L _ D a t a S t o r a g e - _ s t a r t + _ S T A R T _ O F F S E T
bl t r a p _ r e l o c
li r7 , . L _ E x t I n t e r r u p t - _ s t a r t + E X C _ O F F _ S Y S _ R E S E T
li r7 ,. L _ I n s t S t o r a g e - _ s t a r t + _ S T A R T _ O F F S E T
bl t r a p _ r e l o c
li r7 , . L _ A l i g n m e n t - _ s t a r t + E X C _ O F F _ S Y S _ R E S E T
li r7 ,. L _ E x t I n t e r r u p t - _ s t a r t + _ S T A R T _ O F F S E T
bl t r a p _ r e l o c
li r7 , . L _ P r o g r a m C h e c k - _ s t a r t + E X C _ O F F _ S Y S _ R E S E T
li r7 ,. L _ A l i g n m e n t - _ s t a r t + _ S T A R T _ O F F S E T
bl t r a p _ r e l o c
li r7 , . L _ F P U n a v a i l a b l e - _ s t a r t + E X C _ O F F _ S Y S _ R E S E T
li r7 ,. L _ P r o g r a m C h e c k - _ s t a r t + _ S T A R T _ O F F S E T
bl t r a p _ r e l o c
li r7 , . L _ D e c r e m e n t e r - _ s t a r t + E X C _ O F F _ S Y S _ R E S E T
li r7 ,. L _ F P U n a v a i l a b l e - _ s t a r t + _ S T A R T _ O F F S E T
bl t r a p _ r e l o c
li r7 , . L _ I n t e r v a l T i m e r - _ s t a r t + E X C _ O F F _ S Y S _ R E S E T
li r8 , _ e n d _ o f _ v e c t o r s - _ s t a r t + E X C _ O F F _ S Y S _ R E S E T
li r7 ,. L _ D e c r e m e n t e r - _ s t a r t + _ S T A R T _ O F F S E T
bl t r a p _ r e l o c
li r7 ,. L _ I n t e r v a l T i m e r - _ s t a r t + _ S T A R T _ O F F S E T
li r8 ,_ e n d _ o f _ v e c t o r s - _ s t a r t + _ S T A R T _ O F F S E T
2 :
bl t r a p _ r e l o c
addi r7 , r7 , 0 x10 0 / * n e x t e x c e p t i o n v e c t o r * /
cmplw 0 , r7 , r8
addi r7 ,r7 ,0 x10 0 / * n e x t e x c e p t i o n v e c t o r * /
cmplw 0 ,r7 ,r8
blt 2 b
lis r7 ,0 x0
mtspr I V P R , r7
mtspr I V P R ,r7
mtlr r4 / * r e s t o r e l i n k r e g i s t e r * /
blr
@ -1121,13 +1050,13 @@ trap_init:
* Function : relocate e n t r i e s f o r o n e e x c e p t i o n v e c t o r
* /
trap_reloc :
lwz r0 , 0 ( r7 ) / * h d l r . . . * /
add r0 , r0 , r3 / * . . . + = d e s t _ a d d r * /
stw r0 , 0 ( r7 )
lwz r0 ,0 ( r7 ) / * h d l r . . . * /
add r0 ,r0 ,r3 / * . . . + = d e s t _ a d d r * /
stw r0 ,0 ( r7 )
lwz r0 , 4 ( r7 ) / * i n t _ r e t u r n . . . * /
add r0 , r0 , r3 / * . . . + = d e s t _ a d d r * /
stw r0 , 4 ( r7 )
lwz r0 ,4 ( r7 ) / * i n t _ r e t u r n . . . * /
add r0 ,r0 ,r3 / * . . . + = d e s t _ a d d r * /
stw r0 ,4 ( r7 )
blr
@ -1135,13 +1064,13 @@ trap_reloc:
.globl unlock_ram_in_cache
unlock_ram_in_cache :
/* invalidate the INIT_RAM section */
lis r3 , ( C F G _ I N I T _ R A M _ A D D R & ~ 3 1 ) @h
ori r3 , r3 , ( C F G _ I N I T _ R A M _ A D D R & ~ 3 1 ) @l
li r2 ,5 1 2
mtctr r2
1 : icbi r0 , r3
dcbi r0 , r3
addi r3 , r3 , 3 2
lis r3 ,( C F G _ I N I T _ R A M _ A D D R & ~ 3 1 ) @h
ori r3 ,r3 ,( C F G _ I N I T _ R A M _ A D D R & ~ 3 1 ) @l
li r4 ,5 1 2
mtctr r4
1 : icbi r0 ,r3
dcbi r0 ,r3
addi r3 ,r3 ,3 2
bdnz 1 b
sync / * W a i t f o r a l l i c b i t o c o m p l e t e o n b u s * /
isync