Stefan Roese
18 years ago
commit
621a7873ef
@ -0,0 +1,51 @@ |
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#
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# (C) Copyright 2007
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o cmd_katmai.o
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SOBJS = init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend *~
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,267 @@ |
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/*
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* (C) Copyright 2007 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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* |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <i2c.h> |
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#include <asm/byteorder.h> |
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static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
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{ |
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uchar chip; |
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ulong data; |
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int nbytes; |
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extern char console_buffer[]; |
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char sysClock[4]; |
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char cpuClock[4]; |
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char plbClock[4]; |
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char pcixClock[4]; |
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if (argc < 3) { |
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printf ("Usage:\n%s\n", cmdtp->usage); |
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return 1; |
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} |
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if (strcmp(argv[2], "prom0") == 0) |
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chip = IIC0_BOOTPROM_ADDR; |
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else |
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chip = IIC0_ALT_BOOTPROM_ADDR; |
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do { |
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printf("enter sys clock frequency 33 or 66 Mhz or quit to abort\n"); |
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nbytes = readline (" ? "); |
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if (strcmp(console_buffer, "quit") == 0) |
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return 0; |
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if ((strcmp(console_buffer, "33") != 0) & |
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(strcmp(console_buffer, "66") != 0)) |
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nbytes=0; |
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strcpy(sysClock, console_buffer); |
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} while (nbytes == 0); |
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do { |
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if (strcmp(sysClock, "66") == 0) { |
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printf("enter cpu clock frequency 400, 533 Mhz or quit to abort\n"); |
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} else { |
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#ifdef CONFIG_STRESS |
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printf("enter cpu clock frequency 400, 500, 533, 667 Mhz or quit to abort\n"); |
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#else |
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printf("enter cpu clock frequency 400, 500, 533 Mhz or quit to abort\n"); |
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#endif |
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} |
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nbytes = readline (" ? "); |
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if (strcmp(console_buffer, "quit") == 0) |
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return 0; |
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if (strcmp(sysClock, "66") == 0) { |
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if ((strcmp(console_buffer, "400") != 0) & |
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(strcmp(console_buffer, "533") != 0) |
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#ifdef CONFIG_STRESS |
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& (strcmp(console_buffer, "667") != 0) |
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#endif |
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) { |
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nbytes = 0; |
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} |
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} else { |
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if ((strcmp(console_buffer, "400") != 0) & |
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(strcmp(console_buffer, "500") != 0) & |
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(strcmp(console_buffer, "533") != 0) |
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#ifdef CONFIG_STRESS |
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& (strcmp(console_buffer, "667") != 0) |
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#endif |
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) { |
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nbytes = 0; |
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} |
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} |
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strcpy(cpuClock, console_buffer); |
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} while (nbytes == 0); |
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if (strcmp(cpuClock, "500") == 0) |
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strcpy(plbClock, "166"); |
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else if (strcmp(cpuClock, "533") == 0) |
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strcpy(plbClock, "133"); |
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else { |
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do { |
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if (strcmp(cpuClock, "400") == 0) |
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printf("enter plb clock frequency 100, 133 Mhz or quit to abort\n"); |
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#ifdef CONFIG_STRESS |
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if (strcmp(cpuClock, "667") == 0) |
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printf("enter plb clock frequency 133, 166 Mhz or quit to abort\n"); |
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#endif |
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nbytes = readline (" ? "); |
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if (strcmp(console_buffer, "quit") == 0) |
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return 0; |
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if (strcmp(cpuClock, "400") == 0) { |
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if ((strcmp(console_buffer, "100") != 0) & |
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(strcmp(console_buffer, "133") != 0)) |
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nbytes = 0; |
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} |
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#ifdef CONFIG_STRESS |
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if (strcmp(cpuClock, "667") == 0) { |
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if ((strcmp(console_buffer, "133") != 0) & |
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(strcmp(console_buffer, "166") != 0)) |
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nbytes = 0; |
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} |
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#endif |
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strcpy(plbClock, console_buffer); |
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} while (nbytes == 0); |
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} |
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do { |
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printf("enter Pci-X clock frequency 33, 66, 100 or 133 Mhz or quit to abort\n"); |
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nbytes = readline (" ? "); |
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if (strcmp(console_buffer, "quit") == 0) |
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return 0; |
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if ((strcmp(console_buffer, "33") != 0) & |
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(strcmp(console_buffer, "66") != 0) & |
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(strcmp(console_buffer, "100") != 0) & |
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(strcmp(console_buffer, "133") != 0)) { |
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nbytes = 0; |
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} |
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strcpy(pcixClock, console_buffer); |
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} while (nbytes == 0); |
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printf("\nsys clk = %sMhz\n", sysClock); |
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printf("cpu clk = %sMhz\n", cpuClock); |
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printf("plb clk = %sMhz\n", plbClock); |
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printf("Pci-X clk = %sMhz\n", pcixClock); |
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do { |
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printf("\npress [y] to write I2C bootstrap \n"); |
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printf("or [n] to abort. \n"); |
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printf("Don't forget to set board switches \n"); |
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printf("according to your choice before re-starting \n"); |
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printf("(refer to 440spe_uboot_kit_um_1_01.pdf) \n"); |
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nbytes = readline (" ? "); |
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if (strcmp(console_buffer, "n") == 0) |
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return 0; |
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} while (nbytes == 0); |
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if (strcmp(sysClock, "33") == 0) { |
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if ((strcmp(cpuClock, "400") == 0) & |
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(strcmp(plbClock, "100") == 0)) |
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data = 0x8678c206; |
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if ((strcmp(cpuClock, "400") == 0) & |
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(strcmp(plbClock, "133") == 0)) |
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data = 0x8678c2c6; |
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if ((strcmp(cpuClock, "500") == 0)) |
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data = 0x8778f2c6; |
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if ((strcmp(cpuClock, "533") == 0)) |
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data = 0x87790252; |
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#ifdef CONFIG_STRESS |
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if ((strcmp(cpuClock, "667") == 0) & |
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(strcmp(plbClock, "133") == 0)) |
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data = 0x87794256; |
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if ((strcmp(cpuClock, "667") == 0) & |
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(strcmp(plbClock, "166") == 0)) |
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data = 0x87794206; |
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#endif |
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} |
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if (strcmp(sysClock, "66") == 0) { |
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if ((strcmp(cpuClock, "400") == 0) & |
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(strcmp(plbClock, "100") == 0)) |
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data = 0x84706206; |
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if ((strcmp(cpuClock, "400") == 0) & |
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(strcmp(plbClock, "133") == 0)) |
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data = 0x847062c6; |
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if ((strcmp(cpuClock, "533") == 0)) |
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data = 0x85708206; |
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#ifdef CONFIG_STRESS |
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if ((strcmp(cpuClock, "667") == 0) & |
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(strcmp(plbClock, "133") == 0)) |
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data = 0x8570a256; |
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if ((strcmp(cpuClock, "667") == 0) & |
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(strcmp(plbClock, "166") == 0)) |
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data = 0x8570a206; |
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#endif |
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} |
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#ifdef DEBUG |
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printf(" pin strap0 to write in i2c = %x\n", data); |
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#endif /* DEBUG */ |
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if (i2c_write(chip, 0, 1, (uchar *)&data, 4) != 0) |
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printf("Error writing strap0 in %s\n", argv[2]); |
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if (strcmp(pcixClock, "33") == 0) |
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data = 0x00000701; |
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if (strcmp(pcixClock, "66") == 0) |
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data = 0x00000601; |
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if (strcmp(pcixClock, "100") == 0) |
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data = 0x00000501; |
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if (strcmp(pcixClock, "133") == 0) |
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data = 0x00000401; |
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if (strcmp(plbClock, "166") == 0) |
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data |= 0x05950000; |
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else |
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data |= 0x05A50000; |
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#ifdef DEBUG |
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printf(" pin strap1 to write in i2c = %x\n", data); |
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#endif /* DEBUG */ |
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udelay(1000); |
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if (i2c_write(chip, 4, 1, (uchar *)&data, 4) != 0) |
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printf("Error writing strap1 in %s\n", argv[2]); |
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return 0; |
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} |
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U_BOOT_CMD( |
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bootstrap, 3, 1, do_bootstrap, |
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"bootstrap - program the serial device strap\n", |
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"wrclk [prom0|prom1] - program the serial device strap\n" |
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); |
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@ -0,0 +1,38 @@ |
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# AMCC 440SPe Evaluation (Katmai) board
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#
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TEXT_BASE = 0xfffc0000
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PLATFORM_CPPFLAGS += -DCONFIG_440=1
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ifeq ($(debug),1) |
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PLATFORM_CPPFLAGS += -DDEBUG
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endif |
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ifeq ($(dbcr),1) |
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PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
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endif |
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@ -0,0 +1,108 @@ |
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/* |
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* (C) Copyright 2007 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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* |
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* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <ppc_asm.tmpl> |
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#include <config.h> |
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#include <asm-ppc/mmu.h> |
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/************************************************************************** |
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* TLB TABLE |
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* |
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* This table is used by the cpu boot code to setup the initial tlb |
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* entries. Rather than make broad assumptions in the cpu source tree, |
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* this table lets each board set things up however they like. |
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* |
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* Pointer to the table is returned in r1 |
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* |
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*************************************************************************/ |
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.section .bootpg,"ax" |
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/************************************************************************** |
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* TLB table for revA |
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*************************************************************************/ |
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.globl tlbtabA
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tlbtabA: |
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tlbtab_start |
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tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G) |
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|
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/* |
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* TLB entries for SDRAM are not needed on this platform. |
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* They are dynamically generated in the SPD DDR(2) detection |
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* routine. |
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*/ |
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|
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tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I) |
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tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I) |
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|
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tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) |
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tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) |
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tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) |
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tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I) |
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|
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tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) |
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tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) |
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tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) |
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tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I) |
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tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I) |
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tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I) |
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tlbtab_end |
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|
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/************************************************************************** |
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* TLB table for revB |
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* |
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* Notice: revB of the 440SPe chip is very strict about PLB real addresses |
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* and ranges to be mapped for config space: it seems to only work with |
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* d_nnnn_nnnn range (hangs the core upon config transaction attempts when |
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* set otherwise) while revA uses c_nnnn_nnnn. |
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*************************************************************************/ |
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.globl tlbtabB
|
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tlbtabB: |
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tlbtab_start |
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tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G) |
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|
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/* |
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* TLB entries for SDRAM are not needed on this platform. |
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* They are dynamically generated in the SPD DDR(2) detection |
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* routine. |
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*/ |
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|
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tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I) |
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|
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tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I) |
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|
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tlbentry(CFG_ACE_BASE, SZ_1K, 0xE0000000, 4,AC_R|AC_W|SA_G|SA_I) |
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|
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tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) |
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tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) |
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tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) |
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|
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tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I) |
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tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I) |
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tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I) |
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tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I) |
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tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I) |
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tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I) |
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tlbtab_end |
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@ -0,0 +1,514 @@ |
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/*
|
||||
* (C) Copyright 2007 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <ppc4xx.h> |
||||
#include <asm/processor.h> |
||||
#include <i2c.h> |
||||
#include <asm-ppc/io.h> |
||||
|
||||
#include "katmai.h" |
||||
#include "../cpu/ppc4xx/440spe_pcie.h" |
||||
|
||||
#undef PCIE_ENDPOINT |
||||
/* #define PCIE_ENDPOINT 1 */ |
||||
|
||||
int ppc440spe_init_pcie_rootport(int port); |
||||
void ppc440spe_setup_pcie(struct pci_controller *hose, int port); |
||||
|
||||
int board_early_init_f (void) |
||||
{ |
||||
unsigned long mfr; |
||||
unsigned long pfc; |
||||
|
||||
/*----------------------------------------------------------------------+
|
||||
* Interrupt controller setup for the Katmai 440SPe Evaluation board. |
||||
*-----------------------------------------------------------------------+ |
||||
*-----------------------------------------------------------------------+ |
||||
* Interrupt | Source | Pol. | Sensi.| Crit. | |
||||
*-----------+-----------------------------------+-------+-------+-------+ |
||||
* IRQ 00 | UART0 | High | Level | Non | |
||||
* IRQ 01 | UART1 | High | Level | Non | |
||||
* IRQ 02 | IIC0 | High | Level | Non | |
||||
* IRQ 03 | IIC1 | High | Level | Non | |
||||
* IRQ 04 | PCI0X0 MSG IN | High | Level | Non | |
||||
* IRQ 05 | PCI0X0 CMD Write | High | Level | Non | |
||||
* IRQ 06 | PCI0X0 Power Mgt | High | Level | Non | |
||||
* IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non | |
||||
* IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non | |
||||
* IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non | |
||||
* IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non | |
||||
* IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit | |
||||
* IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non | |
||||
* IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non | |
||||
* IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non | |
||||
* IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non | |
||||
* IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non | |
||||
* IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit | |
||||
* IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non | |
||||
* IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non | |
||||
* IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non | |
||||
* IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non | |
||||
* IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non | |
||||
* IRQ 23 | I2O Inbound Doorbell | High | Level | Non | |
||||
* IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non | |
||||
* IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non | |
||||
* IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non | |
||||
* IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non | |
||||
* IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non | |
||||
* IRQ 29 | GPT Down Count Timer | Rising| Edge | Non | |
||||
* IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non | |
||||
* IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. | |
||||
*------------------------------------------------------------------------ |
||||
* IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non | |
||||
* IRQ 33 | MAL Serr | High | Level | Non | |
||||
* IRQ 34 | MAL Txde | High | Level | Non | |
||||
* IRQ 35 | MAL Rxde | High | Level | Non | |
||||
* IRQ 36 | DMC CE or DMC UE | High | Level | Non | |
||||
* IRQ 37 | EBC or UART2 | High |Lvl Edg| Non | |
||||
* IRQ 38 | MAL TX EOB | High | Level | Non | |
||||
* IRQ 39 | MAL RX EOB | High | Level | Non | |
||||
* IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non | |
||||
* IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non | |
||||
* IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non | |
||||
* IRQ 43 | L2 Cache | Risin | Edge | Non | |
||||
* IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non | |
||||
* IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non | |
||||
* IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non | |
||||
* IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | |
||||
* IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | |
||||
* IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non | |
||||
* IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non | |
||||
* IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non | |
||||
* IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | |
||||
* IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non | |
||||
* IRQ 54 | DMA Error | High | Level | Non | |
||||
* IRQ 55 | DMA I2O Error | High | Level | Non | |
||||
* IRQ 56 | Serial ROM | High | Level | Non | |
||||
* IRQ 57 | PCIX0 Error | High | Edge | Non | |
||||
* IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non | |
||||
* IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non | |
||||
* IRQ 60 | EMAC0 Interrupt | High | Level | Non | |
||||
* IRQ 61 | EMAC0 Wake-up | High | Level | Non | |
||||
* IRQ 62 | Reserved | High | Level | Non | |
||||
* IRQ 63 | XOR | High | Level | Non | |
||||
*----------------------------------------------------------------------- |
||||
* IRQ 64 | PE0 AL | High | Level | Non | |
||||
* IRQ 65 | PE0 VPD Access | Risin | Edge | Non | |
||||
* IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | |
||||
* IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | |
||||
* IRQ 68 | PE0 TCR | High | Level | Non | |
||||
* IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | |
||||
* IRQ 70 | PE0 DCR Error | High | Level | Non | |
||||
* IRQ 71 | Reserved | N/A | N/A | Non | |
||||
* IRQ 72 | PE1 AL | High | Level | Non | |
||||
* IRQ 73 | PE1 VPD Access | Risin | Edge | Non | |
||||
* IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | |
||||
* IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | |
||||
* IRQ 76 | PE1 TCR | High | Level | Non | |
||||
* IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | |
||||
* IRQ 78 | PE1 DCR Error | High | Level | Non | |
||||
* IRQ 79 | Reserved | N/A | N/A | Non | |
||||
* IRQ 80 | PE2 AL | High | Level | Non | |
||||
* IRQ 81 | PE2 VPD Access | Risin | Edge | Non | |
||||
* IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | |
||||
* IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | |
||||
* IRQ 84 | PE2 TCR | High | Level | Non | |
||||
* IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | |
||||
* IRQ 86 | PE2 DCR Error | High | Level | Non | |
||||
* IRQ 87 | Reserved | N/A | N/A | Non | |
||||
* IRQ 88 | External IRQ(5) | Progr | Progr | Non | |
||||
* IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | |
||||
* IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | |
||||
* IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | |
||||
* IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | |
||||
* IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | |
||||
* IRQ 94 | Reserved | N/A | N/A | Non | |
||||
* IRQ 95 | Reserved | N/A | N/A | Non | |
||||
*----------------------------------------------------------------------- |
||||
* IRQ 96 | PE0 INTA | High | Level | Non | |
||||
* IRQ 97 | PE0 INTB | High | Level | Non | |
||||
* IRQ 98 | PE0 INTC | High | Level | Non | |
||||
* IRQ 99 | PE0 INTD | High | Level | Non | |
||||
* IRQ 100 | PE1 INTA | High | Level | Non | |
||||
* IRQ 101 | PE1 INTB | High | Level | Non | |
||||
* IRQ 102 | PE1 INTC | High | Level | Non | |
||||
* IRQ 103 | PE1 INTD | High | Level | Non | |
||||
* IRQ 104 | PE2 INTA | High | Level | Non | |
||||
* IRQ 105 | PE2 INTB | High | Level | Non | |
||||
* IRQ 106 | PE2 INTC | High | Level | Non | |
||||
* IRQ 107 | PE2 INTD | Risin | Edge | Non | |
||||
* IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non | |
||||
* IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non | |
||||
* IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non | |
||||
* IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non | |
||||
* IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non | |
||||
* IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non | |
||||
* IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non | |
||||
* IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non | |
||||
* IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non | |
||||
* IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non | |
||||
* IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non | |
||||
* IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non | |
||||
* IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non | |
||||
* IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non | |
||||
* IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non | |
||||
* IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non | |
||||
* IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non | |
||||
* IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non | |
||||
* IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non | |
||||
* IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non | |
||||
*-----------+-----------------------------------+-------+-------+-------+ */ |
||||
/*-------------------------------------------------------------------------+
|
||||
* Put UICs in PowerPC440SPemode. |
||||
* Initialise UIC registers. Clear all interrupts. Disable all interrupts. |
||||
* Set critical interrupt values. Set interrupt polarities. Set interrupt |
||||
* trigger levels. Make bit 0 High priority. Clear all interrupts again. |
||||
*------------------------------------------------------------------------*/ |
||||
mtdcr (uic3sr, 0xffffffff); /* Clear all interrupts */ |
||||
mtdcr (uic3er, 0x00000000); /* disable all interrupts */ |
||||
mtdcr (uic3cr, 0x00000000); /* Set Critical / Non Critical interrupts: */ |
||||
mtdcr (uic3pr, 0xffffffff); /* Set Interrupt Polarities*/ |
||||
mtdcr (uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */ |
||||
mtdcr (uic3vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ |
||||
mtdcr (uic3sr, 0x00000000); /* clear all interrupts*/ |
||||
mtdcr (uic3sr, 0xffffffff); /* clear all interrupts*/ |
||||
|
||||
|
||||
mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */ |
||||
mtdcr (uic2er, 0x00000000); /* disable all interrupts*/ |
||||
mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts*/ |
||||
mtdcr (uic2pr, 0xebebebff); /* Set Interrupt Polarities*/ |
||||
mtdcr (uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */ |
||||
mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ |
||||
mtdcr (uic2sr, 0x00000000); /* clear all interrupts */ |
||||
mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */ |
||||
|
||||
mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts*/ |
||||
mtdcr (uic1er, 0x00000000); /* disable all interrupts*/ |
||||
mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts*/ |
||||
mtdcr (uic1pr, 0xffffffff); /* Set Interrupt Polarities */ |
||||
mtdcr (uic1tr, 0x001f8040); /* Set Interrupt Trigger Levels*/ |
||||
mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ |
||||
mtdcr (uic1sr, 0x00000000); /* clear all interrupts*/ |
||||
mtdcr (uic1sr, 0xffffffff); /* clear all interrupts*/ |
||||
|
||||
mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */ |
||||
mtdcr (uic0er, 0x00000000); /* disable all interrupts excepted cascade to be checked */ |
||||
mtdcr (uic0cr, 0x00104001); /* Set Critical / Non Critical interrupts*/ |
||||
mtdcr (uic0pr, 0xffffffff); /* Set Interrupt Polarities*/ |
||||
mtdcr (uic0tr, 0x010f0004); /* Set Interrupt Trigger Levels */ |
||||
mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ |
||||
mtdcr (uic0sr, 0x00000000); /* clear all interrupts*/ |
||||
mtdcr (uic0sr, 0xffffffff); /* clear all interrupts*/ |
||||
|
||||
/* SDR0_MFR should be part of Ethernet init */ |
||||
mfsdr (sdr_mfr, mfr); |
||||
mfr &= ~SDR0_MFR_ECS_MASK; |
||||
/* mtsdr(sdr_mfr, mfr); */ |
||||
|
||||
/*
|
||||
* Setup GPIO signalling per defines in katmai.h |
||||
*/ |
||||
pfc = PFC0_KATMAI; |
||||
mtsdr(SDR0_PFC0, pfc); |
||||
|
||||
out32(GPIO0_OR_ADDR, GPIO_OR_KATMAI); |
||||
out32(GPIO0_ODR_ADDR, GPIO_ODR_KATMAI); |
||||
out32(GPIO0_TCR_ADDR, GPIO_TCR_KATMAI); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int checkboard (void) |
||||
{ |
||||
char *s = getenv("serial#"); |
||||
|
||||
printf("Board: Katmai - AMCC 440SPe Evaluation Board"); |
||||
if (s != NULL) { |
||||
puts(", serial# "); |
||||
puts(s); |
||||
} |
||||
putc('\n'); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#if defined(CFG_DRAM_TEST) |
||||
int testdram (void) |
||||
{ |
||||
uint *pstart = (uint *) 0x00000000; |
||||
uint *pend = (uint *) 0x08000000; |
||||
uint *p; |
||||
|
||||
for (p = pstart; p < pend; p++) |
||||
*p = 0xaaaaaaaa; |
||||
|
||||
for (p = pstart; p < pend; p++) { |
||||
if (*p != 0xaaaaaaaa) { |
||||
printf ("SDRAM test fails at: %08x\n", (uint) p); |
||||
return 1; |
||||
} |
||||
} |
||||
|
||||
for (p = pstart; p < pend; p++) |
||||
*p = 0x55555555; |
||||
|
||||
for (p = pstart; p < pend; p++) { |
||||
if (*p != 0x55555555) { |
||||
printf ("SDRAM test fails at: %08x\n", (uint) p); |
||||
return 1; |
||||
} |
||||
} |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
/*************************************************************************
|
||||
* pci_pre_init |
||||
* |
||||
* This routine is called just prior to registering the hose and gives |
||||
* the board the opportunity to check things. Returning a value of zero |
||||
* indicates that things are bad & PCI initialization should be aborted. |
||||
* |
||||
* Different boards may wish to customize the pci controller structure |
||||
* (add regions, override default access routines, etc) or perform |
||||
* certain pre-initialization actions. |
||||
* |
||||
************************************************************************/ |
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) |
||||
int pci_pre_init(struct pci_controller * hose ) |
||||
{ |
||||
unsigned long strap; |
||||
|
||||
/*-------------------------------------------------------------------+
|
||||
* The katmai board is always configured as the host & requires the |
||||
* PCI arbiter to be enabled. |
||||
*-------------------------------------------------------------------*/ |
||||
mfsdr(sdr_sdstp1, strap); |
||||
if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) { |
||||
printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); |
||||
return 0; |
||||
} |
||||
|
||||
return 1; |
||||
} |
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ |
||||
|
||||
/*************************************************************************
|
||||
* pci_target_init |
||||
* |
||||
* The bootstrap configuration provides default settings for the pci |
||||
* inbound map (PIM). But the bootstrap config choices are limited and |
||||
* may not be sufficient for a given board. |
||||
* |
||||
************************************************************************/ |
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) |
||||
void pci_target_init(struct pci_controller * hose ) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/*-------------------------------------------------------------------+
|
||||
* Disable everything |
||||
*-------------------------------------------------------------------*/ |
||||
out32r( PCIX0_PIM0SA, 0 ); /* disable */ |
||||
out32r( PCIX0_PIM1SA, 0 ); /* disable */ |
||||
out32r( PCIX0_PIM2SA, 0 ); /* disable */ |
||||
out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ |
||||
|
||||
/*-------------------------------------------------------------------+
|
||||
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 |
||||
* strapping options to not support sizes such as 128/256 MB. |
||||
*-------------------------------------------------------------------*/ |
||||
out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); |
||||
out32r( PCIX0_PIM0LAH, 0 ); |
||||
out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); |
||||
out32r( PCIX0_BAR0, 0 ); |
||||
|
||||
/*-------------------------------------------------------------------+
|
||||
* Program the board's subsystem id/vendor id |
||||
*-------------------------------------------------------------------*/ |
||||
out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); |
||||
out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); |
||||
|
||||
out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); |
||||
} |
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
/*************************************************************************
|
||||
* is_pci_host |
||||
* |
||||
* This routine is called to determine if a pci scan should be |
||||
* performed. With various hardware environments (especially cPCI and |
||||
* PPMC) it's insufficient to depend on the state of the arbiter enable |
||||
* bit in the strap register, or generic host/adapter assumptions. |
||||
* |
||||
* Rather than hard-code a bad assumption in the general 440 code, the |
||||
* 440 pci code requires the board to decide at runtime. |
||||
* |
||||
* Return 0 for adapter mode, non-zero for host (monarch) mode. |
||||
* |
||||
* |
||||
************************************************************************/ |
||||
int is_pci_host(struct pci_controller *hose) |
||||
{ |
||||
/* The katmai board is always configured as host. */ |
||||
return 1; |
||||
} |
||||
|
||||
static struct pci_controller pcie_hose[3] = {{0},{0},{0}}; |
||||
|
||||
void pcie_setup_hoses(void) |
||||
{ |
||||
struct pci_controller *hose; |
||||
int i, bus; |
||||
|
||||
/*
|
||||
* assume we're called after the PCIX hose is initialized, which takes |
||||
* bus ID 0 and therefore start numbering PCIe's from 1. |
||||
*/ |
||||
bus = 1; |
||||
for (i = 0; i <= 2; i++) { |
||||
#ifdef PCIE_ENDPOINT |
||||
if (ppc440spe_init_pcie_endport(i)) { |
||||
#else |
||||
if (ppc440spe_init_pcie_rootport(i)) { |
||||
#endif |
||||
printf("PCIE%d: initialization failed\n", i); |
||||
continue; |
||||
} |
||||
|
||||
hose = &pcie_hose[i]; |
||||
hose->first_busno = bus; |
||||
hose->last_busno = bus; |
||||
bus++; |
||||
|
||||
/* setup mem resource */ |
||||
pci_set_region(hose->regions + 0, |
||||
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, |
||||
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, |
||||
CFG_PCIE_MEMSIZE, |
||||
PCI_REGION_MEM |
||||
); |
||||
hose->region_count = 1; |
||||
pci_register_hose(hose); |
||||
|
||||
#ifdef PCIE_ENDPOINT |
||||
ppc440spe_setup_pcie_endpoint(hose, i); |
||||
/*
|
||||
* Reson for no scanning is endpoint can not generate |
||||
* upstream configuration accesses. |
||||
*/ |
||||
#else |
||||
ppc440spe_setup_pcie_rootpoint(hose, i); |
||||
/*
|
||||
* Config access can only go down stream |
||||
*/ |
||||
hose->last_busno = pci_hose_scan(hose); |
||||
#endif |
||||
} |
||||
} |
||||
#endif /* defined(CONFIG_PCI) */ |
||||
|
||||
int misc_init_f (void) |
||||
{ |
||||
uint reg; |
||||
#if defined(CONFIG_STRESS) |
||||
uint i ; |
||||
uint disp; |
||||
#endif |
||||
|
||||
/* minimal init for PCIe */ |
||||
#if 0 /* test-only: test endpoint at some time, for now rootpoint only */
|
||||
/* pci express 0 Endpoint Mode */ |
||||
mfsdr(SDR0_PE0DLPSET, reg); |
||||
reg &= (~0x00400000); |
||||
mtsdr(SDR0_PE0DLPSET, reg); |
||||
#else |
||||
/* pci express 0 Rootpoint Mode */ |
||||
mfsdr(SDR0_PE0DLPSET, reg); |
||||
reg |= 0x00400000; |
||||
mtsdr(SDR0_PE0DLPSET, reg); |
||||
#endif |
||||
/* pci express 1 Rootpoint Mode */ |
||||
mfsdr(SDR0_PE1DLPSET, reg); |
||||
reg |= 0x00400000; |
||||
mtsdr(SDR0_PE1DLPSET, reg); |
||||
/* pci express 2 Rootpoint Mode */ |
||||
mfsdr(SDR0_PE2DLPSET, reg); |
||||
reg |= 0x00400000; |
||||
mtsdr(SDR0_PE2DLPSET, reg); |
||||
|
||||
#if defined(CONFIG_STRESS) |
||||
/*
|
||||
* All this setting done by linux only needed by stress an charac. test |
||||
* procedure |
||||
* PCIe 1 Rootpoint PCIe2 Endpoint |
||||
* PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level |
||||
*/ |
||||
for (i=0,disp=0; i<8; i++,disp+=3) { |
||||
mfsdr(SDR0_PE0HSSSET1L0+disp, reg); |
||||
reg |= 0x33000000; |
||||
mtsdr(SDR0_PE0HSSSET1L0+disp, reg); |
||||
} |
||||
|
||||
/*PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */ |
||||
for (i=0,disp=0; i<4; i++,disp+=3) { |
||||
mfsdr(SDR0_PE1HSSSET1L0+disp, reg); |
||||
reg |= 0x33000000; |
||||
mtsdr(SDR0_PE1HSSSET1L0+disp, reg); |
||||
} |
||||
|
||||
/*PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */ |
||||
for (i=0,disp=0; i<4; i++,disp+=3) { |
||||
mfsdr(SDR0_PE2HSSSET1L0+disp, reg); |
||||
reg |= 0x33000000; |
||||
mtsdr(SDR0_PE2HSSSET1L0+disp, reg); |
||||
} |
||||
|
||||
reg = 0x21242222; |
||||
mtsdr(SDR0_PE2UTLSET1, reg); |
||||
reg = 0x11000000; |
||||
mtsdr(SDR0_PE2UTLSET2, reg); |
||||
/* pci express 1 Endpoint Mode */ |
||||
reg = 0x00004000; |
||||
mtsdr(SDR0_PE2DLPSET, reg); |
||||
|
||||
mtsdr(SDR0_UART1, 0x2080005a); /* patch for TG */ |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_POST |
||||
/*
|
||||
* Returns 1 if keys pressed to start the power-on long-running tests |
||||
* Called from board_init_f(). |
||||
*/ |
||||
int post_hotkeys_pressed(void) |
||||
{ |
||||
return (ctrlc()); |
||||
} |
||||
#endif |
||||
@ -0,0 +1,65 @@ |
||||
/*
|
||||
* (C) Copyright 2007 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __KATMAI_H_ |
||||
#define __KATMAI_H_ |
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* XX |
||||
* XXXX XX XXX XXX XXXX |
||||
* XX XX XX XX XX XX |
||||
* XX XXX XX XX XX XX XX |
||||
* XX XX XXXXX XX XX XX |
||||
* XXXX XX XXXX XXXX |
||||
* XXXX |
||||
* |
||||
* The 440SPe provices 32 bits of GPIO. By default all GPIO pins |
||||
* are disabled, and must be explicitly enabled by setting a |
||||
* bit in the SDR0_PFC0 indirect DCR. Each GPIO maps 1-to-1 with the |
||||
* corresponding bit in the SDR0_PFC0 register (note that bit numbers |
||||
* reflect the PowerPC convention where bit 0 is the most-significant |
||||
* bit). |
||||
* |
||||
* Katmai specific: |
||||
* RS232_RX_EN# is held HIGH during reset by hardware, keeping the |
||||
* RS232_CTS, DSR & DCD signals coming from the MAX3411 (U26) in |
||||
* Hi-Z condition. This prevents contention between the MAX3411 (U26) |
||||
* and 74CBTLV3125PG (U2) during reset. |
||||
* |
||||
* RS232_RX_EN# is connected as GPIO pin 30. Once the processor |
||||
* is released from reset, this pin must be configured as an output and |
||||
* then driven high to enable the receive signals from the UART transciever. |
||||
*----------------------------------------------------------------------------*/ |
||||
#define GPIO_ENABLE(gpio) (0x80000000 >> (gpio)) |
||||
|
||||
#define PFC0_KATMAI GPIO_ENABLE(30) |
||||
#define GPIO_OR_KATMAI GPIO_ENABLE(30) /* Drive all outputs low except GPIO 30 */ |
||||
#define GPIO_TCR_KATMAI GPIO_ENABLE(30) |
||||
#define GPIO_ODR_KATMAI 0 /* Disable open drain for all outputs */ |
||||
|
||||
#define GPIO0_OR_ADDR (CFG_PERIPHERAL_BASE + 0x700) |
||||
#define GPIO0_TCR_ADDR (CFG_PERIPHERAL_BASE + 0x704) |
||||
#define GPIO0_ODR_ADDR (CFG_PERIPHERAL_BASE + 0x718) |
||||
#define GPIO0_IR_ADDR (CFG_PERIPHERAL_BASE + 0x71C) |
||||
|
||||
#endif /* __KATMAI_H_ */ |
||||
@ -0,0 +1,141 @@ |
||||
/* |
||||
* (C) Copyright 2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
.resetvec 0xFFFFFFFC : |
||||
{ |
||||
*(.resetvec) |
||||
} = 0xffff |
||||
|
||||
.bootpg 0xFFFFF000 : |
||||
{ |
||||
cpu/ppc4xx/start.o (.bootpg) |
||||
} = 0xffff |
||||
|
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/ppc4xx/start.o (.text) |
||||
board/amcc/katmai/init.o (.text) |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
*(.eh_frame) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
@ -1,267 +0,0 @@ |
||||
/*
|
||||
* Copyright (c) 2004 Picture Elements, Inc. |
||||
* Stephen Williams (XXXXXXXXXXXXXXXX) |
||||
* |
||||
* This source code is free software; you can redistribute it |
||||
* and/or modify it in source code form under the terms of the GNU |
||||
* General Public License as published by the Free Software |
||||
* Foundation; either version 2 of the License, or (at your option) |
||||
* any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA |
||||
*/ |
||||
#ident "$Id:$" |
||||
|
||||
/*
|
||||
* The Xilinx SystemACE chip support is activated by defining |
||||
* CONFIG_SYSTEMACE to turn on support, and CFG_SYSTEMACE_BASE |
||||
* to set the base address of the device. This code currently |
||||
* assumes that the chip is connected via a byte-wide bus. |
||||
* |
||||
* The CONFIG_SYSTEMACE also adds to fat support the device class |
||||
* "ace" that allows the user to execute "fatls ace 0" and the |
||||
* like. This works by making the systemace_get_dev function |
||||
* available to cmd_fat.c:get_dev and filling in a block device |
||||
* description that has all the bits needed for FAT support to |
||||
* read sectors. |
||||
* |
||||
* According to Xilinx technical support, before accessing the |
||||
* SystemACE CF you need to set the following control bits: |
||||
* FORCECFGMODE : 1 |
||||
* CFGMODE : 0 |
||||
* CFGSTART : 0 |
||||
*/ |
||||
|
||||
# include <common.h> |
||||
# include <command.h> |
||||
# include <systemace.h> |
||||
# include <part.h> |
||||
# include <asm/io.h> |
||||
|
||||
#ifdef CONFIG_SYSTEMACE |
||||
|
||||
/*
|
||||
* The ace_readw and writew functions read/write 16bit words, but the |
||||
* offset value is the BYTE offset as most used in the Xilinx |
||||
* datasheet for the SystemACE chip. The CFG_SYSTEMACE_BASE is defined |
||||
* to be the base address for the chip, usually in the local |
||||
* peripheral bus. |
||||
*/ |
||||
static unsigned ace_readw(unsigned offset) |
||||
{ |
||||
#if (CFG_SYSTEMACE_WIDTH == 8) |
||||
u16 temp; |
||||
|
||||
#if !defined(__BIG_ENDIAN) |
||||
temp =((u16)readb(CFG_SYSTEMACE_BASE+offset) << 8); |
||||
temp |= (u16)readb(CFG_SYSTEMACE_BASE+offset+1); |
||||
#else |
||||
temp = (u16)readb(CFG_SYSTEMACE_BASE+offset); |
||||
temp |=((u16)readb(CFG_SYSTEMACE_BASE+offset+1) << 8); |
||||
#endif |
||||
return temp; |
||||
#else |
||||
return readw(CFG_SYSTEMACE_BASE+offset); |
||||
#endif |
||||
} |
||||
|
||||
static void ace_writew(unsigned val, unsigned offset) |
||||
{ |
||||
#if (CFG_SYSTEMACE_WIDTH == 8) |
||||
#if !defined(__BIG_ENDIAN) |
||||
writeb((u8)(val>>8), CFG_SYSTEMACE_BASE+offset); |
||||
writeb((u8)val, CFG_SYSTEMACE_BASE+offset+1); |
||||
#else |
||||
writeb((u8)val, CFG_SYSTEMACE_BASE+offset); |
||||
writeb((u8)(val>>8), CFG_SYSTEMACE_BASE+offset+1); |
||||
#endif |
||||
#else |
||||
writew(val, CFG_SYSTEMACE_BASE+offset); |
||||
#endif |
||||
} |
||||
|
||||
/* */ |
||||
|
||||
static unsigned long systemace_read(int dev, |
||||
unsigned long start, |
||||
unsigned long blkcnt, |
||||
unsigned long *buffer); |
||||
|
||||
static block_dev_desc_t systemace_dev = {0}; |
||||
|
||||
static int get_cf_lock(void) |
||||
{ |
||||
int retry = 10; |
||||
|
||||
/* CONTROLREG = LOCKREG */ |
||||
unsigned val=ace_readw(0x18); |
||||
val|=0x0002; |
||||
ace_writew((val&0xffff), 0x18); |
||||
|
||||
/* Wait for MPULOCK in STATUSREG[15:0] */ |
||||
while (! (ace_readw(0x04) & 0x0002)) { |
||||
|
||||
if (retry < 0) |
||||
return -1; |
||||
|
||||
udelay(100000); |
||||
retry -= 1; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void release_cf_lock(void) |
||||
{ |
||||
unsigned val=ace_readw(0x18); |
||||
val&=~(0x0002); |
||||
ace_writew((val&0xffff), 0x18); |
||||
} |
||||
|
||||
block_dev_desc_t * systemace_get_dev(int dev) |
||||
{ |
||||
/* The first time through this, the systemace_dev object is
|
||||
not yet initialized. In that case, fill it in. */ |
||||
if (systemace_dev.blksz == 0) { |
||||
systemace_dev.if_type = IF_TYPE_UNKNOWN; |
||||
systemace_dev.dev = 0; |
||||
systemace_dev.part_type = PART_TYPE_UNKNOWN; |
||||
systemace_dev.type = DEV_TYPE_HARDDISK; |
||||
systemace_dev.blksz = 512; |
||||
systemace_dev.removable = 1; |
||||
systemace_dev.block_read = systemace_read; |
||||
|
||||
init_part(&systemace_dev); |
||||
|
||||
} |
||||
|
||||
return &systemace_dev; |
||||
} |
||||
|
||||
/*
|
||||
* This function is called (by dereferencing the block_read pointer in |
||||
* the dev_desc) to read blocks of data. The return value is the |
||||
* number of blocks read. A zero return indicates an error. |
||||
*/ |
||||
static unsigned long systemace_read(int dev, |
||||
unsigned long start, |
||||
unsigned long blkcnt, |
||||
unsigned long *buffer) |
||||
{ |
||||
int retry; |
||||
unsigned blk_countdown; |
||||
unsigned char*dp = (unsigned char*)buffer; |
||||
unsigned val; |
||||
|
||||
if (get_cf_lock() < 0) { |
||||
unsigned status = ace_readw(0x04); |
||||
|
||||
/* If CFDETECT is false, card is missing. */ |
||||
if (! (status&0x0010)) { |
||||
printf("** CompactFlash card not present. **\n"); |
||||
return 0; |
||||
} |
||||
|
||||
printf("**** ACE locked away from me (STATUSREG=%04x)\n", status); |
||||
return 0; |
||||
} |
||||
|
||||
#ifdef DEBUG_SYSTEMACE |
||||
printf("... systemace read %lu sectors at %lu\n", blkcnt, start); |
||||
#endif |
||||
|
||||
retry = 2000; |
||||
for (;;) { |
||||
val = ace_readw(0x04); |
||||
|
||||
/* If CFDETECT is false, card is missing. */ |
||||
if (! (val & 0x0010)) { |
||||
printf("**** ACE CompactFlash not found.\n"); |
||||
release_cf_lock(); |
||||
return 0; |
||||
} |
||||
|
||||
/* If RDYFORCMD, then we are ready to go. */ |
||||
if (val & 0x0100) |
||||
break; |
||||
|
||||
if (retry < 0) { |
||||
printf("**** SystemACE not ready.\n"); |
||||
release_cf_lock(); |
||||
return 0; |
||||
} |
||||
|
||||
udelay(1000); |
||||
retry -= 1; |
||||
} |
||||
|
||||
/* The SystemACE can only transfer 256 sectors at a time, so
|
||||
limit the current chunk of sectors. The blk_countdown |
||||
variable is the number of sectors left to transfer. */ |
||||
|
||||
blk_countdown = blkcnt; |
||||
while (blk_countdown > 0) { |
||||
unsigned trans = blk_countdown; |
||||
|
||||
if (trans > 256) trans = 256; |
||||
|
||||
#ifdef DEBUG_SYSTEMACE |
||||
printf("... transfer %lu sector in a chunk\n", trans); |
||||
#endif |
||||
/* Write LBA block address */ |
||||
ace_writew((start>> 0) & 0xffff, 0x10); |
||||
ace_writew((start>>16) & 0x00ff, 0x12); |
||||
|
||||
/* NOTE: in the Write Sector count below, a count of 0
|
||||
causes a transfer of 256, so &0xff gives the right |
||||
value for whatever transfer count we want. */ |
||||
|
||||
/* Write sector count | ReadMemCardData. */ |
||||
ace_writew((trans&0xff) | 0x0300, 0x14); |
||||
|
||||
/* Reset the configruation controller */ |
||||
val = ace_readw(0x18); |
||||
val|=0x0080; |
||||
ace_writew(val, 0x18); |
||||
|
||||
retry = trans * 16; |
||||
while (retry > 0) { |
||||
int idx; |
||||
|
||||
/* Wait for buffer to become ready. */ |
||||
while (! (ace_readw(0x04) & 0x0020)) { |
||||
udelay(100); |
||||
} |
||||
|
||||
/* Read 16 words of 2bytes from the sector buffer. */ |
||||
for (idx = 0 ; idx < 16 ; idx += 1) { |
||||
unsigned short val = ace_readw(0x40); |
||||
*dp++ = val & 0xff; |
||||
*dp++ = (val>>8) & 0xff; |
||||
} |
||||
|
||||
retry -= 1; |
||||
} |
||||
|
||||
/* Clear the configruation controller reset */ |
||||
val = ace_readw(0x18); |
||||
val&=~0x0080; |
||||
ace_writew(val, 0x18); |
||||
|
||||
/* Count the blocks we transfer this time. */ |
||||
start += trans; |
||||
blk_countdown -= trans; |
||||
} |
||||
|
||||
release_cf_lock(); |
||||
|
||||
return blkcnt; |
||||
} |
||||
#endif /* CONFIG_SYSTEMACE */ |
||||
@ -0,0 +1,469 @@ |
||||
/*
|
||||
* cpu/ppc4xx/40x_spd_sdram.c |
||||
* This SPD SDRAM detection code supports IBM/AMCC PPC44x cpu with a |
||||
* SDRAM controller. Those are all current 405 PPC's. |
||||
* |
||||
* (C) Copyright 2001 |
||||
* Bill Hunter, Wave 7 Optics, williamhunter@attbi.com |
||||
* |
||||
* Based on code by: |
||||
* |
||||
* Kenneth Johansson ,Ericsson AB. |
||||
* kenneth.johansson@etx.ericsson.se |
||||
* |
||||
* hacked up by bill hunter. fixed so we could run before |
||||
* serial_init and console_init. previous version avoided this by |
||||
* running out of cache memory during serial/console init, then running |
||||
* this code later. |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Jun Gu, Artesyn Technology, jung@artesyncp.com |
||||
* Support for AMCC 440 based on OpenBIOS draminit.c from IBM. |
||||
* |
||||
* (C) Copyright 2005 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/processor.h> |
||||
#include <i2c.h> |
||||
#include <ppc4xx.h> |
||||
|
||||
#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_440) |
||||
|
||||
/*
|
||||
* Set default values |
||||
*/ |
||||
#ifndef CFG_I2C_SPEED |
||||
#define CFG_I2C_SPEED 50000 |
||||
#endif |
||||
|
||||
#ifndef CFG_I2C_SLAVE |
||||
#define CFG_I2C_SLAVE 0xFE |
||||
#endif |
||||
|
||||
#define ONE_BILLION 1000000000 |
||||
|
||||
#define SDRAM0_CFG_DCE 0x80000000 |
||||
#define SDRAM0_CFG_SRE 0x40000000 |
||||
#define SDRAM0_CFG_PME 0x20000000 |
||||
#define SDRAM0_CFG_MEMCHK 0x10000000 |
||||
#define SDRAM0_CFG_REGEN 0x08000000 |
||||
#define SDRAM0_CFG_ECCDD 0x00400000 |
||||
#define SDRAM0_CFG_EMDULR 0x00200000 |
||||
#define SDRAM0_CFG_DRW_SHIFT (31-6) |
||||
#define SDRAM0_CFG_BRPF_SHIFT (31-8) |
||||
|
||||
#define SDRAM0_TR_CASL_SHIFT (31-8) |
||||
#define SDRAM0_TR_PTA_SHIFT (31-13) |
||||
#define SDRAM0_TR_CTP_SHIFT (31-15) |
||||
#define SDRAM0_TR_LDF_SHIFT (31-17) |
||||
#define SDRAM0_TR_RFTA_SHIFT (31-29) |
||||
#define SDRAM0_TR_RCD_SHIFT (31-31) |
||||
|
||||
#define SDRAM0_RTR_SHIFT (31-15) |
||||
#define SDRAM0_ECCCFG_SHIFT (31-11) |
||||
|
||||
/* SDRAM0_CFG enable macro */ |
||||
#define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT ) |
||||
|
||||
#define SDRAM0_BXCR_SZ_MASK 0x000e0000 |
||||
#define SDRAM0_BXCR_AM_MASK 0x0000e000 |
||||
|
||||
#define SDRAM0_BXCR_SZ_SHIFT (31-14) |
||||
#define SDRAM0_BXCR_AM_SHIFT (31-18) |
||||
|
||||
#define SDRAM0_BXCR_SZ(x) ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) ) |
||||
#define SDRAM0_BXCR_AM(x) ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) ) |
||||
|
||||
#ifdef CONFIG_SPDDRAM_SILENT |
||||
# define SPD_ERR(x) do { return 0; } while (0) |
||||
#else |
||||
# define SPD_ERR(x) do { printf(x); return(0); } while (0) |
||||
#endif |
||||
|
||||
#define sdram_HZ_to_ns(hertz) (1000000000/(hertz)) |
||||
|
||||
/* function prototypes */ |
||||
int spd_read(uint addr); |
||||
|
||||
|
||||
/*
|
||||
* This function is reading data from the DIMM module EEPROM over the SPD bus |
||||
* and uses that to program the sdram controller. |
||||
* |
||||
* This works on boards that has the same schematics that the AMCC walnut has. |
||||
* |
||||
* Input: null for default I2C spd functions or a pointer to a custom function |
||||
* returning spd_data. |
||||
*/ |
||||
|
||||
long int spd_sdram(int(read_spd)(uint addr)) |
||||
{ |
||||
int tmp,row,col; |
||||
int total_size,bank_size,bank_code; |
||||
int ecc_on; |
||||
int mode; |
||||
int bank_cnt; |
||||
|
||||
int sdram0_pmit=0x07c00000; |
||||
#ifndef CONFIG_405EP /* not on PPC405EP */ |
||||
int sdram0_besr0=-1; |
||||
int sdram0_besr1=-1; |
||||
int sdram0_eccesr=-1; |
||||
#endif |
||||
int sdram0_ecccfg; |
||||
|
||||
int sdram0_rtr=0; |
||||
int sdram0_tr=0; |
||||
|
||||
int sdram0_b0cr; |
||||
int sdram0_b1cr; |
||||
int sdram0_b2cr; |
||||
int sdram0_b3cr; |
||||
|
||||
int sdram0_cfg=0; |
||||
|
||||
int t_rp; |
||||
int t_rcd; |
||||
int t_ras; |
||||
int t_rc; |
||||
int min_cas; |
||||
|
||||
PPC405_SYS_INFO sys_info; |
||||
unsigned long bus_period_x_10; |
||||
|
||||
/*
|
||||
* get the board info |
||||
*/ |
||||
get_sys_info(&sys_info); |
||||
bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10); |
||||
|
||||
if (read_spd == 0){ |
||||
read_spd=spd_read; |
||||
/*
|
||||
* Make sure I2C controller is initialized |
||||
* before continuing. |
||||
*/ |
||||
i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); |
||||
} |
||||
|
||||
/* Make shure we are using SDRAM */ |
||||
if (read_spd(2) != 0x04) { |
||||
SPD_ERR("SDRAM - non SDRAM memory module found\n"); |
||||
} |
||||
|
||||
/* ------------------------------------------------------------------
|
||||
* configure memory timing register |
||||
* |
||||
* data from DIMM: |
||||
* 27 IN Row Precharge Time ( t RP) |
||||
* 29 MIN RAS to CAS Delay ( t RCD) |
||||
* 127 Component and Clock Detail ,clk0-clk3, junction temp, CAS |
||||
* -------------------------------------------------------------------*/ |
||||
|
||||
/*
|
||||
* first figure out which cas latency mode to use |
||||
* use the min supported mode |
||||
*/ |
||||
|
||||
tmp = read_spd(127) & 0x6; |
||||
if (tmp == 0x02) { /* only cas = 2 supported */ |
||||
min_cas = 2; |
||||
/* t_ck = read_spd(9); */ |
||||
/* t_ac = read_spd(10); */ |
||||
} else if (tmp == 0x04) { /* only cas = 3 supported */ |
||||
min_cas = 3; |
||||
/* t_ck = read_spd(9); */ |
||||
/* t_ac = read_spd(10); */ |
||||
} else if (tmp == 0x06) { /* 2,3 supported, so use 2 */ |
||||
min_cas = 2; |
||||
/* t_ck = read_spd(23); */ |
||||
/* t_ac = read_spd(24); */ |
||||
} else { |
||||
SPD_ERR("SDRAM - unsupported CAS latency \n"); |
||||
} |
||||
|
||||
/* get some timing values, t_rp,t_rcd,t_ras,t_rc
|
||||
*/ |
||||
t_rp = read_spd(27); |
||||
t_rcd = read_spd(29); |
||||
t_ras = read_spd(30); |
||||
t_rc = t_ras + t_rp; |
||||
|
||||
/* The following timing calcs subtract 1 before deviding.
|
||||
* this has effect of using ceiling instead of floor rounding, |
||||
* and also subtracting 1 to convert number to reg value |
||||
*/ |
||||
/* set up CASL */ |
||||
sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT; |
||||
/* set up PTA */ |
||||
sdram0_tr |= ((((t_rp - 1) * 10)/bus_period_x_10) & 0x3) << SDRAM0_TR_PTA_SHIFT; |
||||
/* set up CTP */ |
||||
tmp = (((t_rc - t_rcd - t_rp -1) * 10) / bus_period_x_10) & 0x3; |
||||
if (tmp < 1) |
||||
tmp = 1; |
||||
sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT; |
||||
/* set LDF = 2 cycles, reg value = 1 */ |
||||
sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT; |
||||
/* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */ |
||||
tmp = (((t_rc - 1) * 10) / bus_period_x_10) - 3; |
||||
if (tmp < 0) |
||||
tmp = 0; |
||||
if (tmp > 6) |
||||
tmp = 6; |
||||
sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT; |
||||
/* set RCD = t_rcd/bus_period*/ |
||||
sdram0_tr |= ((((t_rcd - 1) * 10) / bus_period_x_10) &0x3) << SDRAM0_TR_RCD_SHIFT ; |
||||
|
||||
|
||||
/*------------------------------------------------------------------
|
||||
* configure RTR register |
||||
* -------------------------------------------------------------------*/ |
||||
row = read_spd(3); |
||||
col = read_spd(4); |
||||
tmp = read_spd(12) & 0x7f ; /* refresh type less self refresh bit */ |
||||
switch (tmp) { |
||||
case 0x00: |
||||
tmp = 15625; |
||||
break; |
||||
case 0x01: |
||||
tmp = 15625 / 4; |
||||
break; |
||||
case 0x02: |
||||
tmp = 15625 / 2; |
||||
break; |
||||
case 0x03: |
||||
tmp = 15625 * 2; |
||||
break; |
||||
case 0x04: |
||||
tmp = 15625 * 4; |
||||
break; |
||||
case 0x05: |
||||
tmp = 15625 * 8; |
||||
break; |
||||
default: |
||||
SPD_ERR("SDRAM - Bad refresh period \n"); |
||||
} |
||||
/* convert from nsec to bus cycles */ |
||||
tmp = (tmp * 10) / bus_period_x_10; |
||||
sdram0_rtr = (tmp & 0x3ff8) << SDRAM0_RTR_SHIFT; |
||||
|
||||
/*------------------------------------------------------------------
|
||||
* determine the number of banks used |
||||
* -------------------------------------------------------------------*/ |
||||
/* byte 7:6 is module data width */ |
||||
if (read_spd(7) != 0) |
||||
SPD_ERR("SDRAM - unsupported module width\n"); |
||||
tmp = read_spd(6); |
||||
if (tmp < 32) |
||||
SPD_ERR("SDRAM - unsupported module width\n"); |
||||
else if (tmp < 64) |
||||
bank_cnt = 1; /* one bank per sdram side */ |
||||
else if (tmp < 73) |
||||
bank_cnt = 2; /* need two banks per side */ |
||||
else if (tmp < 161) |
||||
bank_cnt = 4; /* need four banks per side */ |
||||
else |
||||
SPD_ERR("SDRAM - unsupported module width\n"); |
||||
|
||||
/* byte 5 is the module row count (refered to as dimm "sides") */ |
||||
tmp = read_spd(5); |
||||
if (tmp == 1) |
||||
; |
||||
else if (tmp==2) |
||||
bank_cnt *= 2; |
||||
else if (tmp==4) |
||||
bank_cnt *= 4; |
||||
else |
||||
bank_cnt = 8; /* 8 is an error code */ |
||||
|
||||
if (bank_cnt > 4) /* we only have 4 banks to work with */ |
||||
SPD_ERR("SDRAM - unsupported module rows for this width\n"); |
||||
|
||||
/* now check for ECC ability of module. We only support ECC
|
||||
* on 32 bit wide devices with 8 bit ECC. |
||||
*/ |
||||
if ((read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8)) { |
||||
sdram0_ecccfg = 0xf << SDRAM0_ECCCFG_SHIFT; |
||||
ecc_on = 1; |
||||
} else { |
||||
sdram0_ecccfg = 0; |
||||
ecc_on = 0; |
||||
} |
||||
|
||||
/*------------------------------------------------------------------
|
||||
* calculate total size |
||||
* -------------------------------------------------------------------*/ |
||||
/* calculate total size and do sanity check */ |
||||
tmp = read_spd(31); |
||||
total_size = 1 << 22; /* total_size = 4MB */ |
||||
/* now multiply 4M by the smallest device row density */ |
||||
/* note that we don't support asymetric rows */ |
||||
while (((tmp & 0x0001) == 0) && (tmp != 0)) { |
||||
total_size = total_size << 1; |
||||
tmp = tmp >> 1; |
||||
} |
||||
total_size *= read_spd(5); /* mult by module rows (dimm sides) */ |
||||
|
||||
/*------------------------------------------------------------------
|
||||
* map rows * cols * banks to a mode |
||||
* -------------------------------------------------------------------*/ |
||||
|
||||
switch (row) { |
||||
case 11: |
||||
switch (col) { |
||||
case 8: |
||||
mode=4; /* mode 5 */ |
||||
break; |
||||
case 9: |
||||
case 10: |
||||
mode=0; /* mode 1 */ |
||||
break; |
||||
default: |
||||
SPD_ERR("SDRAM - unsupported mode\n"); |
||||
} |
||||
break; |
||||
case 12: |
||||
switch (col) { |
||||
case 8: |
||||
mode=3; /* mode 4 */ |
||||
break; |
||||
case 9: |
||||
case 10: |
||||
mode=1; /* mode 2 */ |
||||
break; |
||||
default: |
||||
SPD_ERR("SDRAM - unsupported mode\n"); |
||||
} |
||||
break; |
||||
case 13: |
||||
switch (col) { |
||||
case 8: |
||||
mode=5; /* mode 6 */ |
||||
break; |
||||
case 9: |
||||
case 10: |
||||
if (read_spd(17) == 2) |
||||
mode = 6; /* mode 7 */ |
||||
else |
||||
mode = 2; /* mode 3 */ |
||||
break; |
||||
case 11: |
||||
mode = 2; /* mode 3 */ |
||||
break; |
||||
default: |
||||
SPD_ERR("SDRAM - unsupported mode\n"); |
||||
} |
||||
break; |
||||
default: |
||||
SPD_ERR("SDRAM - unsupported mode\n"); |
||||
} |
||||
|
||||
/*------------------------------------------------------------------
|
||||
* using the calculated values, compute the bank |
||||
* config register values. |
||||
* -------------------------------------------------------------------*/ |
||||
sdram0_b1cr = 0; |
||||
sdram0_b2cr = 0; |
||||
sdram0_b3cr = 0; |
||||
|
||||
/* compute the size of each bank */ |
||||
bank_size = total_size / bank_cnt; |
||||
/* convert bank size to bank size code for ppc4xx
|
||||
by takeing log2(bank_size) - 22 */ |
||||
tmp = bank_size; /* start with tmp = bank_size */ |
||||
bank_code = 0; /* and bank_code = 0 */ |
||||
while (tmp > 1) { /* this takes log2 of tmp */ |
||||
bank_code++; /* and stores result in bank_code */ |
||||
tmp = tmp >> 1; |
||||
} /* bank_code is now log2(bank_size) */ |
||||
bank_code -= 22; /* subtract 22 to get the code */ |
||||
|
||||
tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1; |
||||
sdram0_b0cr = (bank_size * 0) | tmp; |
||||
#ifndef CONFIG_405EP /* not on PPC405EP */ |
||||
if (bank_cnt > 1) |
||||
sdram0_b2cr = (bank_size * 1) | tmp; |
||||
if (bank_cnt > 2) |
||||
sdram0_b1cr = (bank_size * 2) | tmp; |
||||
if (bank_cnt > 3) |
||||
sdram0_b3cr = (bank_size * 3) | tmp; |
||||
#else |
||||
/* PPC405EP chip only supports two SDRAM banks */ |
||||
if (bank_cnt > 1) |
||||
sdram0_b1cr = (bank_size * 1) | tmp; |
||||
if (bank_cnt > 2) |
||||
total_size = 2 * bank_size; |
||||
#endif |
||||
|
||||
/*
|
||||
* enable sdram controller DCE=1 |
||||
* enable burst read prefetch to 32 bytes BRPF=2 |
||||
* leave other functions off |
||||
*/ |
||||
|
||||
/*------------------------------------------------------------------
|
||||
* now that we've done our calculations, we are ready to |
||||
* program all the registers. |
||||
* -------------------------------------------------------------------*/ |
||||
|
||||
#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) |
||||
/* disable memcontroller so updates work */ |
||||
mtsdram0( mem_mcopt1, 0 ); |
||||
|
||||
#ifndef CONFIG_405EP /* not on PPC405EP */ |
||||
mtsdram0( mem_besra , sdram0_besr0 ); |
||||
mtsdram0( mem_besrb , sdram0_besr1 ); |
||||
mtsdram0( mem_ecccf , sdram0_ecccfg ); |
||||
mtsdram0( mem_eccerr, sdram0_eccesr ); |
||||
#endif |
||||
mtsdram0( mem_rtr , sdram0_rtr ); |
||||
mtsdram0( mem_pmit , sdram0_pmit ); |
||||
mtsdram0( mem_mb0cf , sdram0_b0cr ); |
||||
mtsdram0( mem_mb1cf , sdram0_b1cr ); |
||||
#ifndef CONFIG_405EP /* not on PPC405EP */ |
||||
mtsdram0( mem_mb2cf , sdram0_b2cr ); |
||||
mtsdram0( mem_mb3cf , sdram0_b3cr ); |
||||
#endif |
||||
mtsdram0( mem_sdtr1 , sdram0_tr ); |
||||
|
||||
/* SDRAM have a power on delay, 500 micro should do */ |
||||
udelay(500); |
||||
sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR; |
||||
if (ecc_on) |
||||
sdram0_cfg |= SDRAM0_CFG_MEMCHK; |
||||
mtsdram0(mem_mcopt1, sdram0_cfg); |
||||
|
||||
return (total_size); |
||||
} |
||||
|
||||
int spd_read(uint addr) |
||||
{ |
||||
uchar data[2]; |
||||
|
||||
if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0) |
||||
return (int)data[0]; |
||||
else |
||||
return 0; |
||||
} |
||||
|
||||
#endif /* CONFIG_SPD_EEPROM */ |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,184 @@ |
||||
/*
|
||||
* (C) Copyright 2007 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
#if defined(CONFIG_440) |
||||
|
||||
#include <ppc4xx.h> |
||||
#include <ppc440.h> |
||||
#include <asm/io.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
typedef struct region { |
||||
unsigned long base; |
||||
unsigned long size; |
||||
unsigned long tlb_word2_i_value; |
||||
} region_t; |
||||
|
||||
static int add_tlb_entry(unsigned long base_addr, |
||||
unsigned long tlb_word0_size_value, |
||||
unsigned long tlb_word2_i_value) |
||||
{ |
||||
int i; |
||||
unsigned long tlb_word0_value; |
||||
unsigned long tlb_word1_value; |
||||
unsigned long tlb_word2_value; |
||||
|
||||
/* First, find the index of a TLB entry not being used */ |
||||
for (i=0; i<PPC4XX_TLB_SIZE; i++) { |
||||
tlb_word0_value = mftlb1(i); |
||||
if ((tlb_word0_value & TLB_WORD0_V_MASK) == TLB_WORD0_V_DISABLE) |
||||
break; |
||||
} |
||||
if (i >= PPC4XX_TLB_SIZE) |
||||
return -1; |
||||
|
||||
/* Second, create the TLB entry */ |
||||
tlb_word0_value = TLB_WORD0_EPN_ENCODE(base_addr) | TLB_WORD0_V_ENABLE | |
||||
TLB_WORD0_TS_0 | tlb_word0_size_value; |
||||
tlb_word1_value = TLB_WORD1_RPN_ENCODE(base_addr) | TLB_WORD1_ERPN_ENCODE(0); |
||||
tlb_word2_value = TLB_WORD2_U0_DISABLE | TLB_WORD2_U1_DISABLE | |
||||
TLB_WORD2_U2_DISABLE | TLB_WORD2_U3_DISABLE | |
||||
TLB_WORD2_W_DISABLE | tlb_word2_i_value | |
||||
TLB_WORD2_M_DISABLE | TLB_WORD2_G_DISABLE | |
||||
TLB_WORD2_E_DISABLE | TLB_WORD2_UX_ENABLE | |
||||
TLB_WORD2_UW_ENABLE | TLB_WORD2_UR_ENABLE | |
||||
TLB_WORD2_SX_ENABLE | TLB_WORD2_SW_ENABLE | |
||||
TLB_WORD2_SR_ENABLE; |
||||
|
||||
/* Wait for all memory accesses to complete */ |
||||
sync(); |
||||
|
||||
/* Third, add the TLB entries */ |
||||
mttlb1(i, tlb_word0_value); |
||||
mttlb2(i, tlb_word1_value); |
||||
mttlb3(i, tlb_word2_value); |
||||
|
||||
/* Execute an ISYNC instruction so that the new TLB entry takes effect */ |
||||
asm("isync"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void program_tlb_addr(unsigned long base_addr, unsigned long mem_size, |
||||
unsigned long tlb_word2_i_value) |
||||
{ |
||||
int rc; |
||||
int tlb_i; |
||||
|
||||
tlb_i = tlb_word2_i_value; |
||||
while (mem_size != 0) { |
||||
rc = 0; |
||||
/* Add the TLB entries in to map the region. */ |
||||
if (((base_addr & TLB_256MB_ALIGN_MASK) == base_addr) && |
||||
(mem_size >= TLB_256MB_SIZE)) { |
||||
/* Add a 256MB TLB entry */ |
||||
if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_256MB, tlb_i)) == 0) { |
||||
mem_size -= TLB_256MB_SIZE; |
||||
base_addr += TLB_256MB_SIZE; |
||||
} |
||||
} else if (((base_addr & TLB_16MB_ALIGN_MASK) == base_addr) && |
||||
(mem_size >= TLB_16MB_SIZE)) { |
||||
/* Add a 16MB TLB entry */ |
||||
if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_16MB, tlb_i)) == 0) { |
||||
mem_size -= TLB_16MB_SIZE; |
||||
base_addr += TLB_16MB_SIZE; |
||||
} |
||||
} else if (((base_addr & TLB_1MB_ALIGN_MASK) == base_addr) && |
||||
(mem_size >= TLB_1MB_SIZE)) { |
||||
/* Add a 1MB TLB entry */ |
||||
if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_1MB, tlb_i)) == 0) { |
||||
mem_size -= TLB_1MB_SIZE; |
||||
base_addr += TLB_1MB_SIZE; |
||||
} |
||||
} else if (((base_addr & TLB_256KB_ALIGN_MASK) == base_addr) && |
||||
(mem_size >= TLB_256KB_SIZE)) { |
||||
/* Add a 256KB TLB entry */ |
||||
if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_256KB, tlb_i)) == 0) { |
||||
mem_size -= TLB_256KB_SIZE; |
||||
base_addr += TLB_256KB_SIZE; |
||||
} |
||||
} else if (((base_addr & TLB_64KB_ALIGN_MASK) == base_addr) && |
||||
(mem_size >= TLB_64KB_SIZE)) { |
||||
/* Add a 64KB TLB entry */ |
||||
if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_64KB, tlb_i)) == 0) { |
||||
mem_size -= TLB_64KB_SIZE; |
||||
base_addr += TLB_64KB_SIZE; |
||||
} |
||||
} else if (((base_addr & TLB_16KB_ALIGN_MASK) == base_addr) && |
||||
(mem_size >= TLB_16KB_SIZE)) { |
||||
/* Add a 16KB TLB entry */ |
||||
if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_16KB, tlb_i)) == 0) { |
||||
mem_size -= TLB_16KB_SIZE; |
||||
base_addr += TLB_16KB_SIZE; |
||||
} |
||||
} else if (((base_addr & TLB_4KB_ALIGN_MASK) == base_addr) && |
||||
(mem_size >= TLB_4KB_SIZE)) { |
||||
/* Add a 4KB TLB entry */ |
||||
if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_4KB, tlb_i)) == 0) { |
||||
mem_size -= TLB_4KB_SIZE; |
||||
base_addr += TLB_4KB_SIZE; |
||||
} |
||||
} else if (((base_addr & TLB_1KB_ALIGN_MASK) == base_addr) && |
||||
(mem_size >= TLB_1KB_SIZE)) { |
||||
/* Add a 1KB TLB entry */ |
||||
if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_1KB, tlb_i)) == 0) { |
||||
mem_size -= TLB_1KB_SIZE; |
||||
base_addr += TLB_1KB_SIZE; |
||||
} |
||||
} else { |
||||
printf("ERROR: no TLB size exists for the base address 0x%0X.\n", |
||||
base_addr); |
||||
} |
||||
|
||||
if (rc != 0) |
||||
printf("ERROR: no TLB entries available for the base addr 0x%0X.\n", |
||||
base_addr); |
||||
} |
||||
|
||||
return; |
||||
} |
||||
|
||||
/*
|
||||
* Program one (or multiple) TLB entries for one memory region |
||||
* |
||||
* Common usage for boards with SDRAM DIMM modules to dynamically |
||||
* configure the TLB's for the SDRAM |
||||
*/ |
||||
void program_tlb(u32 start, u32 size) |
||||
{ |
||||
region_t region_array; |
||||
|
||||
region_array.base = start; |
||||
region_array.size = size; |
||||
region_array.tlb_word2_i_value = TLB_WORD2_I_ENABLE; /* disable cache (for now) */ |
||||
|
||||
/* Call the routine to add in the tlb entries for the memory regions */ |
||||
program_tlb_addr(region_array.base, region_array.size, |
||||
region_array.tlb_word2_i_value); |
||||
|
||||
return; |
||||
} |
||||
|
||||
#endif /* CONFIG_440 */ |
||||
@ -0,0 +1,252 @@ |
||||
/*
|
||||
* Copyright (c) 2004 Picture Elements, Inc. |
||||
* Stephen Williams (XXXXXXXXXXXXXXXX) |
||||
* |
||||
* This source code is free software; you can redistribute it |
||||
* and/or modify it in source code form under the terms of the GNU |
||||
* General Public License as published by the Free Software |
||||
* Foundation; either version 2 of the License, or (at your option) |
||||
* any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA |
||||
*/ |
||||
|
||||
/*
|
||||
* The Xilinx SystemACE chip support is activated by defining |
||||
* CONFIG_SYSTEMACE to turn on support, and CFG_SYSTEMACE_BASE |
||||
* to set the base address of the device. This code currently |
||||
* assumes that the chip is connected via a byte-wide bus. |
||||
* |
||||
* The CONFIG_SYSTEMACE also adds to fat support the device class |
||||
* "ace" that allows the user to execute "fatls ace 0" and the |
||||
* like. This works by making the systemace_get_dev function |
||||
* available to cmd_fat.c:get_dev and filling in a block device |
||||
* description that has all the bits needed for FAT support to |
||||
* read sectors. |
||||
* |
||||
* According to Xilinx technical support, before accessing the |
||||
* SystemACE CF you need to set the following control bits: |
||||
* FORCECFGMODE : 1 |
||||
* CFGMODE : 0 |
||||
* CFGSTART : 0 |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <systemace.h> |
||||
#include <part.h> |
||||
#include <asm/io.h> |
||||
|
||||
#ifdef CONFIG_SYSTEMACE |
||||
|
||||
/*
|
||||
* The ace_readw and writew functions read/write 16bit words, but the |
||||
* offset value is the BYTE offset as most used in the Xilinx |
||||
* datasheet for the SystemACE chip. The CFG_SYSTEMACE_BASE is defined |
||||
* to be the base address for the chip, usually in the local |
||||
* peripheral bus. |
||||
*/ |
||||
#if (CFG_SYSTEMACE_WIDTH == 8) |
||||
#if !defined(__BIG_ENDIAN) |
||||
#define ace_readw(off) ((readb(CFG_SYSTEMACE_BASE+off)<<8) | \ |
||||
(readb(CFG_SYSTEMACE_BASE+off+1))) |
||||
#define ace_writew(val, off) {writeb(val>>8, CFG_SYSTEMACE_BASE+off); \ |
||||
writeb(val, CFG_SYSTEMACE_BASE+off+1);} |
||||
#else |
||||
#define ace_readw(off) ((readb(CFG_SYSTEMACE_BASE+off)) | \ |
||||
(readb(CFG_SYSTEMACE_BASE+off+1)<<8)) |
||||
#define ace_writew(val, off) {writeb(val, CFG_SYSTEMACE_BASE+off); \ |
||||
writeb(val>>8, CFG_SYSTEMACE_BASE+off+1);} |
||||
#endif |
||||
#else |
||||
#define ace_readw(off) (in16(CFG_SYSTEMACE_BASE+off)) |
||||
#define ace_writew(val, off) (out16(CFG_SYSTEMACE_BASE+off,val)) |
||||
#endif |
||||
|
||||
/* */ |
||||
|
||||
static unsigned long systemace_read(int dev, unsigned long start, |
||||
unsigned long blkcnt, void *buffer); |
||||
|
||||
static block_dev_desc_t systemace_dev = { 0 }; |
||||
|
||||
static int get_cf_lock(void) |
||||
{ |
||||
int retry = 10; |
||||
|
||||
/* CONTROLREG = LOCKREG */ |
||||
unsigned val = ace_readw(0x18); |
||||
val |= 0x0002; |
||||
ace_writew((val & 0xffff), 0x18); |
||||
|
||||
/* Wait for MPULOCK in STATUSREG[15:0] */ |
||||
while (!(ace_readw(0x04) & 0x0002)) { |
||||
|
||||
if (retry < 0) |
||||
return -1; |
||||
|
||||
udelay(100000); |
||||
retry -= 1; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void release_cf_lock(void) |
||||
{ |
||||
unsigned val = ace_readw(0x18); |
||||
val &= ~(0x0002); |
||||
ace_writew((val & 0xffff), 0x18); |
||||
} |
||||
|
||||
block_dev_desc_t *systemace_get_dev(int dev) |
||||
{ |
||||
/* The first time through this, the systemace_dev object is
|
||||
not yet initialized. In that case, fill it in. */ |
||||
if (systemace_dev.blksz == 0) { |
||||
systemace_dev.if_type = IF_TYPE_UNKNOWN; |
||||
systemace_dev.dev = 0; |
||||
systemace_dev.part_type = PART_TYPE_UNKNOWN; |
||||
systemace_dev.type = DEV_TYPE_HARDDISK; |
||||
systemace_dev.blksz = 512; |
||||
systemace_dev.removable = 1; |
||||
systemace_dev.block_read = systemace_read; |
||||
|
||||
/*
|
||||
* Ensure the correct bus mode (8/16 bits) gets enabled |
||||
*/ |
||||
ace_writew(CFG_SYSTEMACE_WIDTH == 8 ? 0 : 0x0001, 0); |
||||
|
||||
init_part(&systemace_dev); |
||||
|
||||
} |
||||
|
||||
return &systemace_dev; |
||||
} |
||||
|
||||
/*
|
||||
* This function is called (by dereferencing the block_read pointer in |
||||
* the dev_desc) to read blocks of data. The return value is the |
||||
* number of blocks read. A zero return indicates an error. |
||||
*/ |
||||
static unsigned long systemace_read(int dev, unsigned long start, |
||||
unsigned long blkcnt, void *buffer) |
||||
{ |
||||
int retry; |
||||
unsigned blk_countdown; |
||||
unsigned char *dp = buffer; |
||||
unsigned val; |
||||
|
||||
if (get_cf_lock() < 0) { |
||||
unsigned status = ace_readw(0x04); |
||||
|
||||
/* If CFDETECT is false, card is missing. */ |
||||
if (!(status & 0x0010)) { |
||||
printf("** CompactFlash card not present. **\n"); |
||||
return 0; |
||||
} |
||||
|
||||
printf("**** ACE locked away from me (STATUSREG=%04x)\n", |
||||
status); |
||||
return 0; |
||||
} |
||||
#ifdef DEBUG_SYSTEMACE |
||||
printf("... systemace read %lu sectors at %lu\n", blkcnt, start); |
||||
#endif |
||||
|
||||
retry = 2000; |
||||
for (;;) { |
||||
val = ace_readw(0x04); |
||||
|
||||
/* If CFDETECT is false, card is missing. */ |
||||
if (!(val & 0x0010)) { |
||||
printf("**** ACE CompactFlash not found.\n"); |
||||
release_cf_lock(); |
||||
return 0; |
||||
} |
||||
|
||||
/* If RDYFORCMD, then we are ready to go. */ |
||||
if (val & 0x0100) |
||||
break; |
||||
|
||||
if (retry < 0) { |
||||
printf("**** SystemACE not ready.\n"); |
||||
release_cf_lock(); |
||||
return 0; |
||||
} |
||||
|
||||
udelay(1000); |
||||
retry -= 1; |
||||
} |
||||
|
||||
/* The SystemACE can only transfer 256 sectors at a time, so
|
||||
limit the current chunk of sectors. The blk_countdown |
||||
variable is the number of sectors left to transfer. */ |
||||
|
||||
blk_countdown = blkcnt; |
||||
while (blk_countdown > 0) { |
||||
unsigned trans = blk_countdown; |
||||
|
||||
if (trans > 256) |
||||
trans = 256; |
||||
|
||||
#ifdef DEBUG_SYSTEMACE |
||||
printf("... transfer %lu sector in a chunk\n", trans); |
||||
#endif |
||||
/* Write LBA block address */ |
||||
ace_writew((start >> 0) & 0xffff, 0x10); |
||||
ace_writew((start >> 16) & 0x0fff, 0x12); |
||||
|
||||
/* NOTE: in the Write Sector count below, a count of 0
|
||||
causes a transfer of 256, so &0xff gives the right |
||||
value for whatever transfer count we want. */ |
||||
|
||||
/* Write sector count | ReadMemCardData. */ |
||||
ace_writew((trans & 0xff) | 0x0300, 0x14); |
||||
|
||||
/* Reset the configruation controller */ |
||||
val = ace_readw(0x18); |
||||
val |= 0x0080; |
||||
ace_writew(val, 0x18); |
||||
|
||||
retry = trans * 16; |
||||
while (retry > 0) { |
||||
int idx; |
||||
|
||||
/* Wait for buffer to become ready. */ |
||||
while (!(ace_readw(0x04) & 0x0020)) { |
||||
udelay(100); |
||||
} |
||||
|
||||
/* Read 16 words of 2bytes from the sector buffer. */ |
||||
for (idx = 0; idx < 16; idx += 1) { |
||||
unsigned short val = ace_readw(0x40); |
||||
*dp++ = val & 0xff; |
||||
*dp++ = (val >> 8) & 0xff; |
||||
} |
||||
|
||||
retry -= 1; |
||||
} |
||||
|
||||
/* Clear the configruation controller reset */ |
||||
val = ace_readw(0x18); |
||||
val &= ~0x0080; |
||||
ace_writew(val, 0x18); |
||||
|
||||
/* Count the blocks we transfer this time. */ |
||||
start += trans; |
||||
blk_countdown -= trans; |
||||
} |
||||
|
||||
release_cf_lock(); |
||||
|
||||
return blkcnt; |
||||
} |
||||
#endif /* CONFIG_SYSTEMACE */ |
||||
@ -1,64 +0,0 @@ |
||||
#ifndef _405gp_i2c_h_ |
||||
#define _405gp_i2c_h_ |
||||
|
||||
#define I2C_REGISTERS_BASE_ADDRESS 0xEF600500 |
||||
#define IIC_MDBUF (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF) |
||||
#define IIC_SDBUF (I2C_REGISTERS_BASE_ADDRESS+IICSDBUF) |
||||
#define IIC_LMADR (I2C_REGISTERS_BASE_ADDRESS+IICLMADR) |
||||
#define IIC_HMADR (I2C_REGISTERS_BASE_ADDRESS+IICHMADR) |
||||
#define IIC_CNTL (I2C_REGISTERS_BASE_ADDRESS+IICCNTL) |
||||
#define IIC_MDCNTL (I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL) |
||||
#define IIC_STS (I2C_REGISTERS_BASE_ADDRESS+IICSTS) |
||||
#define IIC_EXTSTS (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS) |
||||
#define IIC_LSADR (I2C_REGISTERS_BASE_ADDRESS+IICLSADR) |
||||
#define IIC_HSADR (I2C_REGISTERS_BASE_ADDRESS+IICHSADR) |
||||
#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV) |
||||
#define IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK) |
||||
#define IIC_XFRCNT (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT) |
||||
#define IIC_XTCNTLSS (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS) |
||||
#define IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL) |
||||
|
||||
/* MDCNTL Register Bit definition */ |
||||
#define IIC_MDCNTL_HSCL 0x01 |
||||
#define IIC_MDCNTL_EUBS 0x02 |
||||
#define IIC_MDCNTL_EINT 0x04 |
||||
#define IIC_MDCNTL_ESM 0x08 |
||||
#define IIC_MDCNTL_FSM 0x10 |
||||
#define IIC_MDCNTL_EGC 0x20 |
||||
#define IIC_MDCNTL_FMDB 0x40 |
||||
#define IIC_MDCNTL_FSDB 0x80 |
||||
|
||||
/* CNTL Register Bit definition */ |
||||
#define IIC_CNTL_PT 0x01 |
||||
#define IIC_CNTL_READ 0x02 |
||||
#define IIC_CNTL_CHT 0x04 |
||||
#define IIC_CNTL_RPST 0x08 |
||||
/* bit 2/3 for Transfer count*/ |
||||
#define IIC_CNTL_AMD 0x40 |
||||
#define IIC_CNTL_HMT 0x80 |
||||
|
||||
/* STS Register Bit definition */ |
||||
#define IIC_STS_PT 0X01 |
||||
#define IIC_STS_IRQA 0x02 |
||||
#define IIC_STS_ERR 0X04 |
||||
#define IIC_STS_SCMP 0x08 |
||||
#define IIC_STS_MDBF 0x10 |
||||
#define IIC_STS_MDBS 0X20 |
||||
#define IIC_STS_SLPR 0x40 |
||||
#define IIC_STS_SSS 0x80 |
||||
|
||||
/* EXTSTS Register Bit definition */ |
||||
#define IIC_EXTSTS_XFRA 0X01 |
||||
#define IIC_EXTSTS_ICT 0X02 |
||||
#define IIC_EXTSTS_LA 0X04 |
||||
|
||||
/* XTCNTLSS Register Bit definition */ |
||||
#define IIC_XTCNTLSS_SRST 0x01 |
||||
#define IIC_XTCNTLSS_EPI 0x02 |
||||
#define IIC_XTCNTLSS_SDBF 0x04 |
||||
#define IIC_XTCNTLSS_SBDD 0x08 |
||||
#define IIC_XTCNTLSS_SWS 0x10 |
||||
#define IIC_XTCNTLSS_SWC 0x20 |
||||
#define IIC_XTCNTLSS_SRS 0x40 |
||||
#define IIC_XTCNTLSS_SRC 0x80 |
||||
#endif |
||||
@ -1,71 +0,0 @@ |
||||
#ifndef _440_i2c_h_ |
||||
#define _440_i2c_h_ |
||||
|
||||
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
||||
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
||||
#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700) |
||||
#else |
||||
#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400) |
||||
#endif /*CONFIG_440EP CONFIG_440GR*/ |
||||
|
||||
#define I2C_REGISTERS_BASE_ADDRESS I2C_BASE_ADDR |
||||
#define IIC_MDBUF (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF) |
||||
#define IIC_SDBUF (I2C_REGISTERS_BASE_ADDRESS+IICSDBUF) |
||||
#define IIC_LMADR (I2C_REGISTERS_BASE_ADDRESS+IICLMADR) |
||||
#define IIC_HMADR (I2C_REGISTERS_BASE_ADDRESS+IICHMADR) |
||||
#define IIC_CNTL (I2C_REGISTERS_BASE_ADDRESS+IICCNTL) |
||||
#define IIC_MDCNTL (I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL) |
||||
#define IIC_STS (I2C_REGISTERS_BASE_ADDRESS+IICSTS) |
||||
#define IIC_EXTSTS (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS) |
||||
#define IIC_LSADR (I2C_REGISTERS_BASE_ADDRESS+IICLSADR) |
||||
#define IIC_HSADR (I2C_REGISTERS_BASE_ADDRESS+IICHSADR) |
||||
#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV) |
||||
#define IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK) |
||||
#define IIC_XFRCNT (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT) |
||||
#define IIC_XTCNTLSS (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS) |
||||
#define IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL) |
||||
|
||||
/* MDCNTL Register Bit definition */ |
||||
#define IIC_MDCNTL_HSCL 0x01 |
||||
#define IIC_MDCNTL_EUBS 0x02 |
||||
#define IIC_MDCNTL_EINT 0x04 |
||||
#define IIC_MDCNTL_ESM 0x08 |
||||
#define IIC_MDCNTL_FSM 0x10 |
||||
#define IIC_MDCNTL_EGC 0x20 |
||||
#define IIC_MDCNTL_FMDB 0x40 |
||||
#define IIC_MDCNTL_FSDB 0x80 |
||||
|
||||
/* CNTL Register Bit definition */ |
||||
#define IIC_CNTL_PT 0x01 |
||||
#define IIC_CNTL_READ 0x02 |
||||
#define IIC_CNTL_CHT 0x04 |
||||
#define IIC_CNTL_RPST 0x08 |
||||
/* bit 2/3 for Transfer count*/ |
||||
#define IIC_CNTL_AMD 0x40 |
||||
#define IIC_CNTL_HMT 0x80 |
||||
|
||||
/* STS Register Bit definition */ |
||||
#define IIC_STS_PT 0X01 |
||||
#define IIC_STS_IRQA 0x02 |
||||
#define IIC_STS_ERR 0X04 |
||||
#define IIC_STS_SCMP 0x08 |
||||
#define IIC_STS_MDBF 0x10 |
||||
#define IIC_STS_MDBS 0X20 |
||||
#define IIC_STS_SLPR 0x40 |
||||
#define IIC_STS_SSS 0x80 |
||||
|
||||
/* EXTSTS Register Bit definition */ |
||||
#define IIC_EXTSTS_XFRA 0X01 |
||||
#define IIC_EXTSTS_ICT 0X02 |
||||
#define IIC_EXTSTS_LA 0X04 |
||||
|
||||
/* XTCNTLSS Register Bit definition */ |
||||
#define IIC_XTCNTLSS_SRST 0x01 |
||||
#define IIC_XTCNTLSS_EPI 0x02 |
||||
#define IIC_XTCNTLSS_SDBF 0x04 |
||||
#define IIC_XTCNTLSS_SBDD 0x08 |
||||
#define IIC_XTCNTLSS_SWS 0x10 |
||||
#define IIC_XTCNTLSS_SWC 0x20 |
||||
#define IIC_XTCNTLSS_SRS 0x40 |
||||
#define IIC_XTCNTLSS_SRC 0x80 |
||||
#endif |
||||
@ -0,0 +1,122 @@ |
||||
/*
|
||||
* (C) Copyright 2007 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef _4xx_i2c_h_ |
||||
#define _4xx_i2c_h_ |
||||
|
||||
#define IIC_OK 0 |
||||
#define IIC_NOK 1 |
||||
#define IIC_NOK_LA 2 /* Lost arbitration */ |
||||
#define IIC_NOK_ICT 3 /* Incomplete transfer */ |
||||
#define IIC_NOK_XFRA 4 /* Transfer aborted */ |
||||
#define IIC_NOK_DATA 5 /* No data in buffer */ |
||||
#define IIC_NOK_TOUT 6 /* Transfer timeout */ |
||||
|
||||
#define IIC_TIMEOUT 1 /* 1 second */ |
||||
|
||||
#if defined(CONFIG_I2C_MULTI_BUS) |
||||
#define I2C_BUS_OFFS (i2c_bus_num * 0x100) |
||||
#else |
||||
#define I2C_BUS_OFFS (0x000) |
||||
#endif /* CONFIG_I2C_MULTI_BUS */ |
||||
|
||||
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
||||
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
||||
#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700 + I2C_BUS_OFFS) |
||||
#elif defined(CONFIG_440) |
||||
/* all remaining 440 variants */ |
||||
#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400 + I2C_BUS_OFFS) |
||||
#else |
||||
/* all 405 variants */ |
||||
#define I2C_BASE_ADDR (0xEF600500 + I2C_BUS_OFFS) |
||||
#endif |
||||
|
||||
#define I2C_REGISTERS_BASE_ADDRESS I2C_BASE_ADDR |
||||
#define IIC_MDBUF (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF) |
||||
#define IIC_SDBUF (I2C_REGISTERS_BASE_ADDRESS+IICSDBUF) |
||||
#define IIC_LMADR (I2C_REGISTERS_BASE_ADDRESS+IICLMADR) |
||||
#define IIC_HMADR (I2C_REGISTERS_BASE_ADDRESS+IICHMADR) |
||||
#define IIC_CNTL (I2C_REGISTERS_BASE_ADDRESS+IICCNTL) |
||||
#define IIC_MDCNTL (I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL) |
||||
#define IIC_STS (I2C_REGISTERS_BASE_ADDRESS+IICSTS) |
||||
#define IIC_EXTSTS (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS) |
||||
#define IIC_LSADR (I2C_REGISTERS_BASE_ADDRESS+IICLSADR) |
||||
#define IIC_HSADR (I2C_REGISTERS_BASE_ADDRESS+IICHSADR) |
||||
#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV) |
||||
#define IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK) |
||||
#define IIC_XFRCNT (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT) |
||||
#define IIC_XTCNTLSS (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS) |
||||
#define IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL) |
||||
|
||||
/* MDCNTL Register Bit definition */ |
||||
#define IIC_MDCNTL_HSCL 0x01 |
||||
#define IIC_MDCNTL_EUBS 0x02 |
||||
#define IIC_MDCNTL_EINT 0x04 |
||||
#define IIC_MDCNTL_ESM 0x08 |
||||
#define IIC_MDCNTL_FSM 0x10 |
||||
#define IIC_MDCNTL_EGC 0x20 |
||||
#define IIC_MDCNTL_FMDB 0x40 |
||||
#define IIC_MDCNTL_FSDB 0x80 |
||||
|
||||
/* CNTL Register Bit definition */ |
||||
#define IIC_CNTL_PT 0x01 |
||||
#define IIC_CNTL_READ 0x02 |
||||
#define IIC_CNTL_CHT 0x04 |
||||
#define IIC_CNTL_RPST 0x08 |
||||
/* bit 2/3 for Transfer count*/ |
||||
#define IIC_CNTL_AMD 0x40 |
||||
#define IIC_CNTL_HMT 0x80 |
||||
|
||||
/* STS Register Bit definition */ |
||||
#define IIC_STS_PT 0x01 |
||||
#define IIC_STS_IRQA 0x02 |
||||
#define IIC_STS_ERR 0x04 |
||||
#define IIC_STS_SCMP 0x08 |
||||
#define IIC_STS_MDBF 0x10 |
||||
#define IIC_STS_MDBS 0x20 |
||||
#define IIC_STS_SLPR 0x40 |
||||
#define IIC_STS_SSS 0x80 |
||||
|
||||
/* EXTSTS Register Bit definition */ |
||||
#define IIC_EXTSTS_XFRA 0x01 |
||||
#define IIC_EXTSTS_ICT 0x02 |
||||
#define IIC_EXTSTS_LA 0x04 |
||||
|
||||
/* XTCNTLSS Register Bit definition */ |
||||
#define IIC_XTCNTLSS_SRST 0x01 |
||||
#define IIC_XTCNTLSS_EPI 0x02 |
||||
#define IIC_XTCNTLSS_SDBF 0x04 |
||||
#define IIC_XTCNTLSS_SBDD 0x08 |
||||
#define IIC_XTCNTLSS_SWS 0x10 |
||||
#define IIC_XTCNTLSS_SWC 0x20 |
||||
#define IIC_XTCNTLSS_SRS 0x40 |
||||
#define IIC_XTCNTLSS_SRC 0x80 |
||||
|
||||
/* IICx_DIRECTCNTL register */ |
||||
#define IIC_DIRCNTL_SDAC 0x08 |
||||
#define IIC_DIRCNTL_SCC 0x04 |
||||
#define IIC_DIRCNTL_MSDA 0x02 |
||||
#define IIC_DIRCNTL_MSC 0x01 |
||||
|
||||
#define DIRCTNL_FREE(v) (((v) & 0x0f) == 0x0f) |
||||
#endif |
||||
@ -1 +1,8 @@ |
||||
/* */ |
||||
#ifndef __ASM_M68K_IO_H_ |
||||
#define __ASM_M68K_IO_H_ |
||||
|
||||
static inline void sync(void) |
||||
{ |
||||
} |
||||
|
||||
#endif /* __ASM_M68K_IO_H_ */ |
||||
|
||||
@ -0,0 +1,415 @@ |
||||
/*
|
||||
* (C) Copyright 2007 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/************************************************************************
|
||||
* katmai.h - configuration for AMCC Katmai (440SPe) |
||||
***********************************************************************/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_KATMAI 1 /* Board is Katmai */ |
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */ |
||||
#define CONFIG_440 1 /* ... PPC440 family */ |
||||
#define CONFIG_440SPE 1 /* Specifc SPe support */ |
||||
#undef CFG_DRAM_TEST /* Disable-takes long time */ |
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
||||
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ |
||||
#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ |
||||
#undef CONFIG_SHOW_BOOT_PROGRESS |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Base addresses -- Note these are effective addresses where the |
||||
* actual resources get mapped (not physical addresses) |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
||||
#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */ |
||||
|
||||
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ |
||||
#define CFG_FLASH_BASE 0xff000000 /* start of FLASH */ |
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ |
||||
#define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */ |
||||
|
||||
#define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ |
||||
#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ |
||||
#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE |
||||
|
||||
#define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ |
||||
#define CFG_PCIE_MEMSIZE 0x01000000 |
||||
#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ |
||||
|
||||
#define CFG_PCIE0_CFGBASE 0xc0000000 |
||||
#define CFG_PCIE0_XCFGBASE 0xc0000400 |
||||
#define CFG_PCIE1_CFGBASE 0xc0001000 |
||||
#define CFG_PCIE1_XCFGBASE 0xc0001400 |
||||
#define CFG_PCIE2_CFGBASE 0xc0002000 |
||||
#define CFG_PCIE2_XCFGBASE 0xc0002400 |
||||
|
||||
/* System RAM mapped to PCI space */ |
||||
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE |
||||
#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE |
||||
#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) |
||||
|
||||
#define CFG_ACE_BASE 0xe0000000 /* Xilinx ACE controller - Compact Flash */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Initial RAM & stack pointer (placed in internal SRAM) |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_TEMP_STACK_OCM 1 |
||||
#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE |
||||
#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ |
||||
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ |
||||
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ |
||||
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) |
||||
#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_SERIAL_MULTI 1 |
||||
#undef CONFIG_UART1_CONSOLE |
||||
#undef CFG_EXT_SERIAL_CLOCK |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DDR SDRAM |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ |
||||
#define SPD_EEPROM_ADDRESS {0x51, 0x52} /* SPD i2c spd addresses */ |
||||
#define IIC0_DIMM0_ADDR 0x51 |
||||
#define IIC0_DIMM1_ADDR 0x52 |
||||
#undef CONFIG_STRESS |
||||
#undef ENABLE_ECC |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
#define CONFIG_I2C_MULTI_BUS |
||||
#define CONFIG_I2C_CMD_TREE |
||||
#define CFG_SPD_BUS_NUM 0 /* The I2C bus for SPD */ |
||||
|
||||
#define IIC0_BOOTPROM_ADDR 0x50 |
||||
#define IIC0_ALT_BOOTPROM_ADDR 0x54 |
||||
|
||||
#define CFG_I2C_MULTI_EEPROMS |
||||
#define CFG_I2C_EEPROM_ADDR (0x50) |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 |
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 3 |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 |
||||
|
||||
/* I2C RTC */ |
||||
#define CONFIG_RTC_M41T11 1 |
||||
#define CFG_RTC_BUS_NUM 1 /* The I2C bus for RTC */ |
||||
#define CFG_I2C_RTC_ADDR 0x68 |
||||
#define CFG_M41T11_BASE_YEAR 1900 /* play along with linux */ |
||||
|
||||
/* I2C DTT */ |
||||
#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */ |
||||
#define CFG_DTT_BUS_NUM 1 /* The I2C bus for DTT */ |
||||
/*
|
||||
* standard dtt sensor configuration - bottom bit will determine local or |
||||
* remote sensor of the ADM1021, the rest determines index into |
||||
* CFG_DTT_ADM1021 array below. |
||||
*/ |
||||
#define CONFIG_DTT_SENSORS { 0, 1 } |
||||
|
||||
/*
|
||||
* ADM1021 temp sensor configuration (see dtt/adm1021.c for details). |
||||
* there will be one entry in this array for each two (dummy) sensors in |
||||
* CONFIG_DTT_SENSORS. |
||||
* |
||||
* For Katmai board: |
||||
* - only one ADM1021 |
||||
* - i2c addr 0x18 |
||||
* - conversion rate 0x02 = 0.25 conversions/second |
||||
* - ALERT ouput disabled |
||||
* - local temp sensor enabled, min set to 0 deg, max set to 85 deg |
||||
* - remote temp sensor enabled, min set to 0 deg, max set to 85 deg |
||||
*/ |
||||
#define CFG_DTT_ADM1021 { { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} } |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */ |
||||
|
||||
#define CONFIG_PREBOOT "echo;" \ |
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"hostname=katmai\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
|
||||
"flash_nfs=run nfsargs addip addtty;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip addtty;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
|
||||
"bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_4xx\0" \
|
||||
"bootfile=katmai/uImage\0" \
|
||||
"kernel_addr=fff10000\0" \
|
||||
"ramdisk_addr=fff20000\0" \
|
||||
"initrd_high=30000000\0" \
|
||||
"load=tftp 200000 katmai/u-boot.bin\0" \
|
||||
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
|
||||
"cp.b ${fileaddr} fffc0000 ${filesize};" \
|
||||
"setenv filesize;saveenv\0" \
|
||||
"upd=run load;run update\0" \
|
||||
"kozio=bootm ffc60000\0" \
|
||||
"" |
||||
#define CONFIG_BOOTCOMMAND "run flash_self" |
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_DIAG | \
|
||||
CFG_CMD_DTT | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_EXT2 | \
|
||||
CFG_CMD_FAT | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_REGINFO | \
|
||||
CFG_CMD_SDRAM) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */ |
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ |
||||
#define CONFIG_HAS_ETH0 |
||||
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ |
||||
#define CONFIG_PHY_RESET_DELAY 1000 |
||||
#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ |
||||
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
||||
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ |
||||
|
||||
#define CONFIG_NETCONSOLE /* include NetConsole support */ |
||||
#define CONFIG_NET_MULTI /* needed for NetConsole */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
||||
#define CONFIG_LOOPW 1 /* enable loopw command */ |
||||
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ |
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
||||
|
||||
#define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH related |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_FLASH_CFI |
||||
#define CFG_FLASH_CFI_DRIVER |
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
||||
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
||||
|
||||
#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} |
||||
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ |
||||
#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */ |
||||
|
||||
#undef CFG_FLASH_CHECKSUM |
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) |
||||
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) |
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
/* General PCI */ |
||||
#define CONFIG_PCI /* include pci support */ |
||||
#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ |
||||
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ |
||||
#undef CONFIG_PCI_CONFIG_HOST_BRIDGE |
||||
|
||||
/* Board-specific PCI */ |
||||
#define CFG_PCI_PRE_INIT 1 /* enable board pci_pre_init() */ |
||||
#define CFG_PCI_TARGET_INIT /* let board init pci target */ |
||||
#undef CFG_PCI_MASTER_INIT |
||||
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ |
||||
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ |
||||
/* #define CFG_PCI_SUBSYS_ID CFG_PCI_SUBSYS_DEVICEID */ |
||||
|
||||
/*
|
||||
* NETWORK Support (PCI): |
||||
*/ |
||||
/* Support for Intel 82557/82559/82559ER chips. */ |
||||
#define CONFIG_EEPRO100 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Xilinx System ACE support |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_SYSTEMACE 1 /* Enable SystemACE support */ |
||||
#define CFG_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */ |
||||
#define CFG_SYSTEMACE_BASE CFG_ACE_BASE |
||||
#define CONFIG_DOS_PARTITION 1 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup |
||||
*----------------------------------------------------------------------*/ |
||||
|
||||
/* Memory Bank 0 (Flash) initialization */ |
||||
#define CFG_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ |
||||
EBC_BXAP_TWT_ENCODE(7) | \
|
||||
EBC_BXAP_BCE_DISABLE | \
|
||||
EBC_BXAP_BCT_2TRANS | \
|
||||
EBC_BXAP_CSN_ENCODE(0) | \
|
||||
EBC_BXAP_OEN_ENCODE(0) | \
|
||||
EBC_BXAP_WBN_ENCODE(0) | \
|
||||
EBC_BXAP_WBF_ENCODE(0) | \
|
||||
EBC_BXAP_TH_ENCODE(0) | \
|
||||
EBC_BXAP_RE_DISABLED | \
|
||||
EBC_BXAP_SOR_DELAYED | \
|
||||
EBC_BXAP_BEM_WRITEONLY | \
|
||||
EBC_BXAP_PEN_DISABLED) |
||||
#define CFG_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) | \ |
||||
EBC_BXCR_BS_16MB | \
|
||||
EBC_BXCR_BU_RW | \
|
||||
EBC_BXCR_BW_16BIT) |
||||
|
||||
/* Memory Bank 1 (Xilinx System ACE controller) initialization */ |
||||
#define CFG_EBC_PB1AP 0x7F8FFE80 |
||||
#define CFG_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CFG_ACE_BASE) | \ |
||||
EBC_BXCR_BS_1MB | \
|
||||
EBC_BXCR_BU_RW | \
|
||||
EBC_BXCR_BW_16BIT) |
||||
|
||||
/*-------------------------------------------------------------------------
|
||||
* Initialize EBC CONFIG - |
||||
* Keep the Default value, but the bit PDT which has to be set to 1 ?TBC |
||||
* default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 |
||||
*-------------------------------------------------------------------------*/ |
||||
#define CFG_EBC_CFG (EBC_CFG_LE_UNLOCK | \ |
||||
EBC_CFG_PTD_ENABLE | \
|
||||
EBC_CFG_RTC_16PERCLK | \
|
||||
EBC_CFG_ATC_PREVIOUS | \
|
||||
EBC_CFG_DTC_PREVIOUS | \
|
||||
EBC_CFG_CTC_PREVIOUS | \
|
||||
EBC_CFG_OEO_PREVIOUS | \
|
||||
EBC_CFG_EMC_DEFAULT | \
|
||||
EBC_CFG_PME_DISABLE | \
|
||||
EBC_CFG_PR_16) |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ |
||||
#define CFG_CACHELINE_SIZE 32 /* ... */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue