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@ -21,13 +21,17 @@ |
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#include <common.h> |
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#include <netdev.h> |
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#include <malloc.h> |
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#include <fpga.h> |
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#include <video_fb.h> |
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#include <asm/io.h> |
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#include <asm/arch/mem.h> |
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#include <asm/arch/mux.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/omap_gpio.h> |
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#include <asm/arch/mmc_host_def.h> |
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#include <asm/arch/dss.h> |
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#include <asm/arch/clocks.h> |
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#include <i2c.h> |
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#include <spartan3.h> |
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#include <asm/gpio.h> |
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@ -53,6 +57,42 @@ DECLARE_GLOBAL_DATA_PTR; |
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#define FPGA_INIT 119 |
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#define FPGA_DONE 154 |
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#define LCD_PWR 138 |
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#define LCD_PON_PIN 139 |
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#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) |
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static struct { |
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u32 xres; |
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u32 yres; |
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} panel_resolution[] = { |
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{ 480, 272 }, |
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{ 800, 480 } |
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}; |
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static struct panel_config lcd_cfg[] = { |
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{ |
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.timing_h = PANEL_TIMING_H(4, 8, 41), |
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.timing_v = PANEL_TIMING_V(2, 4, 10), |
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.pol_freq = 0x00000000, /* Pol Freq */ |
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.divisor = 0x0001000d, /* 33Mhz Pixel Clock */ |
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.panel_type = 0x01, /* TFT */ |
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.data_lines = 0x03, /* 24 Bit RGB */ |
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.load_mode = 0x02, /* Frame Mode */ |
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.panel_color = 0, |
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}, |
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{ |
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.timing_h = PANEL_TIMING_H(20, 192, 4), |
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.timing_v = PANEL_TIMING_V(2, 20, 10), |
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.pol_freq = 0x00004000, /* Pol Freq */ |
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.divisor = 0x0001000E, /* 36Mhz Pixel Clock */ |
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.panel_type = 0x01, /* TFT */ |
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.data_lines = 0x03, /* 24 Bit RGB */ |
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.load_mode = 0x02, /* Frame Mode */ |
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.panel_color = 0, |
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} |
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}; |
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#endif |
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/* Timing definitions for FPGA */ |
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static const u32 gpmc_fpga[] = { |
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FPGA_GPMC_CONFIG1, |
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@ -254,3 +294,46 @@ int board_mmc_init(bd_t *bis) |
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return omap_mmc_init(0, 0, 0); |
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} |
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#endif |
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#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) |
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int board_video_init(void) |
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{ |
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struct prcm *prcm_base = (struct prcm *)PRCM_BASE; |
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struct panel_config *panel = &lcd_cfg[0]; |
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char *s; |
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u32 index = 0; |
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void *fb; |
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fb = (void *)0x88000000; |
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s = getenv("panel"); |
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if (s) { |
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index = simple_strtoul(s, NULL, 10); |
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if (index < ARRAY_SIZE(lcd_cfg)) |
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panel = &lcd_cfg[index]; |
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else |
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return 0; |
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} |
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panel->frame_buffer = fb; |
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printf("Panel: %dx%d\n", panel_resolution[index].xres, |
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panel_resolution[index].yres); |
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panel->lcd_size = (panel_resolution[index].yres - 1) << 16 | |
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(panel_resolution[index].xres - 1); |
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gpio_request(LCD_PWR, "LCD Power"); |
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gpio_request(LCD_PON_PIN, "LCD Pon"); |
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gpio_direction_output(LCD_PWR, 0); |
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gpio_direction_output(LCD_PON_PIN, 1); |
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setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON); |
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setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON); |
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omap3_dss_panel_config(panel); |
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omap3_dss_enable(); |
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return 0; |
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} |
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#endif |
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