Emails to the board maintainer "Rishi Bhattacharya <rishi@ti.com>" have been bouncing. Tom suggested to remove this board. Remove also omap1510_udc.c because this is the last board to enable it. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Suggested-by: Tom Rini <trini@ti.com>master
Masahiro Yamada
11 years ago
committed by
Tom Rini
parent
9b586031db
commit
62d636aa2a
@ -1,23 +0,0 @@ |
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if TARGET_OMAP5912OSK |
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config SYS_CPU |
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string |
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default "arm926ejs" |
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config SYS_BOARD |
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string |
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default "omap5912osk" |
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config SYS_VENDOR |
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string |
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default "ti" |
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config SYS_SOC |
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string |
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default "omap" |
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config SYS_CONFIG_NAME |
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string |
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default "omap5912osk" |
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endif |
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@ -1,6 +0,0 @@ |
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OMAP5912OSK BOARD |
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M: Rishi Bhattacharya <rishi@ti.com> |
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S: Maintained |
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F: board/ti/omap5912osk/ |
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F: include/configs/omap5912osk.h |
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F: configs/omap5912osk_defconfig |
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@ -1,9 +0,0 @@ |
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := omap5912osk.o
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obj-y += lowlevel_init.o
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@ -1,30 +0,0 @@ |
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#
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# (C) Copyright 2002-2004
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# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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#
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# (C) Copyright 2003
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# Texas Instruments, <www.ti.com>
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# Kshitij Gupta <Kshitij@ti.com>
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#
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# (C) Copyright 2004
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# Texas Instruments, <www.ti.com>
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# Rishi Bhattacharya <rishi@ti.com>
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#
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# TI OSK board with OMAP5912 (ARM925EJS) cpu
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# see http://www.ti.com/ for more information on Texas Instruments
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#
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# OSK has 1 bank of 32 MB SDRAM
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# Physical Address:
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# 1000'0000 to 1200'0000
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#
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#
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# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
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# (mem base + reserved)
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#
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# When running from RAM use address 1108'0000, otherwise when
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# booting from NOR flash link to address 0000'0000.
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#
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CONFIG_SYS_TEXT_BASE = 0x00000000
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#CONFIG_SYS_TEXT_BASE = 0x11080000
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@ -1,477 +0,0 @@ |
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/* |
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* Board specific setup info |
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* |
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* (C) Copyright 2003 |
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* Texas Instruments, <www.ti.com> |
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* Kshitij Gupta <Kshitij@ti.com>
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* |
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* Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004 |
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* |
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* Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004 |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <config.h> |
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#include <version.h> |
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#if defined(CONFIG_OMAP1610) |
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#include <./configs/omap1510.h> |
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#endif |
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.globl lowlevel_init
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lowlevel_init: |
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/*------------------------------------------------------* |
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* Ensure i-cache is enabled * |
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* To configure TC regs without fetching instruction * |
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*------------------------------------------------------*/ |
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mrc p15, 0, r0, c1, c0 |
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orr r0, r0, #0x1000 |
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mcr p15, 0, r0, c1, c0 |
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/*------------------------------------------------------* |
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*mask all IRQs by setting all bits in the INTMR default* |
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*------------------------------------------------------*/ |
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mov r1, #0xffffffff |
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ldr r0, =REG_IHL1_MIR |
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str r1, [r0] |
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ldr r0, =REG_IHL2_MIR |
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str r1, [r0] |
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/*------------------------------------------------------* |
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* Set up ARM CLM registers (IDLECT1) * |
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*------------------------------------------------------*/ |
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ldr r0, REG_ARM_IDLECT1 |
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ldr r1, VAL_ARM_IDLECT1 |
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str r1, [r0] |
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/*------------------------------------------------------* |
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* Set up ARM CLM registers (IDLECT2) * |
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*------------------------------------------------------*/ |
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ldr r0, REG_ARM_IDLECT2 |
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ldr r1, VAL_ARM_IDLECT2 |
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str r1, [r0] |
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/*------------------------------------------------------* |
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* Set up ARM CLM registers (IDLECT3) * |
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*------------------------------------------------------*/ |
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ldr r0, REG_ARM_IDLECT3 |
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ldr r1, VAL_ARM_IDLECT3 |
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str r1, [r0] |
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mov r1, #0x01 /* PER_EN bit */ |
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ldr r0, REG_ARM_RSTCT2 |
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strh r1, [r0] /* CLKM; Peripheral reset. */
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/* Set CLKM to Sync-Scalable */ |
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mov r1, #0x1000 |
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ldr r0, REG_ARM_SYSST |
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mov r2, #0 |
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1: cmp r2, #1 |
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streqh r1, [r0] |
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add r2, r2, #1 |
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cmp r2, #0x100 /* wait for any bubbles to finish */ |
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bne 1b |
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ldr r1, VAL_ARM_CKCTL |
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ldr r0, REG_ARM_CKCTL |
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strh r1, [r0] |
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/* a few nops to let settle */ |
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nop |
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nop |
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nop |
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nop |
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nop |
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nop |
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nop |
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nop |
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nop |
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nop |
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/* setup DPLL 1 */ |
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/* Ramp up the clock to 96Mhz */ |
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ldr r1, VAL_DPLL1_CTL |
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ldr r0, REG_DPLL1_CTL |
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strh r1, [r0] |
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ands r1, r1, #0x10 /* Check if PLL is enabled. */ |
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beq lock_end /* Do not look for lock if BYPASS selected */ |
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2: |
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ldrh r1, [r0] |
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ands r1, r1, #0x01 /* Check the LOCK bit.*/ |
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beq 2b /* loop until bit goes hi. */ |
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lock_end: |
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/*------------------------------------------------------* |
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* Turn off the watchdog during init... * |
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*------------------------------------------------------*/ |
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ldr r0, REG_WATCHDOG |
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ldr r1, WATCHDOG_VAL1 |
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str r1, [r0] |
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ldr r1, WATCHDOG_VAL2 |
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str r1, [r0] |
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ldr r0, REG_WSPRDOG |
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ldr r1, WSPRDOG_VAL1 |
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str r1, [r0] |
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ldr r0, REG_WWPSDOG |
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watch1Wait: |
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ldr r1, [r0] |
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tst r1, #0x10 |
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bne watch1Wait |
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ldr r0, REG_WSPRDOG |
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ldr r1, WSPRDOG_VAL2 |
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str r1, [r0] |
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ldr r0, REG_WWPSDOG |
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watch2Wait: |
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ldr r1, [r0] |
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tst r1, #0x10 |
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bne watch2Wait |
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/* Set memory timings corresponding to the new clock speed */ |
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ldr r3, VAL_SDRAM_CONFIG_SDF0 |
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/* Check execution location to determine current execution location |
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* and branch to appropriate initialization code. |
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*/ |
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mov r0, #0x10000000 /* Load physical SDRAM base. */ |
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mov r1, pc /* Get current execution location. */ |
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cmp r1, r0 /* Compare. */ |
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bge skip_sdram /* Skip over EMIF-fast initialization if running from SDRAM. */ |
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/* identify the device revision, -- TMX or TMP(TMS) */ |
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ldr r0, REG_DEVICE_ID |
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ldr r1, [r0] |
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ldr r0, VAL_DEVICE_ID_TMP |
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mov r1, r1, lsl #15 |
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mov r1, r1, lsr #16 |
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cmp r0, r1 |
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bne skip_TMP_Patch |
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/* Enable TMP/TMS device new features */ |
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mov r0, #1 |
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ldr r1, REG_TC_EMIFF_DOUBLER |
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str r0, [r1] |
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/* Enable new ac parameters */ |
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mov r0, #0x0b |
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ldr r1, REG_SDRAM_CONFIG2 |
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str r0, [r1] |
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ldr r3, VAL_SDRAM_CONFIG_SDF1 |
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skip_TMP_Patch: |
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/* |
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* Delay for SDRAM initialization. |
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*/ |
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mov r0, #0x1800 /* value should be checked */ |
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3: |
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subs r0, r0, #0x1 /* Decrement count */ |
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bne 3b |
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/* |
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* Set SDRAM control values. Disable refresh before MRS command. |
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*/ |
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/* mobile ddr operation */ |
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ldr r0, REG_SDRAM_OPERATION |
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mov r2, #07 |
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str r2, [r0] |
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/* config register */ |
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ldr r0, REG_SDRAM_CONFIG |
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str r3, [r0] |
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/* manual command register */ |
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ldr r0, REG_SDRAM_MANUAL_CMD |
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/* issue set cke high */ |
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mov r1, #CMD_SDRAM_CKE_SET_HIGH |
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str r1, [r0] |
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/* issue nop */ |
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mov r1, #CMD_SDRAM_NOP |
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str r1, [r0] |
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mov r2, #0x0100 |
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waitMDDR1: |
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subs r2, r2, #1 |
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bne waitMDDR1 /* delay loop */ |
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/* issue precharge */ |
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mov r1, #CMD_SDRAM_PRECHARGE |
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str r1, [r0] |
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/* issue autorefresh x 2 */ |
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mov r1, #CMD_SDRAM_AUTOREFRESH |
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str r1, [r0] |
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str r1, [r0] |
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/* mrs register ddr mobile */ |
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ldr r0, REG_SDRAM_MRS |
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mov r1, #0x33 |
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str r1, [r0] |
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/* emrs1 low-power register */ |
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ldr r0, REG_SDRAM_EMRS1 |
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/* self refresh on all banks */ |
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mov r1, #0 |
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str r1, [r0] |
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ldr r0, REG_DLL_URD_CONTROL |
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ldr r1, DLL_URD_CONTROL_VAL |
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str r1, [r0] |
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ldr r0, REG_DLL_LRD_CONTROL |
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ldr r1, DLL_LRD_CONTROL_VAL |
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str r1, [r0] |
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ldr r0, REG_DLL_WRT_CONTROL |
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ldr r1, DLL_WRT_CONTROL_VAL |
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str r1, [r0] |
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/* delay loop */ |
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mov r0, #0x0100 |
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waitMDDR2: |
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subs r0, r0, #1 |
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bne waitMDDR2 |
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/* |
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* Delay for SDRAM initialization. |
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*/ |
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mov r0, #0x1800 |
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4: |
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subs r0, r0, #1 /* Decrement count. */ |
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bne 4b |
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b common_tc |
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skip_sdram: |
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ldr r0, REG_SDRAM_CONFIG |
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str r3, [r0] |
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common_tc: |
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/* slow interface */ |
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ldr r1, VAL_TC_EMIFS_CS0_CONFIG |
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ldr r0, REG_TC_EMIFS_CS0_CONFIG |
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str r1, [r0] /* Chip Select 0 */ |
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ldr r1, VAL_TC_EMIFS_CS1_CONFIG |
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ldr r0, REG_TC_EMIFS_CS1_CONFIG |
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str r1, [r0] /* Chip Select 1 */ |
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ldr r1, VAL_TC_EMIFS_CS3_CONFIG |
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ldr r0, REG_TC_EMIFS_CS3_CONFIG |
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str r1, [r0] /* Chip Select 3 */ |
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ldr r1, VAL_TC_EMIFS_DWS |
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ldr r0, REG_TC_EMIFS_DWS |
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str r1, [r0] /* Enable EMIFS.RDY for CS1 (ether) */ |
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#ifdef CONFIG_H2_OMAP1610 |
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/* inserting additional 2 clock cycle hold time for LAN */ |
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ldr r0, REG_TC_EMIFS_CS1_ADVANCED |
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ldr r1, VAL_TC_EMIFS_CS1_ADVANCED |
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str r1, [r0] |
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#endif |
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/* Start MPU Timer 1 */ |
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ldr r0, REG_MPU_LOAD_TIMER |
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ldr r1, VAL_MPU_LOAD_TIMER |
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str r1, [r0] |
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ldr r0, REG_MPU_CNTL_TIMER |
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ldr r1, VAL_MPU_CNTL_TIMER |
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str r1, [r0] |
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/* |
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* Setup a temporary stack |
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*/ |
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ldr sp, SRAM_STACK |
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bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ |
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/* |
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* Save the old lr(passed in ip) and the current lr to stack |
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*/ |
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push {ip, lr} |
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/* |
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* go setup pll, mux, memory |
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*/ |
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bl s_init |
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pop {ip, pc} |
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/* back to arch calling code */ |
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mov pc, lr |
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/* the literal pools origin */ |
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.ltorg |
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REG_DEVICE_ID: /* 32 bits */ |
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.word 0xfffe2004
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REG_TC_EMIFS_CONFIG: |
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.word 0xfffecc0c
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REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */ |
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.word 0xfffecc10
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REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */ |
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.word 0xfffecc14
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REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */ |
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.word 0xfffecc18
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REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */ |
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.word 0xfffecc1c
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REG_TC_EMIFS_DWS: /* 32 bits */ |
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.word 0xfffecc40
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#ifdef CONFIG_H2_OMAP1610 |
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REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */ |
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.word 0xfffecc54
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#endif |
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/* MPU clock/reset/power mode control registers */ |
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REG_ARM_CKCTL: /* 16 bits */ |
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.word 0xfffece00
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REG_ARM_IDLECT3: /* 16 bits */ |
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.word 0xfffece24
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REG_ARM_IDLECT2: /* 16 bits */ |
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.word 0xfffece08
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REG_ARM_IDLECT1: /* 16 bits */ |
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.word 0xfffece04
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REG_ARM_RSTCT2: /* 16 bits */ |
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.word 0xfffece14
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REG_ARM_SYSST: /* 16 bits */ |
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.word 0xfffece18
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/* DPLL control registers */ |
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REG_DPLL1_CTL: /* 16 bits */ |
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.word 0xfffecf00
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/* Watch Dog register */ |
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/* secure watchdog stop */ |
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REG_WSPRDOG: |
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.word 0xfffeb048
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/* watchdog write pending */ |
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REG_WWPSDOG: |
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.word 0xfffeb034
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WSPRDOG_VAL1: |
|
||||||
.word 0x0000aaaa
|
|
||||||
WSPRDOG_VAL2: |
|
||||||
.word 0x00005555
|
|
||||||
|
|
||||||
/* SDRAM config is: auto refresh enabled, 16 bit 4 bank, |
|
||||||
counter @8192 rows, 10 ns, 8 burst */
|
|
||||||
REG_SDRAM_CONFIG: |
|
||||||
.word 0xfffecc20
|
|
||||||
REG_SDRAM_CONFIG2: |
|
||||||
.word 0xfffecc3c
|
|
||||||
REG_TC_EMIFF_DOUBLER: /* 32 bits */ |
|
||||||
.word 0xfffecc60
|
|
||||||
|
|
||||||
/* Operation register */ |
|
||||||
REG_SDRAM_OPERATION: |
|
||||||
.word 0xfffecc80
|
|
||||||
|
|
||||||
/* Manual command register */ |
|
||||||
REG_SDRAM_MANUAL_CMD: |
|
||||||
.word 0xfffecc84
|
|
||||||
|
|
||||||
/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ |
|
||||||
REG_SDRAM_MRS: |
|
||||||
.word 0xfffecc70
|
|
||||||
|
|
||||||
/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ |
|
||||||
REG_SDRAM_EMRS1: |
|
||||||
.word 0xfffecc78
|
|
||||||
|
|
||||||
/* WRT DLL register */ |
|
||||||
REG_DLL_WRT_CONTROL: |
|
||||||
.word 0xfffecc68
|
|
||||||
DLL_WRT_CONTROL_VAL: |
|
||||||
.word 0x03f00002 /* Phase of 72deg, write offset +31 */ |
|
||||||
|
|
||||||
/* URD DLL register */ |
|
||||||
REG_DLL_URD_CONTROL: |
|
||||||
.word 0xfffeccc0
|
|
||||||
DLL_URD_CONTROL_VAL: |
|
||||||
.word 0x00800002 /* Phase of 72deg, read offset +31 */ |
|
||||||
|
|
||||||
/* LRD DLL register */ |
|
||||||
REG_DLL_LRD_CONTROL: |
|
||||||
.word 0xfffecccc
|
|
||||||
DLL_LRD_CONTROL_VAL: |
|
||||||
.word 0x00800002 /* read offset +31 */ |
|
||||||
|
|
||||||
REG_WATCHDOG: |
|
||||||
.word 0xfffec808
|
|
||||||
WATCHDOG_VAL1: |
|
||||||
.word 0x000000f5
|
|
||||||
WATCHDOG_VAL2: |
|
||||||
.word 0x000000a0
|
|
||||||
|
|
||||||
REG_MPU_LOAD_TIMER: |
|
||||||
.word 0xfffec504
|
|
||||||
REG_MPU_CNTL_TIMER: |
|
||||||
.word 0xfffec500
|
|
||||||
VAL_MPU_LOAD_TIMER: |
|
||||||
.word 0xffffffff
|
|
||||||
VAL_MPU_CNTL_TIMER: |
|
||||||
.word 0xffffffa1
|
|
||||||
|
|
||||||
/* 96 MHz Samsung Mobile DDR */ |
|
||||||
/* Original setting for TMX device */ |
|
||||||
VAL_SDRAM_CONFIG_SDF0: |
|
||||||
.word 0x0014e6fe
|
|
||||||
|
|
||||||
/* NEW_SYS_FREQ mode (valid only TMP/TMS devices) */ |
|
||||||
VAL_SDRAM_CONFIG_SDF1: |
|
||||||
.word 0x0114e6fe
|
|
||||||
|
|
||||||
VAL_ARM_CKCTL: |
|
||||||
.word 0x2000 /* was: 0x3000, now use CLK_REF for timer input */ |
|
||||||
VAL_DPLL1_CTL: |
|
||||||
.word 0x2830
|
|
||||||
|
|
||||||
#ifdef CONFIG_OSK_OMAP5912 |
|
||||||
VAL_TC_EMIFS_CS0_CONFIG: |
|
||||||
.word 0x002130b0
|
|
||||||
VAL_TC_EMIFS_CS1_CONFIG: |
|
||||||
.word 0x00001133
|
|
||||||
VAL_TC_EMIFS_CS2_CONFIG: |
|
||||||
.word 0x000055f0
|
|
||||||
VAL_TC_EMIFS_CS3_CONFIG: |
|
||||||
.word 0x88013141
|
|
||||||
VAL_TC_EMIFS_DWS: /* Enable EMIFS.RDY for CS1 access (ether) */ |
|
||||||
.word 0x000000c0
|
|
||||||
VAL_DEVICE_ID_TMP: /* TMP/TMS=0xb65f, TMX=0xb58c */ |
|
||||||
.word 0xb65f
|
|
||||||
#endif |
|
||||||
|
|
||||||
#ifdef CONFIG_H2_OMAP1610 |
|
||||||
VAL_TC_EMIFS_CS0_CONFIG: |
|
||||||
.word 0x00203331
|
|
||||||
VAL_TC_EMIFS_CS1_CONFIG: |
|
||||||
.word 0x8180fff3
|
|
||||||
VAL_TC_EMIFS_CS2_CONFIG: |
|
||||||
.word 0xf800f22a
|
|
||||||
VAL_TC_EMIFS_CS3_CONFIG: |
|
||||||
.word 0x88013141
|
|
||||||
VAL_TC_EMIFS_CS1_ADVANCED: |
|
||||||
.word 0x00000022
|
|
||||||
#endif |
|
||||||
|
|
||||||
VAL_ARM_IDLECT1: |
|
||||||
.word 0x00000400
|
|
||||||
VAL_ARM_IDLECT2: |
|
||||||
.word 0x00000886
|
|
||||||
VAL_ARM_IDLECT3: |
|
||||||
.word 0x00000015
|
|
||||||
|
|
||||||
SRAM_STACK: |
|
||||||
.word CONFIG_SYS_INIT_SP_ADDR
|
|
||||||
|
|
||||||
/* command values */ |
|
||||||
.equ CMD_SDRAM_NOP, 0x00000000 |
|
||||||
.equ CMD_SDRAM_PRECHARGE, 0x00000001 |
|
||||||
.equ CMD_SDRAM_AUTOREFRESH, 0x00000002 |
|
||||||
.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007 |
|
||||||
@ -1,307 +0,0 @@ |
|||||||
/*
|
|
||||||
* (C) Copyright 2002 |
|
||||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
|
||||||
* Marius Groeger <mgroeger@sysgo.de> |
|
||||||
* |
|
||||||
* (C) Copyright 2002 |
|
||||||
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> |
|
||||||
* |
|
||||||
* (C) Copyright 2003 |
|
||||||
* Texas Instruments, <www.ti.com> |
|
||||||
* Kshitij Gupta <Kshitij@ti.com> |
|
||||||
* |
|
||||||
* (C) Copyright 2004 |
|
||||||
* Texas Instruments, <www.ti.com> |
|
||||||
* Rishi Bhattacharya <rishi@ti.com> |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: GPL-2.0+ |
|
||||||
*/ |
|
||||||
|
|
||||||
#include <common.h> |
|
||||||
#include <netdev.h> |
|
||||||
#if defined(CONFIG_OMAP1610) |
|
||||||
#include <./configs/omap1510.h> |
|
||||||
#endif |
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR; |
|
||||||
|
|
||||||
void flash__init (void); |
|
||||||
void ether__init (void); |
|
||||||
void set_muxconf_regs (void); |
|
||||||
void peripheral_power_enable (void); |
|
||||||
|
|
||||||
#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) |
|
||||||
|
|
||||||
static inline void delay (unsigned long loops) |
|
||||||
{ |
|
||||||
__asm__ volatile ("1:\n" |
|
||||||
"subs %0, %1, #1\n" |
|
||||||
"bne 1b":"=r" (loops):"0" (loops)); |
|
||||||
} |
|
||||||
|
|
||||||
/*
|
|
||||||
* Miscellaneous platform dependent initialisations |
|
||||||
*/ |
|
||||||
|
|
||||||
int board_init (void) |
|
||||||
{ |
|
||||||
gd->bd->bi_arch_number = MACH_TYPE_OMAP_OSK; |
|
||||||
|
|
||||||
/* adress of boot parameters */ |
|
||||||
gd->bd->bi_boot_params = 0x10000100; |
|
||||||
|
|
||||||
flash__init(); |
|
||||||
ether__init(); |
|
||||||
|
|
||||||
return 0; |
|
||||||
} |
|
||||||
|
|
||||||
void s_init(void) |
|
||||||
{ |
|
||||||
/* Configure MUX settings */ |
|
||||||
set_muxconf_regs (); |
|
||||||
peripheral_power_enable (); |
|
||||||
|
|
||||||
/* this speeds up your boot a quite a bit. However to make it
|
|
||||||
* work, you need make sure your kernel startup flush bug is fixed. |
|
||||||
* ... rkw ... |
|
||||||
*/ |
|
||||||
icache_enable (); |
|
||||||
} |
|
||||||
|
|
||||||
/******************************
|
|
||||||
Routine: |
|
||||||
Description: |
|
||||||
******************************/ |
|
||||||
void flash__init (void) |
|
||||||
{ |
|
||||||
#define EMIFS_GlB_Config_REG 0xfffecc0c |
|
||||||
unsigned int regval; |
|
||||||
regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG); |
|
||||||
/* Turn off write protection for flash devices. */ |
|
||||||
regval = regval | 0x0001; |
|
||||||
*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval; |
|
||||||
} |
|
||||||
/*************************************************************
|
|
||||||
Routine:ether__init |
|
||||||
Description: take the Ethernet controller out of reset and wait |
|
||||||
for the EEPROM load to complete. |
|
||||||
*************************************************************/ |
|
||||||
void ether__init (void) |
|
||||||
{ |
|
||||||
#define ETH_CONTROL_REG 0x0480000b |
|
||||||
int i; |
|
||||||
|
|
||||||
*((volatile unsigned short *) 0xfffece08) = 0x03FF; |
|
||||||
*((volatile unsigned short *) 0xfffb3824) = 0x8000; |
|
||||||
*((volatile unsigned short *) 0xfffb3830) = 0x0000; |
|
||||||
*((volatile unsigned short *) 0xfffb3834) = 0x0009; |
|
||||||
*((volatile unsigned short *) 0xfffb3838) = 0x0009; |
|
||||||
*((volatile unsigned short *) 0xfffb3818) = 0x0002; |
|
||||||
*((volatile unsigned short *) 0xfffb382C) = 0x0048; |
|
||||||
*((volatile unsigned short *) 0xfffb3824) = 0x8603; |
|
||||||
udelay (3); |
|
||||||
for (i=0;i<2000;i++); |
|
||||||
*((volatile unsigned short *) 0xfffb381C) = 0x6610; |
|
||||||
udelay (30); |
|
||||||
for (i=0;i<10000;i++); |
|
||||||
|
|
||||||
*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; |
|
||||||
udelay (3); |
|
||||||
|
|
||||||
|
|
||||||
} |
|
||||||
|
|
||||||
/******************************
|
|
||||||
Routine: |
|
||||||
Description: |
|
||||||
******************************/ |
|
||||||
int dram_init(void) |
|
||||||
{ |
|
||||||
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); |
|
||||||
|
|
||||||
return 0; |
|
||||||
} |
|
||||||
|
|
||||||
void dram_init_banksize(void) |
|
||||||
{ |
|
||||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
|
||||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
|
||||||
} |
|
||||||
|
|
||||||
/******************************************************
|
|
||||||
Routine: set_muxconf_regs |
|
||||||
Description: Setting up the configuration Mux registers |
|
||||||
specific to the hardware |
|
||||||
*******************************************************/ |
|
||||||
void set_muxconf_regs (void) |
|
||||||
{ |
|
||||||
volatile unsigned int *MuxConfReg; |
|
||||||
/* set each registers to its reset value; */ |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0); |
|
||||||
/* setup for UART1 */ |
|
||||||
*MuxConfReg &= ~(0x02000000); /* bit 25 */ |
|
||||||
/* setup for UART2 */ |
|
||||||
*MuxConfReg &= ~(0x01000000); /* bit 24 */ |
|
||||||
/* Disable Uwire CS Hi-Z */ |
|
||||||
*MuxConfReg |= 0x08000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6); |
|
||||||
/*setup mux for UART3 */ |
|
||||||
*MuxConfReg |= 0x00000001; /* bit3, 1, 0 (mux0 5,5,26) */ |
|
||||||
*MuxConfReg &= ~0x0000003e; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8); |
|
||||||
/* Disable Uwire CS Hi-Z */ |
|
||||||
*MuxConfReg |= 0x00001200; /*bit 9 for CS0 12 for CS3 */ |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9); |
|
||||||
/* Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the */ |
|
||||||
/* hardware will actually use TX and RTS based on bit 25 in */ |
|
||||||
/* FUNC_MUX_CTRL_0. I told you this thing was screwy! */ |
|
||||||
*MuxConfReg |= 0x00201000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C); |
|
||||||
/* setup for UART2 */ |
|
||||||
/* Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the */ |
|
||||||
/* hardware will actually use TX and RTS based on bit 24 in */ |
|
||||||
/* FUNC_MUX_CTRL_0. */ |
|
||||||
*MuxConfReg |= 0x09000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_D); |
|
||||||
*MuxConfReg |= 0x00000020; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
/* mux setup for SD/MMC driver */ |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2); |
|
||||||
*MuxConfReg &= 0xFFFE0FFF; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); |
|
||||||
/* bit 13 for MMC2 XOR_CLK */ |
|
||||||
*MuxConfReg &= ~(0x00002000); |
|
||||||
/* bit 29 for UART 1 */ |
|
||||||
*MuxConfReg &= ~(0x00002000); |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0); |
|
||||||
/* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */ |
|
||||||
*MuxConfReg |= 0x000C0000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL); |
|
||||||
*MuxConfReg &= ~(0x00000070); |
|
||||||
*MuxConfReg &= ~(0x00000008); |
|
||||||
*MuxConfReg |= 0x00000003; |
|
||||||
*MuxConfReg |= 0x00000180; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); |
|
||||||
/* bit 17, software controls VBUS */ |
|
||||||
*MuxConfReg &= ~(0x00020000); |
|
||||||
/* Enable USB 48 and 12M clocks */ |
|
||||||
*MuxConfReg |= 0x00000200; |
|
||||||
*MuxConfReg &= ~(0x00000180); |
|
||||||
/*2.75V for MMCSDIO1 */ |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0); |
|
||||||
*MuxConfReg = 0x00001FE7; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) PU_PD_SEL_0); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) PU_PD_SEL_1); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) PU_PD_SEL_3); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) PU_PD_SEL_4); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4); |
|
||||||
*MuxConfReg = 0x00000000; |
|
||||||
/* Turn on UART2 48 MHZ clock */ |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); |
|
||||||
*MuxConfReg |= 0x40000000; |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) USB_OTG_CTRL); |
|
||||||
/* setup for USB VBus detection OMAP161x */ |
|
||||||
*MuxConfReg |= 0x00040000; /* bit 18 */ |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2); |
|
||||||
/* PullUps for SD/MMC driver */ |
|
||||||
*MuxConfReg |= ~(0xFFFE0FFF); |
|
||||||
MuxConfReg = |
|
||||||
(volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0); |
|
||||||
*MuxConfReg = COMP_MODE_ENABLE; |
|
||||||
} |
|
||||||
|
|
||||||
/******************************************************
|
|
||||||
Routine: peripheral_power_enable |
|
||||||
Description: Enable the power for UART1 |
|
||||||
*******************************************************/ |
|
||||||
void peripheral_power_enable (void) |
|
||||||
{ |
|
||||||
#define UART1_48MHZ_ENABLE ((unsigned short)0x0200) |
|
||||||
#define SW_CLOCK_REQUEST ((volatile unsigned short *)0xFFFE0834) |
|
||||||
|
|
||||||
*SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE; |
|
||||||
} |
|
||||||
|
|
||||||
/*
|
|
||||||
* Check Board Identity |
|
||||||
*/ |
|
||||||
int checkboard(void) |
|
||||||
{ |
|
||||||
char buf[64]; |
|
||||||
int i = getenv_f("serial#", buf, sizeof(buf)); |
|
||||||
|
|
||||||
puts("Board: OSK5912"); |
|
||||||
|
|
||||||
if (i > 0) { |
|
||||||
puts(", serial# "); |
|
||||||
puts(buf); |
|
||||||
} |
|
||||||
putc('\n'); |
|
||||||
|
|
||||||
return (0); |
|
||||||
} |
|
||||||
|
|
||||||
#ifdef CONFIG_CMD_NET |
|
||||||
int board_eth_init(bd_t *bis) |
|
||||||
{ |
|
||||||
int rc = 0; |
|
||||||
#ifdef CONFIG_LAN91C96 |
|
||||||
rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); |
|
||||||
#endif |
|
||||||
return rc; |
|
||||||
} |
|
||||||
#endif |
|
||||||
@ -1,2 +0,0 @@ |
|||||||
CONFIG_ARM=y |
|
||||||
CONFIG_TARGET_OMAP5912OSK=y |
|
||||||
File diff suppressed because it is too large
Load Diff
@ -1,756 +0,0 @@ |
|||||||
/*
|
|
||||||
* |
|
||||||
* BRIEF MODULE DESCRIPTION |
|
||||||
* OMAP hardware map |
|
||||||
* |
|
||||||
* Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com)
|
|
||||||
* Author: RidgeRun, Inc. |
|
||||||
* Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: GPL-2.0+ |
|
||||||
*/ |
|
||||||
|
|
||||||
#include <linux/sizes.h> |
|
||||||
|
|
||||||
/*
|
|
||||||
There are 2 sets of general I/O --> |
|
||||||
1. GPIO (shared between ARM & DSP, configured by ARM) |
|
||||||
2. MPUIO which can be used only by the ARM. |
|
||||||
|
|
||||||
Base address FFFB:5000 is where the ARM accesses the MPUIO control registers |
|
||||||
(see 7.2.2 of the TRM for MPUIO reg definitions). |
|
||||||
|
|
||||||
Base address E101:5000 is reserved for ARM access of the same MPUIO control |
|
||||||
regs, but via the DSP I/O map. This address is unavailable on 1510. |
|
||||||
|
|
||||||
Base address FFFC:E000 is where the ARM accesses the GPIO config registers |
|
||||||
directly via its own peripheral bus. |
|
||||||
|
|
||||||
Base address E101:E000 is where the ARM can access the same GPIO config |
|
||||||
registers, but the access takes place through the ARM port interface (called |
|
||||||
API or MPUI) via the DSP's peripheral bus (DSP I/O space). |
|
||||||
|
|
||||||
Therefore, the ARM should setup the GPIO regs thru the FFFC:E000 addresses |
|
||||||
instead of the E101:E000 addresses. The DSP has only read access of the pin |
|
||||||
control register, so this may explain the inability to write to E101:E018. |
|
||||||
Try accessing pin control reg at FFFC:E018. |
|
||||||
*/ |
|
||||||
#define OMAP1510_GPIO_BASE 0xfffce000 |
|
||||||
#define OMAP1510_GPIO_START OMAP1510_GPIO_BASE |
|
||||||
#define OMAP1510_GPIO_SIZE SZ_4K |
|
||||||
|
|
||||||
#define OMAP1510_MCBSP1_BASE 0xE1011000 |
|
||||||
#define OMAP1510_MCBSP1_SIZE SZ_4K |
|
||||||
#define OMAP1510_MCBSP1_START 0xE1011000 |
|
||||||
|
|
||||||
#define OMAP1510_MCBSP2_BASE 0xFFFB1000 |
|
||||||
|
|
||||||
#define OMAP1510_MCBSP3_BASE 0xE1017000 |
|
||||||
#define OMAP1510_MCBSP3_SIZE SZ_4K |
|
||||||
#define OMAP1510_MCBSP3_START 0xE1017000 |
|
||||||
|
|
||||||
/*
|
|
||||||
* Where's the flush address (for flushing D and I cache?) |
|
||||||
*/ |
|
||||||
#define FLUSH_BASE 0xdf000000 |
|
||||||
#define FLUSH_BASE_PHYS 0x00000000 |
|
||||||
|
|
||||||
#ifndef __ASSEMBLER__ |
|
||||||
|
|
||||||
#define PCIO_BASE 0 |
|
||||||
|
|
||||||
/*
|
|
||||||
* RAM definitions |
|
||||||
*/ |
|
||||||
#define MAPTOPHYS(a) ((unsigned long)(a) - PAGE_OFFSET) |
|
||||||
#define KERNTOPHYS(a) ((unsigned long)(&a)) |
|
||||||
#define KERNEL_BASE (0x10008000) |
|
||||||
#endif |
|
||||||
|
|
||||||
/* macro to get at IO space when running virtually */ |
|
||||||
#define IO_ADDRESS(x) ((x)) |
|
||||||
|
|
||||||
/* ----------------------------------------------------------------------------
|
|
||||||
* OMAP1510 system registers |
|
||||||
* ---------------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
|
|
||||||
#define OMAP1510_UART1_BASE 0xfffb0000 /* "BLUETOOTH-UART" */ |
|
||||||
#define OMAP1510_UART2_BASE 0xfffb0800 /* "MODEM-UART" */ |
|
||||||
#define OMAP1510_RTC_BASE 0xfffb4800 /* RTC */ |
|
||||||
#define OMAP1510_UART3_BASE 0xfffb9800 /* Shared MPU/DSP UART */ |
|
||||||
#define OMAP1510_COM_MCBSP2_BASE 0xffff1000 /* Com McBSP2 */ |
|
||||||
#define OMAP1510_AUDIO_MCBSP_BASE 0xffff1800 /* Audio McBSP2 */ |
|
||||||
#define OMAP1510_ARMIO_BASE 0xfffb5000 /* keyboard/gpio */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* OMAP1510 UART3 Registers |
|
||||||
*/ |
|
||||||
|
|
||||||
#define OMAP_MPU_UART3_BASE 0xFFFB9800 /* UART3 through MPU bus */ |
|
||||||
|
|
||||||
/* UART3 Registers Maping through MPU bus */ |
|
||||||
|
|
||||||
#define UART3_RHR (OMAP_MPU_UART3_BASE + 0) |
|
||||||
#define UART3_THR (OMAP_MPU_UART3_BASE + 0) |
|
||||||
#define UART3_DLL (OMAP_MPU_UART3_BASE + 0) |
|
||||||
#define UART3_IER (OMAP_MPU_UART3_BASE + 4) |
|
||||||
#define UART3_DLH (OMAP_MPU_UART3_BASE + 4) |
|
||||||
#define UART3_IIR (OMAP_MPU_UART3_BASE + 8) |
|
||||||
#define UART3_FCR (OMAP_MPU_UART3_BASE + 8) |
|
||||||
#define UART3_EFR (OMAP_MPU_UART3_BASE + 8) |
|
||||||
#define UART3_LCR (OMAP_MPU_UART3_BASE + 0x0C) |
|
||||||
#define UART3_MCR (OMAP_MPU_UART3_BASE + 0x10) |
|
||||||
#define UART3_XON1_ADDR1 (OMAP_MPU_UART3_BASE + 0x10) |
|
||||||
#define UART3_XON2_ADDR2 (OMAP_MPU_UART3_BASE + 0x14) |
|
||||||
#define UART3_LSR (OMAP_MPU_UART3_BASE + 0x14) |
|
||||||
#define UART3_TCR (OMAP_MPU_UART3_BASE + 0x18) |
|
||||||
#define UART3_MSR (OMAP_MPU_UART3_BASE + 0x18) |
|
||||||
#define UART3_XOFF1 (OMAP_MPU_UART3_BASE + 0x18) |
|
||||||
#define UART3_XOFF2 (OMAP_MPU_UART3_BASE + 0x1C) |
|
||||||
#define UART3_SPR (OMAP_MPU_UART3_BASE + 0x1C) |
|
||||||
#define UART3_TLR (OMAP_MPU_UART3_BASE + 0x1C) |
|
||||||
#define UART3_MDR1 (OMAP_MPU_UART3_BASE + 0x20) |
|
||||||
#define UART3_MDR2 (OMAP_MPU_UART3_BASE + 0x24) |
|
||||||
#define UART3_SFLSR (OMAP_MPU_UART3_BASE + 0x28) |
|
||||||
#define UART3_TXFLL (OMAP_MPU_UART3_BASE + 0x28) |
|
||||||
#define UART3_RESUME (OMAP_MPU_UART3_BASE + 0x2C) |
|
||||||
#define UART3_TXFLH (OMAP_MPU_UART3_BASE + 0x2C) |
|
||||||
#define UART3_SFREGL (OMAP_MPU_UART3_BASE + 0x30) |
|
||||||
#define UART3_RXFLL (OMAP_MPU_UART3_BASE + 0x30) |
|
||||||
#define UART3_SFREGH (OMAP_MPU_UART3_BASE + 0x34) |
|
||||||
#define UART3_RXFLH (OMAP_MPU_UART3_BASE + 0x34) |
|
||||||
#define UART3_BLR (OMAP_MPU_UART3_BASE + 0x38) |
|
||||||
#define UART3_ACREG (OMAP_MPU_UART3_BASE + 0x3C) |
|
||||||
#define UART3_DIV16 (OMAP_MPU_UART3_BASE + 0x3C) |
|
||||||
#define UART3_SCR (OMAP_MPU_UART3_BASE + 0x40) |
|
||||||
#define UART3_SSR (OMAP_MPU_UART3_BASE + 0x44) |
|
||||||
#define UART3_EBLR (OMAP_MPU_UART3_BASE + 0x48) |
|
||||||
#define UART3_OSC_12M_SEL (OMAP_MPU_UART3_BASE + 0x4C) |
|
||||||
#define UART3_MVR (OMAP_MPU_UART3_BASE + 0x50) |
|
||||||
|
|
||||||
/*
|
|
||||||
* Configuration Registers |
|
||||||
*/ |
|
||||||
#define FUNC_MUX_CTRL_0 0xfffe1000 |
|
||||||
#define FUNC_MUX_CTRL_1 0xfffe1004 |
|
||||||
#define FUNC_MUX_CTRL_2 0xfffe1008 |
|
||||||
#define COMP_MODE_CTRL_0 0xfffe100c |
|
||||||
#define FUNC_MUX_CTRL_3 0xfffe1010 |
|
||||||
#define FUNC_MUX_CTRL_4 0xfffe1014 |
|
||||||
#define FUNC_MUX_CTRL_5 0xfffe1018 |
|
||||||
#define FUNC_MUX_CTRL_6 0xfffe101C |
|
||||||
#define FUNC_MUX_CTRL_7 0xfffe1020 |
|
||||||
#define FUNC_MUX_CTRL_8 0xfffe1024 |
|
||||||
#define FUNC_MUX_CTRL_9 0xfffe1028 |
|
||||||
#define FUNC_MUX_CTRL_A 0xfffe102C |
|
||||||
#define FUNC_MUX_CTRL_B 0xfffe1030 |
|
||||||
#define FUNC_MUX_CTRL_C 0xfffe1034 |
|
||||||
#define FUNC_MUX_CTRL_D 0xfffe1038 |
|
||||||
#define PULL_DWN_CTRL_0 0xfffe1040 |
|
||||||
#define PULL_DWN_CTRL_1 0xfffe1044 |
|
||||||
#define PULL_DWN_CTRL_2 0xfffe1048 |
|
||||||
#define PULL_DWN_CTRL_3 0xfffe104c |
|
||||||
#define GATE_INH_CTRL_0 0xfffe1050 |
|
||||||
#define VOLTAGE_CTRL_0 0xfffe1060 |
|
||||||
#define TEST_DBG_CTRL_0 0xfffe1070 |
|
||||||
|
|
||||||
#define MOD_CONF_CTRL_0 0xfffe1080 |
|
||||||
|
|
||||||
#ifdef CONFIG_OMAP1610 /* 1610 Configuration Register */ |
|
||||||
|
|
||||||
#define USB_OTG_CTRL 0xFFFB040C |
|
||||||
#define USB_TRANSCEIVER_CTRL 0xFFFE1064 |
|
||||||
#define PULL_DWN_CTRL_4 0xFFFE10AC |
|
||||||
#define PU_PD_SEL_0 0xFFFE10B4 |
|
||||||
#define PU_PD_SEL_1 0xFFFE10B8 |
|
||||||
#define PU_PD_SEL_2 0xFFFE10BC |
|
||||||
#define PU_PD_SEL_3 0xFFFE10C0 |
|
||||||
#define PU_PD_SEL_4 0xFFFE10C4 |
|
||||||
|
|
||||||
#endif |
|
||||||
/*
|
|
||||||
* Traffic Controller Memory Interface Registers |
|
||||||
*/ |
|
||||||
#define TCMIF_BASE 0xfffecc00 |
|
||||||
#define IMIF_PRIO (TCMIF_BASE + 0x00) |
|
||||||
#define EMIFS_PRIO_REG (TCMIF_BASE + 0x04) |
|
||||||
#define EMIFF_PRIO_REG (TCMIF_BASE + 0x08) |
|
||||||
#define EMIFS_CONFIG_REG (TCMIF_BASE + 0x0c) |
|
||||||
#define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10) |
|
||||||
#define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14) |
|
||||||
#define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18) |
|
||||||
#define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c) |
|
||||||
#define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20) |
|
||||||
#define EMIFF_MRS (TCMIF_BASE + 0x24) |
|
||||||
#define TC_TIMEOUT1 (TCMIF_BASE + 0x28) |
|
||||||
#define TC_TIMEOUT2 (TCMIF_BASE + 0x2c) |
|
||||||
#define TC_TIMEOUT3 (TCMIF_BASE + 0x30) |
|
||||||
#define TC_ENDIANISM (TCMIF_BASE + 0x34) |
|
||||||
#define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c) |
|
||||||
#define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40) |
|
||||||
|
|
||||||
/*
|
|
||||||
* LCD Panel |
|
||||||
*/ |
|
||||||
#define TI925_LCD_BASE 0xFFFEC000 |
|
||||||
#define TI925_LCD_CONTROL (TI925_LCD_BASE) |
|
||||||
#define TI925_LCD_TIMING0 (TI925_LCD_BASE+0x4) |
|
||||||
#define TI925_LCD_TIMING1 (TI925_LCD_BASE+0x8) |
|
||||||
#define TI925_LCD_TIMING2 (TI925_LCD_BASE+0xc) |
|
||||||
#define TI925_LCD_STATUS (TI925_LCD_BASE+0x10) |
|
||||||
#define TI925_LCD_SUBPANEL (TI925_LCD_BASE+0x14) |
|
||||||
|
|
||||||
#define OMAP_LCD_CONTROL TI925_LCD_CONTROL |
|
||||||
|
|
||||||
/* I2C Registers */ |
|
||||||
|
|
||||||
#define I2C_BASE 0xfffb3800 |
|
||||||
|
|
||||||
#define I2C_REV (I2C_BASE + 0x00) |
|
||||||
#define I2C_IE (I2C_BASE + 0x04) |
|
||||||
#define I2C_STAT (I2C_BASE + 0x08) |
|
||||||
#define I2C_IV (I2C_BASE + 0x0c) |
|
||||||
#define I2C_BUF (I2C_BASE + 0x14) |
|
||||||
#define I2C_CNT (I2C_BASE + 0x18) |
|
||||||
#define I2C_DATA (I2C_BASE + 0x1c) |
|
||||||
#define I2C_CON (I2C_BASE + 0x24) |
|
||||||
#define I2C_OA (I2C_BASE + 0x28) |
|
||||||
#define I2C_SA (I2C_BASE + 0x2c) |
|
||||||
#define I2C_PSC (I2C_BASE + 0x30) |
|
||||||
#define I2C_SCLL (I2C_BASE + 0x34) |
|
||||||
#define I2C_SCLH (I2C_BASE + 0x38) |
|
||||||
#define I2C_SYSTEST (I2C_BASE + 0x3c) |
|
||||||
|
|
||||||
/* I2C masks */ |
|
||||||
|
|
||||||
/* I2C Interrupt Enable Register (I2C_IE): */ |
|
||||||
|
|
||||||
#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ |
|
||||||
#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ |
|
||||||
#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ |
|
||||||
#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ |
|
||||||
#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ |
|
||||||
|
|
||||||
/* I2C Status Register (I2C_STAT): */ |
|
||||||
|
|
||||||
#define I2C_STAT_SBD (1 << 15) /* Single byte data */ |
|
||||||
#define I2C_STAT_BB (1 << 12) /* Bus busy */ |
|
||||||
#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ |
|
||||||
#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ |
|
||||||
#define I2C_STAT_AAS (1 << 9) /* Address as slave */ |
|
||||||
#define I2C_STAT_AD0 (1 << 8) /* Address zero */ |
|
||||||
#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ |
|
||||||
#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ |
|
||||||
#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ |
|
||||||
#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ |
|
||||||
#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ |
|
||||||
|
|
||||||
/* I2C Interrupt Vector Register (I2C_IV): */ |
|
||||||
|
|
||||||
/* I2C Interrupt Code Register (I2C_INTCODE): */ |
|
||||||
|
|
||||||
#define I2C_INTCODE_MASK 7 |
|
||||||
#define I2C_INTCODE_NONE 0 |
|
||||||
#define I2C_INTCODE_AL 1 /* Arbitration lost */ |
|
||||||
#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ |
|
||||||
#define I2C_INTCODE_ARDY 3 /* Register access ready */ |
|
||||||
#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ |
|
||||||
#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ |
|
||||||
|
|
||||||
/* I2C Buffer Configuration Register (I2C_BUF): */ |
|
||||||
|
|
||||||
#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ |
|
||||||
#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ |
|
||||||
|
|
||||||
/* I2C Configuration Register (I2C_CON): */ |
|
||||||
|
|
||||||
#define I2C_CON_EN (1 << 15) /* I2C module enable */ |
|
||||||
#define I2C_CON_BE (1 << 14) /* Big endian mode */ |
|
||||||
#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ |
|
||||||
#define I2C_CON_MST (1 << 10) /* Master/slave mode */ |
|
||||||
#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */ |
|
||||||
#define I2C_CON_XA (1 << 8) /* Expand address */ |
|
||||||
#define I2C_CON_RM (1 << 2) /* Repeat mode (master mode only) */ |
|
||||||
#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ |
|
||||||
#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ |
|
||||||
|
|
||||||
/* I2C System Test Register (I2C_SYSTEST): */ |
|
||||||
|
|
||||||
#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ |
|
||||||
#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode (on breakpoint) */ |
|
||||||
#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ |
|
||||||
#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ |
|
||||||
#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ |
|
||||||
#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ |
|
||||||
#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ |
|
||||||
#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* MMC/SD Host Controller Registers |
|
||||||
*/ |
|
||||||
|
|
||||||
#define OMAP_MMC_CMD 0xFFFB7800 /* MMC Command */ |
|
||||||
#define OMAP_MMC_ARGL 0xFFFB7804 /* MMC argument low */ |
|
||||||
#define OMAP_MMC_ARGH 0xFFFB7808 /* MMC argument high */ |
|
||||||
#define OMAP_MMC_CON 0xFFFB780C /* MMC system configuration */ |
|
||||||
#define OMAP_MMC_STAT 0xFFFB7810 /* MMC status */ |
|
||||||
#define OMAP_MMC_IE 0xFFFB7814 /* MMC system interrupt enable */ |
|
||||||
#define OMAP_MMC_CTO 0xFFFB7818 /* MMC command time-out */ |
|
||||||
#define OMAP_MMC_DTO 0xFFFB781C /* MMC data time-out */ |
|
||||||
#define OMAP_MMC_DATA 0xFFFB7820 /* MMC TX/RX FIFO data */ |
|
||||||
#define OMAP_MMC_BLEN 0xFFFB7824 /* MMC block length */ |
|
||||||
#define OMAP_MMC_NBLK 0xFFFB7828 /* MMC number of blocks */ |
|
||||||
#define OMAP_MMC_BUF 0xFFFB782C /* MMC buffer configuration */ |
|
||||||
#define OMAP_MMC_SPI 0xFFFB7830 /* MMC serial port interface */ |
|
||||||
#define OMAP_MMC_SDIO 0xFFFB7834 /* MMC SDIO mode configuration */ |
|
||||||
#define OMAP_MMC_SYST 0xFFFB7838 /* MMC system test */ |
|
||||||
#define OMAP_MMC_REV 0xFFFB783C /* MMC module version */ |
|
||||||
#define OMAP_MMC_RSP0 0xFFFB7840 /* MMC command response 0 */ |
|
||||||
#define OMAP_MMC_RSP1 0xFFFB7844 /* MMC command response 1 */ |
|
||||||
#define OMAP_MMC_RSP2 0xFFFB7848 /* MMC command response 2 */ |
|
||||||
#define OMAP_MMC_RSP3 0xFFFB784C /* MMC command response 3 */ |
|
||||||
#define OMAP_MMC_RSP4 0xFFFB7850 /* MMC command response 4 */ |
|
||||||
#define OMAP_MMC_RSP5 0xFFFB7854 /* MMC command response 5 */ |
|
||||||
#define OMAP_MMC_RSP6 0xFFFB7858 /* MMC command response 6 */ |
|
||||||
#define OMAP_MMC_RSP7 0xFFFB785C /* MMC command response 4 */ |
|
||||||
|
|
||||||
/* MMC masks */ |
|
||||||
|
|
||||||
#define OMAP_MMC_END_OF_CMD (1 << 0) /* End of command phase */ |
|
||||||
#define OMAP_MMC_CARD_BUSY (1 << 2) /* Card enter busy state */ |
|
||||||
#define OMAP_MMC_BLOCK_RS (1 << 3) /* Block received/sent */ |
|
||||||
#define OMAP_MMC_EOF_BUSY (1 << 4) /* Card exit busy state */ |
|
||||||
#define OMAP_MMC_DATA_TIMEOUT (1 << 5) /* Data response time-out */ |
|
||||||
#define OMAP_MMC_DATA_CRC (1 << 6) /* Date CRC error */ |
|
||||||
#define OMAP_MMC_CMD_TIMEOUT (1 << 7) /* Command response time-out */ |
|
||||||
#define OMAP_MMC_CMD_CRC (1 << 8) /* Command CRC error */ |
|
||||||
#define OMAP_MMC_A_FULL (1 << 10) /* Buffer almost full */ |
|
||||||
#define OMAP_MMC_A_EMPTY (1 << 11) /* Buffer almost empty */ |
|
||||||
#define OMAP_MMC_OCR_BUSY (1 << 12) /* OCR busy */ |
|
||||||
#define OMAP_MMC_CARD_IRQ (1 << 13) /* Card IRQ received */ |
|
||||||
#define OMAP_MMC_CARD_ERR (1 << 14) /* Card status error in response */ |
|
||||||
|
|
||||||
/* 2.9.2 MPUI Interface Registers FFFE:C900 */ |
|
||||||
|
|
||||||
#define MPUI_CTRL_REG (volatile __u32 *)(0xfffec900) |
|
||||||
#define MPUI_DEBUG_ADDR (volatile __u32 *)(0xfffec904) |
|
||||||
#define MPUI_DEBUG_DATA (volatile __u32 *)(0xfffec908) |
|
||||||
#define MPUI_DEBUG_FLAG (volatile __u16 *)(0xfffec90c) |
|
||||||
#define MPUI_STATUS_REG (volatile __u16 *)(0xfffec910) |
|
||||||
#define MPUI_DSP_STATUS_REG (volatile __u16 *)(0xfffec914) |
|
||||||
#define MPUI_DSP_BOOT_CONFIG (volatile __u16 *)(0xfffec918) |
|
||||||
#define MPUI_DSP_API_CONFIG (volatile __u16 *)(0xfffec91c) |
|
||||||
|
|
||||||
/* 2.9.6 Traffic Controller Memory Interface Registers: */ |
|
||||||
#define OMAP_IMIF_PRIO_REG 0xfffecc00 |
|
||||||
#define OMAP_EMIFS_PRIO_REG 0xfffecc04 |
|
||||||
#define OMAP_EMIFF_PRIO_REG 0xfffecc08 |
|
||||||
#define OMAP_EMIFS_CONFIG_REG 0xfffecc0c |
|
||||||
#define OMAP_EMIFS_CS0_CONFIG 0xfffecc10 |
|
||||||
#define OMAP_EMIFS_CS1_CONFIG 0xfffecc14 |
|
||||||
#define OMAP_EMIFS_CS2_CONFIG 0xfffecc18 |
|
||||||
#define OMAP_EMIFS_CS3_CONFIG 0xfffecc1c |
|
||||||
#define OMAP_EMIFF_SDRAM_CONFIG 0xfffecc20 |
|
||||||
#define OMAP_EMIFF_MRS 0xfffecc24 |
|
||||||
#define OMAP_TIMEOUT1 0xfffecc28 |
|
||||||
#define OMAP_TIMEOUT2 0xfffecc2c |
|
||||||
#define OMAP_TIMEOUT3 0xfffecc30 |
|
||||||
#define OMAP_ENDIANISM 0xfffecc34 |
|
||||||
|
|
||||||
/* 2.9.10 EMIF Slow Interface Configuration Register (EMIFS_CONFIG_REG): */ |
|
||||||
#define OMAP_EMIFS_CONFIG_FR (1 << 4) |
|
||||||
#define OMAP_EMIFS_CONFIG_PDE (1 << 3) |
|
||||||
#define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2) |
|
||||||
#define OMAP_EMIFS_CONFIG_BM (1 << 1) |
|
||||||
#define OMAP_EMIFS_CONFIG_WP (1 << 0) |
|
||||||
|
|
||||||
/*
|
|
||||||
* Memory chunk set aside for the Framebuffer in SRAM |
|
||||||
*/ |
|
||||||
#define SRAM_FRAMEBUFFER_MEMORY OMAP1510_SRAM_BASE |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* DMA |
|
||||||
*/ |
|
||||||
|
|
||||||
#define OMAP1510_DMA_BASE 0xFFFED800 |
|
||||||
#define OMAP_DMA_BASE OMAP1510_DMA_BASE |
|
||||||
|
|
||||||
/* Global Register selection */ |
|
||||||
#define NO_GLOBAL_DMA_ACCESS 0 |
|
||||||
|
|
||||||
/* Channel select field
|
|
||||||
* NOTE: all other channels are linear, chan0 is 0, chan1 is 1, etc... |
|
||||||
*/ |
|
||||||
#define LCD_CHANNEL 0xc |
|
||||||
|
|
||||||
/* Register Select Field (LCD) */ |
|
||||||
#define DMA_LCD_CTRL 0 |
|
||||||
#define DMA_LCD_TOP_F1_L 1 |
|
||||||
#define DMA_LCD_TOP_F1_U 2 |
|
||||||
#define DMA_LCD_BOT_F1_L 3 |
|
||||||
#define DMA_LCD_BOT_F1_U 4 |
|
||||||
|
|
||||||
#define LCD_FRAME_MODE (1<<0) |
|
||||||
#define LCD_FRAME_IT_IE (1<<1) |
|
||||||
#define LCD_BUS_ERROR_IT_IE (1<<2) |
|
||||||
#define LCD_FRAME_1_IT_COND (1<<3) |
|
||||||
#define LCD_FRAME_2_IT_COND (1<<4) |
|
||||||
#define LCD_BUS_ERROR_IT_COND (1<<5) |
|
||||||
#define LCD_SOURCE_IMIF (1<<6) |
|
||||||
|
|
||||||
/*
|
|
||||||
* Real-Time Clock |
|
||||||
*/ |
|
||||||
|
|
||||||
#define RTC_SECONDS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x00) |
|
||||||
#define RTC_MINUTES (volatile __u8 *)(OMAP1510_RTC_BASE + 0x04) |
|
||||||
#define RTC_HOURS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x08) |
|
||||||
#define RTC_DAYS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x0C) |
|
||||||
#define RTC_MONTHS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x10) |
|
||||||
#define RTC_YEARS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x14) |
|
||||||
#define RTC_CTRL (volatile __u8 *)(OMAP1510_RTC_BASE + 0x40) |
|
||||||
|
|
||||||
|
|
||||||
/* ---------------------------------------------------------------------------
|
|
||||||
* OMAP1510 Interrupt Handlers |
|
||||||
* --------------------------------------------------------------------------- |
|
||||||
* |
|
||||||
*/ |
|
||||||
#define OMAP_IH1_BASE 0xfffecb00 |
|
||||||
#define OMAP_IH2_BASE 0xfffe0000 |
|
||||||
#define OMAP1510_ITR 0x0 |
|
||||||
#define OMAP1510_MASK 0x4 |
|
||||||
|
|
||||||
#define INTERRUPT_HANDLER_BASE OMAP_IH1_BASE |
|
||||||
#define INTERRUPT_INPUT_REGISTER OMAP1510_ITR |
|
||||||
#define INTERRUPT_MASK_REGISTER OMAP1510_MASK |
|
||||||
|
|
||||||
|
|
||||||
/* ---------------------------------------------------------------------------
|
|
||||||
* OMAP1510 TIMERS |
|
||||||
* --------------------------------------------------------------------------- |
|
||||||
* |
|
||||||
*/ |
|
||||||
|
|
||||||
#define OMAP1510_32kHz_TIMER_BASE 0xfffb9000 |
|
||||||
|
|
||||||
/* 32k Timer Registers */ |
|
||||||
#define TIMER32k_CR 0x08 |
|
||||||
#define TIMER32k_TVR 0x00 |
|
||||||
#define TIMER32k_TCR 0x04 |
|
||||||
|
|
||||||
/* 32k Timer Control Register definition */ |
|
||||||
#define TIMER32k_TSS (1<<0) |
|
||||||
#define TIMER32k_TRB (1<<1) |
|
||||||
#define TIMER32k_INT (1<<2) |
|
||||||
#define TIMER32k_ARL (1<<3) |
|
||||||
|
|
||||||
/* MPU Timer base addresses */ |
|
||||||
#define OMAP1510_MPUTIMER_BASE 0xfffec500 |
|
||||||
#define OMAP1510_MPUTIMER_OFF 0x00000100 |
|
||||||
|
|
||||||
#define OMAP1510_TIMER1_BASE 0xfffec500 |
|
||||||
#define OMAP1510_TIMER2_BASE 0xfffec600 |
|
||||||
#define OMAP1510_TIMER3_BASE 0xfffec700 |
|
||||||
|
|
||||||
/* MPU Timer Registers */ |
|
||||||
#define CNTL_TIMER 0 |
|
||||||
#define LOAD_TIM 4 |
|
||||||
#define READ_TIM 8 |
|
||||||
|
|
||||||
/* CNTL_TIMER register bits */ |
|
||||||
#define MPUTIM_FREE (1<<6) |
|
||||||
#define MPUTIM_CLOCK_ENABLE (1<<5) |
|
||||||
#define MPUTIM_PTV_MASK (0x7<<MPUTIM_PTV_BIT) |
|
||||||
#define MPUTIM_PTV_BIT 2 |
|
||||||
#define MPUTIM_AR (1<<1) |
|
||||||
#define MPUTIM_ST (1<<0) |
|
||||||
|
|
||||||
/* ---------------------------------------------------------------------------
|
|
||||||
* OMAP1510 GPIO (SHARED) |
|
||||||
* --------------------------------------------------------------------------- |
|
||||||
* |
|
||||||
*/ |
|
||||||
#define GPIO_DATA_INPUT_REG (OMAP1510_GPIO_BASE + 0x0) |
|
||||||
#define GPIO_DATA_OUTPUT_REG (OMAP1510_GPIO_BASE + 0x4) |
|
||||||
#define GPIO_DIR_CONTROL_REG (OMAP1510_GPIO_BASE + 0x8) |
|
||||||
#define GPIO_INT_CONTROL_REG (OMAP1510_GPIO_BASE + 0xc) |
|
||||||
#define GPIO_INT_MASK_REG (OMAP1510_GPIO_BASE + 0x10) |
|
||||||
#define GPIO_INT_STATUS_REG (OMAP1510_GPIO_BASE + 0x14) |
|
||||||
#define GPIO_PIN_CONTROL_REG (OMAP1510_GPIO_BASE + 0x18) |
|
||||||
|
|
||||||
|
|
||||||
/* ---------------------------
|
|
||||||
* OMAP1510 MPUIO (ARM only) |
|
||||||
*---------------------------- |
|
||||||
*/ |
|
||||||
#define OMAP1510_MPUIO_BASE 0xFFFB5000 |
|
||||||
#define MPUIO_DATA_INPUT_REG (OMAP1510_MPUIO_BASE + 0x0) |
|
||||||
#define MPUIO_DATA_OUTPUT_REG (OMAP1510_MPUIO_BASE + 0x4) |
|
||||||
#define MPUIO_DIR_CONTROL_REG (OMAP1510_MPUIO_BASE + 0x8) |
|
||||||
|
|
||||||
/* ---------------------------------------------------------------------------
|
|
||||||
* OMAP1510 TIPB (only) |
|
||||||
* --------------------------------------------------------------------------- |
|
||||||
* |
|
||||||
*/ |
|
||||||
#define TIPB_PUBLIC_CNTL_BASE 0xfffed300 |
|
||||||
#define MPU_PUBLIC_TIPB_CNTL_REG (TIPB_PUBLIC_CNTL_BASE + 0x8) |
|
||||||
#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00 |
|
||||||
#define MPU_PRIVATE_TIPB_CNTL_REG (TIPB_PRIVATE_CNTL_BASE + 0x8) |
|
||||||
|
|
||||||
/*
|
|
||||||
* --------------------------------------------------------------------------- |
|
||||||
* OMAP1510 Camera Interface |
|
||||||
* --------------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
#define CAMERA_BASE (IO_BASE + 0x6800) |
|
||||||
#define CAM_CTRLCLOCK_REG (CAMERA_BASE + 0x00) |
|
||||||
#define CAM_IT_STATUS_REG (CAMERA_BASE + 0x04) |
|
||||||
#define CAM_MODE_REG (CAMERA_BASE + 0x08) |
|
||||||
#define CAM_STATUS_REG (CAMERA_BASE + 0x0C) |
|
||||||
#define CAM_CAMDATA_REG (CAMERA_BASE + 0x10) |
|
||||||
#define CAM_GPIO_REG (CAMERA_BASE + 0x14) |
|
||||||
#define CAM_PEAK_CTR_REG (CAMERA_BASE + 0x18) |
|
||||||
|
|
||||||
#if 0 |
|
||||||
#ifndef __ASSEMBLY__ |
|
||||||
typedef struct { |
|
||||||
__u32 ctrlclock; |
|
||||||
__u32 it_status; |
|
||||||
__u32 mode; |
|
||||||
__u32 status; |
|
||||||
__u32 camdata; |
|
||||||
__u32 gpio; |
|
||||||
__u32 peak_counter; |
|
||||||
} camera_regs_t; |
|
||||||
#endif |
|
||||||
#endif |
|
||||||
|
|
||||||
/* CTRLCLOCK bit shifts */ |
|
||||||
#define FOSCMOD_BIT 0 |
|
||||||
#define FOSCMOD_MASK (0x7 << FOSCMOD_BIT) |
|
||||||
#define FOSCMOD_12MHz 0x0 |
|
||||||
#define FOSCMOD_6MHz 0x2 |
|
||||||
#define FOSCMOD_9_6MHz 0x4 |
|
||||||
#define FOSCMOD_24MHz 0x5 |
|
||||||
#define FOSCMOD_8MHz 0x6 |
|
||||||
#define POLCLK (1<<3) |
|
||||||
#define CAMEXCLK_EN (1<<4) |
|
||||||
#define MCLK_EN (1<<5) |
|
||||||
#define DPLL_EN (1<<6) |
|
||||||
#define LCLK_EN (1<<7) |
|
||||||
|
|
||||||
/* IT_STATUS bit shifts */ |
|
||||||
#define V_UP (1<<0) |
|
||||||
#define V_DOWN (1<<1) |
|
||||||
#define H_UP (1<<2) |
|
||||||
#define H_DOWN (1<<3) |
|
||||||
#define FIFO_FULL (1<<4) |
|
||||||
#define DATA_XFER (1<<5) |
|
||||||
|
|
||||||
/* MODE bit shifts */ |
|
||||||
#define CAMOSC (1<<0) |
|
||||||
#define IMGSIZE_BIT 1 |
|
||||||
#define IMGSIZE_MASK (0x3 << IMGSIZE_BIT) |
|
||||||
#define IMGSIZE_CIF (0x0 << IMGSIZE_BIT) /* 352x288 */ |
|
||||||
#define IMGSIZE_QCIF (0x1 << IMGSIZE_BIT) /* 176x144 */ |
|
||||||
#define IMGSIZE_VGA (0x2 << IMGSIZE_BIT) /* 640x480 */ |
|
||||||
#define IMGSIZE_QVGA (0x3 << IMGSIZE_BIT) /* 320x240 */ |
|
||||||
#define ORDERCAMD (1<<3) |
|
||||||
#define EN_V_UP (1<<4) |
|
||||||
#define EN_V_DOWN (1<<5) |
|
||||||
#define EN_H_UP (1<<6) |
|
||||||
#define EN_H_DOWN (1<<7) |
|
||||||
#define EN_DMA (1<<8) |
|
||||||
#define THRESHOLD (1<<9) |
|
||||||
#define THRESHOLD_BIT 9 |
|
||||||
#define THRESHOLD_MASK (0x7f<<9) |
|
||||||
#define EN_NIRQ (1<<16) |
|
||||||
#define EN_FIFO_FULL (1<<17) |
|
||||||
#define RAZ_FIFO (1<<18) |
|
||||||
|
|
||||||
/* STATUS bit shifts */ |
|
||||||
#define VSTATUS (1<<0) |
|
||||||
#define HSTATUS (1<<1) |
|
||||||
|
|
||||||
/* GPIO bit shifts */ |
|
||||||
#define CAM_RST (1<<0) |
|
||||||
|
|
||||||
|
|
||||||
/*********************
|
|
||||||
* Watchdog timer. |
|
||||||
*********************/ |
|
||||||
#define WDTIM_BASE 0xfffec800 |
|
||||||
#define WDTIM_CONTROL (WDTIM_BASE+0x00) |
|
||||||
#define WDTIM_LOAD (WDTIM_BASE+0x04) |
|
||||||
#define WDTIM_READ (WDTIM_BASE+0x04) |
|
||||||
#define WDTIM_MODE (WDTIM_BASE+0x08) |
|
||||||
|
|
||||||
/* Values to write to mode register to disable the watchdog function. */ |
|
||||||
#define DISABLE_SEQ1 0xF5 |
|
||||||
#define DISABLE_SEQ2 0xA0 |
|
||||||
|
|
||||||
/* WDTIM_CONTROL bit definitions. */ |
|
||||||
#define WDTIM_CONTROL_ST BIT7 |
|
||||||
|
|
||||||
|
|
||||||
/* ---------------------------------------------------------------------------
|
|
||||||
* Differentiating processor versions for those who care. |
|
||||||
* --------------------------------------------------------------------------- |
|
||||||
* |
|
||||||
*/ |
|
||||||
#define OMAP1509 0 |
|
||||||
#define OMAP1510 1 |
|
||||||
|
|
||||||
#define OMAP1510_ID_CODE_REG 0xfffed404 |
|
||||||
|
|
||||||
#ifndef __ASSEMBLY__ |
|
||||||
int cpu_type(void); |
|
||||||
#endif |
|
||||||
|
|
||||||
/*****************************************************************************/ |
|
||||||
|
|
||||||
#define CLKGEN_RESET_BASE (0xfffece00) |
|
||||||
#define ARM_CKCTL (volatile __u16 *)(CLKGEN_RESET_BASE + 0x0) |
|
||||||
#define ARM_IDLECT1 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x4) |
|
||||||
#define ARM_IDLECT2 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x8) |
|
||||||
#define ARM_EWUPCT (volatile __u16 *)(CLKGEN_RESET_BASE + 0xC) |
|
||||||
#define ARM_RSTCT1 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x10) |
|
||||||
#define ARM_RSTCT2 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x14) |
|
||||||
#define ARM_SYSST (volatile __u16 *)(CLKGEN_RESET_BASE + 0x18) |
|
||||||
|
|
||||||
|
|
||||||
#define CK_CLKIN 12 /* MHz */ |
|
||||||
#define CK_RATEF 1 |
|
||||||
#define CK_IDLEF 2 |
|
||||||
#define CK_ENABLEF 4 |
|
||||||
#define CK_SELECTF 8 |
|
||||||
#ifndef __ASSEMBLER__ |
|
||||||
#define CK_DPLL1 ((volatile __u16 *)0xfffecf00) |
|
||||||
#else |
|
||||||
#define CK_DPLL1 (0xfffecf00) |
|
||||||
#endif |
|
||||||
#define SETARM_IDLE_SHIFT |
|
||||||
|
|
||||||
/* ARM_CKCTL bit shifts */ |
|
||||||
#define PERDIV 0 |
|
||||||
#define LCDDIV 2 |
|
||||||
#define ARMDIV 4 |
|
||||||
#define DSPDIV 6 |
|
||||||
#define TCDIV 8 |
|
||||||
#define DSPMMUDIV 10 |
|
||||||
#define ARM_TIMXO 12 |
|
||||||
#define EN_DSPCK 13 |
|
||||||
#define ARM_INTHCK_SEL 14 /* REVISIT -- where is this used? */ |
|
||||||
|
|
||||||
#define ARM_CKCTL_RSRVD_BIT15 (1 << 15) |
|
||||||
#define ARM_CKCTL_ARM_INTHCK_SEL (1 << 14) |
|
||||||
#define ARM_CKCTL_EN_DSPCK (1 << 13) |
|
||||||
#define ARM_CKCTL_ARM_TIMXO (1 << 12) |
|
||||||
#define ARM_CKCTL_DSPMMU_DIV1 (1 << 11) |
|
||||||
#define ARM_CKCTL_DSPMMU_DIV2 (1 << 10) |
|
||||||
#define ARM_CKCTL_TCDIV1 (1 << 9) |
|
||||||
#define ARM_CKCTL_TCDIV2 (1 << 8) |
|
||||||
#define ARM_CKCTL_DSPDIV1 (1 << 7) |
|
||||||
#define ARM_CKCTL_DSPDIV0 (1 << 6) |
|
||||||
#define ARM_CKCTL_ARMDIV1 (1 << 5) |
|
||||||
#define ARM_CKCTL_ARMDIV0 (1 << 4) |
|
||||||
#define ARM_CKCTL_LCDDIV1 (1 << 3) |
|
||||||
#define ARM_CKCTL_LCDDIV0 (1 << 2) |
|
||||||
#define ARM_CKCTL_PERDIV1 (1 << 1) |
|
||||||
#define ARM_CKCTL_PERDIV0 (1 << 0) |
|
||||||
|
|
||||||
/* ARM_IDLECT1 bit shifts */ |
|
||||||
#define IDLWDT_ARM 0 |
|
||||||
#define IDLXORP_ARM 1 |
|
||||||
#define IDLPER_ARM 2 |
|
||||||
#define IDLLCD_ARM 3 |
|
||||||
#define IDLLB_ARM 4 |
|
||||||
#define IDLHSAB_ARM 5 |
|
||||||
#define IDLIF_ARM 6 |
|
||||||
#define IDLDPLL_ARM 7 |
|
||||||
#define IDLAPI_ARM 8 |
|
||||||
#define IDLTIM_ARM 9 |
|
||||||
#define SETARM_IDLE 11 |
|
||||||
|
|
||||||
/* ARM_IDLECT2 bit shifts */ |
|
||||||
#define EN_WDTCK 0 |
|
||||||
#define EN_XORPCK 1 |
|
||||||
#define EN_PERCK 2 |
|
||||||
#define EN_LCDCK 3 |
|
||||||
#define EN_LBCK 4 |
|
||||||
#define EN_HSABCK 5 |
|
||||||
#define EN_APICK 6 |
|
||||||
#define EN_TIMCK 7 |
|
||||||
#define DMACK_REQ 8 |
|
||||||
#define EN_GPIOCK 9 |
|
||||||
#define EN_LBFREECK 10 |
|
||||||
|
|
||||||
#define ARM_RSTCT1_SW_RST (1 << 3) |
|
||||||
#define ARM_RSTCT1_DSP_RST (1 << 2) |
|
||||||
#define ARM_RSTCT1_DSP_EN (1 << 1) |
|
||||||
#define ARM_RSTCT1_ARM_RST (1 << 0) |
|
||||||
|
|
||||||
/* ARM_RSTCT2 bit shifts */ |
|
||||||
#define EN_PER 0 |
|
||||||
|
|
||||||
#define ARM_SYSST_RSRVD_BIT15 (1 << 15) |
|
||||||
#define ARM_SYSST_RSRVD_BIT14 (1 << 14) |
|
||||||
#define ARM_SYSST_CLOCK_SELECT2 (1 << 13) |
|
||||||
#define ARM_SYSST_CLOCK_SELECT1 (1 << 12) |
|
||||||
#define ARM_SYSST_CLOCK_SELECT0 (1 << 11) |
|
||||||
#define ARM_SYSST_RSRVD_BIT10 (1 << 10) |
|
||||||
#define ARM_SYSST_RSRVD_BIT9 (1 << 9) |
|
||||||
#define ARM_SYSST_RSRVD_BIT8 (1 << 8) |
|
||||||
#define ARM_SYSST_RSRVD_BIT7 (1 << 7) |
|
||||||
#define ARM_SYSST_IDLE_DSP (1 << 6) |
|
||||||
#define ARM_SYSST_POR (1 << 5) |
|
||||||
#define ARM_SYSST_EXT_RST (1 << 4) |
|
||||||
#define ARM_SYSST_ARM_MCRST (1 << 3) |
|
||||||
#define ARM_SYSST_ARM_WDRST (1 << 2) |
|
||||||
#define ARM_SYSST_GLOB_SWRST (1 << 1) |
|
||||||
#define ARM_SYSST_DSP_WDRST (1 << 0) |
|
||||||
|
|
||||||
/* Table 15-23. DPLL Control Registers: */ |
|
||||||
#define DPLL_CTL_REG (volatile __u16 *)(0xfffecf00) |
|
||||||
|
|
||||||
/* Table 15-24. Control Register (CTL_REG): */ |
|
||||||
|
|
||||||
#define DPLL_CTL_REG_IOB (1 << 13) |
|
||||||
#define DPLL_CTL_REG_PLL_MULT Fld(5,0) |
|
||||||
|
|
||||||
/*****************************************************************************/ |
|
||||||
|
|
||||||
/* OMAP INTERRUPT REGISTERS */ |
|
||||||
#define IRQ_ITR 0x00 |
|
||||||
#define IRQ_MIR 0x04 |
|
||||||
#define IRQ_SIR_IRQ 0x10 |
|
||||||
#define IRQ_SIR_FIQ 0x14 |
|
||||||
#define IRQ_CONTROL_REG 0x18 |
|
||||||
#define IRQ_ISR 0x9c |
|
||||||
#define IRQ_ILR0 0x1c |
|
||||||
|
|
||||||
#define REG_IHL1_MIR (OMAP_IH1_BASE+IRQ_MIR) |
|
||||||
#define REG_IHL2_MIR (OMAP_IH2_BASE+IRQ_MIR) |
|
||||||
|
|
||||||
/* INTERRUPT LEVEL REGISTER BITS */ |
|
||||||
#define ILR_PRIORITY_MASK (0x3c) |
|
||||||
#define ILR_PRIORITY_SHIFT (2) |
|
||||||
#define ILR_LEVEL_TRIGGER (1<<1) |
|
||||||
#define ILR_FIQ (1<<0) |
|
||||||
|
|
||||||
#define IRQ_LEVEL_INT 1 |
|
||||||
#define IRQ_EDGE_INT 0 |
|
||||||
|
|
||||||
/* Macros to access registers */ |
|
||||||
#define outb(v,p) *(volatile u8 *) (p) = v |
|
||||||
#define outw(v,p) *(volatile u16 *) (p) = v |
|
||||||
#define outl(v,p) *(volatile u32 *) (p) = v |
|
||||||
|
|
||||||
#define inb(p) *(volatile u8 *) (p) |
|
||||||
#define inw(p) *(volatile u16 *) (p) |
|
||||||
#define inl(p) *(volatile u32 *) (p) |
|
||||||
@ -1,174 +0,0 @@ |
|||||||
/*
|
|
||||||
* (C) Copyright 2003 |
|
||||||
* Texas Instruments. |
|
||||||
* Kshitij Gupta <kshitij@ti.com> |
|
||||||
* Configuation settings for the TI OMAP Innovator board. |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: GPL-2.0+ |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifndef __CONFIG_H |
|
||||||
#define __CONFIG_H |
|
||||||
|
|
||||||
/*
|
|
||||||
* High Level Configuration Options |
|
||||||
* (easy to change) |
|
||||||
*/ |
|
||||||
#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ |
|
||||||
#define CONFIG_OMAP 1 /* in a TI OMAP core */ |
|
||||||
#define CONFIG_OMAP1610 1 /* 5912 is same as 1610 */ |
|
||||||
#define CONFIG_OSK_OMAP5912 1 /* a OSK Board */ |
|
||||||
|
|
||||||
#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */ |
|
||||||
#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */ |
|
||||||
|
|
||||||
/* input clock of PLL */ |
|
||||||
/* the OMAP5912 OSK has 12MHz input clock */ |
|
||||||
#define CONFIG_SYS_CLK_FREQ 12000000 |
|
||||||
|
|
||||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
|
||||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
|
||||||
#define CONFIG_INITRD_TAG 1 /* Required for ramdisk support */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* Size of malloc() pool |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
|
||||||
|
|
||||||
/*
|
|
||||||
* Hardware drivers |
|
||||||
*/ |
|
||||||
/*
|
|
||||||
*/ |
|
||||||
#define CONFIG_LAN91C96 |
|
||||||
#define CONFIG_LAN91C96_BASE 0x04800300 |
|
||||||
#define CONFIG_LAN91C96_EXT_PHY |
|
||||||
|
|
||||||
/*
|
|
||||||
* NS16550 Configuration |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_NS16550 |
|
||||||
#define CONFIG_SYS_NS16550_SERIAL |
|
||||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4) |
|
||||||
#define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ |
|
||||||
#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart |
|
||||||
on helen */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* select serial console configuration |
|
||||||
*/ |
|
||||||
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP5912 OSK */ |
|
||||||
|
|
||||||
/* allow to overwrite serial and ethaddr */ |
|
||||||
#define CONFIG_ENV_OVERWRITE |
|
||||||
#define CONFIG_CONS_INDEX 1 |
|
||||||
#define CONFIG_BAUDRATE 115200 |
|
||||||
|
|
||||||
/*
|
|
||||||
* Command line configuration. |
|
||||||
*/ |
|
||||||
#include <config_cmd_default.h> |
|
||||||
|
|
||||||
#define CONFIG_CMD_DHCP |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BOOTP options |
|
||||||
*/ |
|
||||||
#define CONFIG_BOOTP_SUBNETMASK |
|
||||||
#define CONFIG_BOOTP_GATEWAY |
|
||||||
#define CONFIG_BOOTP_HOSTNAME |
|
||||||
#define CONFIG_BOOTP_BOOTPATH |
|
||||||
|
|
||||||
|
|
||||||
#include <configs/omap1510.h> |
|
||||||
|
|
||||||
#define CONFIG_BOOTDELAY 3 |
|
||||||
#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd \ |
|
||||||
root=/dev/nfs rw nfsroot=157.87.82.48:\
|
|
||||||
/home/mwd/myfs/target ip=dhcp" |
|
||||||
#define CONFIG_NETMASK 255.255.254.0 /* talk on MY local net */ |
|
||||||
#define CONFIG_IPADDR 156.117.97.156 /* static IP I currently own */ |
|
||||||
#define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */ |
|
||||||
#define CONFIG_BOOTFILE "uImage" /* file to load */ |
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_KGDB) |
|
||||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
|
||||||
#endif |
|
||||||
|
|
||||||
/*
|
|
||||||
* Miscellaneous configurable options |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
|
||||||
#define CONFIG_SYS_PROMPT "OMAP5912 OSK # " /* Monitor Command Prompt */ |
|
||||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
|
||||||
/* Print Buffer Size */ |
|
||||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
|
||||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
|
||||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ |
|
||||||
#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */ |
|
||||||
|
|
||||||
/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
|
|
||||||
* DPLL1. This time is further subdivided by a local divisor. |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */ |
|
||||||
#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Physical Memory Map |
|
||||||
*/ |
|
||||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
|
||||||
#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ |
|
||||||
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ |
|
||||||
|
|
||||||
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
|
||||||
#define PHYS_FLASH_2 0x01000000 /* Flash Bank #2 */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ |
|
||||||
|
|
||||||
#define PHYS_SRAM 0x20000000 |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* FLASH driver setup |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ |
|
||||||
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } |
|
||||||
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
|
||||||
#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */ |
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ |
|
||||||
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
|
||||||
|
|
||||||
/* timeout values are in ticks */ |
|
||||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
|
||||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* FLASH and environment organization |
|
||||||
*/ |
|
||||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
|
||||||
/* addr of environment */ |
|
||||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) |
|
||||||
|
|
||||||
#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ |
|
||||||
#define CONFIG_ENV_OFFSET 0x40000 /* environment starts here */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
|
||||||
#define CONFIG_SYS_INIT_RAM_ADDR PHYS_SRAM |
|
||||||
#define CONFIG_SYS_INIT_RAM_SIZE (250 * 1024) |
|
||||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
|
||||||
CONFIG_SYS_INIT_RAM_SIZE) |
|
||||||
|
|
||||||
#endif /* __CONFIG_H */ |
|
||||||
Loading…
Reference in new issue