All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>master
Ed Swarthout
17 years ago
committed by
Wolfgang Denk
parent
63e22764d2
commit
63cec5814f
@ -1,146 +0,0 @@ |
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/*
|
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* Copyright (C) Freescale Semiconductor,Inc. |
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* 2005, 2006. All rights reserved. |
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* |
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* Ed Swarthout (ed.swarthout@freescale.com) |
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* Jason Jin (Jason.jin@freescale.com) |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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/*
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* PCIE Configuration space access support for PCIE Bridge |
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*/ |
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#include <common.h> |
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#include <pci.h> |
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|
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#if defined(CONFIG_PCI) |
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void |
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pci_mpc86xx_init(struct pci_controller *hose) |
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{ |
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volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; |
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volatile ccsr_pex_t *pcie1 = &immap->im_pex1; |
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u16 temp16; |
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u32 temp32; |
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volatile ccsr_gur_t *gur = &immap->im_gur; |
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uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; |
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uint pcie1_host = (host1_agent == 2) || (host1_agent == 3); |
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uint pcie1_agent = (host1_agent == 0) || (host1_agent == 1); |
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uint devdisr = gur->devdisr; |
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uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; |
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|
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if ((io_sel == 2 || io_sel == 3 || io_sel == 5 || io_sel == 6 || |
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io_sel == 7 || io_sel == 0xf) |
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&& !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { |
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printf("PCI-EXPRESS 1: Configured as %s \n", |
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pcie1_agent ? "Agent" : "Host"); |
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if (pcie1_agent) |
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return; /*Don't scan bus when configured as agent */ |
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printf(" Scanning PCIE bus"); |
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debug("0x%08x=0x%08x ", |
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&pcie1->pme_msg_det, |
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pcie1->pme_msg_det); |
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if (pcie1->pme_msg_det) { |
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pcie1->pme_msg_det = 0xffffffff; |
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debug(" with errors. Clearing. Now 0x%08x", |
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pcie1->pme_msg_det); |
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} |
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debug("\n"); |
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} else { |
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printf("PCI-EXPRESS 1 disabled!\n"); |
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return; |
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} |
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|
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/*
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* Set first_bus=0 only skipped B0:D0:F0 which is |
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* a reserved device in M1575, but make it easy for |
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* most of the scan process. |
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*/ |
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hose->first_busno = 0x00; |
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hose->last_busno = 0xfe; |
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pcie_setup_indirect(hose, (CFG_IMMR + 0x8000), (CFG_IMMR + 0x8004)); |
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pci_hose_read_config_word(hose, |
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PCI_BDF(0, 0, 0), PCI_COMMAND, &temp16); |
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temp16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | |
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PCI_COMMAND_MEMORY | PCI_COMMAND_IO; |
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pci_hose_write_config_word(hose, |
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PCI_BDF(0, 0, 0), PCI_COMMAND, temp16); |
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pci_hose_write_config_word(hose, PCI_BDF(0, 0, 0), PCI_STATUS, 0xffff); |
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pci_hose_write_config_byte(hose, |
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PCI_BDF(0, 0, 0), PCI_LATENCY_TIMER, 0x80); |
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|
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pci_hose_read_config_dword(hose, PCI_BDF(0, 0, 0), PCI_PRIMARY_BUS, |
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&temp32); |
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temp32 = (temp32 & 0xff000000) | (0xff) | (0x0 << 8) | (0xfe << 16); |
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pci_hose_write_config_dword(hose, PCI_BDF(0, 0, 0), PCI_PRIMARY_BUS, |
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temp32); |
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pcie1->powar1 = 0; |
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pcie1->powar2 = 0; |
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pcie1->piwar1 = 0; |
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pcie1->piwar1 = 0; |
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pcie1->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; |
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pcie1->powar1 = 0x8004401c; /* 512M MEM space */ |
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pcie1->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; |
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pcie1->potear1 = 0x00000000; |
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pcie1->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; |
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pcie1->powar2 = 0x80088017; /* 16M IO space */ |
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pcie1->potar2 = 0x00000000; |
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pcie1->potear2 = 0x00000000; |
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pcie1->pitar1 = 0x00000000; |
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pcie1->piwbar1 = 0x00000000; |
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/* Enable, Prefetch, Local Mem, * Snoop R/W, 2G */ |
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pcie1->piwar1 = 0xa0f5501e; |
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|
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pci_set_region(hose->regions + 0, |
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CFG_PCI_MEMORY_BUS, |
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CFG_PCI_MEMORY_PHYS, |
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CFG_PCI_MEMORY_SIZE, |
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PCI_REGION_MEM | PCI_REGION_MEMORY); |
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|
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pci_set_region(hose->regions + 1, |
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CFG_PCI1_MEM_BASE, |
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CFG_PCI1_MEM_PHYS, |
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CFG_PCI1_MEM_SIZE, |
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PCI_REGION_MEM); |
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|
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pci_set_region(hose->regions + 2, |
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CFG_PCI1_IO_BASE, |
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CFG_PCI1_IO_PHYS, |
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CFG_PCI1_IO_SIZE, |
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PCI_REGION_IO); |
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hose->region_count = 3; |
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pci_register_hose(hose); |
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hose->last_busno = pci_hose_scan(hose); |
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debug("pcie_mpc86xx_init: last_busno %x\n", hose->last_busno); |
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debug("pcie_mpc86xx init: current_busno %x\n ", hose->current_busno); |
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printf("....PCIE1 scan & enumeration done\n"); |
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} |
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#endif /* CONFIG_PCI */ |
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@ -1,199 +0,0 @@ |
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/*
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* Support for indirect PCI bridges. |
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* |
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* Copyright (c) Freescale Semiconductor, Inc. |
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* 2006. All rights reserved. |
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* |
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* Jason Jin <Jason.jin@freescale.com> |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License |
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* as published by the Free Software Foundation; either version |
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* 2 of the License, or (at your option) any later version. |
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* |
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* partly derived from |
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* arch/powerpc/platforms/86xx/mpc86xx_pcie.c |
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*/ |
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#include <common.h> |
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#ifdef CONFIG_PCI |
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#include <asm/processor.h> |
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#include <asm/io.h> |
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#include <pci.h> |
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#define PCI_CFG_OUT out_be32 |
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#define PEX_FIX out_be32(hose->cfg_addr+0x4, 0x0400ffff) |
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static int |
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indirect_read_config_pcie(struct pci_controller *hose, |
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pci_dev_t dev, |
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int offset, |
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int len, |
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u32 *val) |
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{ |
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int bus = PCI_BUS(dev); |
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|
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volatile unsigned char *cfg_data; |
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u32 temp; |
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PEX_FIX; |
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if (bus == 0xff) { |
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PCI_CFG_OUT(hose->cfg_addr, |
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dev | (offset & 0xfc) | 0x80000001); |
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} else { |
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PCI_CFG_OUT(hose->cfg_addr, |
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dev | (offset & 0xfc) | 0x80000000); |
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} |
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/*
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* Note: the caller has already checked that offset is |
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* suitably aligned and that len is 1, 2 or 4. |
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*/ |
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/* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */ |
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cfg_data = hose->cfg_data; |
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PEX_FIX; |
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temp = in_le32((u32 *) cfg_data); |
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switch (len) { |
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case 1: |
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*val = (temp >> (((offset & 3)) * 8)) & 0xff; |
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break; |
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case 2: |
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*val = (temp >> (((offset & 3)) * 8)) & 0xffff; |
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break; |
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default: |
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*val = temp; |
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break; |
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} |
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return 0; |
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} |
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static int |
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indirect_write_config_pcie(struct pci_controller *hose, |
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pci_dev_t dev, |
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int offset, |
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int len, |
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u32 val) |
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{ |
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int bus = PCI_BUS(dev); |
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volatile unsigned char *cfg_data; |
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u32 temp; |
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|
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PEX_FIX; |
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if (bus == 0xff) { |
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PCI_CFG_OUT(hose->cfg_addr, |
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dev | (offset & 0xfc) | 0x80000001); |
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} else { |
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PCI_CFG_OUT(hose->cfg_addr, |
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dev | (offset & 0xfc) | 0x80000000); |
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} |
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|
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/*
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* Note: the caller has already checked that offset is |
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* suitably aligned and that len is 1, 2 or 4. |
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*/ |
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/* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */ |
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cfg_data = hose->cfg_data; |
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switch (len) { |
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case 1: |
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PEX_FIX; |
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temp = in_le32((u32 *) cfg_data); |
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temp = (temp & ~(0xff << ((offset & 3) * 8))) | |
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(val << ((offset & 3) * 8)); |
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PEX_FIX; |
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out_le32((u32 *) cfg_data, temp); |
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break; |
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case 2: |
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PEX_FIX; |
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temp = in_le32((u32 *) cfg_data); |
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temp = (temp & ~(0xffff << ((offset & 3) * 8))); |
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temp |= (val << ((offset & 3) * 8)); |
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PEX_FIX; |
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out_le32((u32 *) cfg_data, temp); |
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break; |
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default: |
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PEX_FIX; |
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out_le32((u32 *) cfg_data, val); |
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break; |
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} |
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PEX_FIX; |
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return 0; |
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} |
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|
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static int |
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indirect_read_config_byte_pcie(struct pci_controller *hose, |
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pci_dev_t dev, |
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int offset, |
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u8 *val) |
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{ |
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u32 val32; |
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indirect_read_config_pcie(hose, dev, offset, 1, &val32); |
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*val = (u8) val32; |
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return 0; |
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} |
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|
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static int |
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indirect_read_config_word_pcie(struct pci_controller *hose, |
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pci_dev_t dev, |
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int offset, |
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u16 *val) |
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{ |
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u32 val32; |
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indirect_read_config_pcie(hose, dev, offset, 2, &val32); |
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*val = (u16) val32; |
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return 0; |
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} |
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|
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static int |
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indirect_read_config_dword_pcie(struct pci_controller *hose, |
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pci_dev_t dev, |
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int offset, |
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u32 *val) |
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{ |
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return indirect_read_config_pcie(hose, dev, offset, 4, val); |
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} |
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|
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static int |
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indirect_write_config_byte_pcie(struct pci_controller *hose, |
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pci_dev_t dev, |
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int offset, |
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u8 val) |
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{ |
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return indirect_write_config_pcie(hose, dev, offset, 1, (u32) val); |
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} |
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|
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static int |
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indirect_write_config_word_pcie(struct pci_controller *hose, |
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pci_dev_t dev, |
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int offset, |
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unsigned short val) |
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{ |
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return indirect_write_config_pcie(hose, dev, offset, 2, (u32) val); |
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} |
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|
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static int |
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indirect_write_config_dword_pcie(struct pci_controller *hose, |
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pci_dev_t dev, |
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int offset, |
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u32 val) |
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{ |
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return indirect_write_config_pcie(hose, dev, offset, 4, val); |
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} |
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|
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void |
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pcie_setup_indirect(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) |
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{ |
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pci_set_ops(hose, |
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indirect_read_config_byte_pcie, |
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indirect_read_config_word_pcie, |
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indirect_read_config_dword_pcie, |
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indirect_write_config_byte_pcie, |
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indirect_write_config_word_pcie, |
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indirect_write_config_dword_pcie); |
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|
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hose->cfg_addr = (unsigned int *)cfg_addr; |
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hose->cfg_data = (unsigned char *)cfg_data; |
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} |
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|
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#endif /* CONFIG_PCI */ |
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@ -0,0 +1,180 @@ |
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/*
|
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* Copyright 2007 Freescale Semiconductor, Inc. |
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* |
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* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License |
||||
* Version 2 as published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#define DEBUG |
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#include <common.h> |
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|
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#ifdef CONFIG_FSL_PCI_INIT |
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|
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/*
|
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* PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's |
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* |
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* Initialize controller and call the common driver/pci pci_hose_scan to |
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* scan for bridges and devices. |
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* |
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* Hose fields which need to be pre-initialized by board specific code: |
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* regions[] |
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* first_busno |
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* |
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* Fields updated: |
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* last_busno |
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*/ |
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|
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#include <pci.h> |
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#include <asm/immap_fsl_pci.h> |
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|
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void pciauto_prescan_setup_bridge(struct pci_controller *hose, |
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pci_dev_t dev, int sub_bus); |
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void pciauto_postscan_setup_bridge(struct pci_controller *hose, |
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pci_dev_t dev, int sub_bus); |
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|
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void pciauto_config_init(struct pci_controller *hose); |
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void |
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fsl_pci_init(struct pci_controller *hose) |
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{ |
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u16 temp16; |
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u32 temp32; |
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int busno = hose->first_busno; |
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int enabled; |
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u16 ltssm; |
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u8 temp8; |
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int r; |
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int bridge; |
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr; |
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pci_dev_t dev = PCI_BDF(busno,0,0); |
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|
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/* Initialize ATMU registers based on hose regions and flags */ |
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volatile pot_t *po=&pci->pot[1]; /* skip 0 */ |
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volatile pit_t *pi=&pci->pit[0]; /* ranges from: 3 to 1 */ |
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|
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#ifdef DEBUG |
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int neg_link_w; |
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#endif |
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|
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for (r=0; r<hose->region_count; r++) { |
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if (hose->regions[r].flags & PCI_REGION_MEMORY) { /* inbound */ |
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pi->pitar = (hose->regions[r].bus_start >> 12) & 0x000fffff; |
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pi->piwbar = (hose->regions[r].phys_start >> 12) & 0x000fffff; |
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pi->piwbear = 0; |
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pi->piwar = PIWAR_EN | PIWAR_PF | PIWAR_LOCAL | |
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PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | |
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(__ilog2(hose->regions[r].size) - 1); |
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pi++; |
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} else { /* Outbound */ |
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po->powbar = (hose->regions[r].phys_start >> 12) & 0x000fffff; |
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po->potar = (hose->regions[r].bus_start >> 12) & 0x000fffff; |
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po->potear = 0; |
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if (hose->regions[r].flags & PCI_REGION_IO) |
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po->powar = POWAR_EN | POWAR_IO_READ | POWAR_IO_WRITE | |
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(__ilog2(hose->regions[r].size) - 1); |
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else |
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po->powar = POWAR_EN | POWAR_MEM_READ | POWAR_MEM_WRITE | |
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(__ilog2(hose->regions[r].size) - 1); |
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po++; |
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} |
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} |
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|
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pci_register_hose(hose); |
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pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */ |
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hose->current_busno = hose->first_busno; |
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|
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pci->pedr = 0xffffffff; /* Clear any errors */ |
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pci->peer = 0xffffffff; /* Enable Error Interupts */ |
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pci_hose_read_config_dword (hose, dev, PCI_DCR, &temp32); |
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temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */ |
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pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32); |
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|
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pci_hose_read_config_byte (hose, dev, PCI_HEADER_TYPE, &temp8); |
||||
bridge = temp8 & PCI_HEADER_TYPE_BRIDGE; /* Bridge, such as pcie */ |
||||
|
||||
if ( bridge ) { |
||||
|
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pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); |
||||
enabled = ltssm >= PCI_LTSSM_L0; |
||||
|
||||
if (!enabled) { |
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debug("....PCIE link error. Skipping scan." |
||||
"LTSSM=0x%02x\n", temp16); |
||||
hose->last_busno = hose->first_busno; |
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return; |
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} |
||||
|
||||
pci->pme_msg_det = 0xffffffff; |
||||
pci->pme_msg_int_en = 0xffffffff; |
||||
#ifdef DEBUG |
||||
pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16); |
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neg_link_w = (temp16 & 0x3f0 ) >> 4; |
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debug("...PCIE LTSSM=0x%x, Negotiated link width=%d\n", |
||||
ltssm, neg_link_w); |
||||
#endif |
||||
hose->current_busno++; /* Start scan with secondary */ |
||||
pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); |
||||
|
||||
} else { |
||||
#if 0 |
||||
/* done in pci_hose_config_device() */ |
||||
pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16); |
||||
temp16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | |
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PCI_COMMAND_MEMORY | PCI_COMMAND_IO; |
||||
pci_hose_write_config_word(hose, dev, PCI_COMMAND, temp16); |
||||
pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); |
||||
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); |
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#endif |
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} |
||||
|
||||
/* Call setup to allocate PCSRBAR window */ |
||||
pciauto_setup_device(hose, dev, 1, hose->pci_mem, |
||||
hose->pci_prefetch, hose->pci_io); |
||||
|
||||
printf (" Scanning PCI bus %02x\n", hose->current_busno); |
||||
hose->last_busno = pci_hose_scan_bus(hose,hose->current_busno); |
||||
|
||||
if ( bridge ) { /* update limit regs and subordinate busno */ |
||||
pciauto_postscan_setup_bridge(hose, dev, hose->last_busno); |
||||
} |
||||
|
||||
/* Clear all error indications */ |
||||
|
||||
if (pci->pme_msg_det && pci->pme_msg_det != 0xffffffff) { |
||||
debug("pci_fsl_init: pme_msg_det@%x=%x. Clearing\n", |
||||
&pci->pme_msg_det, pci->pme_msg_det); |
||||
pci->pme_msg_det = 0xffffffff; |
||||
} |
||||
|
||||
if (pci->pedr) { |
||||
debug("pci_fsl_init: pedr@%x=%x. Clearing\n", |
||||
&pci->pedr, pci->pedr); |
||||
pci->pedr = 0xffffffff; |
||||
} |
||||
|
||||
pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16); |
||||
if (temp16) { |
||||
debug("pci_fsl_init: PCI_DSR@%x=%x. Clearing\n", |
||||
PCI_DSR, temp16); |
||||
pci_hose_write_config_word(hose, dev, |
||||
PCI_DSR, 0xffff); |
||||
} |
||||
|
||||
pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16); |
||||
if (temp16) { |
||||
debug("pci_fsl_init: PCI_SEC_STATUS@%x=%x. Clearing\n", |
||||
PCI_SEC_STATUS, temp16); |
||||
pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff); |
||||
} |
||||
} |
||||
|
||||
#endif /* CONFIG_FSL_PCI */ |
||||
@ -0,0 +1,150 @@ |
||||
/* (C) Copyright 2007 Freescale Semiconductor, Inc.
|
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#ifndef __IMMAP_85xx_fsl_pci__ |
||||
#define __IMMAP_85xx_fsl_pci__ |
||||
|
||||
/*
|
||||
* Common PCI/PCIE Register structure for mpc85xx and mpc86xx |
||||
*/ |
||||
|
||||
/*
|
||||
* PCI Translation Registers |
||||
*/ |
||||
typedef struct pci_outbound_window { |
||||
u32 potar; /* 0x00 - Address */ |
||||
u32 potear; /* 0x04 - Address Extended */ |
||||
u32 powbar; /* 0x08 - Window Base Address */ |
||||
u32 res1; |
||||
u32 powar; /* 0x10 - Window Attributes */ |
||||
#define POWAR_EN 0x80000000 |
||||
#define POWAR_IO_READ 0x00080000 |
||||
#define POWAR_MEM_READ 0x00040000 |
||||
#define POWAR_IO_WRITE 0x00008000 |
||||
#define POWAR_MEM_WRITE 0x00004000 |
||||
u32 res2[3]; |
||||
} pot_t; |
||||
|
||||
typedef struct pci_inbound_window { |
||||
u32 pitar; /* 0x00 - Address */ |
||||
u32 res1; |
||||
u32 piwbar; /* 0x08 - Window Base Address */ |
||||
u32 piwbear; /* 0x0c - Window Base Address Extended */ |
||||
u32 piwar; /* 0x10 - Window Attributes */ |
||||
#define PIWAR_EN 0x80000000 |
||||
#define PIWAR_PF 0x20000000 |
||||
#define PIWAR_LOCAL 0x00f00000 |
||||
#define PIWAR_READ_SNOOP 0x00050000 |
||||
#define PIWAR_WRITE_SNOOP 0x00005000 |
||||
u32 res2[3]; |
||||
} pit_t; |
||||
|
||||
/* PCI/PCI Express Registers */ |
||||
typedef struct ccsr_pci { |
||||
u32 cfg_addr; /* 0x000 - PCI Configuration Address Register */ |
||||
u32 cfg_data; /* 0x004 - PCI Configuration Data Register */ |
||||
u32 int_ack; /* 0x008 - PCI Interrupt Acknowledge Register */ |
||||
u32 out_comp_to; /* 0x00C - PCI Outbound Completion Timeout Register */ |
||||
u32 out_conf_to; /* 0x010 - PCI Configuration Timeout Register */ |
||||
u32 config; /* 0x014 - PCIE CONFIG Register */ |
||||
char res2[8]; |
||||
u32 pme_msg_det; /* 0x020 - PCIE PME & message detect register */ |
||||
u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */ |
||||
u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */ |
||||
u32 pm_command; /* 0x02c - PCIE PM Command register */ |
||||
char res4[3016]; /* (- #xbf8 #x30)3016 */ |
||||
u32 block_rev1; /* 0xbf8 - PCIE Block Revision register 1 */ |
||||
u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */ |
||||
|
||||
pot_t pot[5]; /* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */ |
||||
u32 res5[64]; |
||||
pit_t pit[3]; /* 0xda0 - 0xdff Inbound ATMU's 3, 2, and 1 */ |
||||
#define PIT3 0 |
||||
#define PIT2 1 |
||||
#define PIT1 2 |
||||
|
||||
#if 0 |
||||
u32 potar0; /* 0xc00 - PCI Outbound Transaction Address Register 0 */ |
||||
u32 potear0; /* 0xc04 - PCI Outbound Translation Extended Address Register 0 */ |
||||
char res5[8]; |
||||
u32 powar0; /* 0xc10 - PCI Outbound Window Attributes Register 0 */ |
||||
char res6[12]; |
||||
u32 potar1; /* 0xc20 - PCI Outbound Transaction Address Register 1 */ |
||||
u32 potear1; /* 0xc24 - PCI Outbound Translation Extended Address Register 1 */ |
||||
u32 powbar1; /* 0xc28 - PCI Outbound Window Base Address Register 1 */ |
||||
char res7[4]; |
||||
u32 powar1; /* 0xc30 - PCI Outbound Window Attributes Register 1 */ |
||||
char res8[12]; |
||||
u32 potar2; /* 0xc40 - PCI Outbound Transaction Address Register 2 */ |
||||
u32 potear2; /* 0xc44 - PCI Outbound Translation Extended Address Register 2 */ |
||||
u32 powbar2; /* 0xc48 - PCI Outbound Window Base Address Register 2 */ |
||||
char res9[4]; |
||||
u32 powar2; /* 0xc50 - PCI Outbound Window Attributes Register 2 */ |
||||
char res10[12]; |
||||
u32 potar3; /* 0xc60 - PCI Outbound Transaction Address Register 3 */ |
||||
u32 potear3; /* 0xc64 - PCI Outbound Translation Extended Address Register 3 */ |
||||
u32 powbar3; /* 0xc68 - PCI Outbound Window Base Address Register 3 */ |
||||
char res11[4]; |
||||
u32 powar3; /* 0xc70 - PCI Outbound Window Attributes Register 3 */ |
||||
char res12[12]; |
||||
u32 potar4; /* 0xc80 - PCI Outbound Transaction Address Register 4 */ |
||||
u32 potear4; /* 0xc84 - PCI Outbound Translation Extended Address Register 4 */ |
||||
u32 powbar4; /* 0xc88 - PCI Outbound Window Base Address Register 4 */ |
||||
char res13[4]; |
||||
u32 powar4; /* 0xc90 - PCI Outbound Window Attributes Register 4 */ |
||||
char res14[268]; |
||||
u32 pitar3; /* 0xda0 - PCI Inbound Translation Address Register 3 */ |
||||
char res15[4]; |
||||
u32 piwbar3; /* 0xda8 - PCI Inbound Window Base Address Register 3 */ |
||||
u32 piwbear3; /* 0xdac - PCI Inbound Window Base Extended Address Register 3 */ |
||||
u32 piwar3; /* 0xdb0 - PCI Inbound Window Attributes Register 3 */ |
||||
char res16[12]; |
||||
u32 pitar2; /* 0xdc0 - PCI Inbound Translation Address Register 2 */ |
||||
char res17[4]; |
||||
u32 piwbar2; /* 0xdc8 - PCI Inbound Window Base Address Register 2 */ |
||||
u32 piwbear2; /* 0xdcc - PCI Inbound Window Base Extended Address Register 2 */ |
||||
u32 piwar2; /* 0xdd0 - PCI Inbound Window Attributes Register 2 */ |
||||
char res18[12]; |
||||
u32 pitar1; /* 0xde0 - PCI Inbound Translation Address Register 1 */ |
||||
char res19[4]; |
||||
u32 piwbar1; /* 0xde8 - PCI Inbound Window Base Address Register 1 */ |
||||
char res20[4]; |
||||
u32 piwar1; /* 0xdf0 - PCI Inbound Window Attributes Register 1 */ |
||||
char res21[12]; |
||||
#endif |
||||
u32 pedr; /* 0xe00 - PCI Error Detect Register */ |
||||
u32 pecdr; /* 0xe04 - PCI Error Capture Disable Register */ |
||||
u32 peer; /* 0xe08 - PCI Error Interrupt Enable Register */ |
||||
u32 peattrcr; /* 0xe0c - PCI Error Attributes Capture Register */ |
||||
u32 peaddrcr; /* 0xe10 - PCI Error Address Capture Register */ |
||||
/* u32 perr_disr * 0xe10 - PCIE Erorr Disable Register */ |
||||
u32 peextaddrcr; /* 0xe14 - PCI Error Extended Address Capture Register */ |
||||
u32 pedlcr; /* 0xe18 - PCI Error Data Low Capture Register */ |
||||
u32 pedhcr; /* 0xe1c - PCI Error Error Data High Capture Register */ |
||||
u32 gas_timr; /* 0xe20 - PCI Gasket Timer Register */ |
||||
/* u32 perr_cap_stat; * 0xe20 - PCIE Error Capture Status Register */ |
||||
char res22[4]; |
||||
u32 perr_cap0; /* 0xe28 - PCIE Error Capture Register 0 */ |
||||
u32 perr_cap1; /* 0xe2c - PCIE Error Capture Register 1 */ |
||||
u32 perr_cap2; /* 0xe30 - PCIE Error Capture Register 2 */ |
||||
u32 perr_cap3; /* 0xe34 - PCIE Error Capture Register 3 */ |
||||
char res23[456]; /* (- #x1000 #xe38) 456 */ |
||||
} ccsr_fsl_pci_t; |
||||
|
||||
#endif /*__IMMAP_fsl_pci__*/ |
||||
Loading…
Reference in new issue