This patch performs the following: 1) Convert the assembly code for memory and clock initialization to C code. 2) Move the memory and clock init codes from board/samsung to arch/arm 3) Creat a common lowlevel_init file across Exynos4 and Exynos5. Converted the common lowlevel_init from assembly to C-code 4) Made spl_boot.c and tzpc_init.c common for both exynos4 and exynos5. 5) Enable CONFIG_SKIP_LOWLEVEL_INIT as stack pointer initialisation is already done in _main. 6) exynos-uboot-spl.lds made common across SMDKV310, Origen and SMDK5250. TEST: Tested SD-MMC boot on SMDK5250 and Origen. Tested USB and SPI boot on SMDK5250 Compile tested for SMDKV310. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>master
parent
198a40b9f6
commit
643be9c07e
@ -0,0 +1,95 @@ |
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/*
|
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* Clock Initialization for board based on EXYNOS4210 |
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* |
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* Copyright (C) 2013 Samsung Electronics |
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* Rajeshwari Shinde <rajeshwari.s@samsung.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <config.h> |
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#include <version.h> |
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#include <asm/io.h> |
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#include <asm/arch/cpu.h> |
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#include <asm/arch/clk.h> |
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#include <asm/arch/clock.h> |
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#include "common_setup.h" |
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#include "exynos4_setup.h" |
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|
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/*
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* system_clock_init: Initialize core clock and bus clock. |
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* void system_clock_init(void) |
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*/ |
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void system_clock_init(void) |
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{ |
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struct exynos4_clock *clk = |
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(struct exynos4_clock *)samsung_get_base_clock(); |
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|
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writel(CLK_SRC_CPU_VAL, &clk->src_cpu); |
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sdelay(0x10000); |
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writel(CLK_SRC_TOP0_VAL, &clk->src_top0); |
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writel(CLK_SRC_TOP1_VAL, &clk->src_top1); |
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writel(CLK_SRC_DMC_VAL, &clk->src_dmc); |
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writel(CLK_SRC_LEFTBUS_VAL, &clk->src_leftbus); |
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writel(CLK_SRC_RIGHTBUS_VAL, &clk->src_rightbus); |
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writel(CLK_SRC_FSYS_VAL, &clk->src_fsys); |
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writel(CLK_SRC_PERIL0_VAL, &clk->src_peril0); |
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writel(CLK_SRC_CAM_VAL, &clk->src_cam); |
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writel(CLK_SRC_MFC_VAL, &clk->src_mfc); |
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writel(CLK_SRC_G3D_VAL, &clk->src_g3d); |
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writel(CLK_SRC_LCD0_VAL, &clk->src_lcd0); |
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sdelay(0x10000); |
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writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0); |
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writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1); |
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writel(CLK_DIV_DMC0_VAL, &clk->div_dmc0); |
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writel(CLK_DIV_DMC1_VAL, &clk->div_dmc1); |
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writel(CLK_DIV_LEFTBUS_VAL, &clk->div_leftbus); |
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writel(CLK_DIV_RIGHTBUS_VAL, &clk->div_rightbus); |
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writel(CLK_DIV_TOP_VAL, &clk->div_top); |
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writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1); |
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writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2); |
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writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3); |
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writel(CLK_DIV_PERIL0_VAL, &clk->div_peril0); |
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writel(CLK_DIV_CAM_VAL, &clk->div_cam); |
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writel(CLK_DIV_MFC_VAL, &clk->div_mfc); |
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writel(CLK_DIV_G3D_VAL, &clk->div_g3d); |
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writel(CLK_DIV_LCD0_VAL, &clk->div_lcd0); |
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|
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/* Set PLL locktime */ |
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writel(PLL_LOCKTIME, &clk->apll_lock); |
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writel(PLL_LOCKTIME, &clk->mpll_lock); |
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writel(PLL_LOCKTIME, &clk->epll_lock); |
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writel(PLL_LOCKTIME, &clk->vpll_lock); |
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|
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writel(APLL_CON1_VAL, &clk->apll_con1); |
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writel(APLL_CON0_VAL, &clk->apll_con0); |
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writel(MPLL_CON1_VAL, &clk->mpll_con1); |
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writel(MPLL_CON0_VAL, &clk->mpll_con0); |
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writel(EPLL_CON1_VAL, &clk->epll_con1); |
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writel(EPLL_CON0_VAL, &clk->epll_con0); |
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writel(VPLL_CON1_VAL, &clk->vpll_con1); |
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writel(VPLL_CON0_VAL, &clk->vpll_con0); |
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sdelay(0x30000); |
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} |
@ -0,0 +1,45 @@ |
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/*
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* Common APIs for EXYNOS based board |
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* |
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* Copyright (C) 2013 Samsung Electronics |
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* Rajeshwari Shinde <rajeshwari.s@samsung.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#define DMC_OFFSET 0x10000 |
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/*
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* Memory initialization |
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* |
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* @param reset Reset PHY during initialization. |
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*/ |
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void mem_ctrl_init(int reset); |
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|
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/* System Clock initialization */ |
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void system_clock_init(void); |
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|
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/*
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* Init subsystems according to the reset status |
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* |
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* @return 0 for a normal boot, non-zero for a resume |
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*/ |
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int do_lowlevel_init(void); |
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|
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void sdelay(unsigned long); |
@ -0,0 +1,213 @@ |
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/*
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* Memory setup for board based on EXYNOS4210 |
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* |
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* Copyright (C) 2013 Samsung Electronics |
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* Rajeshwari Shinde <rajeshwari.s@samsung.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <config.h> |
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#include <asm/arch/dmc.h> |
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#include "common_setup.h" |
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#include "exynos4_setup.h" |
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struct mem_timings mem = { |
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.direct_cmd_msr = { |
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DIRECT_CMD1, DIRECT_CMD2, DIRECT_CMD3, DIRECT_CMD4 |
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}, |
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.timingref = TIMINGREF_VAL, |
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.timingrow = TIMINGROW_VAL, |
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.timingdata = TIMINGDATA_VAL, |
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.timingpower = TIMINGPOWER_VAL, |
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.zqcontrol = ZQ_CONTROL_VAL, |
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.control0 = CONTROL0_VAL, |
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.control1 = CONTROL1_VAL, |
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.control2 = CONTROL2_VAL, |
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.concontrol = CONCONTROL_VAL, |
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.prechconfig = PRECHCONFIG, |
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.memcontrol = MEMCONTROL_VAL, |
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.memconfig0 = MEMCONFIG0_VAL, |
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.memconfig1 = MEMCONFIG1_VAL, |
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.dll_resync = FORCE_DLL_RESYNC, |
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.dll_on = DLL_CONTROL_ON, |
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}; |
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static void phy_control_reset(int ctrl_no, struct exynos4_dmc *dmc) |
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{ |
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if (ctrl_no) { |
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writel((mem.control1 | (1 << mem.dll_resync)), |
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&dmc->phycontrol1); |
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writel((mem.control1 | (0 << mem.dll_resync)), |
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&dmc->phycontrol1); |
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} else { |
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writel((mem.control0 | (0 << mem.dll_on)), |
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&dmc->phycontrol0); |
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writel((mem.control0 | (1 << mem.dll_on)), |
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&dmc->phycontrol0); |
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} |
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} |
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static void dmc_config_mrs(struct exynos4_dmc *dmc, int chip) |
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{ |
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int i; |
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unsigned long mask = 0; |
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if (chip) |
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mask = DIRECT_CMD_CHIP1_SHIFT; |
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for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) { |
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writel(mem.direct_cmd_msr[i] | mask, |
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&dmc->directcmd); |
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} |
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} |
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static void dmc_init(struct exynos4_dmc *dmc) |
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{ |
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/*
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* DLL Parameter Setting: |
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* Termination: Enable R/W |
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* Phase Delay for DQS Cleaning: 180' Shift |
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*/ |
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writel(mem.control1, &dmc->phycontrol1); |
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/*
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* ZQ Calibration |
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* Termination: Disable |
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* Auto Calibration Start: Enable |
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*/ |
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writel(mem.zqcontrol, &dmc->phyzqcontrol); |
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sdelay(0x100000); |
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/*
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* Update DLL Information: |
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* Force DLL Resyncronization |
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*/ |
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phy_control_reset(1, dmc); |
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phy_control_reset(0, dmc); |
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/* Set DLL Parameters */ |
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writel(mem.control1, &dmc->phycontrol1); |
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/* DLL Start */ |
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writel((mem.control0 | CTRL_START | CTRL_DLL_ON), &dmc->phycontrol0); |
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writel(mem.control2, &dmc->phycontrol2); |
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/* Set Clock Ratio of Bus clock to Memory Clock */ |
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writel(mem.concontrol, &dmc->concontrol); |
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/*
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* Memor Burst length: 8 |
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* Number of chips: 2 |
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* Memory Bus width: 32 bit |
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* Memory Type: DDR3 |
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* Additional Latancy for PLL: 1 Cycle |
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*/ |
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writel(mem.memcontrol, &dmc->memcontrol); |
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writel(mem.memconfig0, &dmc->memconfig0); |
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writel(mem.memconfig1, &dmc->memconfig1); |
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/* Config Precharge Policy */ |
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writel(mem.prechconfig, &dmc->prechconfig); |
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/*
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* TimingAref, TimingRow, TimingData, TimingPower Setting: |
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* Values as per Memory AC Parameters |
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*/ |
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writel(mem.timingref, &dmc->timingref); |
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writel(mem.timingrow, &dmc->timingrow); |
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writel(mem.timingdata, &dmc->timingdata); |
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writel(mem.timingpower, &dmc->timingpower); |
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/* Chip0: NOP Command: Assert and Hold CKE to high level */ |
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writel(DIRECT_CMD_NOP, &dmc->directcmd); |
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sdelay(0x100000); |
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/* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */ |
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dmc_config_mrs(dmc, 0); |
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sdelay(0x100000); |
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/* Chip0: ZQINIT */ |
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writel(DIRECT_CMD_ZQ, &dmc->directcmd); |
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sdelay(0x100000); |
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writel((DIRECT_CMD_NOP | DIRECT_CMD_CHIP1_SHIFT), &dmc->directcmd); |
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sdelay(0x100000); |
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/* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */ |
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dmc_config_mrs(dmc, 1); |
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sdelay(0x100000); |
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/* Chip1: ZQINIT */ |
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writel((DIRECT_CMD_ZQ | DIRECT_CMD_CHIP1_SHIFT), &dmc->directcmd); |
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sdelay(0x100000); |
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phy_control_reset(1, dmc); |
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sdelay(0x100000); |
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/* turn on DREX0, DREX1 */ |
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writel((mem.concontrol | AREF_EN), &dmc->concontrol); |
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} |
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void mem_ctrl_init(int reset) |
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{ |
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struct exynos4_dmc *dmc; |
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/*
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* Async bridge configuration at CPU_core: |
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* 1: half_sync |
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* 0: full_sync |
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*/ |
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writel(1, ASYNC_CONFIG); |
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#ifdef CONFIG_ORIGEN |
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/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */ |
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writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE + |
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APB_SFR_INTERLEAVE_CONF_OFFSET); |
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/* Update MIU Configuration */ |
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writel(APB_SFR_ARBRITATION_CONF_VAL, EXYNOS4_MIU_BASE + |
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APB_SFR_ARBRITATION_CONF_OFFSET); |
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#else |
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writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE + |
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APB_SFR_INTERLEAVE_CONF_OFFSET); |
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writel(INTERLEAVE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE + |
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ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET); |
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writel(INTERLEAVE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE + |
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ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET); |
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writel(INTERLEAVE_ADDR_MAP_EN, EXYNOS4_MIU_BASE + |
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ABP_SFR_SLV_ADDRMAP_CONF_OFFSET); |
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#ifdef CONFIG_MIU_LINEAR |
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writel(SLAVE0_SINGLE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE + |
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ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET); |
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writel(SLAVE0_SINGLE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE + |
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ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET); |
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writel(SLAVE1_SINGLE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE + |
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ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET); |
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writel(SLAVE1_SINGLE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE + |
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ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET); |
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writel(APB_SFR_SLV_ADDR_MAP_CONF_VAL, EXYNOS4_MIU_BASE + |
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ABP_SFR_SLV_ADDRMAP_CONF_OFFSET); |
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#endif |
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#endif |
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/* DREX0 */ |
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dmc = (struct exynos4_dmc *)samsung_get_base_dmc_ctrl(); |
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dmc_init(dmc); |
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dmc = (struct exynos4_dmc *)(samsung_get_base_dmc_ctrl() |
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+ DMC_OFFSET); |
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dmc_init(dmc); |
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} |
@ -0,0 +1,73 @@ |
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/*
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* Lowlevel setup for EXYNOS5 based board |
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* |
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* Copyright (C) 2013 Samsung Electronics |
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* Rajeshwari Shinde <rajeshwari.s@samsung.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#include <common.h> |
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#include <config.h> |
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#include <asm/arch/cpu.h> |
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#include <asm/arch/dmc.h> |
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#include <asm/arch/power.h> |
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#include <asm/arch/tzpc.h> |
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#include <asm/arch/periph.h> |
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#include <asm/arch/pinmux.h> |
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#include "common_setup.h" |
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|
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/* These are the things we can do during low-level init */ |
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enum { |
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DO_WAKEUP = 1 << 0, |
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DO_CLOCKS = 1 << 1, |
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DO_MEM_RESET = 1 << 2, |
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DO_UART = 1 << 3, |
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}; |
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|
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int do_lowlevel_init(void) |
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{ |
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uint32_t reset_status; |
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int actions = 0; |
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|
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arch_cpu_init(); |
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|
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reset_status = get_reset_status(); |
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|
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switch (reset_status) { |
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case S5P_CHECK_SLEEP: |
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actions = DO_CLOCKS | DO_WAKEUP; |
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break; |
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case S5P_CHECK_DIDLE: |
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case S5P_CHECK_LPA: |
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actions = DO_WAKEUP; |
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break; |
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default: |
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/* This is a normal boot (not a wake from sleep) */ |
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actions = DO_CLOCKS | DO_MEM_RESET; |
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} |
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|
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if (actions & DO_CLOCKS) { |
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system_clock_init(); |
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mem_ctrl_init(actions & DO_MEM_RESET); |
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tzpc_init(); |
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} |
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|
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return actions & DO_WAKEUP; |
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} |
@ -1,357 +0,0 @@ |
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/* |
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* Lowlevel setup for ORIGEN board based on EXYNOS4210 |
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* |
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* Copyright (C) 2011 Samsung Electronics |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
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*/ |
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|
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#include <config.h> |
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#include <version.h> |
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#include <asm/arch/cpu.h> |
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#include "origen_setup.h" |
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/* |
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* Register usages: |
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* |
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* r5 has zero always |
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* r7 has GPIO part1 base 0x11400000 |
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* r6 has GPIO part2 base 0x11000000 |
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*/ |
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|
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_TEXT_BASE: |
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.word CONFIG_SYS_TEXT_BASE
|
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|
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.globl lowlevel_init
|
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lowlevel_init: |
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push {lr} |
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|
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/* r5 has always zero */ |
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mov r5, #0 |
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ldr r7, =EXYNOS4_GPIO_PART1_BASE |
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ldr r6, =EXYNOS4_GPIO_PART2_BASE |
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|
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/* check reset status */ |
||||
ldr r0, =(EXYNOS4_POWER_BASE + INFORM1_OFFSET) |
||||
ldr r1, [r0] |
||||
|
||||
/* AFTR wakeup reset */ |
||||
ldr r2, =S5P_CHECK_DIDLE |
||||
cmp r1, r2 |
||||
beq exit_wakeup |
||||
|
||||
/* LPA wakeup reset */ |
||||
ldr r2, =S5P_CHECK_LPA |
||||
cmp r1, r2 |
||||
beq exit_wakeup |
||||
|
||||
/* Sleep wakeup reset */ |
||||
ldr r2, =S5P_CHECK_SLEEP |
||||
cmp r1, r2 |
||||
beq wakeup_reset |
||||
|
||||
/* |
||||
* If U-boot is already running in ram, no need to relocate U-Boot. |
||||
* Memory controller must be configured before relocating U-Boot |
||||
* in ram. |
||||
*/ |
||||
ldr r0, =0x0ffffff /* r0 <- Mask Bits*/ |
||||
bic r1, pc, r0 /* pc <- current addr of code */ |
||||
/* r1 <- unmasked bits of pc */ |
||||
ldr r2, _TEXT_BASE /* r2 <- original base addr in ram */ |
||||
bic r2, r2, r0 /* r2 <- unmasked bits of r2*/ |
||||
cmp r1, r2 /* compare r1, r2 */ |
||||
beq 1f /* r0 == r1 then skip sdram init */ |
||||
|
||||
/* init system clock */ |
||||
bl system_clock_init |
||||
|
||||
/* Memory initialize */ |
||||
bl mem_ctrl_asm_init |
||||
|
||||
1: |
||||
/* for UART */ |
||||
bl uart_asm_init |
||||
bl arch_cpu_init |
||||
bl tzpc_init |
||||
pop {pc} |
||||
|
||||
wakeup_reset: |
||||
bl system_clock_init |
||||
bl mem_ctrl_asm_init |
||||
bl arch_cpu_init |
||||
bl tzpc_init |
||||
|
||||
exit_wakeup: |
||||
/* Load return address and jump to kernel */ |
||||
ldr r0, =(EXYNOS4_POWER_BASE + INFORM0_OFFSET) |
||||
|
||||
/* r1 = physical address of exynos4210_cpu_resume function */ |
||||
ldr r1, [r0] |
||||
|
||||
/* Jump to kernel*/ |
||||
mov pc, r1 |
||||
nop |
||||
nop |
||||
|
||||
/* |
||||
* system_clock_init: Initialize core clock and bus clock. |
||||
* void system_clock_init(void) |
||||
*/ |
||||
system_clock_init: |
||||
push {lr} |
||||
ldr r0, =EXYNOS4_CLOCK_BASE |
||||
|
||||
/* APLL(1), MPLL(1), CORE(0), HPM(0) */ |
||||
ldr r1, =CLK_SRC_CPU_VAL |
||||
ldr r2, =CLK_SRC_CPU_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* wait ?us */ |
||||
mov r1, #0x10000 |
||||
2: subs r1, r1, #1 |
||||
bne 2b |
||||
|
||||
ldr r1, =CLK_SRC_TOP0_VAL |
||||
ldr r2, =CLK_SRC_TOP0_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
ldr r1, =CLK_SRC_TOP1_VAL |
||||
ldr r2, =CLK_SRC_TOP1_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* DMC */ |
||||
ldr r1, =CLK_SRC_DMC_VAL |
||||
ldr r2, =CLK_SRC_DMC_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/*CLK_SRC_LEFTBUS */ |
||||
ldr r1, =CLK_SRC_LEFTBUS_VAL |
||||
ldr r2, =CLK_SRC_LEFTBUS_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/*CLK_SRC_RIGHTBUS */ |
||||
ldr r1, =CLK_SRC_RIGHTBUS_VAL |
||||
ldr r2, =CLK_SRC_RIGHTBUS_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */ |
||||
ldr r1, =CLK_SRC_FSYS_VAL |
||||
ldr r2, =CLK_SRC_FSYS_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* UART[0:4] */ |
||||
ldr r1, =CLK_SRC_PERIL0_VAL |
||||
ldr r2, =CLK_SRC_PERIL0_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* CAM , FIMC 0-3 */ |
||||
ldr r1, =CLK_SRC_CAM_VAL |
||||
ldr r2, =CLK_SRC_CAM_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* MFC */ |
||||
ldr r1, =CLK_SRC_MFC_VAL |
||||
ldr r2, =CLK_SRC_MFC_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* G3D */ |
||||
ldr r1, =CLK_SRC_G3D_VAL |
||||
ldr r2, =CLK_SRC_G3D_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* LCD0 */ |
||||
ldr r1, =CLK_SRC_LCD0_VAL |
||||
ldr r2, =CLK_SRC_LCD0_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* wait ?us */ |
||||
mov r1, #0x10000 |
||||
3: subs r1, r1, #1 |
||||
bne 3b |
||||
|
||||
/* CLK_DIV_CPU0 */ |
||||
ldr r1, =CLK_DIV_CPU0_VAL |
||||
ldr r2, =CLK_DIV_CPU0_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* CLK_DIV_CPU1 */ |
||||
ldr r1, =CLK_DIV_CPU1_VAL |
||||
ldr r2, =CLK_DIV_CPU1_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* CLK_DIV_DMC0 */ |
||||
ldr r1, =CLK_DIV_DMC0_VAL |
||||
ldr r2, =CLK_DIV_DMC0_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/*CLK_DIV_DMC1 */ |
||||
ldr r1, =CLK_DIV_DMC1_VAL |
||||
ldr r2, =CLK_DIV_DMC1_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* CLK_DIV_LEFTBUS */ |
||||
ldr r1, =CLK_DIV_LEFTBUS_VAL |
||||
ldr r2, =CLK_DIV_LEFTBUS_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* CLK_DIV_RIGHTBUS */ |
||||
ldr r1, =CLK_DIV_RIGHTBUS_VAL |
||||
ldr r2, =CLK_DIV_RIGHTBUS_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* CLK_DIV_TOP */ |
||||
ldr r1, =CLK_DIV_TOP_VAL |
||||
ldr r2, =CLK_DIV_TOP_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* MMC[0:1] */ |
||||
ldr r1, =CLK_DIV_FSYS1_VAL /* 800(MPLL) / (15 + 1) */ |
||||
ldr r2, =CLK_DIV_FSYS1_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* MMC[2:3] */ |
||||
ldr r1, =CLK_DIV_FSYS2_VAL /* 800(MPLL) / (15 + 1) */ |
||||
ldr r2, =CLK_DIV_FSYS2_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* MMC4 */ |
||||
ldr r1, =CLK_DIV_FSYS3_VAL /* 800(MPLL) / (15 + 1) */ |
||||
ldr r2, =CLK_DIV_FSYS3_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* CLK_DIV_PERIL0: UART Clock Divisors */ |
||||
ldr r1, =CLK_DIV_PERIL0_VAL |
||||
ldr r2, =CLK_DIV_PERIL0_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* CAM, FIMC 0-3: CAM Clock Divisors */ |
||||
ldr r1, =CLK_DIV_CAM_VAL |
||||
ldr r2, =CLK_DIV_CAM_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* CLK_DIV_MFC: MFC Clock Divisors */ |
||||
ldr r1, =CLK_DIV_MFC_VAL |
||||
ldr r2, =CLK_DIV_MFC_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* CLK_DIV_G3D: G3D Clock Divisors */ |
||||
ldr r1, =CLK_DIV_G3D_VAL |
||||
ldr r2, =CLK_DIV_G3D_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* CLK_DIV_LCD0: LCD0 Clock Divisors */ |
||||
ldr r1, =CLK_DIV_LCD0_VAL |
||||
ldr r2, =CLK_DIV_LCD0_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* Set PLL locktime */ |
||||
ldr r1, =PLL_LOCKTIME |
||||
ldr r2, =APLL_LOCK_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
ldr r1, =PLL_LOCKTIME |
||||
ldr r2, =MPLL_LOCK_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
ldr r1, =PLL_LOCKTIME |
||||
ldr r2, =EPLL_LOCK_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
ldr r1, =PLL_LOCKTIME |
||||
ldr r2, =VPLL_LOCK_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* APLL_CON1 */ |
||||
ldr r1, =APLL_CON1_VAL |
||||
ldr r2, =APLL_CON1_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* APLL_CON0 */ |
||||
ldr r1, =APLL_CON0_VAL |
||||
ldr r2, =APLL_CON0_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* MPLL_CON1 */ |
||||
ldr r1, =MPLL_CON1_VAL |
||||
ldr r2, =MPLL_CON1_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* MPLL_CON0 */ |
||||
ldr r1, =MPLL_CON0_VAL |
||||
ldr r2, =MPLL_CON0_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* EPLL */ |
||||
ldr r1, =EPLL_CON1_VAL |
||||
ldr r2, =EPLL_CON1_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* EPLL_CON0 */ |
||||
ldr r1, =EPLL_CON0_VAL |
||||
ldr r2, =EPLL_CON0_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* VPLL_CON1 */ |
||||
ldr r1, =VPLL_CON1_VAL |
||||
ldr r2, =VPLL_CON1_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* VPLL_CON0 */ |
||||
ldr r1, =VPLL_CON0_VAL |
||||
ldr r2, =VPLL_CON0_OFFSET |
||||
str r1, [r0, r2] |
||||
|
||||
/* wait ?us */ |
||||
mov r1, #0x30000 |
||||
4: subs r1, r1, #1 |
||||
bne 4b |
||||
|
||||
pop {pc} |
||||
/* |
||||
* uart_asm_init: Initialize UART in asm mode, 115200bps fixed. |
||||
* void uart_asm_init(void) |
||||
*/ |
||||
.globl uart_asm_init
|
||||
uart_asm_init: |
||||
|
||||
/* setup UART0-UART3 GPIOs (part1) */ |
||||
mov r0, r7 |
||||
ldr r1, =EXYNOS4_GPIO_A0_CON_VAL |
||||
str r1, [r0, #EXYNOS4_GPIO_A0_CON_OFFSET] |
||||
ldr r1, =EXYNOS4_GPIO_A1_CON_VAL |
||||
str r1, [r0, #EXYNOS4_GPIO_A1_CON_OFFSET] |
||||
|
||||
ldr r0, =EXYNOS4_UART_BASE |
||||
add r0, r0, #EXYNOS4_DEFAULT_UART_OFFSET |
||||
|
||||
ldr r1, =ULCON_VAL |
||||
str r1, [r0, #ULCON_OFFSET] |
||||
ldr r1, =UCON_VAL |
||||
str r1, [r0, #UCON_OFFSET] |
||||
ldr r1, =UFCON_VAL |
||||
str r1, [r0, #UFCON_OFFSET] |
||||
ldr r1, =UBRDIV_VAL |
||||
str r1, [r0, #UBRDIV_OFFSET] |
||||
ldr r1, =UFRACVAL_VAL |
||||
str r1, [r0, #UFRACVAL_OFFSET] |
||||
mov pc, lr |
||||
nop |
||||
nop |
||||
nop |
||||
|
@ -1,421 +0,0 @@ |
||||
/* |
||||
* Memory setup for ORIGEN board based on EXYNOS4210 |
||||
* |
||||
* Copyright (C) 2011 Samsung Electronics |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include "origen_setup.h" |
||||
#define SET_MIU |
||||
|
||||
.globl mem_ctrl_asm_init
|
||||
mem_ctrl_asm_init: |
||||
/* |
||||
* Async bridge configuration at CPU_core: |
||||
* 1: half_sync |
||||
* 0: full_sync |
||||
*/ |
||||
ldr r0, =ASYNC_CONFIG |
||||
mov r1, #1 |
||||
str r1, [r0] |
||||
|
||||
#ifdef SET_MIU |
||||
ldr r0, =EXYNOS4_MIU_BASE |
||||
/* Interleave: 2Bit, Interleave_bit1: 0x21, Interleave_bit2: 0x7 */ |
||||
ldr r1, =0x20001507 |
||||
str r1, [r0, #APB_SFR_INTERLEAVE_CONF_OFFSET] |
||||
|
||||
/* Update MIU Configuration */ |
||||
ldr r1, =0x00000001 |
||||
str r1, [r0, #APB_SFR_ARBRITATION_CONF_OFFSET] |
||||
#endif |
||||
/* DREX0 */ |
||||
ldr r0, =EXYNOS4_DMC0_BASE |
||||
|
||||
/* |
||||
* DLL Parameter Setting: |
||||
* Termination: Enable R/W |
||||
* Phase Delay for DQS Cleaning: 180' Shift |
||||
*/ |
||||
ldr r1, =0xe0000086 |
||||
str r1, [r0, #DMC_PHYCONTROL1] |
||||
|
||||
/* |
||||
* ZQ Calibration |
||||
* Termination: Disable |
||||
* Auto Calibration Start: Enable |
||||
*/ |
||||
ldr r1, =0xE3855703 |
||||
str r1, [r0, #DMC_PHYZQCONTROL] |
||||
|
||||
/* Wait ?us*/ |
||||
mov r2, #0x100000 |
||||
1: subs r2, r2, #1 |
||||
bne 1b |
||||
|
||||
/* |
||||
* Update DLL Information: |
||||
* Force DLL Resyncronization |
||||
*/ |
||||
ldr r1, =0xe000008e |
||||
str r1, [r0, #DMC_PHYCONTROL1] |
||||
|
||||
/* Reset Force DLL Resyncronization */ |
||||
ldr r1, =0xe0000086 |
||||
str r1, [r0, #DMC_PHYCONTROL1] |
||||
|
||||
/* Enable Differential DQS, DLL Off*/ |
||||
ldr r1, =0x71101008 |
||||
str r1, [r0, #DMC_PHYCONTROL0] |
||||
|
||||
/* Activate PHY DLL: DLL On */ |
||||
ldr r1, =0x7110100A |
||||
str r1, [r0, #DMC_PHYCONTROL0] |
||||
|
||||
/* Set DLL Parameters */ |
||||
ldr r1, =0xe0000086 |
||||
str r1, [r0, #DMC_PHYCONTROL1] |
||||
|
||||
/* DLL Start */ |
||||
ldr r1, =0x7110100B |
||||
str r1, [r0, #DMC_PHYCONTROL0] |
||||
|
||||
ldr r1, =0x00000000 |
||||
str r1, [r0, #DMC_PHYCONTROL2] |
||||
|
||||
/* Set Clock Ratio of Bus clock to Memory Clock */ |
||||
ldr r1, =0x0FFF301a |
||||
str r1, [r0, #DMC_CONCONTROL] |
||||
|
||||
/* |
||||
* Memor Burst length: 8 |
||||
* Number of chips: 2 |
||||
* Memory Bus width: 32 bit |
||||
* Memory Type: DDR3 |
||||
* Additional Latancy for PLL: 1 Cycle |
||||
*/ |
||||
ldr r1, =0x00312640 |
||||
str r1, [r0, #DMC_MEMCONTROL] |
||||
|
||||
/* |
||||
* Memory Configuration Chip 0 |
||||
* Address Mapping: Interleaved |
||||
* Number of Column address Bits: 10 bits |
||||
* Number of Rows Address Bits: 14 |
||||
* Number of Banks: 8 |
||||
*/ |
||||
ldr r1, =0x20e01323 |
||||
str r1, [r0, #DMC_MEMCONFIG0] |
||||
|
||||
/* |
||||
* Memory Configuration Chip 1 |
||||
* Address Mapping: Interleaved |
||||
* Number of Column address Bits: 10 bits |
||||
* Number of Rows Address Bits: 14 |
||||
* Number of Banks: 8 |
||||
*/ |
||||
ldr r1, =0x40e01323 |
||||
str r1, [r0, #DMC_MEMCONFIG1] |
||||
|
||||
/* Config Precharge Policy */ |
||||
ldr r1, =0xff000000 |
||||
str r1, [r0, #DMC_PRECHCONFIG] |
||||
|
||||
/* |
||||
* TimingAref, TimingRow, TimingData, TimingPower Setting: |
||||
* Values as per Memory AC Parameters |
||||
*/ |
||||
ldr r1, =0x000000BB |
||||
str r1, [r0, #DMC_TIMINGAREF] |
||||
ldr r1, =0x4046654f |
||||
str r1, [r0, #DMC_TIMINGROW] |
||||
ldr r1, =0x46400506 |
||||
str r1, [r0, #DMC_TIMINGDATA] |
||||
ldr r1, =0x52000A3C |
||||
str r1, [r0, #DMC_TIMINGPOWER] |
||||
|
||||
/* Chip0: NOP Command: Assert and Hold CKE to high level */ |
||||
ldr r1, =0x07000000 |
||||
str r1, [r0, #DMC_DIRECTCMD] |
||||
|
||||
/* Wait ?us*/ |
||||
mov r2, #0x100000 |
||||
2: subs r2, r2, #1 |
||||
bne 2b |
||||
|
||||
/* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */ |
||||
ldr r1, =0x00020000 |
||||
str r1, [r0, #DMC_DIRECTCMD] |
||||
ldr r1, =0x00030000 |
||||
str r1, [r0, #DMC_DIRECTCMD] |
||||
ldr r1, =0x00010002 |
||||
str r1, [r0, #DMC_DIRECTCMD] |
||||
ldr r1, =0x00000328 |
||||
str r1, [r0, #DMC_DIRECTCMD] |
||||
|
||||
/* Wait ?us*/ |
||||
mov r2, #0x100000 |
||||
3: subs r2, r2, #1 |
||||
bne 3b |
||||
|
||||
/* Chip0: ZQINIT */ |
||||
ldr r1, =0x0a000000 |
||||
str r1, [r0, #DMC_DIRECTCMD] |
||||
|
||||
/* Wait ?us*/ |
||||
mov r2, #0x100000 |
||||
4: subs r2, r2, #1 |
||||
bne 4b |
||||
|
||||
/* Chip1: NOP Command: Assert and Hold CKE to high level */ |
||||
ldr r1, =0x07100000 |
||||
str r1, [r0, #DMC_DIRECTCMD] |
||||
|
||||
/* Wait ?us*/ |
||||
mov r2, #0x100000 |
||||
5: subs r2, r2, #1 |
||||
bne 5b |
||||
|
||||
/* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */ |
||||
ldr r1, =0x00120000 |
||||
str r1, [r0, #DMC_DIRECTCMD] |
||||
ldr r1, =0x00130000 |
||||
str r1, [r0, #DMC_DIRECTCMD] |
||||
ldr r1, =0x00110002 |
||||
str r1, [r0, #DMC_DIRECTCMD] |
||||
ldr r1, =0x00100328 |
||||
str r1, [r0, #DMC_DIRECTCMD] |
||||
|
||||
/* Wait ?us*/ |
||||
mov r2, #0x100000 |
||||
6: subs r2, r2, #1 |
||||
bne 6b |
||||
|
||||
/* Chip1: ZQINIT */ |
||||
ldr r1, =0x0a100000 |
||||
str r1, [r0, #DMC_DIRECTCMD] |
||||
|
||||
/* Wait ?us*/ |
||||
mov r2, #0x100000 |
||||
7: subs r2, r2, #1 |
||||
bne 7b |
||||
|
||||
ldr r1, =0xe000008e |
||||
str r1, [r0, #DMC_PHYCONTROL1] |
||||
ldr r1, =0xe0000086 |
||||
str r1, [r0, #DMC_PHYCONTROL1] |
||||
|
||||
/* Wait ?us*/ |
||||
mov r2, #0x100000 |
||||
8: subs r2, r2, #1 |
||||
bne 8b |
||||
|
||||
/* DREX1 */ |
||||
ldr r0, =EXYNOS4_DMC1_BASE @0x10410000
|
||||
|
||||
/* |
||||
* DLL Parameter Setting: |
||||
* Termination: Enable R/W |
||||
* Phase Delay for DQS Cleaning: 180' Shift |
||||
*/ |
||||
ldr r1, =0xe0000086 |
||||
str r1, [r0, #DMC_PHYCONTROL1] |
||||
|
||||
/* |
||||
* ZQ Calibration: |
||||
* Termination: Disable |
||||
* Auto Calibration Start: Enable |
||||
*/ |
||||
ldr r1, =0xE3855703 |
||||
str r1, [r0, #DMC_PHYZQCONTROL] |
||||
|
||||
/* Wait ?us*/ |
||||
mov r2, #0x100000 |
||||
1: subs r2, r2, #1 |
||||
bne 1b |
||||
|
||||
/* |
||||
* Update DLL Information: |
||||
* Force DLL Resyncronization |
||||
*/ |
||||
ldr r1, =0xe000008e |
||||
str r1, [r0, #DMC_PHYCONTROL1] |
||||
|
||||
/* Reset Force DLL Resyncronization */ |
||||
ldr r1, =0xe0000086 |
||||
str r1, [r0, #DMC_PHYCONTROL1] |
||||
|
||||
/* Enable Differential DQS, DLL Off*/ |
||||
ldr r1, =0x71101008 |
||||
str r1, [r0, #DMC_PHYCONTROL0] |
||||
|
||||
/* Activate PHY DLL: DLL On */ |
||||
ldr r1, =0x7110100A |
||||
str r1, [r0, #DMC_PHYCONTROL0] |
||||
|
||||
/* Set DLL Parameters */ |
||||
ldr r1, =0xe0000086 |
||||
str r1, [r0, #DMC_PHYCONTROL1] |
||||
|
||||
/* DLL Start */ |
||||
ldr r1, =0x7110100B |
||||
str r1, [r0, #DMC_PHYCONTROL0] |
||||
|
||||
ldr r1, =0x00000000 |
||||
str r1, [r0, #DMC_PHYCONTROL2] |
||||
|
||||
/* Set Clock Ratio of Bus clock to Memory Clock */ |
||||
ldr r1, =0x0FFF301a |
||||
str r1, [r0, #DMC_CONCONTROL] |
||||
|
||||
/* |
||||
* Memor Burst length: 8 |
||||
* Number of chips: 2 |
||||
* Memory Bus width: 32 bit |
||||
* Memory Type: DDR3 |
||||
* Additional Latancy for PLL: 1 Cycle |
||||
*/ |
||||
ldr r1, =0x00312640 |
||||
str r1, [r0, #DMC_MEMCONTROL] |
||||
|
||||
/* |
||||
* Memory Configuration Chip 0 |
||||
* Address Mapping: Interleaved |
||||
* Number of Column address Bits: 10 bits |
||||
* Number of Rows Address Bits: 14 |
||||
* Number of Banks: 8 |
||||
*/ |
||||
ldr r1, =0x20e01323 |
||||
str r1, [r0, #DMC_MEMCONFIG0] |
||||
|
||||
/* |
||||
* Memory Configuration Chip 1 |
||||
* Address Mapping: Interleaved |
||||
* Number of Column address Bits: 10 bits |
||||
* Number of Rows Address Bits: 14 |
||||
* Number of Banks: 8 |
||||
*/ |
||||
ldr r1, =0x40e01323 |
||||
str r1, [r0, #DMC_MEMCONFIG1] |
||||
|
||||
/* Config Precharge Policy */ |
||||
ldr r1, =0xff000000 |
||||
str r1, [r0, #DMC_PRECHCONFIG] |
||||
|
||||
/* |
||||
* TimingAref, TimingRow, TimingData, TimingPower Setting: |
||||
* Values as per Memory AC Parameters |
||||
*/ |
||||
ldr r1, =0x000000BB |
||||
str r1, [r0, #DMC_TIMINGAREF] |
||||
ldr r1, =0x4046654f |
||||
str r1, [r0, #DMC_TIMINGROW] |
||||
ldr r1, =0x46400506 |
||||
str r1, [r0, #DMC_TIMINGDATA] |
||||
ldr r1, =0x52000A3C |
||||
str r1, [r0, #DMC_TIMINGPOWER] |
||||
|
||||
/* Chip0: NOP Command: Assert and Hold CKE to high level */ |
||||
ldr r1, =0x07000000 |
||||
str r1, [r0, #DMC_DIRECTCMD] |
||||
|
||||
/* Wait ?us*/ |
||||
mov r2, #0x100000 |
||||
2: subs r2, r2, #1 |
||||
bne 2b |
||||
|
||||
/* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */ |
||||
ldr r1, =0x00020000 |
||||
str r1, [r0, #DMC_DIRECTCMD] |
||||
ldr r1, =0x00030000 |
||||
str r1, [r0, #DMC_DIRECTCMD] |
||||
ldr r1, =0x00010002 |
||||
str r1, [r0, #DMC_DIRECTCMD] |
||||
ldr r1, =0x00000328 |
||||
str r1, [r0, #DMC_DIRECTCMD] |
||||
|
||||
/* Wait ?us*/ |
||||
mov r2, #0x100000 |
||||
3: subs r2, r2, #1 |
||||
bne 3b |
||||
|
||||
/* Chip 0: ZQINIT */ |
||||
ldr r1, =0x0a000000 |
||||
str r1, [r0, #DMC_DIRECTCMD] |
||||
|
||||
/* Wait ?us*/ |
||||
mov r2, #0x100000 |
||||
4: subs r2, r2, #1 |
||||
bne 4b |
||||
|
||||
/* Chip1: NOP Command: Assert and Hold CKE to high level */ |
||||
ldr r1, =0x07100000 |
||||
str r1, [r0, #DMC_DIRECTCMD] |
||||
|
||||
/* Wait ?us*/ |
||||
mov r2, #0x100000 |
||||
5: subs r2, r2, #1 |
||||
bne 5b |
||||
|
||||
/* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */ |
||||
ldr r1, =0x00120000 |
||||
str r1, [r0, #DMC_DIRECTCMD] |
||||
ldr r1, =0x00130000 |
||||
str r1, [r0, #DMC_DIRECTCMD] |
||||
ldr r1, =0x00110002 |
||||
str r1, [r0, #DMC_DIRECTCMD] |
||||
ldr r1, =0x00100328 |
||||
str r1, [r0, #DMC_DIRECTCMD] |
||||
|
||||
/* Wait ?us*/ |
||||
mov r2, #0x100000 |
||||
6: subs r2, r2, #1 |
||||
bne 6b |
||||
|
||||
/* Chip1: ZQINIT */ |
||||
ldr r1, =0x0a100000 |
||||
str r1, [r0, #DMC_DIRECTCMD] |
||||
|
||||
/* Wait ?us*/ |
||||
mov r2, #0x100000 |
||||
7: subs r2, r2, #1 |
||||
bne 7b |
||||
|
||||
ldr r1, =0xe000008e |
||||
str r1, [r0, #DMC_PHYCONTROL1] |
||||
ldr r1, =0xe0000086 |
||||
str r1, [r0, #DMC_PHYCONTROL1] |
||||
|
||||
/* Wait ?us*/ |
||||
mov r2, #0x100000 |
||||
8: subs r2, r2, #1 |
||||
bne 8b |
||||
|
||||
/* turn on DREX0, DREX1 */ |
||||
ldr r0, =EXYNOS4_DMC0_BASE |
||||
ldr r1, =0x0FFF303a |
||||
str r1, [r0, #DMC_CONCONTROL] |
||||
|
||||
ldr r0, =EXYNOS4_DMC1_BASE |
||||
ldr r1, =0x0FFF303a |
||||
str r1, [r0, #DMC_CONCONTROL] |
||||
|
||||
mov pc, lr |
@ -1,58 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2011 Samsung Electronics |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include<common.h> |
||||
#include<config.h> |
||||
|
||||
/*
|
||||
* Copy U-boot from mmc to RAM: |
||||
* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains |
||||
* Pointer to API (Data transfer from mmc to ram) |
||||
*/ |
||||
void copy_uboot_to_ram(void) |
||||
{ |
||||
u32 (*copy_bl2)(u32, u32, u32) = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR; |
||||
|
||||
copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); |
||||
} |
||||
|
||||
void board_init_f(unsigned long bootflag) |
||||
{ |
||||
__attribute__((noreturn)) void (*uboot)(void); |
||||
copy_uboot_to_ram(); |
||||
|
||||
/* Jump to U-Boot image */ |
||||
uboot = (void *)CONFIG_SYS_TEXT_BASE; |
||||
(*uboot)(); |
||||
/* Never returns Here */ |
||||
} |
||||
|
||||
/* Place Holders */ |
||||
void board_init_r(gd_t *id, ulong dest_addr) |
||||
{ |
||||
/* Function attribute is no-return */ |
||||
/* This Function never executes */ |
||||
while (1) |
||||
; |
||||
} |
||||
|
||||
void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {} |
@ -1,414 +0,0 @@ |
||||
/* |
||||
* Lowlevel setup for SMDKV310 board based on EXYNOS4210 |
||||
* |
||||
* Copyright (C) 2011 Samsung Electronics |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <version.h> |
||||
#include <asm/arch/cpu.h> |
||||
|
||||
/* |
||||
* Register usages: |
||||
* |
||||
* r5 has zero always |
||||
* r7 has GPIO part1 base 0x11400000 |
||||
* r6 has GPIO part2 base 0x11000000 |
||||
*/ |
||||
|
||||
#define MEM_DLLl_ON |
||||
|
||||
_TEXT_BASE: |
||||
.word CONFIG_SYS_TEXT_BASE
|
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init: |
||||
push {lr} |
||||
|
||||
/* r5 has always zero */ |
||||
mov r5, #0 |
||||
ldr r7, =EXYNOS4_GPIO_PART1_BASE |
||||
ldr r6, =EXYNOS4_GPIO_PART2_BASE |
||||
|
||||
/* check reset status */ |
||||
ldr r0, =(EXYNOS4_POWER_BASE + 0x81C) @ INFORM7
|
||||
ldr r1, [r0] |
||||
|
||||
/* AFTR wakeup reset */ |
||||
ldr r2, =S5P_CHECK_DIDLE |
||||
cmp r1, r2 |
||||
beq exit_wakeup |
||||
|
||||
/* Sleep wakeup reset */ |
||||
ldr r2, =S5P_CHECK_SLEEP |
||||
cmp r1, r2 |
||||
beq wakeup_reset |
||||
|
||||
/* |
||||
* If U-boot is already running in ram, no need to relocate U-Boot. |
||||
* Memory controller must be configured before relocating U-Boot |
||||
* in ram. |
||||
*/ |
||||
ldr r0, =0x00ffffff /* r0 <- Mask Bits*/ |
||||
bic r1, pc, r0 /* pc <- current addr of code */ |
||||
/* r1 <- unmasked bits of pc */ |
||||
|
||||
ldr r2, _TEXT_BASE /* r2 <- original base addr in ram */ |
||||
bic r2, r2, r0 /* r2 <- unmasked bits of r2*/ |
||||
cmp r1, r2 /* compare r1, r2 */ |
||||
beq 1f /* r0 == r1 then skip sdram init */ |
||||
|
||||
/* init system clock */ |
||||
bl system_clock_init |
||||
|
||||
/* Memory initialize */ |
||||
bl mem_ctrl_asm_init |
||||
|
||||
1: |
||||
/* for UART */ |
||||
bl uart_asm_init |
||||
bl arch_cpu_init |
||||
bl tzpc_init |
||||
pop {pc} |
||||
|
||||
wakeup_reset: |
||||
bl system_clock_init |
||||
bl mem_ctrl_asm_init |
||||
bl arch_cpu_init |
||||
bl tzpc_init |
||||
|
||||
exit_wakeup: |
||||
/* Load return address and jump to kernel */ |
||||
ldr r0, =(EXYNOS4_POWER_BASE + 0x800) @ INFORM0
|
||||
|
||||
/* r1 = physical address of exynos4210_cpu_resume function */ |
||||
ldr r1, [r0] |
||||
|
||||
/* Jump to kernel*/ |
||||
mov pc, r1 |
||||
nop |
||||
nop |
||||
|
||||
/* |
||||
* system_clock_init: Initialize core clock and bus clock. |
||||
* void system_clock_init(void) |
||||
*/ |
||||
system_clock_init: |
||||
push {lr} |
||||
ldr r0, =EXYNOS4_CLOCK_BASE |
||||
|
||||
/* APLL(1), MPLL(1), CORE(0), HPM(0) */ |
||||
ldr r1, =0x0101 |
||||
ldr r2, =0x14200 @CLK_SRC_CPU
|
||||
str r1, [r0, r2] |
||||
|
||||
/* wait ?us */ |
||||
mov r1, #0x10000 |
||||
2: subs r1, r1, #1 |
||||
bne 2b |
||||
|
||||
ldr r1, =0x00 |
||||
ldr r2, =0x0C210 @CLK_SRC_TOP0
|
||||
str r1, [r0, r2] |
||||
|
||||
ldr r1, =0x00 |
||||
ldr r2, =0x0C214 @CLK_SRC_TOP1_OFFSET
|
||||
str r1, [r0, r2] |
||||
|
||||
/* DMC */ |
||||
ldr r1, =0x00 |
||||
ldr r2, =0x10200 @CLK_SRC_DMC_OFFSET
|
||||
str r1, [r0, r2] |
||||
|
||||
/*CLK_SRC_LEFTBUS */ |
||||
ldr r1, =0x00 |
||||
ldr r2, =0x04200 @CLK_SRC_LEFTBUS_OFFSET
|
||||
str r1, [r0, r2] |
||||
|
||||
/*CLK_SRC_RIGHTBUS */ |
||||
ldr r1, =0x00 |
||||
ldr r2, =0x08200 @CLK_SRC_RIGHTBUS_OFFSET
|
||||
str r1, [r0, r2] |
||||
|
||||
/* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */ |
||||
ldr r1, =0x066666 |
||||
ldr r2, =0x0C240 @ CLK_SRC_FSYS
|
||||
str r1, [r0, r2] |
||||
|
||||
/* UART[0:4], PWM: SCLKMPLL(6) */ |
||||
ldr r1, =0x06666666 |
||||
ldr r2, =0x0C250 @CLK_SRC_PERIL0_OFFSET
|
||||
str r1, [r0, r2] |
||||
|
||||
/* wait ?us */ |
||||
mov r1, #0x10000 |
||||
3: subs r1, r1, #1 |
||||
bne 3b |
||||
|
||||
/* |
||||
* CLK_DIV_CPU0: |
||||
* |
||||
* PCLK_DBG_RATIO[20] 0x1 |
||||
* ATB_RATIO[16] 0x3 |
||||
* PERIPH_RATIO[12] 0x3 |
||||
* COREM1_RATIO[8] 0x7 |
||||
* COREM0_RATIO[4] 0x3 |
||||
*/ |
||||
ldr r1, =0x0133730 |
||||
ldr r2, =0x14500 @CLK_DIV_CPU0_OFFSET
|
||||
str r1, [r0, r2] |
||||
|
||||
/* CLK_DIV_CPU1: COPY_RATIO [0] 0x3 */ |
||||
ldr r1, =0x03 |
||||
ldr r2, =0x14504 @CLK_DIV_CPU1_OFFSET
|
||||
str r1, [r0, r2] |
||||
|
||||
/* |
||||
* CLK_DIV_DMC0: |
||||
* |
||||
* CORE_TIMERS_RATIO[28] 0x1 |
||||
* COPY2_RATIO[24] 0x3 |
||||
* DMCP_RATIO[20] 0x1 |
||||
* DMCD_RATIO[16] 0x1 |
||||
* DMC_RATIO[12] 0x1 |
||||
* DPHY_RATIO[8] 0x1 |
||||
* ACP_PCLK_RATIO[4] 0x1 |
||||
* ACP_RATIO[0] 0x3 |
||||
*/ |
||||
ldr r1, =0x13111113 |
||||
ldr r2, =0x010500 @CLK_DIV_DMC0_OFFSET
|
||||
str r1, [r0, r2] |
||||
|
||||
/* |
||||
* CLK_DIV_DMC1: |
||||
* |
||||
* DPM_RATIO[24] 0x1 |
||||
* DVSEM_RATIO[16] 0x1 |
||||
* PWI_RATIO[8] 0x1 |
||||
*/ |
||||
ldr r1, =0x01010100 |
||||
ldr r2, =0x010504 @CLK_DIV_DMC1_OFFSET
|
||||
str r1, [r0, r2] |
||||
|
||||
/* |
||||
* CLK_DIV_LEFRBUS: |
||||
* |
||||
* GPL_RATIO[4] 0x1 |
||||
* GDL_RATIO[0] 0x3 |
||||
*/ |
||||
ldr r1, =0x013 |
||||
ldr r2, =0x04500 @CLK_DIV_LEFTBUS_OFFSET
|
||||
str r1, [r0, r2] |
||||
|
||||
/* |
||||
* CLK_DIV_RIGHTBUS: |
||||
* |
||||
* GPR_RATIO[4] 0x1 |
||||
* GDR_RATIO[0] 0x3 |
||||
*/ |
||||
ldr r1, =0x013 |
||||
ldr r2, =0x08500 @CLK_DIV_RIGHTBUS_OFFSET
|
||||
str r1, [r0, r2] |
||||
|
||||
/* |
||||
* CLK_DIV_TOP: |
||||
* |
||||
* ONENAND_RATIO[16] 0x0 |
||||
* ACLK_133_RATIO[12] 0x5 |
||||
* ACLK_160_RATIO[8] 0x4 |
||||
* ACLK_100_RATIO[4] 0x7 |
||||
* ACLK_200_RATIO[0] 0x3 |
||||
*/ |
||||
ldr r1, =0x05473 |
||||
ldr r2, =0x0C510 @CLK_DIV_TOP_OFFSET
|
||||
str r1, [r0, r2] |
||||
|
||||
/* MMC[0:1] */ |
||||
ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */ |
||||
ldr r2, =0x0C544 @ CLK_DIV_FSYS1
|
||||
str r1, [r0, r2] |
||||
|
||||
/* MMC[2:3] */ |
||||
ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */ |
||||
ldr r2, =0x0C548 @ CLK_DIV_FSYS2
|
||||
str r1, [r0, r2] |
||||
|
||||
/* MMC4 */ |
||||
ldr r1, =0x000f /* 800(MPLL) / (15 + 1) */ |
||||
ldr r2, =0x0C54C @ CLK_DIV_FSYS3
|
||||
str r1, [r0, r2] |
||||
|
||||
/* wait ?us */ |
||||
mov r1, #0x10000 |
||||
4: subs r1, r1, #1 |
||||
bne 4b |
||||
|
||||
/* |
||||
* CLK_DIV_PERIL0: |
||||
* |
||||
* UART5_RATIO[20] 8 |
||||
* UART4_RATIO[16] 8 |
||||
* UART3_RATIO[12] 8 |
||||
* UART2_RATIO[8] 8 |
||||
* UART1_RATIO[4] 8 |
||||
* UART0_RATIO[0] 8 |
||||
*/ |
||||
ldr r1, =0x774777 |
||||
ldr r2, =0x0C550 @CLK_DIV_PERIL0_OFFSET
|
||||
str r1, [r0, r2] |
||||
|
||||
/* SLIMBUS: ???, PWM */ |
||||
ldr r1, =0x8 |
||||
ldr r2, =0x0C55C @ CLK_DIV_PERIL3
|
||||
str r1, [r0, r2] |
||||
|
||||
/* Set PLL locktime */ |
||||
ldr r1, =0x01C20 |
||||
ldr r2, =0x014000 @APLL_LOCK_OFFSET
|
||||
str r1, [r0, r2] |
||||
ldr r1, =0x01C20 |
||||
ldr r2, =0x014008 @MPLL_LOCK_OFFSET
|
||||
str r1, [r0, r2] |
||||
ldr r1, =0x01C20 |
||||
ldr r2, =0x0C010 @EPLL_LOCK_OFFSET
|
||||
str r1, [r0, r2] |
||||
ldr r1, =0x01C20 |
||||
ldr r2, =0x0C020 @VPLL_LOCK_OFFSET
|
||||
str r1, [r0, r2] |
||||
|
||||
/* |
||||
* APLL_CON1: |
||||
* |
||||
* APLL_AFC_ENB[31] 0x1 |
||||
* APLL_AFC[0] 0xC |
||||
*/ |
||||
ldr r1, =0x8000000C |
||||
ldr r2, =0x014104 @APLL_CON1_OFFSET
|
||||
str r1, [r0, r2] |
||||
|
||||
/* |
||||
* APLL_CON0: |
||||
* |
||||
* APLL_MDIV[16] 0xFA |
||||
* APLL_PDIV[8] 0x6 |
||||
* APLL_SDIV[0] 0x1 |
||||
*/ |
||||
ldr r1, =0x80FA0601 |
||||
ldr r2, =0x014100 @APLL_CON0_OFFSET
|
||||
str r1, [r0, r2] |
||||
|
||||
/* |
||||
* MPLL_CON1: |
||||
* |
||||
* MPLL_AFC_ENB[31] 0x1 |
||||
* MPLL_AFC[0] 0x1C |
||||
*/ |
||||
ldr r1, =0x0000001C |
||||
ldr r2, =0x01410C @MPLL_CON1_OFFSET
|
||||
str r1, [r0, r2] |
||||
|
||||
/* |
||||
* MPLL_CON0: |
||||
* |
||||
* MPLL_MDIV[16] 0xC8 |
||||
* MPLL_PDIV[8] 0x6 |
||||
* MPLL_SDIV[0] 0x1 |
||||
*/ |
||||
ldr r1, =0x80C80601 |
||||
ldr r2, =0x014108 @MPLL_CON0_OFFSET
|
||||
str r1, [r0, r2] |
||||
|
||||
/* EPLL */ |
||||
ldr r1, =0x0 |
||||
ldr r2, =0x0C114 @EPLL_CON1_OFFSET
|
||||
str r1, [r0, r2] |
||||
|
||||
/* |
||||
* EPLL_CON0: |
||||
* |
||||
* EPLL_MDIV[16] 0x30 |
||||
* EPLL_PDIV[8] 0x3 |
||||
* EPLL_SDIV[0] 0x2 |
||||
*/ |
||||
ldr r1, =0x80300302 |
||||
ldr r2, =0x0C110 @EPLL_CON0_OFFSET
|
||||
str r1, [r0, r2] |
||||
|
||||
/* |
||||
* VPLL_CON1: |
||||
* |
||||
* VPLL_MRR[24] 0x11 |
||||
* VPLL_MFR[16] 0x0 |
||||
* VPLL_K[0] 0x400 |
||||
*/ |
||||
ldr r1, =0x11000400 |
||||
ldr r2, =0x0C124 @VPLL_CON1_OFFSET
|
||||
str r1, [r0, r2] |
||||
|
||||
/* |
||||
* VPLL_CON0: |
||||
* |
||||
* VPLL_MDIV[16] 0x35 |
||||
* VPLL_PDIV[8] 0x3 |
||||
* VPLL_SDIV[0] 0x2 |
||||
*/ |
||||
ldr r1, =0x80350302 |
||||
ldr r2, =0x0C120 @VPLL_CON0_OFFSET
|
||||
str r1, [r0, r2] |
||||
|
||||
/* wait ?us */ |
||||
mov r1, #0x30000 |
||||
3: subs r1, r1, #1 |
||||
bne 3b |
||||
|
||||
pop {pc} |
||||
/* |
||||
* uart_asm_init: Initialize UART in asm mode, 115200bps fixed. |
||||
* void uart_asm_init(void) |
||||
*/ |
||||
.globl uart_asm_init
|
||||
uart_asm_init: |
||||
|
||||
/* setup UART0-UART3 GPIOs (part1) */ |
||||
mov r0, r7 |
||||
ldr r1, =0x22222222 |
||||
str r1, [r0, #0x00] @ EXYNOS4_GPIO_A0_OFFSET
|
||||
ldr r1, =0x00222222 |
||||
str r1, [r0, #0x20] @ EXYNOS4_GPIO_A1_OFFSET
|
||||
|
||||
ldr r0, =EXYNOS4_UART_BASE |
||||
add r0, r0, #EXYNOS4_DEFAULT_UART_OFFSET |
||||
|
||||
ldr r1, =0x3C5 |
||||
str r1, [r0, #0x4] |
||||
ldr r1, =0x111 |
||||
str r1, [r0, #0x8] |
||||
ldr r1, =0x3 |
||||
str r1, [r0, #0x0] |
||||
ldr r1, =0x35 |
||||
str r1, [r0, #0x28] |
||||
ldr r1, =0x4 |
||||
str r1, [r0, #0x2c] |
||||
|
||||
mov pc, lr |
||||
nop |
||||
nop |
||||
nop |
@ -1,365 +0,0 @@ |
||||
/* |
||||
* Memory setup for SMDKV310 board based on EXYNOS4210 |
||||
* |
||||
* Copyright (C) 2011 Samsung Electronics |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
|
||||
#define SET_MIU |
||||
|
||||
#define MEM_DLL |
||||
|
||||
#ifdef CONFIG_CLK_800_330_165 |
||||
#define DRAM_CLK_330 |
||||
#endif |
||||
#ifdef CONFIG_CLK_1000_200_200 |
||||
#define DRAM_CLK_200 |
||||
#endif |
||||
#ifdef CONFIG_CLK_1000_330_165 |
||||
#define DRAM_CLK_330 |
||||
#endif |
||||
#ifdef CONFIG_CLK_1000_400_200 |
||||
#define DRAM_CLK_400 |
||||
#endif |
||||
|
||||
.globl mem_ctrl_asm_init
|
||||
mem_ctrl_asm_init: |
||||
|
||||
/* |
||||
* Async bridge configuration at CPU_core: |
||||
* 1: half_sync |
||||
* 0: full_sync |
||||
*/ |
||||
ldr r0, =0x10010350 |
||||
mov r1, #1 |
||||
str r1, [r0] |
||||
|
||||
#ifdef SET_MIU |
||||
ldr r0, =EXYNOS4_MIU_BASE @0x10600000
|
||||
#ifdef CONFIG_MIU_1BIT_INTERLEAVED |
||||
ldr r1, =0x0000000c |
||||
str r1, [r0, #0x400] @MIU_INTLV_CONFIG
|
||||
ldr r1, =0x40000000 |
||||
str r1, [r0, #0x808] @MIU_INTLV_START_ADDR
|
||||
ldr r1, =0xbfffffff |
||||
str r1, [r0, #0x810] @MIU_INTLV_END_ADDR
|
||||
ldr r1, =0x00000001 |
||||
str r1, [r0, #0x800] @MIU_MAPPING_UPDATE
|
||||
#endif |
||||
#ifdef CONFIG_MIU_2BIT_INTERLEAVED |
||||
ldr r1, =0x2000150c |
||||
str r1, [r0, #0x400] @MIU_INTLV_CONFIG
|
||||
ldr r1, =0x40000000 |
||||
str r1, [r0, #0x808] @MIU_INTLV_START_ADDR
|
||||
ldr r1, =0xbfffffff |
||||
str r1, [r0, #0x810] @MIU_INTLV_END_ADDR
|
||||
ldr r1, =0x00000001 |
||||
str r1, [r0, #0x800] @MIU_MAPPING_UPDATE
|
||||
#endif |
||||
#ifdef CONFIG_MIU_LINEAR |
||||
ldr r1, =0x40000000 |
||||
str r1, [r0, #0x818] @MIU_SINGLE_MAPPING0_START_ADDR
|
||||
ldr r1, =0x7fffffff |
||||
str r1, [r0, #0x820] @MIU_SINGLE_MAPPING0_END_ADDR
|
||||
ldr r1, =0x80000000 |
||||
str r1, [r0, #0x828] @MIU_SINGLE_MAPPING1_START_ADDR
|
||||
ldr r1, =0xbfffffff |
||||
str r1, [r0, #0x830] @MIU_SINGLE_MAPPING1_END_ADDR]
|
||||
ldr r1, =0x00000006 |
||||
str r1, [r0, #0x800] @MIU_MAPPING_UPDATE
|
||||
#endif |
||||
#endif |
||||
/* DREX0 */ |
||||
ldr r0, =EXYNOS4_DMC0_BASE @0x10400000
|
||||
|
||||
ldr r1, =0xe0000086 |
||||
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
|
||||
|
||||
ldr r1, =0xE3855703 |
||||
str r1, [r0, #0x44] @DMC_PHYZQCONTROL
|
||||
|
||||
mov r2, #0x100000 |
||||
1: subs r2, r2, #1 |
||||
bne 1b |
||||
|
||||
ldr r1, =0xe000008e |
||||
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
|
||||
ldr r1, =0xe0000086 |
||||
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
|
||||
|
||||
ldr r1, =0x71101008 |
||||
str r1, [r0, #0x18] @DMC_PHYCONTROL0
|
||||
ldr r1, =0x7110100A |
||||
str r1, [r0, #0x18] @DMC_PHYCONTROL0
|
||||
ldr r1, =0xe0000086 |
||||
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
|
||||
ldr r1, =0x7110100B |
||||
str r1, [r0, #0x18] @DMC_PHYCONTROL0
|
||||
|
||||
ldr r1, =0x00000000 |
||||
str r1, [r0, #0x20] @DMC_PHYCONTROL2
|
||||
|
||||
ldr r1, =0x0FFF301a |
||||
str r1, [r0, #0x00] @DMC_CONCONTROL
|
||||
ldr r1, =0x00312640 |
||||
str r1, [r0, #0x04] @DMC_MEMCONTROL]
|
||||
|
||||
#ifdef CONFIG_MIU_LINEAR |
||||
ldr r1, =0x40e01323 |
||||
str r1, [r0, #0x08] @DMC_MEMCONFIG0
|
||||
ldr r1, =0x60e01323 |
||||
str r1, [r0, #0x0C] @DMC_MEMCONFIG1
|
||||
#else /* @MIU_1BIT_INTERLEAVED | MIU_2BIT_INTERLEAVED */
|
||||
ldr r1, =0x20e01323 |
||||
str r1, [r0, #0x08] @DMC_MEMCONFIG0
|
||||
ldr r1, =0x40e01323 |
||||
str r1, [r0, #0x0C] @DMC_MEMCONFIG1
|
||||
#endif |
||||
|
||||
ldr r1, =0xff000000 |
||||
str r1, [r0, #0x14] @DMC_PRECHCONFIG
|
||||
|
||||
ldr r1, =0x000000BC |
||||
str r1, [r0, #0x30] @DMC_TIMINGAREF
|
||||
|
||||
#ifdef DRAM_CLK_330 |
||||
ldr r1, =0x3545548d |
||||
str r1, [r0, #0x34] @DMC_TIMINGROW
|
||||
ldr r1, =0x45430506 |
||||
str r1, [r0, #0x38] @DMC_TIMINGDATA
|
||||
ldr r1, =0x4439033c |
||||
str r1, [r0, #0x3C] @DMC_TIMINGPOWER
|
||||
#endif |
||||
#ifdef DRAM_CLK_400 |
||||
ldr r1, =0x4046654f |
||||
str r1, [r0, #0x34] @DMC_TIMINGROW
|
||||
ldr r1, =0x56500506 |
||||
str r1, [r0, #0x38] @DMC_TIMINGDATA
|
||||
ldr r1, =0x5444033d |
||||
str r1, [r0, #0x3C] @DMC_TIMINGPOWER
|
||||
#endif |
||||
ldr r1, =0x07000000 |
||||
str r1, [r0, #0x10] @DMC_DIRECTCMD
|
||||
|
||||
mov r2, #0x100000 |
||||
2: subs r2, r2, #1 |
||||
bne 2b |
||||
|
||||
ldr r1, =0x00020000 |
||||
str r1, [r0, #0x10] @DMC_DIRECTCMD
|
||||
ldr r1, =0x00030000 |
||||
str r1, [r0, #0x10] @DMC_DIRECTCMD
|
||||
ldr r1, =0x00010002 |
||||
str r1, [r0, #0x10] @DMC_DIRECTCMD
|
||||
ldr r1, =0x00000328 |
||||
str r1, [r0, #0x10] @DMC_DIRECTCMD
|
||||
|
||||
mov r2, #0x100000 |
||||
3: subs r2, r2, #1 |
||||
bne 3b |
||||
|
||||
ldr r1, =0x0a000000 |
||||
str r1, [r0, #0x10] @DMC_DIRECTCMD
|
||||
|
||||
mov r2, #0x100000 |
||||
4: subs r2, r2, #1 |
||||
bne 4b |
||||
|
||||
ldr r1, =0x07100000 |
||||
str r1, [r0, #0x10] @DMC_DIRECTCMD
|
||||
|
||||
mov r2, #0x100000 |
||||
5: subs r2, r2, #1 |
||||
bne 5b |
||||
|
||||
ldr r1, =0x00120000 |
||||
str r1, [r0, #0x10] @DMC_DIRECTCMD
|
||||
ldr r1, =0x00130000 |
||||
str r1, [r0, #0x10] @DMC_DIRECTCMD
|
||||
ldr r1, =0x00110002 |
||||
str r1, [r0, #0x10] @DMC_DIRECTCMD
|
||||
ldr r1, =0x00100328 |
||||
str r1, [r0, #0x10] @DMC_DIRECTCMD
|
||||
|
||||
mov r2, #0x100000 |
||||
6: subs r2, r2, #1 |
||||
bne 6b |
||||
|
||||
ldr r1, =0x0a100000 |
||||
str r1, [r0, #0x10] @DMC_DIRECTCMD
|
||||
|
||||
mov r2, #0x100000 |
||||
7: subs r2, r2, #1 |
||||
bne 7b |
||||
|
||||
ldr r1, =0xe000008e |
||||
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
|
||||
ldr r1, =0xe0000086 |
||||
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
|
||||
|
||||
mov r2, #0x100000 |
||||
8: subs r2, r2, #1 |
||||
bne 8b |
||||
|
||||
/* DREX1 */ |
||||
ldr r0, =EXYNOS4_DMC1_BASE @0x10410000
|
||||
|
||||
ldr r1, =0xe0000086 |
||||
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
|
||||
|
||||
ldr r1, =0xE3855703 |
||||
str r1, [r0, #0x44] @DMC_PHYZQCONTROL
|
||||
|
||||
mov r2, #0x100000 |
||||
1: subs r2, r2, #1 |
||||
bne 1b |
||||
|
||||
ldr r1, =0xe000008e |
||||
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
|
||||
ldr r1, =0xe0000086 |
||||
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
|
||||
|
||||
ldr r1, =0x71101008 |
||||
str r1, [r0, #0x18] @DMC_PHYCONTROL0
|
||||
ldr r1, =0x7110100A |
||||
str r1, [r0, #0x18] @DMC_PHYCONTROL0
|
||||
ldr r1, =0xe0000086 |
||||
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
|
||||
ldr r1, =0x7110100B |
||||
str r1, [r0, #0x18] @DMC_PHYCONTROL0
|
||||
|
||||
ldr r1, =0x00000000 |
||||
str r1, [r0, #0x20] @DMC_PHYCONTROL2
|
||||
|
||||
ldr r1, =0x0FFF301a |
||||
str r1, [r0, #0x00] @DMC_CONCONTROL
|
||||
ldr r1, =0x00312640 |
||||
str r1, [r0, #0x04] @DMC_MEMCONTROL]
|
||||
|
||||
#ifdef CONFIG_MIU_LINEAR |
||||
ldr r1, =0x40e01323 |
||||
str r1, [r0, #0x08] @DMC_MEMCONFIG0
|
||||
ldr r1, =0x60e01323 |
||||
str r1, [r0, #0x0C] @DMC_MEMCONFIG1
|
||||
#else /* @MIU_1BIT_INTERLEAVED | MIU_2BIT_INTERLEAVED */
|
||||
ldr r1, =0x20e01323 |
||||
str r1, [r0, #0x08] @DMC_MEMCONFIG0
|
||||
ldr r1, =0x40e01323 |
||||
str r1, [r0, #0x0C] @DMC_MEMCONFIG1
|
||||
#endif |
||||
|
||||
ldr r1, =0xff000000 |
||||
str r1, [r0, #0x14] @DMC_PRECHCONFIG
|
||||
|
||||
ldr r1, =0x000000BC |
||||
str r1, [r0, #0x30] @DMC_TIMINGAREF
|
||||
|
||||
#ifdef DRAM_CLK_330 |
||||
ldr r1, =0x3545548d |
||||
str r1, [r0, #0x34] @DMC_TIMINGROW
|
||||
ldr r1, =0x45430506 |
||||
str r1, [r0, #0x38] @DMC_TIMINGDATA
|
||||
ldr r1, =0x4439033c |
||||
str r1, [r0, #0x3C] @DMC_TIMINGPOWER
|
||||
#endif |
||||
#ifdef DRAM_CLK_400 |
||||
ldr r1, =0x4046654f |
||||
str r1, [r0, #0x34] @DMC_TIMINGROW
|
||||
ldr r1, =0x56500506 |
||||
str r1, [r0, #0x38] @DMC_TIMINGDATA
|
||||
ldr r1, =0x5444033d |
||||
str r1, [r0, #0x3C] @DMC_TIMINGPOWER
|
||||
#endif |
||||
|
||||
ldr r1, =0x07000000 |
||||
str r1, [r0, #0x10] @DMC_DIRECTCMD
|
||||
|
||||
mov r2, #0x100000 |
||||
2: subs r2, r2, #1 |
||||
bne 2b |
||||
|
||||
ldr r1, =0x00020000 |
||||
str r1, [r0, #0x10] @DMC_DIRECTCMD
|
||||
ldr r1, =0x00030000 |
||||
str r1, [r0, #0x10] @DMC_DIRECTCMD
|
||||
ldr r1, =0x00010002 |
||||
str r1, [r0, #0x10] @DMC_DIRECTCMD
|
||||
ldr r1, =0x00000328 |
||||
str r1, [r0, #0x10] @DMC_DIRECTCMD
|
||||
|
||||
mov r2, #0x100000 |
||||
3: subs r2, r2, #1 |
||||
bne 3b |
||||
|
||||
ldr r1, =0x0a000000 |
||||
str r1, [r0, #0x10] @DMC_DIRECTCMD
|
||||
|
||||
mov r2, #0x100000 |
||||
4: subs r2, r2, #1 |
||||
bne 4b |
||||
|
||||
ldr r1, =0x07100000 |
||||
str r1, [r0, #0x10] @DMC_DIRECTCMD
|
||||
|
||||
mov r2, #0x100000 |
||||
5: subs r2, r2, #1 |
||||
bne 5b |
||||
|
||||
ldr r1, =0x00120000 |
||||
str r1, [r0, #0x10] @DMC_DIRECTCMD
|
||||
ldr r1, =0x00130000 |
||||
str r1, [r0, #0x10] @DMC_DIRECTCMD
|
||||
ldr r1, =0x00110002 |
||||
str r1, [r0, #0x10] @DMC_DIRECTCMD
|
||||
ldr r1, =0x00100328 |
||||
str r1, [r0, #0x10] @DMC_DIRECTCMD
|
||||
|
||||
mov r2, #0x100000 |
||||
6: subs r2, r2, #1 |
||||
bne 6b |
||||
|
||||
ldr r1, =0x0a100000 |
||||
str r1, [r0, #0x10] @DMC_DIRECTCMD
|
||||
|
||||
mov r2, #0x100000 |
||||
7: subs r2, r2, #1 |
||||
bne 7b |
||||
|
||||
ldr r1, =0xe000008e |
||||
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
|
||||
ldr r1, =0xe0000086 |
||||
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
|
||||
|
||||
mov r2, #0x100000 |
||||
8: subs r2, r2, #1 |
||||
bne 8b |
||||
|
||||
/* turn on DREX0, DREX1 */ |
||||
ldr r0, =0x10400000 @APB_DMC_0_BASE
|
||||
ldr r1, =0x0FFF303a |
||||
str r1, [r0, #0x00] @DMC_CONCONTROL
|
||||
|
||||
ldr r0, =0x10410000 @APB_DMC_1_BASE
|
||||
ldr r1, =0x0FFF303a |
||||
str r1, [r0, #0x00] @DMC_CONCONTROL
|
||||
|
||||
mov pc, lr |
@ -1,60 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2011 Samsung Electronics |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include<common.h> |
||||
#include<config.h> |
||||
|
||||
/*
|
||||
* Copy U-boot from mmc to RAM: |
||||
* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains |
||||
* API (Data transfer from mmc to ram) |
||||
*/ |
||||
void copy_uboot_to_ram(void) |
||||
{ |
||||
u32 (*copy_bl2)(u32, u32, u32) = (void *)COPY_BL2_FNPTR_ADDR; |
||||
|
||||
copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); |
||||
} |
||||
|
||||
void board_init_f(unsigned long bootflag) |
||||
{ |
||||
__attribute__((noreturn)) void (*uboot)(void); |
||||
copy_uboot_to_ram(); |
||||
|
||||
/* Jump to U-Boot image */ |
||||
uboot = (void *)CONFIG_SYS_TEXT_BASE; |
||||
(*uboot)(); |
||||
/* Never returns Here */ |
||||
} |
||||
|
||||
/* Place Holders */ |
||||
void board_init_r(gd_t *id, ulong dest_addr) |
||||
{ |
||||
/*Function attribute is no-return*/ |
||||
/*This Function never executes*/ |
||||
while (1) |
||||
; |
||||
} |
||||
|
||||
void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) |
||||
{ |
||||
} |
Loading…
Reference in new issue