@ -187,6 +187,10 @@
* at C F G _ S D R A M _ B A S E a n d a n o t h e r 1 2 8 M B c a c h e a b l e i n s t r u c t i o n r e g i o n c o v e r i n g
* NOR f l a s h a t C F G _ F L A S H _ B A S E . D i s a b l e a l l c a c h e a b l e d a t a r e g i o n s .
* /
# if ! d e f i n e d ( C F G _ F L A S H _ B A S E )
/* If not already defined, set it to the "last" 128MByte region */
# define C F G _ F L A S H _ B A S E 0 x f80 0 0 0 0 0
# endif
# if ! d e f i n e d ( C F G _ I C A C H E _ S A C R _ V A L U E )
# define C F G _ I C A C H E _ S A C R _ V A L U E \
( PPC_ 1 2 8 M B _ S A C R _ V A L U E ( C F G _ S D R A M _ B A S E + ( 0 < < 2 0 ) ) | \
@ -486,97 +490,6 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
/* Continue from 'normal' start */
/*----------------------------------------------------------------*/
2 :
# if d e f i n e d ( C O N F I G _ N A N D _ S P L )
# if d e f i n e d ( C O N F I G _ 4 4 0 E P X ) | | d e f i n e d ( C O N F I G _ 4 4 0 G R X ) | | \
defined( C O N F I G _ 4 6 0 E X ) | | d e f i n e d ( C O N F I G _ 4 6 0 G T )
/ *
* Enable i n t e r n a l S R A M ( o n l y o n 4 4 0 E P x / G R x , 4 4 0 E P / G R h a v e n o O C M )
* /
lis r2 ,0 x7 f f f
ori r2 ,r2 ,0 x f f f f
mfdcr r1 ,i s r a m 0 _ d p c
and r1 ,r1 ,r2 / * D i s a b l e p a r i t y c h e c k * /
mtdcr i s r a m 0 _ d p c ,r1
mfdcr r1 ,i s r a m 0 _ p m e g
and r1 ,r1 ,r2 / * D i s a b l e p w r m g m t * /
mtdcr i s r a m 0 _ p m e g ,r1
# if d e f i n e d ( C O N F I G _ 4 6 0 E X ) | | d e f i n e d ( C O N F I G _ 4 6 0 G T )
lis r1 ,0 x40 0 0 / * B A S = 8 0 0 0 _ 0 0 0 0 * /
ori r1 ,r1 ,0 x45 8 0 / * 1 6 k * /
mtdcr i s r a m 0 _ s b0 c r ,r1
# endif
# endif
# if d e f i n e d ( C O N F I G _ 4 4 0 E P )
/ *
* On 4 4 0 E P w i t h n o i n t e r n a l S R A M , w e s e t u p S D R A M v e r y e a r l y
* and c o p y t h e N A N D _ S P L t o S D R A M a n d j u m p t o i t
* /
/* Clear Dcache to use as RAM */
addis r3 ,r0 ,C F G _ I N I T _ R A M _ A D D R @h
ori r3 ,r3 ,C F G _ I N I T _ R A M _ A D D R @l
addis r4 ,r0 ,C F G _ I N I T _ R A M _ E N D @h
ori r4 ,r4 ,C F G _ I N I T _ R A M _ E N D @l
rlwinm. r5 ,r4 ,0 ,2 7 ,3 1
rlwinm r5 ,r4 ,2 7 ,5 ,3 1
beq . . d _ r a n 3
addi r5 ,r5 ,0 x00 0 1
. .d_ran3 :
mtctr r5
. .d_ag3 :
dcbz r0 ,r3
addi r3 ,r3 ,3 2
bdnz . . d _ a g 3
/*----------------------------------------------------------------*/
/* Setup the stack in internal SRAM */
/*----------------------------------------------------------------*/
lis r1 ,C F G _ I N I T _ R A M _ A D D R @h
ori r1 ,r1 ,C F G _ I N I T _ S P _ O F F S E T @l
li r0 ,0
stwu r0 ,- 4 ( r1 )
stwu r0 ,- 4 ( r1 ) / * T e r m i n a t e c a l l c h a i n * /
stwu r1 ,- 8 ( r1 ) / * S a v e b a c k c h a i n a n d m o v e S P * /
lis r0 ,R E S E T _ V E C T O R @h /* Address of reset vector */
ori r0 ,r0 , R E S E T _ V E C T O R @l
stwu r1 ,- 8 ( r1 ) / * S a v e b a c k c h a i n a n d m o v e S P * /
stw r0 ,+ 1 2 ( r1 ) / * S a v e r e t u r n a d d r ( u n d e r f l o w v e c t ) * /
sync
bl e a r l y _ s d r a m _ i n i t
sync
# endif / * C O N F I G _ 4 4 0 E P * /
/ *
* Copy S P L f r o m c a c h e i n t o i n t e r n a l S R A M
* /
li r4 ,( C F G _ N A N D _ B O O T _ S P L _ S I Z E > > 2 ) - 1
mtctr r4
lis r2 ,C F G _ N A N D _ B O O T _ S P L _ S R C @h
ori r2 ,r2 ,C F G _ N A N D _ B O O T _ S P L _ S R C @l
lis r3 ,C F G _ N A N D _ B O O T _ S P L _ D S T @h
ori r3 ,r3 ,C F G _ N A N D _ B O O T _ S P L _ D S T @l
spl_loop :
lwzu r4 ,4 ( r2 )
stwu r4 ,4 ( r3 )
bdnz s p l _ l o o p
/ *
* Jump t o c o d e i n R A M
* /
bl 0 0 f
00 : mflr r10
lis r3 ,( C F G _ N A N D _ B O O T _ S P L _ S R C - C F G _ N A N D _ B O O T _ S P L _ D S T ) @h
ori r3 ,r3 ,( C F G _ N A N D _ B O O T _ S P L _ S R C - C F G _ N A N D _ B O O T _ S P L _ D S T ) @l
sub r10 ,r10 ,r3
addi r10 ,r10 ,2 8
mtlr r10
blr
start_ram :
sync
isync
# endif / * C O N F I G _ N A N D _ S P L * /
bl 3 f
b _ s t a r t
@ -831,7 +744,7 @@ _start:
stw r0 ,+ 1 2 ( r1 ) / * S a v e r e t u r n a d d r ( u n d e r f l o w v e c t ) * /
# ifdef C O N F I G _ N A N D _ S P L
bl n a n d _ b o o t / * w i l l n o t r e t u r n * /
bl n a n d _ b o o t _ c o m m o n / * w i l l n o t r e t u r n * /
# else
GET_ G O T
@ -992,12 +905,13 @@ _start:
ori r4 , r4 , C F G _ D C A C H E _ S A C R _ V A L U E @l
mtdccr r4
# if ! ( d e f i n e d ( C F G _ E B C _ P B 0 A P ) & & d e f i n e d ( C F G _ E B C _ P B 0 C R ) ) | | d e f i n e d ( C O N F I G _ 4 0 5 E X )
# if ! ( d e f i n e d ( C F G _ E B C _ P B 0 A P ) & & d e f i n e d ( C F G _ E B C _ P B 0 C R ) )
/*----------------------------------------------------------------------- */
/* Tune the speed and size for flash CS0 */
/*----------------------------------------------------------------------- */
bl e x t _ b u s _ c n t l r _ i n i t
# endif
# if ! ( d e f i n e d ( C F G _ I N I T _ D C A C H E _ C S ) | | d e f i n e d ( C F G _ T E M P _ S T A C K _ O C M ) )
/ *
* For b o a r d s t h a t d o n ' t h a v e O C M a n d c a n ' t u s e t h e d a t a c a c h e
@ -1085,38 +999,6 @@ _start:
# endif / * C O N F I G _ 4 0 5 E Z * /
# endif
# ifdef C O N F I G _ N A N D _ S P L
/ *
* Copy S P L f r o m c a c h e i n t o i n t e r n a l S R A M
* /
li r4 ,( C F G _ N A N D _ B O O T _ S P L _ S I Z E > > 2 ) - 1
mtctr r4
lis r2 ,C F G _ N A N D _ B O O T _ S P L _ S R C @h
ori r2 ,r2 ,C F G _ N A N D _ B O O T _ S P L _ S R C @l
lis r3 ,C F G _ N A N D _ B O O T _ S P L _ D S T @h
ori r3 ,r3 ,C F G _ N A N D _ B O O T _ S P L _ D S T @l
spl_loop :
lwzu r4 ,4 ( r2 )
stwu r4 ,4 ( r3 )
bdnz s p l _ l o o p
/ *
* Jump t o c o d e i n R A M
* /
bl 0 0 f
00 : mflr r10
lis r3 ,( C F G _ N A N D _ B O O T _ S P L _ S R C - C F G _ N A N D _ B O O T _ S P L _ D S T ) @h
ori r3 ,r3 ,( C F G _ N A N D _ B O O T _ S P L _ S R C - C F G _ N A N D _ B O O T _ S P L _ D S T ) @l
sub r10 ,r10 ,r3
addi r10 ,r10 ,2 8
mtlr r10
blr
start_ram :
sync
isync
# endif / * C O N F I G _ N A N D _ S P L * /
/*----------------------------------------------------------------------- */
/* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
/*----------------------------------------------------------------------- */
@ -1243,7 +1125,7 @@ start_ram:
bl s d r a m _ i n i t
# ifdef C O N F I G _ N A N D _ S P L
bl n a n d _ b o o t / * w i l l n o t r e t u r n * /
bl n a n d _ b o o t _ c o m m o n / * w i l l n o t r e t u r n * /
# else
GET_ G O T / * i n i t i a l i z e G O T a c c e s s * /
@ -2180,3 +2062,75 @@ pll_wait:
blr
function_ e p i l o g ( m f t l b1 )
# endif / * C O N F I G _ 4 4 0 * /
# if d e f i n e d ( C O N F I G _ N A N D _ S P L )
/ *
* void n a n d _ b o o t _ r e l o c a t e ( d s t , s r c , b y t e s )
*
* r3 = D e s t i n a t i o n a d d r e s s t o c o p y c o d e t o ( i n S D R A M )
* r4 = S o u r c e a d d r e s s t o c o p y c o d e f r o m
* r5 = s i z e t o c o p y i n b y t e s
* /
nand_boot_relocate :
mr r6 ,r3
mr r7 ,r4
mflr r8
/ *
* Copy S P L f r o m i c a c h e i n t o S D R A M
* /
subi r3 ,r3 ,4
subi r4 ,r4 ,4
srwi r5 ,r5 ,2
mtctr r5
. .spl_loop :
lwzu r0 ,4 ( r4 )
stwu r0 ,4 ( r3 )
bdnz . . s p l _ l o o p
/ *
* Calculate " c o r r e c t e d " l i n k r e g i s t e r , s o t h a t w e " c o n t i n u e "
* in e x e c u t i o n i n d e s t i n a t i o n r a n g e
* /
sub r3 ,r7 ,r6 / * r3 = s r c - d s t * /
sub r8 ,r8 ,r3 / * r8 = l i n k - r e g - ( s r c - d s t ) * /
mtlr r8
blr
nand_boot_common :
/ *
* First i n i t i a l i z e S D R A M . I t h a s t o b e a v a i l a b l e * b e f o r e * c a l l i n g
* nand_ b o o t ( ) .
* /
lis r3 ,C F G _ S D R A M _ B A S E @h
ori r3 ,r3 ,C F G _ S D R A M _ B A S E @l
bl i n i t d r a m
/ *
* Now c o p y t h e 4 k S P L c o d e i n t o S D R A M a n d c o n t i n u e e x e c u t i o n
* from t h e r e .
* /
lis r3 ,C F G _ N A N D _ B O O T _ S P L _ D S T @h
ori r3 ,r3 ,C F G _ N A N D _ B O O T _ S P L _ D S T @l
lis r4 ,C F G _ N A N D _ B O O T _ S P L _ S R C @h
ori r4 ,r4 ,C F G _ N A N D _ B O O T _ S P L _ S R C @l
lis r5 ,C F G _ N A N D _ B O O T _ S P L _ S I Z E @h
ori r5 ,r5 ,C F G _ N A N D _ B O O T _ S P L _ S I Z E @l
bl n a n d _ b o o t _ r e l o c a t e
/ *
* We' r e r u n n i n g f r o m S D R A M n o w ! ! !
*
* It i s n e c e s s a r y f o r 4 x x s y s t e m s t o r e l o c a t e f r o m r u n n i n g a t
* the o r i g i n a l l o c a t i o n ( 0 x f f f f f x x x ) t o s o m e w h e r e e l s e ( S D R A M
* preferably) . T h i s i s b e c a u s e C S 0 n e e d s t o b e r e c o n f i g u r e d f o r
* NAND a c c e s s . A n d w e c a n ' t r e c o n f i g u r e t h i s C S w h e n c u r r e n t l y
* " running" f r o m i t .
* /
/ *
* Finally c a l l n a n d _ b o o t ( ) t o l o a d m a i n N A N D U - B o o t i m a g e f r o m
* NAND a n d j u m p t o i t .
* /
bl n a n d _ b o o t / * w i l l n o t r e t u r n * /
# endif / * C O N F I G _ N A N D _ S P L * /