Wolfgang Denk
17 years ago
commit
6525489323
@ -0,0 +1,409 @@ |
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/*
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle |
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* Copyright (C) 1999 by Silicon Graphics, Inc. |
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* Copyright (C) 2001 MIPS Technologies, Inc. |
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* Copyright (C) 2002 Maciej W. Rozycki |
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* |
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* Some useful macros for MIPS assembler code |
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* |
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* Some of the routines below contain useless nops that will be optimized |
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* away by gas in -O mode. These nops are however required to fill delay |
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* slots in noreorder mode. |
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*/ |
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#ifndef __ASM_ASM_H |
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#define __ASM_ASM_H |
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#include <asm/sgidefs.h> |
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#ifndef CAT |
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#ifdef __STDC__ |
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#define __CAT(str1, str2) str1##str2 |
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#else |
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#define __CAT(str1, str2) str1/**/str2 |
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#endif |
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#define CAT(str1, str2) __CAT(str1, str2) |
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#endif |
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/*
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* PIC specific declarations |
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* Not used for the kernel but here seems to be the right place. |
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*/ |
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#ifdef __PIC__ |
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#define CPRESTORE(register) \ |
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.cprestore register |
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#define CPADD(register) \ |
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.cpadd register |
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#define CPLOAD(register) \ |
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.cpload register |
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#else |
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#define CPRESTORE(register) |
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#define CPADD(register) |
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#define CPLOAD(register) |
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#endif |
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/*
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* LEAF - declare leaf routine |
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*/ |
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#define LEAF(symbol) \ |
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.globl symbol; \
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.align 2; \
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.type symbol, @function; \
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.ent symbol, 0; \
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symbol: .frame sp, 0, ra |
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/*
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* NESTED - declare nested routine entry point |
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*/ |
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#define NESTED(symbol, framesize, rpc) \ |
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.globl symbol; \
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.align 2; \
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.type symbol, @function; \
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.ent symbol, 0; \
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symbol: .frame sp, framesize, rpc |
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/*
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* END - mark end of function |
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*/ |
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#define END(function) \ |
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.end function; \
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.size function, .-function |
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/*
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* EXPORT - export definition of symbol |
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*/ |
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#define EXPORT(symbol) \ |
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.globl symbol; \
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symbol: |
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/*
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* FEXPORT - export definition of a function symbol |
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*/ |
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#define FEXPORT(symbol) \ |
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.globl symbol; \
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.type symbol, @function; \
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symbol: |
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/*
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* ABS - export absolute symbol |
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*/ |
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#define ABS(symbol,value) \ |
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.globl symbol; \
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symbol = value |
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#define PANIC(msg) \ |
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.set push; \
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.set reorder; \
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PTR_LA a0, 8f; \
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jal panic; \
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9: b 9b; \
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.set pop; \
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TEXT(msg) |
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/*
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* Print formatted string |
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*/ |
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#ifdef CONFIG_PRINTK |
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#define PRINT(string) \ |
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.set push; \
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.set reorder; \
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PTR_LA a0, 8f; \
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jal printk; \
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.set pop; \
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TEXT(string) |
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#else |
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#define PRINT(string) |
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#endif |
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#define TEXT(msg) \ |
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.pushsection .data; \
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8: .asciiz msg; \
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.popsection; |
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/*
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* Build text tables |
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*/ |
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#define TTABLE(string) \ |
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.pushsection .text; \
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.word 1f; \
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.popsection \
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.pushsection .data; \
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1: .asciiz string; \
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.popsection |
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/*
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* MIPS IV pref instruction. |
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* Use with .set noreorder only! |
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* |
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* MIPS IV implementations are free to treat this as a nop. The R5000 |
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* is one of them. So we should have an option not to use this instruction. |
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*/ |
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#ifdef CONFIG_CPU_HAS_PREFETCH |
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#define PREF(hint,addr) \ |
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.set push; \
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.set mips4; \
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pref hint, addr; \
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.set pop |
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#define PREFX(hint,addr) \ |
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.set push; \
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.set mips4; \
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prefx hint, addr; \
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.set pop |
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#else /* !CONFIG_CPU_HAS_PREFETCH */ |
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#define PREF(hint, addr) |
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#define PREFX(hint, addr) |
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#endif /* !CONFIG_CPU_HAS_PREFETCH */ |
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/*
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* MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs. |
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*/ |
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#if (_MIPS_ISA == _MIPS_ISA_MIPS1) |
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#define MOVN(rd, rs, rt) \ |
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.set push; \
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.set reorder; \
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beqz rt, 9f; \
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move rd, rs; \
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.set pop; \
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9: |
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#define MOVZ(rd, rs, rt) \ |
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.set push; \
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.set reorder; \
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bnez rt, 9f; \
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move rd, rs; \
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.set pop; \
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9: |
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#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */ |
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#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) |
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#define MOVN(rd, rs, rt) \ |
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.set push; \
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.set noreorder; \
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bnezl rt, 9f; \
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move rd, rs; \
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.set pop; \
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9: |
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#define MOVZ(rd, rs, rt) \ |
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.set push; \
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.set noreorder; \
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beqzl rt, 9f; \
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move rd, rs; \
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.set pop; \
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9: |
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#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */ |
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#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \ |
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(_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64) |
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#define MOVN(rd, rs, rt) \ |
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movn rd, rs, rt |
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#define MOVZ(rd, rs, rt) \ |
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movz rd, rs, rt |
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#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */ |
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/*
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* Stack alignment |
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*/ |
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#if (_MIPS_SIM == _MIPS_SIM_ABI32) |
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#define ALSZ 7 |
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#define ALMASK ~7 |
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#endif |
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#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) |
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#define ALSZ 15 |
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#define ALMASK ~15 |
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#endif |
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/*
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* Macros to handle different pointer/register sizes for 32/64-bit code |
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*/ |
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/*
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* Size of a register |
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*/ |
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#ifdef __mips64 |
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#define SZREG 8 |
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#else |
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#define SZREG 4 |
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#endif |
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/*
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* Use the following macros in assemblercode to load/store registers, |
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* pointers etc. |
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*/ |
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#if (_MIPS_SIM == _MIPS_SIM_ABI32) |
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#define REG_S sw |
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#define REG_L lw |
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#define REG_SUBU subu |
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#define REG_ADDU addu |
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#endif |
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#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) |
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#define REG_S sd |
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#define REG_L ld |
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#define REG_SUBU dsubu |
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#define REG_ADDU daddu |
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#endif |
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/*
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* How to add/sub/load/store/shift C int variables. |
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*/ |
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#if (_MIPS_SZINT == 32) |
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#define INT_ADD add |
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#define INT_ADDU addu |
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#define INT_ADDI addi |
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#define INT_ADDIU addiu |
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#define INT_SUB sub |
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#define INT_SUBU subu |
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#define INT_L lw |
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#define INT_S sw |
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#define INT_SLL sll |
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#define INT_SLLV sllv |
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#define INT_SRL srl |
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#define INT_SRLV srlv |
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#define INT_SRA sra |
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#define INT_SRAV srav |
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#endif |
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#if (_MIPS_SZINT == 64) |
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#define INT_ADD dadd |
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#define INT_ADDU daddu |
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#define INT_ADDI daddi |
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#define INT_ADDIU daddiu |
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#define INT_SUB dsub |
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#define INT_SUBU dsubu |
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#define INT_L ld |
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#define INT_S sd |
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#define INT_SLL dsll |
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#define INT_SLLV dsllv |
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#define INT_SRL dsrl |
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#define INT_SRLV dsrlv |
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#define INT_SRA dsra |
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#define INT_SRAV dsrav |
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#endif |
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/*
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* How to add/sub/load/store/shift C long variables. |
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*/ |
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#if (_MIPS_SZLONG == 32) |
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#define LONG_ADD add |
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#define LONG_ADDU addu |
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#define LONG_ADDI addi |
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#define LONG_ADDIU addiu |
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#define LONG_SUB sub |
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#define LONG_SUBU subu |
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#define LONG_L lw |
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#define LONG_S sw |
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#define LONG_SLL sll |
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#define LONG_SLLV sllv |
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#define LONG_SRL srl |
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#define LONG_SRLV srlv |
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#define LONG_SRA sra |
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#define LONG_SRAV srav |
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#define LONG .word |
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#define LONGSIZE 4 |
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#define LONGMASK 3 |
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#define LONGLOG 2 |
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#endif |
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#if (_MIPS_SZLONG == 64) |
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#define LONG_ADD dadd |
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#define LONG_ADDU daddu |
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#define LONG_ADDI daddi |
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#define LONG_ADDIU daddiu |
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#define LONG_SUB dsub |
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#define LONG_SUBU dsubu |
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#define LONG_L ld |
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#define LONG_S sd |
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#define LONG_SLL dsll |
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#define LONG_SLLV dsllv |
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#define LONG_SRL dsrl |
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#define LONG_SRLV dsrlv |
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#define LONG_SRA dsra |
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#define LONG_SRAV dsrav |
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#define LONG .dword |
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#define LONGSIZE 8 |
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#define LONGMASK 7 |
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#define LONGLOG 3 |
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#endif |
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/*
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* How to add/sub/load/store/shift pointers. |
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*/ |
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#if (_MIPS_SZPTR == 32) |
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#define PTR_ADD add |
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#define PTR_ADDU addu |
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#define PTR_ADDI addi |
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#define PTR_ADDIU addiu |
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#define PTR_SUB sub |
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#define PTR_SUBU subu |
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#define PTR_L lw |
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#define PTR_S sw |
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#define PTR_LA la |
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#define PTR_LI li |
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#define PTR_SLL sll |
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#define PTR_SLLV sllv |
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#define PTR_SRL srl |
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#define PTR_SRLV srlv |
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#define PTR_SRA sra |
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#define PTR_SRAV srav |
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#define PTR_SCALESHIFT 2 |
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#define PTR .word |
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#define PTRSIZE 4 |
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#define PTRLOG 2 |
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#endif |
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#if (_MIPS_SZPTR == 64) |
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#define PTR_ADD dadd |
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#define PTR_ADDU daddu |
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#define PTR_ADDI daddi |
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#define PTR_ADDIU daddiu |
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#define PTR_SUB dsub |
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#define PTR_SUBU dsubu |
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#define PTR_L ld |
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#define PTR_S sd |
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#define PTR_LA dla |
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#define PTR_LI dli |
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#define PTR_SLL dsll |
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#define PTR_SLLV dsllv |
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#define PTR_SRL dsrl |
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#define PTR_SRLV dsrlv |
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#define PTR_SRA dsra |
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#define PTR_SRAV dsrav |
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#define PTR_SCALESHIFT 3 |
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#define PTR .dword |
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#define PTRSIZE 8 |
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#define PTRLOG 3 |
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#endif |
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/*
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* Some cp0 registers were extended to 64bit for MIPS III. |
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*/ |
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#if (_MIPS_SIM == _MIPS_SIM_ABI32) |
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#define MFC0 mfc0 |
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#define MTC0 mtc0 |
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#endif |
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#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) |
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#define MFC0 dmfc0 |
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#define MTC0 dmtc0 |
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#endif |
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#define SSNOP sll zero, zero, 1 |
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#ifdef CONFIG_SGI_IP28 |
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/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */ |
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#include <asm/cacheops.h> |
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#define R10KCBARRIER(addr) cache Cache_Barrier, addr; |
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#else |
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#define R10KCBARRIER(addr) |
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#endif |
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#endif /* __ASM_ASM_H */ |
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@ -0,0 +1,14 @@ |
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/*
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Copyright (C) 1997, 1999, 2001, 06 by Ralf Baechle |
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* Copyright (C) 2001 MIPS Technologies, Inc. |
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*/ |
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#ifndef _ASM_REBOOT_H |
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#define _ASM_REBOOT_H |
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extern void _machine_restart(void); |
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#endif /* _ASM_REBOOT_H */ |
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@ -1,52 +1,100 @@ |
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/*
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* include/asm-mips/regdefs.h |
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* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Copyright (C) 1994, 1995 by Ralf Baechle |
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* Copyright (C) 1985 MIPS Computer Systems, Inc. |
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* Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle |
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* Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc. |
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*/ |
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#ifndef _ASM_REGDEF_H |
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#define _ASM_REGDEF_H |
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#include <asm/sgidefs.h> |
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|
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#ifndef __ASM_MIPS_REGDEF_H |
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#define __ASM_MIPS_REGDEF_H |
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#if _MIPS_SIM == _MIPS_SIM_ABI32 |
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|
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/*
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* Symbolic register names for 32 bit ABI |
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*/ |
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#define zero $0 /* wired zero */ |
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#define AT $1 /* assembler temp - uppercase because of ".set at" */ |
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#define v0 $2 /* return value */ |
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#define v1 $3 |
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#define a0 $4 /* argument registers */ |
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#define a1 $5 |
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#define a2 $6 |
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#define a3 $7 |
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#define t0 $8 /* caller saved */ |
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#define t1 $9 |
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#define t2 $10 |
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#define t3 $11 |
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#define t4 $12 |
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#define t5 $13 |
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#define t6 $14 |
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#define t7 $15 |
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#define s0 $16 /* callee saved */ |
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#define s1 $17 |
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#define s2 $18 |
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#define s3 $19 |
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#define s4 $20 |
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#define s5 $21 |
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#define s6 $22 |
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#define s7 $23 |
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#define t8 $24 /* caller saved */ |
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#define t9 $25 |
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#define jp $25 /* PIC jump register */ |
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#define k0 $26 /* kernel scratch */ |
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#define k1 $27 |
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#define gp $28 /* global pointer */ |
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#define sp $29 /* stack pointer */ |
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#define fp $30 /* frame pointer */ |
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#define zero $0 /* wired zero */ |
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#define AT $1 /* assembler temp - uppercase because of ".set at" */ |
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#define v0 $2 /* return value */ |
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#define v1 $3 |
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#define a0 $4 /* argument registers */ |
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#define a1 $5 |
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#define a2 $6 |
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#define a3 $7 |
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#define t0 $8 /* caller saved */ |
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#define t1 $9 |
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#define t2 $10 |
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#define t3 $11 |
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#define t4 $12 |
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#define t5 $13 |
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#define t6 $14 |
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#define t7 $15 |
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#define s0 $16 /* callee saved */ |
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#define s1 $17 |
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#define s2 $18 |
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#define s3 $19 |
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#define s4 $20 |
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#define s5 $21 |
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#define s6 $22 |
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#define s7 $23 |
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#define t8 $24 /* caller saved */ |
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#define t9 $25 |
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#define jp $25 /* PIC jump register */ |
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#define k0 $26 /* kernel scratch */ |
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#define k1 $27 |
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#define gp $28 /* global pointer */ |
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#define sp $29 /* stack pointer */ |
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#define fp $30 /* frame pointer */ |
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#define s8 $30 /* same like fp! */ |
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#define ra $31 /* return address */ |
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#define ra $31 /* return address */ |
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|
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#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ |
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|
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#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 |
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|
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#define zero $0 /* wired zero */ |
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#define AT $at /* assembler temp - uppercase because of ".set at" */ |
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#define v0 $2 /* return value - caller saved */ |
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#define v1 $3 |
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#define a0 $4 /* argument registers */ |
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#define a1 $5 |
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#define a2 $6 |
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#define a3 $7 |
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#define a4 $8 /* arg reg 64 bit; caller saved in 32 bit */ |
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#define ta0 $8 |
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#define a5 $9 |
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#define ta1 $9 |
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#define a6 $10 |
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#define ta2 $10 |
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#define a7 $11 |
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#define ta3 $11 |
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#define t0 $12 /* caller saved */ |
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#define t1 $13 |
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#define t2 $14 |
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#define t3 $15 |
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#define s0 $16 /* callee saved */ |
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#define s1 $17 |
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#define s2 $18 |
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#define s3 $19 |
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#define s4 $20 |
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#define s5 $21 |
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#define s6 $22 |
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#define s7 $23 |
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#define t8 $24 /* caller saved */ |
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#define t9 $25 /* callee address for PIC/temp */ |
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#define jp $25 /* PIC jump register */ |
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#define k0 $26 /* kernel temporary */ |
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#define k1 $27 |
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#define gp $28 /* global pointer - caller saved for PIC */ |
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#define sp $29 /* stack pointer */ |
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#define fp $30 /* frame pointer */ |
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#define s8 $30 /* callee saved */ |
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#define ra $31 /* return address */ |
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#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */ |
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#endif /* __ASM_MIPS_REGDEF_H */ |
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#endif /* _ASM_REGDEF_H */ |
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|
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Reference in new issue