Let arch/x86/Kconfig prompt board vendor first, then select the board model under that vendor. This way arch/x86/Kconfig only needs concern board vendor and leave the supported target list to board/<vendor>/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>master
Bin Meng
10 years ago
committed by
Simon Glass
parent
f82a7840f1
commit
65c4ac0a83
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# |
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# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
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# |
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# SPDX-License-Identifier: GPL-2.0+ |
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# |
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if VENDOR_COREBOOT |
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|
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choice |
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prompt "Mainboard model" |
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config TARGET_COREBOOT |
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bool "coreboot" |
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help |
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This target is used for running U-Boot on top of coreboot. In |
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this case coreboot does the early inititalisation, and U-Boot |
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takes over once the RAM, video and CPU are fully running. |
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U-Boot is loaded as a fallback payload from coreboot, in |
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coreboot terminology. This method was used for the Chromebook |
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Pixel when launched. |
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endchoice |
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source "board/coreboot/coreboot/Kconfig" |
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endif |
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@ -0,0 +1,43 @@ |
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# |
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# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
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# |
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# SPDX-License-Identifier: GPL-2.0+ |
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# |
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if VENDOR_GOOGLE |
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choice |
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prompt "Mainboard model" |
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config TARGET_CHROMEBOOK_LINK |
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bool "Chromebook link" |
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help |
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This is the Chromebook Pixel released in 2013. It uses an Intel |
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i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of |
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SDRAM. It has a Panther Point platform controller hub, PCIe |
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WiFi and Bluetooth. It also includes a 720p webcam, USB SD |
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reader, microphone and speakers, display port and 32GB SATA |
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solid state drive. There is a Chrome OS EC connected on LPC, |
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and it provides a 2560x1700 high resolution touch-enabled LCD |
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display. |
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config TARGET_CHROMEBOX_PANTHER |
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bool "Chromebox panther (not available)" |
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select n |
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help |
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Note: At present this must be used with coreboot. See README.x86 |
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for instructions. |
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|
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This is the Asus Chromebox CN60 released in 2014. It uses an Intel |
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Haswell Celeron 2955U Dual Core CPU with 2GB of SDRAM. It has a |
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Lynx Point platform controller hub, PCIe WiFi and Bluetooth. It also |
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includes a USB SD reader, four USB3 ports, display port and HDMI |
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video output and a 16GB SATA solid state drive. There is no Chrome |
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OS EC on this model. |
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endchoice |
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source "board/google/chromebook_link/Kconfig" |
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source "board/google/chromebox_panther/Kconfig" |
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endif |
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@ -0,0 +1,51 @@ |
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# |
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# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
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# |
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# SPDX-License-Identifier: GPL-2.0+ |
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# |
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if VENDOR_INTEL |
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choice |
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prompt "Mainboard model" |
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config TARGET_CROWNBAY |
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bool "Crown Bay" |
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help |
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This is the Intel Crown Bay Customer Reference Board. It contains |
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the Intel Atom Processor E6xx populated on the COM Express module |
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with 1GB DDR2 soldered down memory and a carrier board with the |
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Intel Platform Controller Hub EG20T, other system components and |
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peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS. |
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config TARGET_GALILEO |
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bool "Galileo" |
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help |
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This is the Intel Galileo board, which is the first in a family of |
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Arduino-certified development and prototyping boards based on Intel |
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architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit |
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single-core, single-thread, Intel Pentium processor instrunction set |
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architecture (ISA) compatible, operating at speeds up to 400Mhz, |
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along with 256MB DDR3 memory. It supports a wide range of industry |
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standard I/O interfaces, including a full-sized mini-PCIe slot, |
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one 100Mb Ethernet port, a microSD card slot, a USB host port and |
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a USB client port. |
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|
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config TARGET_MINNOWMAX |
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bool "Minnowboard MAX" |
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help |
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This is the Intel Minnowboard MAX. It contains an Atom E3800 |
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processor in a small form factor with Ethernet, micro-SD, USB 2, |
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USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out. |
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It requires some binary blobs - see README.x86 for details. |
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Note that PCIE_ECAM_BASE is set up by the FSP so the value used |
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by U-Boot matches that value. |
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endchoice |
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source "board/intel/crownbay/Kconfig" |
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source "board/intel/galileo/Kconfig" |
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source "board/intel/minnowmax/Kconfig" |
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endif |
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@ -1,5 +1,6 @@ |
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CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x01110000" |
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CONFIG_X86=y |
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CONFIG_VENDOR_COREBOOT=y |
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CONFIG_TARGET_COREBOOT=y |
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CONFIG_OF_CONTROL=y |
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CONFIG_DM_PCI=y |
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