x86: coreboot: Fix cosmetic issues

Clean up arch/x86/cpu/coreboot.c to fix several cosmetic issues.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

arch/x86/cpu/coreboot/coreboot.c

@@ -7,16 +7,10 @@
  */
 
 #include <common.h>
-#include <asm/u-boot-x86.h>
-#include <flash.h>
 #include <netdev.h>
-#include <ns16550.h>
-#include <asm/msr.h>
-#include <asm/cache.h>
-#include <asm/cpu.h>
 #include <asm/io.h>
+#include <asm/msr.h>
 #include <asm/mtrr.h>
-#include <asm/arch/tables.h>
 #include <asm/arch/sysinfo.h>
 #include <asm/arch/timestamp.h>
 
@@ -53,13 +47,6 @@ int last_stage_init(void)
 	return 0;
 }
 
-#ifndef CONFIG_SYS_NO_FLASH
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
-	return 0;
-}
-#endif
-
 int board_eth_init(bd_t *bis)
 {
 	return pci_eth_init(bis);
@@ -67,7 +54,8 @@ int board_eth_init(bd_t *bis)
 
 void board_final_cleanup(void)
 {
-	/* Un-cache the ROM so the kernel has one
+	/*
+	 * Un-cache the ROM so the kernel has one
 	 * more MTRR available.
 	 *
 	 * Coreboot should have assigned this to the
@@ -91,15 +79,6 @@ void board_final_cleanup(void)
 	outb(0xcb, 0xb2);
 }
 
-void panic_puts(const char *str)
-{
-	NS16550_t port = (NS16550_t)0x3f8;
-
-	NS16550_init(port, 1);
-	while (*str)
-		NS16550_putc(port, *str++);
-}
-
 int misc_init_r(void)
 {
 	return 0;

arch/x86/include/asm/u-boot-x86.h

@@ -16,7 +16,6 @@ void init_gd(gd_t *id, u64 *gdt_addr);
 void setup_gdt(gd_t *id, u64 *gdt_addr);
 int init_cache(void);
 int cleanup_before_linux(void);
-void panic_puts(const char *str);
 
 /* cpu/.../timer.c */
 void timer_isr(void *);