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@ -536,7 +536,7 @@ static const struct venc_regs venc_config_std_tv = { |
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* Configure Timings for DVI D |
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* Configure Timings for DVI D |
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*/ |
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*/ |
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static const struct panel_config dvid_cfg = { |
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static const struct panel_config dvid_cfg = { |
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.timing_h = 0x0ff03f31, /* Horizantal timing */ |
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.timing_h = 0x0ff03f31, /* Horizontal timing */ |
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.timing_v = 0x01400504, /* Vertical timing */ |
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.timing_v = 0x01400504, /* Vertical timing */ |
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.pol_freq = 0x00007028, /* Pol Freq */ |
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.pol_freq = 0x00007028, /* Pol Freq */ |
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.divisor = 0x00010006, /* 72Mhz Pixel Clock */ |
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.divisor = 0x00010006, /* 72Mhz Pixel Clock */ |
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@ -548,7 +548,7 @@ static const struct panel_config dvid_cfg = { |
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}; |
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}; |
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static const struct panel_config dvid_cfg_xm = { |
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static const struct panel_config dvid_cfg_xm = { |
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.timing_h = 0x1a4024c9, /* Horizantal timing */ |
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.timing_h = 0x1a4024c9, /* Horizontal timing */ |
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.timing_v = 0x02c00509, /* Vertical timing */ |
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.timing_v = 0x02c00509, /* Vertical timing */ |
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.pol_freq = 0x00007028, /* Pol Freq */ |
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.pol_freq = 0x00007028, /* Pol Freq */ |
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.divisor = 0x00010001, /* 96MHz Pixel Clock */ |
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.divisor = 0x00010001, /* 96MHz Pixel Clock */ |
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