@ -34,57 +34,16 @@
# ifdef CONFIG_PCI1
static struct pci_controller pci1_hose ;
# endif
# ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose ;
# endif
# ifdef CONFIG_PCIE2
static struct pci_controller pcie2_hose ;
# endif
# ifdef CONFIG_PCIE3
static struct pci_controller pcie3_hose ;
# endif
/*
* 85 xx and 86 xx share naming conventions , but different layout .
* Correlate names to CPU - specific values to share common
* PCI code .
*/
# if defined(CONFIG_MPC85xx)
# define MPC8xxx_DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE
# define MPC8xxx_DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2
# define MPC8xxx_DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3
# define MPC8xxx_PORDEVSR_IO_SEL MPC85xx_PORDEVSR_IO_SEL
# define MPC8xxx_PORDEVSR_IO_SEL_SHIFT MPC85xx_PORDEVSR_IO_SEL_SHIFT
# define MPC8xxx_PORBMSR_HA MPC85xx_PORBMSR_HA
# define MPC8xxx_PORBMSR_HA_SHIFT MPC85xx_PORBMSR_HA_SHIFT
# elif defined(CONFIG_MPC86xx)
# define MPC8xxx_DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIEX1
# define MPC8xxx_DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIEX2
# define MPC8xxx_DEVDISR_PCIE3 0 /* 8641 doesn't have PCIe3 */
# define MPC8xxx_PORDEVSR_IO_SEL MPC8641_PORDEVSR_IO_SEL
# define MPC8xxx_PORDEVSR_IO_SEL_SHIFT MPC8641_PORDEVSR_IO_SEL_SHIFT
# define MPC8xxx_PORBMSR_HA MPC8641_PORBMSR_HA
# define MPC8xxx_PORBMSR_HA_SHIFT MPC8641_PORBMSR_HA_SHIFT
# endif
void pci_init_board ( void )
{
struct fsl_pci_info pci_info [ 3 ] ;
int first_free_busno = 0 ;
int num = 0 ;
int pcie_ep ;
__maybe_unused int pcie_configured ;
# if defined(CONFIG_MPC85xx)
# ifdef CONFIG_PCI1
int pcie_ep ;
struct fsl_pci_info pci_info ;
volatile ccsr_gur_t * gur = ( void * ) ( CONFIG_SYS_MPC85xx_GUTS_ADDR ) ;
# elif defined(CONFIG_MPC86xx)
immap_t * immap = ( immap_t * ) CONFIG_SYS_IMMR ;
volatile ccsr_gur_t * gur = & immap - > im_gur ;
# endif
u32 devdisr = in_be32 ( & gur - > devdisr ) ;
# ifdef CONFIG_PCI1
u32 pordevsr = in_be32 ( & gur - > pordevsr ) ;
uint pci_spd_norm = in_be32 ( & gur - > pordevsr ) & MPC85xx_PORDEVSR_PCI1_SPD ;
uint pci_32 = in_be32 ( & gur - > pordevsr ) & MPC85xx_PORDEVSR_PCI1_PCI32 ;
uint pci_arb = in_be32 ( & gur - > pordevsr ) & MPC85xx_PORDEVSR_PCI1_ARB ;
@ -92,8 +51,13 @@ void pci_init_board(void)
uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000 ;
if ( ! ( devdisr & MPC85xx_DEVDISR_PCI1 ) ) {
SET_STD_PCI_INFO ( pci_info [ num ] , 1 ) ;
pcie_ep = fsl_setup_hose ( & pci1_hose , pci_info [ num ] . regs ) ;
SET_STD_PCI_INFO ( pci_info , 1 ) ;
set_next_law ( pci_info . mem_phys ,
law_size_bits ( pci_info . mem_size ) , pci_info . law ) ;
set_next_law ( pci_info . io_phys ,
law_size_bits ( pci_info . io_size ) , pci_info . law ) ;
pcie_ep = fsl_setup_hose ( & pci1_hose , pci_info . regs ) ;
printf ( " PCI1: %d bit %s, %s %d MHz, %s, %s \n " ,
pci_32 ? 32 : 64 ,
pcix ? " PCIX " : " PCI " ,
@ -102,66 +66,18 @@ void pci_init_board(void)
pcie_ep ? " agent " : " host " ,
pci_arb ? " arbiter " : " external-arbiter " ) ;
first_free_busno = fsl_pci_init_port ( & pci_info [ num + + ] ,
first_free_busno = fsl_pci_init_port ( & pci_info ,
& pci1_hose , first_free_busno ) ;
} else {
printf ( " PCI1: disabled \n " ) ;
}
# elif defined CONFIG_MPC8548
volatile ccsr_gur_t * gur = ( void * ) ( CONFIG_SYS_MPC85xx_GUTS_ADDR ) ;
/* PCI1 not present on MPC8572 */
setbits_be32 ( & gur - > devdisr , MPC85xx_DEVDISR_PCI1 ) ;
# endif
# ifdef CONFIG_PCIE1
pcie_configured = is_serdes_configured ( PCIE1 ) ;
if ( pcie_configured & & ! ( devdisr & MPC8xxx_DEVDISR_PCIE1 ) ) {
SET_STD_PCIE_INFO ( pci_info [ num ] , 1 ) ;
pcie_ep = fsl_setup_hose ( & pcie1_hose , pci_info [ num ] . regs ) ;
printf ( " PCIE1: connected as %s \n " ,
pcie_ep ? " Endpoint " : " Root Complex " ) ;
first_free_busno = fsl_pci_init_port ( & pci_info [ num + + ] ,
& pcie1_hose , first_free_busno ) ;
} else {
printf ( " PCIE1: disabled \n " ) ;
}
# else
setbits_be32 ( & gur - > devdisr , MPC8xxx_DEVDISR_PCIE1 ) ;
# endif /* CONFIG_PCIE1 */
# ifdef CONFIG_PCIE2
pcie_configured = is_serdes_configured ( PCIE2 ) ;
if ( pcie_configured & & ! ( devdisr & MPC8xxx_DEVDISR_PCIE2 ) ) {
SET_STD_PCIE_INFO ( pci_info [ num ] , 2 ) ;
pcie_ep = fsl_setup_hose ( & pcie2_hose , pci_info [ num ] . regs ) ;
printf ( " PCIE2: connected as %s \n " ,
pcie_ep ? " Endpoint " : " Root Complex " ) ;
first_free_busno = fsl_pci_init_port ( & pci_info [ num + + ] ,
& pcie2_hose , first_free_busno ) ;
} else {
printf ( " PCIE2: disabled \n " ) ;
}
# else
setbits_be32 ( & gur - > devdisr , MPC8xxx_DEVDISR_PCIE2 ) ;
# endif /* CONFIG_PCIE2 */
# ifdef CONFIG_PCIE3
pcie_configured = is_serdes_configured ( PCIE3 ) ;
if ( pcie_configured & & ! ( devdisr & MPC8xxx_DEVDISR_PCIE3 ) ) {
SET_STD_PCIE_INFO ( pci_info [ num ] , 3 ) ;
pcie_ep = fsl_setup_hose ( & pcie3_hose , pci_info [ num ] . regs ) ;
printf ( " PCIE3: connected as %s \n " ,
pcie_ep ? " Endpoint " : " Root Complex " ) ;
first_free_busno = fsl_pci_init_port ( & pci_info [ num + + ] ,
& pcie3_hose , first_free_busno ) ;
} else {
printf ( " PCIE3: disabled \n " ) ;
}
# else
setbits_be32 ( & gur - > devdisr , MPC8xxx_DEVDISR_PCIE3 ) ;
# endif /* CONFIG_PCIE3 */
fsl_pcie_init_board ( first_free_busno ) ;
}
# if defined(CONFIG_OF_BOARD_SETUP)