This is a low-cost ARMv8 SoC from Socionext Inc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>master
Masahiro Yamada
9 years ago
parent
7381db86a9
commit
667dbcd01d
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/*
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* Copyright (C) 2016 Socionext Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <linux/bitops.h> |
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#include <linux/io.h> |
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#include "../init.h" |
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#include "../sg-regs.h" |
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void uniphier_ld11_clk_init(void) |
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{ |
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if (readl(SG_PINMON0) & BIT(27)) { |
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/* if booted without stand-by MPU */ |
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writel(1, SG_ETPHYPSHUT); |
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writel(1, SG_ETPHYCNT); |
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udelay(1); /* wait for regulator level 1.1V -> 2.5V */ |
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writel(3, SG_ETPHYCNT); |
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writel(3, SG_ETPHYPSHUT); |
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writel(7, SG_ETPHYCNT); |
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} |
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} |
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/*
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* Copyright (C) 2016 Socionext Inc. |
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*/ |
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#include <common.h> |
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#include <linux/io.h> |
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#include <linux/sizes.h> |
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#include <asm/processor.h> |
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#include "../init.h" |
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#include "umc64-regs.h" |
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#define CONFIG_DDR_FREQ 1866 |
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#define DRAM_CH_NR 2 |
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enum dram_freq { |
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DRAM_FREQ_1600M, |
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DRAM_FREQ_NR, |
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}; |
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enum dram_size { |
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DRAM_SZ_256M, |
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DRAM_SZ_512M, |
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DRAM_SZ_NR, |
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}; |
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/* umc */ |
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static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20}; |
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static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08}; |
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static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04}; |
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static u32 umc_cmdctle[DRAM_FREQ_NR] = {0x0078071D}; |
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static u32 umc_cmdctlf[DRAM_FREQ_NR] = {0x02000200}; |
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static u32 umc_cmdctlg[DRAM_FREQ_NR] = {0x08080808}; |
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static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000810}; |
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static u32 umc_rdatactl_d1[DRAM_FREQ_NR] = {0x00000810}; |
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static u32 umc_wdatactl_d0[DRAM_FREQ_NR] = {0x00000004}; |
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static u32 umc_wdatactl_d1[DRAM_FREQ_NR] = {0x00000004}; |
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static u32 umc_odtctl_d0[DRAM_FREQ_NR] = {0x02000002}; |
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static u32 umc_odtctl_d1[DRAM_FREQ_NR] = {0x02000002}; |
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static u32 umc_acssetb[DRAM_CH_NR] = {0x00000200, 0x00000203}; |
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static u32 umc_memconfch[DRAM_FREQ_NR] = {0x00023605}; |
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static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq, |
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unsigned long size, int ch) |
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{ |
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writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA); |
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writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB); |
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writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC); |
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writel(umc_cmdctle[freq], dc_base + UMC_CMDCTLE); |
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writel(umc_cmdctlf[freq], dc_base + UMC_CMDCTLF); |
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writel(umc_cmdctlg[freq], dc_base + UMC_CMDCTLG); |
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writel(umc_rdatactl_d0[freq], dc_base + UMC_RDATACTL_D0); |
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writel(umc_rdatactl_d1[freq], dc_base + UMC_RDATACTL_D1); |
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writel(umc_wdatactl_d0[freq], dc_base + UMC_WDATACTL_D0); |
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writel(umc_wdatactl_d1[freq], dc_base + UMC_WDATACTL_D1); |
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writel(umc_odtctl_d0[freq], dc_base + UMC_ODTCTL_D0); |
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writel(umc_odtctl_d1[freq], dc_base + UMC_ODTCTL_D1); |
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writel(0x00000003, dc_base + UMC_ACSSETA); |
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writel(0x00000103, dc_base + UMC_FLOWCTLG); |
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writel(umc_acssetb[ch], dc_base + UMC_ACSSETB); |
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writel(0x02020200, dc_base + UMC_SPCSETB); |
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writel(umc_memconfch[freq], dc_base + UMC_MEMCONFCH); |
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writel(0x00000002, dc_base + UMC_ACFETCHCTRL); |
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return 0; |
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} |
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static int umc_ch_init(void __iomem *umc_ch_base, |
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enum dram_freq freq, unsigned long size, int ch) |
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{ |
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void __iomem *dc_base = umc_ch_base; |
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return umc_dc_init(dc_base, freq, size, ch); |
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} |
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static void um_init(void __iomem *um_base) |
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{ |
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writel(0x00000001, um_base + UMC_SIORST); |
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writel(0x00000001, um_base + UMC_VO0RST); |
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writel(0x00000001, um_base + UMC_VPERST); |
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writel(0x00000001, um_base + UMC_RGLRST); |
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writel(0x00000001, um_base + UMC_A2DRST); |
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writel(0x00000001, um_base + UMC_DMDRST); |
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} |
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int uniphier_ld11_umc_init(const struct uniphier_board_data *bd) |
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{ |
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void __iomem *um_base = (void __iomem *)0x5B800000; |
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void __iomem *umc_ch_base = (void __iomem *)0x5BC00000; |
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enum dram_freq freq; |
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int ch, ret; |
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switch (bd->dram_freq) { |
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case 1600: |
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freq = DRAM_FREQ_1600M; |
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break; |
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default: |
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pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq); |
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return -EINVAL; |
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} |
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for (ch = 0; ch < bd->dram_nr_ch; ch++) { |
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unsigned long size = bd->dram_ch[ch].size; |
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unsigned int width = bd->dram_ch[ch].width; |
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ret = umc_ch_init(umc_ch_base, freq, size / (width / 16), ch); |
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if (ret) { |
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pr_err("failed to initialize UMC ch%d\n", ch); |
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return ret; |
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} |
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umc_ch_base += 0x00200000; |
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} |
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um_init(um_base); |
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return 0; |
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} |
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@ -0,0 +1,32 @@ |
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/*
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* Copyright (C) 2016 Socionext Inc. |
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <linux/io.h> |
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#include "../init.h" |
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#include "../sc64-regs.h" |
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int uniphier_ld11_early_clk_init(const struct uniphier_board_data *bd) |
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{ |
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u32 tmp; |
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/* deassert reset */ |
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tmp = readl(SC_RSTCTRL7); |
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tmp |= SC_RSTCTRL7_UMC31 | SC_RSTCTRL7_UMC30; |
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writel(tmp, SC_RSTCTRL7); |
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/* provide clocks */ |
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tmp = readl(SC_CLKCTRL4); |
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tmp |= SC_CLKCTRL4_PERI; |
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writel(tmp, SC_CLKCTRL4); |
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tmp = readl(SC_CLKCTRL7); |
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tmp |= SC_CLKCTRL7_UMC31 | SC_CLKCTRL7_UMC30; |
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writel(tmp, SC_CLKCTRL7); |
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return 0; |
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} |
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@ -0,0 +1,59 @@ |
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/*
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* Copyright (C) 2016 Socionext Inc. |
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <spl.h> |
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#include "../init.h" |
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#include "../micro-support-card.h" |
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int uniphier_ld11_init(const struct uniphier_board_data *bd) |
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{ |
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uniphier_sbc_init_savepin(bd); |
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uniphier_pxs2_sbc_init(bd); |
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uniphier_ld20_early_pin_init(bd); |
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support_card_reset(); |
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support_card_init(); |
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led_puts("L0"); |
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memconf_init(bd); |
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led_puts("L1"); |
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uniphier_ld11_early_clk_init(bd); |
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led_puts("L2"); |
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led_puts("L3"); |
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#ifdef CONFIG_SPL_SERIAL_SUPPORT |
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preloader_console_init(); |
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#endif |
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led_puts("L4"); |
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{ |
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int res; |
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res = uniphier_ld11_umc_init(bd); |
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if (res < 0) { |
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while (1) |
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; |
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} |
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} |
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led_puts("L5"); |
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dcache_disable(); |
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led_puts("L6"); |
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return 0; |
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} |
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@ -0,0 +1,31 @@ |
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CONFIG_ARM=y |
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CONFIG_ARCH_UNIPHIER=y |
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CONFIG_SYS_MALLOC_F_LEN=0x2000 |
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CONFIG_ARCH_UNIPHIER_LD11=y |
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CONFIG_MICRO_SUPPORT_CARD=y |
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CONFIG_SYS_TEXT_BASE=0x84000000 |
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CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld11-ref" |
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CONFIG_HUSH_PARSER=y |
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# CONFIG_CMD_XIMG is not set |
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# CONFIG_CMD_ENV_EXISTS is not set |
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CONFIG_CMD_MMC=y |
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CONFIG_CMD_I2C=y |
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CONFIG_CMD_USB=y |
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# CONFIG_CMD_FPGA is not set |
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CONFIG_CMD_GPIO=y |
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CONFIG_CMD_TFTPPUT=y |
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CONFIG_CMD_PING=y |
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CONFIG_CMD_TIME=y |
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# CONFIG_CMD_MISC is not set |
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CONFIG_CMD_FAT=y |
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CONFIG_NET_RANDOM_ETHADDR=y |
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CONFIG_SPL_OF_TRANSLATE=y |
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CONFIG_GPIO_UNIPHIER=y |
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CONFIG_PINCTRL=y |
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CONFIG_SPL_PINCTRL=y |
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CONFIG_UNIPHIER_SERIAL=y |
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CONFIG_USB=y |
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CONFIG_DM_USB=y |
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CONFIG_USB_EHCI_HCD=y |
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CONFIG_USB_EHCI_GENERIC=y |
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CONFIG_USB_STORAGE=y |
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