x86: baytrail: Remove "serial-debug-port-*" settings

"serial-debug-port-address" and "serial-debug-port-type" settings
are actually reserved in the FSP UPD data structure. Remove them.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

arch/x86/cpu/baytrail/fsp_configs.c

@@ -193,10 +193,6 @@ void update_fsp_configs(struct fsp_config_data *config,
 	fsp_upd->aperture_size = fdtdec_get_int(blob, node, "fsp,aperture-size",
 						2);
 	fsp_upd->gtt_size = fdtdec_get_int(blob, node, "fsp,gtt-size", 2);
-	fsp_upd->serial_debug_port_address = fdtdec_get_int(blob, node,
-			"fsp,serial-debug-port-address", 0x3f8);
-	fsp_upd->serial_debug_port_type = fdtdec_get_int(blob, node,
-			"fsp,serial-debug-port-type", 1);
 	fsp_upd->mrc_debug_msg = fdtdec_get_bool(blob, node,
 						 "fsp,mrc-debug-msg");
 	fsp_upd->isp_enable = fdtdec_get_bool(blob, node, "fsp,isp-enable");

arch/x86/dts/bayleybay.dts

@@ -263,8 +263,6 @@
 		fsp,igd-dvmt50-pre-alloc = <2>;
 		fsp,aperture-size = <2>;
 		fsp,gtt-size = <2>;
-		fsp,serial-debug-port-address = <0x3f8>;
-		fsp,serial-debug-port-type = <1>;
 		fsp,scc-enable-pci-mode;
 		fsp,os-selection = <4>;
 		fsp,emmc45-ddr50-enabled;

arch/x86/dts/baytrail_som-db5800-som-6867.dts

@@ -285,8 +285,6 @@
 		fsp,scc-enable-pci-mode;
 		fsp,os-selection = <4>;
 		fsp,enable-igd;
-		fsp,serial-debug-port-address = <0x3f8>;
-		fsp,serial-debug-port-type = <1>;
 	};
 
 	microcode {

arch/x86/dts/minnowmax.dts

@@ -287,8 +287,6 @@
 		fsp,igd-dvmt50-pre-alloc = <2>;
 		fsp,aperture-size = <2>;
 		fsp,gtt-size = <2>;
-		fsp,serial-debug-port-address = <0x3f8>;
-		fsp,serial-debug-port-type = <1>;
 		fsp,scc-enable-pci-mode;
 		fsp,os-selection = <4>;
 		fsp,emmc45-ddr50-enabled;

arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h

@@ -64,8 +64,7 @@ struct __packed upd_region {
 	uint8_t igd_dvmt50_pre_alloc;		/* Offset 0x0043 */
 	uint8_t aperture_size;			/* Offset 0x0044 */
 	uint8_t gtt_size;			/* Offset 0x0045 */
-	uint32_t serial_debug_port_address;	/* Offset 0x0046 */
-	uint8_t serial_debug_port_type;		/* Offset 0x004a */
+	uint8_t reserved2[5];			/* Offset 0x0046 */
 	uint8_t mrc_debug_msg;			/* Offset 0x004b */
 	uint8_t isp_enable;			/* Offset 0x004c */
 	uint8_t scc_enable_pci_mode;		/* Offset 0x004d */

doc/device-tree-bindings/misc/intel,baytrail-fsp.txt

@@ -60,8 +60,6 @@ discovered by the FSP and used to setup main memory.
 - fsp,igd-dvmt50-pre-alloc
 - fsp,aperture-size
 - fsp,gtt-size
-- fsp,serial-debug-port-address
-- fsp,serial-debug-port-type
 - fsp,os-selection
 - fsp,emmc45-retune-timer-value