diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c
index 31b079b..04912b8 100644
--- a/board/davedenx/aria/aria.c
+++ b/board/davedenx/aria/aria.c
@@ -55,37 +55,6 @@ DECLARE_GLOBAL_DATA_PTR;
 int board_early_init_f(void)
 {
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	u32 spridr;
-
-	/*
-	 * Initialize Local Window for the On Board FPGA access
-	 */
-	out_be32(&im->sysconf.lpcs2aw,
-		CSAW_START(CONFIG_SYS_ARIA_FPGA_BASE) |
-		CSAW_STOP(CONFIG_SYS_ARIA_FPGA_BASE, CONFIG_SYS_ARIA_FPGA_SIZE)
-	);
-	out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
-	sync_law(&im->sysconf.lpcs2aw);
-
-	/*
-	 * Initialize Local Window for the On Board SRAM access
-	 */
-	out_be32(&im->sysconf.lpcs6aw,
-		CSAW_START(CONFIG_SYS_ARIA_SRAM_BASE) |
-		CSAW_STOP(CONFIG_SYS_ARIA_SRAM_BASE, CONFIG_SYS_ARIA_SRAM_SIZE)
-	);
-	out_be32(&im->lpc.cs_cfg[6], CONFIG_SYS_CS6_CFG);
-	sync_law(&im->sysconf.lpcs6aw);
-
-	/*
-	 * Configure Flash Speed
-	 */
-	out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
-
-	spridr = in_be32(&im->sysconf.spridr);
-
-	if (SVR_MJREV(spridr) >= 2)
-		out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
 
 	/*
 	 * Enable clocks
diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c
index 748ad7c..19e6e1f 100644
--- a/board/esd/mecp5123/mecp5123.c
+++ b/board/esd/mecp5123/mecp5123.c
@@ -65,18 +65,9 @@ int eeprom_write_enable(unsigned dev_addr, int state)
 int board_early_init_f(void)
 {
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	u32 spridr;
 	int i;
 
 	/*
-	 * Initialize Local Window for NOR FLASH access
-	 */
-	out_be32(&im->sysconf.lpcs0aw,
-		 CSAW_START(CONFIG_SYS_FLASH_BASE) |
-		 CSAW_STOP(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE));
-	sync_law(&im->sysconf.lpcs0aw);
-
-	/*
 	 * Initialize Local Window for boot access
 	 */
 	out_be32(&im->sysconf.lpbaw,
@@ -84,28 +75,6 @@ int board_early_init_f(void)
 	sync_law(&im->sysconf.lpbaw);
 
 	/*
-	 * Initialize Local Window for VPC3 access
-	 */
-	out_be32(&im->sysconf.lpcs1aw,
-		 CSAW_START(CONFIG_SYS_VPC3_BASE) |
-		 CSAW_STOP(CONFIG_SYS_VPC3_BASE, CONFIG_SYS_VPC3_SIZE));
-	sync_law(&im->sysconf.lpcs1aw);
-
-	/*
-	 * Configure Flash Speed
-	 */
-	out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
-
-	/*
-	 * Configure VPC3 Speed
-	 */
-	out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG);
-
-	spridr = in_be32(&im->sysconf.spridr);
-	if (SVR_MJREV(spridr) >= 2)
-		out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
-
-	/*
 	 * Enable clocks
 	 */
 	out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c
index 97eeab3..4b58dbc 100644
--- a/board/freescale/mpc5121ads/mpc5121ads.c
+++ b/board/freescale/mpc5121ads/mpc5121ads.c
@@ -84,18 +84,6 @@ void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
 int board_early_init_f(void)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 spridr;
-
-	/*
-	 * Initialize Local Window for the CPLD registers access (CS2 selects
-	 * the CPLD chip)
-	 */
-	out_be32(&im->sysconf.lpcs2aw,
-		CSAW_START(CONFIG_SYS_CPLD_BASE) |
-		CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE)
-	);
-	out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
-	sync_law(&im->sysconf.lpcs2aw);
 
 	/*
 	 * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
@@ -114,15 +102,6 @@ int board_early_init_f(void)
 		out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32);
 	}
 #endif
-	/*
-	 * Configure Flash Speed
-	 */
-	out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
-
-	spridr = in_be32(&im->sysconf.spridr);
-
-	if (SVR_MJREV (spridr) >= 2)
-		out_be32 (&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
 
 	/*
 	 * Enable clocks
diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c
index a2a1323..9a164ee 100644
--- a/board/pdm360ng/pdm360ng.c
+++ b/board/pdm360ng/pdm360ng.c
@@ -64,32 +64,6 @@ int board_early_init_f(void)
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 
 	/*
-	 * Initialize Local Window for FLASH-Bank1 access (CS1)
-	 */
-	out_be32(&im->sysconf.lpcs1aw,
-		CSAW_START(CONFIG_SYS_FLASH1_BASE) |
-		CSAW_STOP(CONFIG_SYS_FLASH1_BASE, CONFIG_SYS_FLASH_SIZE)
-	);
-	out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG);
-
-	/*
-	 * Local Window for MRAM access (CS2)
-	 */
-	out_be32(&im->sysconf.lpcs2aw,
-		CSAW_START(CONFIG_SYS_MRAM_BASE) |
-		CSAW_STOP(CONFIG_SYS_MRAM_BASE, CONFIG_SYS_MRAM_SIZE)
-	);
-	out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
-
-	sync_law(&im->sysconf.lpcs2aw);
-
-	/*
-	 * Configure Flash Speed
-	 */
-	out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
-	out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
-
-	/*
 	 * Enable clocks
 	 */
 	out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
diff --git a/include/configs/aria.h b/include/configs/aria.h
index 0b31c50..6b6e400 100644
--- a/include/configs/aria.h
+++ b/include/configs/aria.h
@@ -266,11 +266,16 @@
 #define CONFIG_SYS_ARIA_SRAM_BASE	(CONFIG_SYS_SRAM_BASE + \
 					 CONFIG_SYS_SRAM_SIZE)
 #define CONFIG_SYS_ARIA_SRAM_SIZE	0x00100000	/* reserve 1MB-window */
+#define CONFIG_SYS_CS6_START		CONFIG_SYS_ARIA_SRAM_BASE
+#define CONFIG_SYS_CS6_SIZE		CONFIG_SYS_ARIA_SRAM_SIZE
 
 #define CONFIG_SYS_ARIA_FPGA_BASE	(CONFIG_SYS_ARIA_SRAM_BASE + \
 					 CONFIG_SYS_ARIA_SRAM_SIZE)
 #define CONFIG_SYS_ARIA_FPGA_SIZE	0x20000		/* 128 KB */
 
+#define CONFIG_SYS_CS2_START		CONFIG_SYS_ARIA_FPGA_BASE
+#define CONFIG_SYS_CS2_SIZE		CONFIG_SYS_ARIA_FPGA_SIZE
+
 #define CONFIG_SYS_CS0_CFG		0x05059150
 #define CONFIG_SYS_CS2_CFG		(	(5 << 24) | \
 						(5 << 16) | \
diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h
index cafc273..1e09ff2 100644
--- a/include/configs/mecp5123.h
+++ b/include/configs/mecp5123.h
@@ -191,6 +191,10 @@
 #define CONFIG_SYS_SRAM_BASE		0x30000000
 #define CONFIG_SYS_SRAM_SIZE		0x00020000	/* 128 KB */
 
+/* Initialize Local Window for NOR FLASH access */
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+
 /* ALE active low, data size 4bytes */
 #define CONFIG_SYS_CS0_CFG		0x05051150
 
@@ -201,6 +205,9 @@
 #define CONFIG_SYS_CS1_CFG		0x1f1f3090
 #define CONFIG_SYS_VPC3_BASE		0x82000000	/* start of VPC3 space */
 #define CONFIG_SYS_VPC3_SIZE		0x00010000	/* max VPC3 size */
+/* Initialize Local Window for VPC3 access */
+#define CONFIG_SYS_CS1_START		CONFIG_SYS_VPC3_BASE
+#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_VPC3_SIZE
 
 /* Use SRAM for initial stack */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE /* Init RAM addr */
diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h
index 3f55d35..a64df61 100644
--- a/include/configs/mpc5121ads.h
+++ b/include/configs/mpc5121ads.h
@@ -258,6 +258,8 @@
  */
 #define CONFIG_SYS_CPLD_BASE		0x82000000
 #define CONFIG_SYS_CPLD_SIZE		0x00010000	/* 64 KB */
+#define CONFIG_SYS_CS2_START		CONFIG_SYS_CPLD_BASE
+#define CONFIG_SYS_CS2_SIZE		CONFIG_SYS_CPLD_SIZE
 
 #define CONFIG_SYS_SRAM_BASE		0x30000000
 #define CONFIG_SYS_SRAM_SIZE		0x00020000	/* 128 KB */
diff --git a/include/configs/pdm360ng.h b/include/configs/pdm360ng.h
index 671e9eb..0773121 100644
--- a/include/configs/pdm360ng.h
+++ b/include/configs/pdm360ng.h
@@ -206,6 +206,9 @@
 #define CONFIG_SYS_SRAM_BASE		0x50000000
 #define CONFIG_SYS_SRAM_SIZE		0x00020000	/* 128 KB */
 
+#define CONFIG_SYS_CS1_START		CONFIG_SYS_FLASH1_BASE
+#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_FLASH_SIZE
+
 /* ALE active low, data size 4 bytes */
 #define CONFIG_SYS_CS0_CFG		0x05059350
 /* ALE active low, data size 4 bytes */
@@ -213,6 +216,9 @@
 
 #define CONFIG_SYS_MRAM_BASE		0x50040000
 #define CONFIG_SYS_MRAM_SIZE		0x00020000
+#define CONFIG_SYS_CS2_START		CONFIG_SYS_MRAM_BASE
+#define CONFIG_SYS_CS2_SIZE		CONFIG_SYS_MRAM_SIZE
+
 /* ALE active low, data size 4 bytes */
 #define CONFIG_SYS_CS2_CFG		0x05059110