- Added support for custom keyboards, initialized by defining a
board-specific drv_keyboard_init as well as defining CONFIG_KEYBOARD .
- Added support for the RBC823 board.
- cpu/mpc8xx/lcd.c now automatically calculates the
Horizontal Pixel Count field.
* Fix alignment problem in BOOTP (dhcp_leasetime option)
[pointed out by Nicolas Lacressonnire, 2 Jun 2003]
* Patch by Mark Rakes, 14 May 2003:
add support for Intel e1000 gig cards.
* Patch by Nye Liu, 3 Jun 2003:
fix critical typo in MAMR definition (include/mpc8xx.h)
* Fix requirement to align U-Boot image on 16 kB boundaries on PPC.
* Patch by Klaus Heydeck, 2 Jun 2003
Minor changes for KUP4K configuration
master
wdenk
22 years ago
parent
7a8e9bed17
commit
682011ff69
@ -0,0 +1,40 @@ |
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#
|
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# (C) Copyright 2000
|
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
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#
|
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# See file CREDITS for list of people who contributed to this
|
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# project.
|
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#
|
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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# MA 02111-1307 USA
|
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#
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|
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS = $(BOARD).o flash.o kbd.o
|
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|
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$(LIB): .depend $(OBJS) |
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$(AR) crv $@ $^
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|
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#########################################################################
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|
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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|
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sinclude .depend |
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|
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#########################################################################
|
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@ -0,0 +1,28 @@ |
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#
|
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# (C) Copyright 2000
|
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
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#
|
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# See file CREDITS for list of people who contributed to this
|
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# project.
|
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#
|
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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# MA 02111-1307 USA
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#
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#
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# RBC823 boards
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#
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TEXT_BASE = 0xFFF00000
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@ -0,0 +1,470 @@ |
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/*
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* (C) Copyright 2000 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <mpc8xx.h> |
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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static ulong flash_get_size (vu_long *addr, flash_info_t *info); |
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static int write_word (flash_info_t *info, ulong dest, ulong data); |
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static void flash_get_offsets (ulong base, flash_info_t *info); |
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|
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/*-----------------------------------------------------------------------
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*/ |
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unsigned long flash_init (void) |
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{ |
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unsigned long size_b0, size_b1; |
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int i; |
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/* Init: no FLASHes known */ |
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for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) |
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flash_info[i].flash_id = FLASH_UNKNOWN; |
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|
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/* Detect size */ |
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size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); |
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/* Setup offsets */ |
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flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); |
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#if CFG_MONITOR_BASE >= CFG_FLASH_BASE |
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/* Monitor protection ON by default */ |
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flash_protect(FLAG_PROTECT_SET, |
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CFG_MONITOR_BASE, |
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CFG_MONITOR_BASE+monitor_flash_len-1, |
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&flash_info[0]); |
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#endif |
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size_b1 = 0 ; |
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flash_info[1].flash_id = FLASH_UNKNOWN; |
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flash_info[1].sector_count = -1; |
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flash_info[0].size = size_b0; |
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flash_info[1].size = size_b1; |
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return (size_b0 + size_b1); |
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} |
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|
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/*-----------------------------------------------------------------------
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* Fix this to support variable sector sizes |
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*/ |
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static void flash_get_offsets (ulong base, flash_info_t *info) |
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{ |
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int i; |
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|
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/* set up sector start address table */ |
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if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { |
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/* set sector offsets for bottom boot block type */ |
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for (i = 0; i < info->sector_count; i++) |
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info->start[i] = base + (i * 0x00010000); |
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} |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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void flash_print_info (flash_info_t *info) |
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{ |
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int i; |
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if (info->flash_id == FLASH_UNKNOWN) |
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{ |
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puts ("missing or unknown FLASH type\n"); |
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return; |
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} |
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|
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switch (info->flash_id & FLASH_VENDMASK) |
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{ |
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case FLASH_MAN_AMD: printf ("AMD "); break; |
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case FLASH_MAN_FUJ: printf ("FUJITSU "); break; |
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case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; |
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default: printf ("Unknown Vendor "); break; |
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} |
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switch (info->flash_id & FLASH_TYPEMASK) |
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{ |
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case FLASH_AM040: printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); |
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break; |
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case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); |
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break; |
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case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); |
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break; |
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case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); |
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break; |
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case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); |
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break; |
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case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); |
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break; |
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case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); |
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break; |
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case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); |
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break; |
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case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); |
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break; |
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default: printf ("Unknown Chip Type\n"); |
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break; |
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} |
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if (info->size >> 20) { |
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printf (" Size: %ld MB in %d Sectors\n", |
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info->size >> 20, |
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info->sector_count); |
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} else { |
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printf (" Size: %ld KB in %d Sectors\n", |
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info->size >> 10, |
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info->sector_count); |
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} |
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puts (" Sector Start Addresses:"); |
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for (i=0; i<info->sector_count; ++i) |
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{ |
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if ((i % 5) == 0) |
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{ |
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puts ("\n "); |
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} |
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printf (" %08lX%s", |
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info->start[i], |
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info->protect[i] ? " (RO)" : " "); |
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} |
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putc ('\n'); |
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return; |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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/*
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* The following code cannot be run from FLASH! |
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*/ |
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static ulong flash_get_size (vu_long *addr, flash_info_t *info) |
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{ |
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short i; |
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volatile unsigned char *caddr; |
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char value; |
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caddr = (volatile unsigned char *)addr ; |
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/* Write auto select command: read Manufacturer ID */ |
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#if 0 |
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printf("Base address is: %08x\n", caddr); |
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#endif |
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caddr[0x0555] = 0xAA; |
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caddr[0x02AA] = 0x55; |
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caddr[0x0555] = 0x90; |
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value = caddr[0]; |
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#if 0 |
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printf("Manufact ID: %02x\n", value); |
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#endif |
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switch (value) |
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{ |
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case 0x01: |
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case AMD_MANUFACT: |
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info->flash_id = FLASH_MAN_AMD; |
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break; |
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case FUJ_MANUFACT: |
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info->flash_id = FLASH_MAN_FUJ; |
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break; |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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info->sector_count = 0; |
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info->size = 0; |
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break; |
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} |
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value = caddr[1]; /* device ID */ |
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#if 0 |
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printf("Device ID: %02x\n", value); |
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#endif |
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switch (value) |
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{ |
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case AMD_ID_LV040B: |
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info->flash_id += FLASH_AM040; |
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info->sector_count = 8; |
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info->size = 0x00080000; |
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break; /* => 512Kb */ |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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return (0); /* => no or unknown flash */ |
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} |
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flash_get_offsets ((ulong)addr, &flash_info[0]); |
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|
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/* check for protected sectors */ |
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for (i = 0; i < info->sector_count; i++) |
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{ |
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/* read sector protection at sector address, (A7 .. A0) = 0x02 */ |
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/* D0 = 1 if protected */ |
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caddr = (volatile unsigned char *)(info->start[i]); |
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info->protect[i] = caddr[2] & 1; |
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} |
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|
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/*
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* Prevent writes to uninitialized FLASH. |
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*/ |
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if (info->flash_id != FLASH_UNKNOWN) |
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{ |
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caddr = (volatile unsigned char *)info->start[0]; |
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*caddr = 0xF0; /* reset bank */ |
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} |
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|
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return (info->size); |
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} |
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|
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|
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/*-----------------------------------------------------------------------
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*/ |
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|
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int flash_erase (flash_info_t *info, int s_first, int s_last) |
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{ |
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volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]); |
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int flag, prot, sect, l_sect; |
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ulong start, now, last; |
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|
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if ((s_first < 0) || (s_first > s_last)) { |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("- missing\n"); |
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} else { |
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printf ("- no sectors to erase\n"); |
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} |
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return 1; |
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} |
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|
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if ((info->flash_id == FLASH_UNKNOWN) || |
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(info->flash_id > FLASH_AMD_COMP)) { |
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printf ("Can't erase unknown flash type - aborted\n"); |
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return 1; |
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} |
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|
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prot = 0; |
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for (sect=s_first; sect<=s_last; ++sect) { |
||||
if (info->protect[sect]) { |
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prot++; |
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} |
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} |
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|
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if (prot) { |
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printf ("- Warning: %d protected sectors will not be erased!\n", |
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prot); |
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} else { |
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printf ("\n"); |
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} |
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|
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l_sect = -1; |
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|
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/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
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addr[0x0555] = 0xAA; |
||||
addr[0x02AA] = 0x55; |
||||
addr[0x0555] = 0x80; |
||||
addr[0x0555] = 0xAA; |
||||
addr[0x02AA] = 0x55; |
||||
|
||||
/* Start erase on unprotected sectors */ |
||||
for (sect = s_first; sect<=s_last; sect++) { |
||||
if (info->protect[sect] == 0) { /* not protected */ |
||||
addr = (volatile unsigned char *)(info->start[sect]); |
||||
addr[0] = 0x30; |
||||
l_sect = sect; |
||||
} |
||||
} |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
/* wait at least 80us - let's wait 1 ms */ |
||||
udelay (1000); |
||||
|
||||
/*
|
||||
* We wait for the last triggered sector |
||||
*/ |
||||
if (l_sect < 0) |
||||
goto DONE; |
||||
|
||||
start = get_timer (0); |
||||
last = start; |
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addr = (volatile unsigned char *)(info->start[l_sect]); |
||||
|
||||
while ((addr[0] & 0xFF) != 0xFF) |
||||
{ |
||||
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { |
||||
printf ("Timeout\n"); |
||||
return 1; |
||||
} |
||||
/* show that we're waiting */ |
||||
if ((now - last) > 1000) { /* every second */ |
||||
putc ('.'); |
||||
last = now; |
||||
} |
||||
} |
||||
|
||||
DONE: |
||||
/* reset to read mode */ |
||||
addr = (volatile unsigned char *)info->start[0]; |
||||
|
||||
addr[0] = 0xF0; /* reset bank */ |
||||
|
||||
printf (" done\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
||||
{ |
||||
ulong cp, wp, data; |
||||
int i, l, rc; |
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */ |
||||
|
||||
/*
|
||||
* handle unaligned start bytes |
||||
*/ |
||||
if ((l = addr - wp) != 0) { |
||||
data = 0; |
||||
for (i=0, cp=wp; i<l; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
for (; i<4 && cnt>0; ++i) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
++cp; |
||||
} |
||||
for (; cnt==0 && i<4; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
|
||||
if ((rc = write_word(info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
} |
||||
|
||||
/*
|
||||
* handle word aligned part |
||||
*/ |
||||
while (cnt >= 4) { |
||||
data = 0; |
||||
for (i=0; i<4; ++i) { |
||||
data = (data << 8) | *src++; |
||||
} |
||||
if ((rc = write_word(info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
cnt -= 4; |
||||
} |
||||
|
||||
if (cnt == 0) { |
||||
return (0); |
||||
} |
||||
|
||||
/*
|
||||
* handle unaligned tail bytes |
||||
*/ |
||||
data = 0; |
||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
} |
||||
for (; i<4; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
|
||||
return (write_word(info, wp, data)); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
static int write_word (flash_info_t *info, ulong dest, ulong data) |
||||
{ |
||||
volatile unsigned char *addr = (volatile unsigned char*)(info->start[0]), |
||||
*cdest,*cdata; |
||||
ulong start; |
||||
int flag, count = 4 ; |
||||
|
||||
cdest = (volatile unsigned char *)dest ; |
||||
cdata = (volatile unsigned char *)&data ; |
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
if ((*((vu_long *)dest) & data) != data) { |
||||
return (2); |
||||
} |
||||
|
||||
while(count--) |
||||
{ |
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
addr[0x0555] = 0xAA; |
||||
addr[0x02AA] = 0x55; |
||||
addr[0x0555] = 0xA0; |
||||
|
||||
*cdest = *cdata; |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
/* data polling for D7 */ |
||||
start = get_timer (0); |
||||
while ((*cdest ^ *cdata) & 0x80) |
||||
{ |
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { |
||||
return (1); |
||||
} |
||||
} |
||||
|
||||
cdata++ ; |
||||
cdest++ ; |
||||
} |
||||
return (0); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
@ -0,0 +1,269 @@ |
||||
/*
|
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/* Modified by Udi Finkelstein
|
||||
* |
||||
* This file includes communication routines for SMC1 that can run even if |
||||
* SMC2 have already been initialized. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <watchdog.h> |
||||
#include <commproc.h> |
||||
#include <devices.h> |
||||
#include <lcd.h> |
||||
|
||||
#define SMC_INDEX 0 |
||||
#define PROFF_SMC PROFF_SMC1 |
||||
#define CPM_CR_CH_SMC CPM_CR_CH_SMC1 |
||||
|
||||
#define RBC823_KBD_BAUDRATE 38400 |
||||
#define CPM_KEYBOARD_BASE 0x1000 |
||||
/*
|
||||
* Minimal serial functions needed to use one of the SMC ports |
||||
* as serial console interface. |
||||
*/ |
||||
|
||||
void smc1_setbrg (void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
volatile immap_t *im = (immap_t *)CFG_IMMR; |
||||
volatile cpm8xx_t *cp = &(im->im_cpm); |
||||
|
||||
/* Set up the baud rate generator.
|
||||
* See 8xx_io/commproc.c for details. |
||||
* |
||||
* Wire BRG2 to SMC1, BRG1 to SMC2 |
||||
*/ |
||||
|
||||
cp->cp_simode = 0x00001000; |
||||
|
||||
cp->cp_brgc2 = |
||||
(((gd->cpu_clk / 16 / RBC823_KBD_BAUDRATE)-1) << 1) | CPM_BRG_EN; |
||||
} |
||||
|
||||
int smc1_init (void) |
||||
{ |
||||
volatile immap_t *im = (immap_t *)CFG_IMMR; |
||||
volatile smc_t *sp; |
||||
volatile smc_uart_t *up; |
||||
volatile cbd_t *tbdf, *rbdf; |
||||
volatile cpm8xx_t *cp = &(im->im_cpm); |
||||
uint dpaddr; |
||||
|
||||
/* initialize pointers to SMC */ |
||||
|
||||
sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]); |
||||
up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC]; |
||||
|
||||
/* Disable transmitter/receiver.
|
||||
*/ |
||||
sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); |
||||
|
||||
/* Enable SDMA.
|
||||
*/ |
||||
im->im_siu_conf.sc_sdcr = 1; |
||||
|
||||
/* clear error conditions */ |
||||
#ifdef CFG_SDSR |
||||
im->im_sdma.sdma_sdsr = CFG_SDSR; |
||||
#else |
||||
im->im_sdma.sdma_sdsr = 0x83; |
||||
#endif |
||||
|
||||
/* clear SDMA interrupt mask */ |
||||
#ifdef CFG_SDMR |
||||
im->im_sdma.sdma_sdmr = CFG_SDMR; |
||||
#else |
||||
im->im_sdma.sdma_sdmr = 0x00; |
||||
#endif |
||||
|
||||
/* Use Port B for SMC1 instead of other functions.
|
||||
*/ |
||||
cp->cp_pbpar |= 0x000000c0; |
||||
cp->cp_pbdir &= ~0x000000c0; |
||||
cp->cp_pbodr &= ~0x000000c0; |
||||
|
||||
/* Set the physical address of the host memory buffers in
|
||||
* the buffer descriptors. |
||||
*/ |
||||
|
||||
#ifdef CFG_ALLOC_DPRAM |
||||
dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ; |
||||
#else |
||||
dpaddr = CPM_KEYBOARD_BASE ; |
||||
#endif |
||||
|
||||
/* Allocate space for two buffer descriptors in the DP ram.
|
||||
* For now, this address seems OK, but it may have to |
||||
* change with newer versions of the firmware. |
||||
* damm: allocating space after the two buffers for rx/tx data |
||||
*/ |
||||
|
||||
rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr]; |
||||
rbdf->cbd_bufaddr = (uint) (rbdf+2); |
||||
rbdf->cbd_sc = 0; |
||||
tbdf = rbdf + 1; |
||||
tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; |
||||
tbdf->cbd_sc = 0; |
||||
|
||||
/* Set up the uart parameters in the parameter ram.
|
||||
*/ |
||||
up->smc_rbase = dpaddr; |
||||
up->smc_tbase = dpaddr+sizeof(cbd_t); |
||||
up->smc_rfcr = SMC_EB; |
||||
up->smc_tfcr = SMC_EB; |
||||
|
||||
/* Set UART mode, 8 bit, no parity, one stop.
|
||||
* Enable receive and transmit. |
||||
*/ |
||||
sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; |
||||
|
||||
/* Mask all interrupts and remove anything pending.
|
||||
*/ |
||||
sp->smc_smcm = 0; |
||||
sp->smc_smce = 0xff; |
||||
|
||||
/* Set up the baud rate generator.
|
||||
*/ |
||||
smc1_setbrg (); |
||||
|
||||
/* Make the first buffer the only buffer.
|
||||
*/ |
||||
tbdf->cbd_sc |= BD_SC_WRAP; |
||||
rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; |
||||
|
||||
/* Single character receive.
|
||||
*/ |
||||
up->smc_mrblr = 1; |
||||
up->smc_maxidl = 0; |
||||
|
||||
/* Initialize Tx/Rx parameters.
|
||||
*/ |
||||
|
||||
while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ |
||||
; |
||||
|
||||
cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG; |
||||
|
||||
while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ |
||||
; |
||||
|
||||
/* Enable transmitter/receiver.
|
||||
*/ |
||||
sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
void smc1_putc(const char c) |
||||
{ |
||||
volatile cbd_t *tbdf; |
||||
volatile char *buf; |
||||
volatile smc_uart_t *up; |
||||
volatile immap_t *im = (immap_t *)CFG_IMMR; |
||||
volatile cpm8xx_t *cpmp = &(im->im_cpm); |
||||
|
||||
up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; |
||||
|
||||
tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase]; |
||||
|
||||
/* Wait for last character to go.
|
||||
*/ |
||||
|
||||
buf = (char *)tbdf->cbd_bufaddr; |
||||
|
||||
*buf = c; |
||||
tbdf->cbd_datlen = 1; |
||||
tbdf->cbd_sc |= BD_SC_READY; |
||||
__asm__("eieio"); |
||||
|
||||
while (tbdf->cbd_sc & BD_SC_READY) { |
||||
WATCHDOG_RESET (); |
||||
__asm__("eieio"); |
||||
} |
||||
} |
||||
|
||||
int smc1_getc(void) |
||||
{ |
||||
volatile cbd_t *rbdf; |
||||
volatile unsigned char *buf; |
||||
volatile smc_uart_t *up; |
||||
volatile immap_t *im = (immap_t *)CFG_IMMR; |
||||
volatile cpm8xx_t *cpmp = &(im->im_cpm); |
||||
unsigned char c; |
||||
|
||||
up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; |
||||
|
||||
rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase]; |
||||
|
||||
/* Wait for character to show up.
|
||||
*/ |
||||
buf = (unsigned char *)rbdf->cbd_bufaddr; |
||||
|
||||
while (rbdf->cbd_sc & BD_SC_EMPTY) |
||||
WATCHDOG_RESET (); |
||||
|
||||
c = *buf; |
||||
rbdf->cbd_sc |= BD_SC_EMPTY; |
||||
|
||||
return(c); |
||||
} |
||||
|
||||
int smc1_tstc(void) |
||||
{ |
||||
volatile cbd_t *rbdf; |
||||
volatile smc_uart_t *up; |
||||
volatile immap_t *im = (immap_t *)CFG_IMMR; |
||||
volatile cpm8xx_t *cpmp = &(im->im_cpm); |
||||
|
||||
up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; |
||||
|
||||
rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase]; |
||||
|
||||
return(!(rbdf->cbd_sc & BD_SC_EMPTY)); |
||||
} |
||||
|
||||
/* search for keyboard and register it if found */ |
||||
int drv_keyboard_init(void) |
||||
{ |
||||
int error = 0; |
||||
device_t kbd_dev; |
||||
|
||||
if (0) { |
||||
/* register the keyboard */ |
||||
memset (&kbd_dev, 0, sizeof(device_t)); |
||||
strcpy(kbd_dev.name, "kbd"); |
||||
kbd_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; |
||||
kbd_dev.putc = NULL; |
||||
kbd_dev.puts = NULL; |
||||
kbd_dev.getc = smc1_getc; |
||||
kbd_dev.tstc = smc1_tstc; |
||||
error = device_register (&kbd_dev); |
||||
} else { |
||||
lcd_is_enabled = 0; |
||||
lcd_disable(); |
||||
} |
||||
return error; |
||||
} |
||||
@ -0,0 +1,292 @@ |
||||
/*
|
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include "mpc8xx.h" |
||||
#include <linux/mtd/doc2000.h> |
||||
|
||||
extern int kbd_init(void); |
||||
extern int drv_kbd_init(void); |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
static long int dram_size (long int, long int *, long int); |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
#define _NOT_USED_ 0xFFFFFFFF |
||||
|
||||
const uint sdram_table[] = |
||||
{ |
||||
/*
|
||||
* Single Read. (Offset 0 in UPMA RAM) |
||||
*/ |
||||
0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, |
||||
0x1FF77C47, /* last */ |
||||
/*
|
||||
* SDRAM Initialization (offset 5 in UPMA RAM) |
||||
* |
||||
* This is no UPM entry point. The following definition uses |
||||
* the remaining space to establish an initialization |
||||
* sequence, which is executed by a RUN command. |
||||
* |
||||
*/ |
||||
0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */ |
||||
/*
|
||||
* Burst Read. (Offset 8 in UPMA RAM) |
||||
*/ |
||||
0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, |
||||
0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
/*
|
||||
* Single Write. (Offset 18 in UPMA RAM) |
||||
*/ |
||||
0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
/*
|
||||
* Burst Write. (Offset 20 in UPMA RAM) |
||||
*/ |
||||
0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, |
||||
0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ |
||||
_NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
/*
|
||||
* Refresh (Offset 30 in UPMA RAM) |
||||
*/ |
||||
0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, |
||||
0xFFFFFC84, 0xFFFFFC07, /* last */ |
||||
_NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
/*
|
||||
* Exception. (Offset 3c in UPMA RAM) |
||||
*/ |
||||
0x1FF7FC07, /* last */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
}; |
||||
|
||||
const uint static_table[] = |
||||
{ |
||||
/*
|
||||
* Single Read. (Offset 0 in UPMA RAM) |
||||
*/ |
||||
0x0FFFFC04, 0x0FF3FC04, 0x0FF3CC04, 0x0FF3CC04, |
||||
0x0FF3EC04, 0x0FF3CC00, 0x0FF7FC04, 0x3FFFFC04, |
||||
0xFFFFFC04, 0xFFFFFC05, /* last */ |
||||
_NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
/*
|
||||
* Single Write. (Offset 18 in UPMA RAM) |
||||
*/ |
||||
0x0FFFFC04, 0x00FFFC04, 0x00FFFC04, 0x00FFFC04, |
||||
0x01FFFC00, 0x3FFFFC04, 0xFFFFFC04, 0xFFFFFC05, /* last */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
}; |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
/*
|
||||
* Check Board Identity: |
||||
* |
||||
* Test TQ ID string (TQM8xx...) |
||||
* If present, check for "L" type (no second DRAM bank), |
||||
* otherwise "L" type is assumed as default. |
||||
* |
||||
* Return 1 for "L" type, 0 else. |
||||
*/ |
||||
|
||||
int checkboard (void) |
||||
{ |
||||
unsigned char *s = getenv("serial#"); |
||||
|
||||
if (!s || strncmp(s, "TQM8", 4)) { |
||||
printf ("### No HW ID - assuming RBC823\n"); |
||||
return (0); |
||||
} |
||||
|
||||
puts(s); |
||||
putc ('\n'); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
long int initdram (int board_type) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
||||
long int size_b0, size8, size9; |
||||
|
||||
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); |
||||
|
||||
/*
|
||||
* 1 Bank of 64Mbit x 2 devices
|
||||
*/ |
||||
memctl->memc_mptpr = CFG_MPTPR_1BK_4K; |
||||
memctl->memc_mar = 0x00000088; |
||||
|
||||
/*
|
||||
* Map controller SDRAM bank 0 |
||||
*/ |
||||
memctl->memc_or4 = CFG_OR4_PRELIM; |
||||
memctl->memc_br4 = CFG_BR4_PRELIM; |
||||
memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ |
||||
udelay(200); |
||||
|
||||
/*
|
||||
* Perform SDRAM initializsation sequence
|
||||
*/ |
||||
memctl->memc_mcr = 0x80008105; /* SDRAM bank 0 */ |
||||
udelay(1); |
||||
memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_8X; |
||||
udelay(200); |
||||
memctl->memc_mcr = 0x80008130; /* SDRAM bank 0 - execute twice */ |
||||
udelay(1); |
||||
memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_4X; |
||||
udelay(200);
|
||||
|
||||
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ |
||||
udelay (1000); |
||||
|
||||
/*
|
||||
* Preliminary prescaler for refresh (depends on number of |
||||
* banks): This value is selected for four cycles every 62.4 us |
||||
* with two SDRAM banks or four cycles every 31.2 us with one |
||||
* bank. It will be adjusted after memory sizing. |
||||
*/ |
||||
memctl->memc_mptpr = CFG_MPTPR_2BK_4K; // 16: but should be: CFG_MPTPR_1BK_4K
|
||||
|
||||
/*
|
||||
* Check Bank 0 Memory Size for re-configuration |
||||
* |
||||
* try 8 column mode |
||||
*/ |
||||
size8 = dram_size (CFG_MAMR_8COL, (ulong *)SDRAM_BASE4_PRELIM, SDRAM_MAX_SIZE); |
||||
udelay (1000); |
||||
|
||||
/*
|
||||
* try 9 column mode |
||||
*/ |
||||
size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE4_PRELIM, SDRAM_MAX_SIZE); |
||||
|
||||
if (size8 < size9) { /* leave configuration at 9 columns */ |
||||
size_b0 = size9; |
||||
/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ |
||||
} else { /* back to 8 columns */ |
||||
size_b0 = size8; |
||||
memctl->memc_mamr = CFG_MAMR_8COL; |
||||
udelay(500); |
||||
/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ |
||||
} |
||||
|
||||
udelay (1000); |
||||
|
||||
/*
|
||||
* Adjust refresh rate depending on SDRAM type, both banks |
||||
* For types > 128 MBit leave it at the current (fast) rate |
||||
*/ |
||||
if ((size_b0 < 0x02000000) ) { |
||||
/* reduce to 15.6 us (62.4 us / quad) */ |
||||
memctl->memc_mptpr = CFG_MPTPR_2BK_4K; |
||||
udelay(1000); |
||||
} |
||||
|
||||
/* SDRAM Bank 0 is bigger - map first */ |
||||
|
||||
memctl->memc_or4 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; |
||||
memctl->memc_br4 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; |
||||
|
||||
udelay(10000); |
||||
|
||||
return (size_b0); |
||||
} |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
/*
|
||||
* Check memory range for valid RAM. A simple memory test determines |
||||
* the actually available RAM size between addresses `base' and |
||||
* `base + maxsize'. Some (not all) hardware errors are detected: |
||||
* - short between address lines |
||||
* - short between data lines |
||||
*/ |
||||
|
||||
static long int dram_size (long int mamr_value, long int *base, long int maxsize) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
||||
volatile long int *addr; |
||||
long int cnt, val; |
||||
|
||||
memctl->memc_mamr = mamr_value; |
||||
|
||||
for (cnt = maxsize/sizeof(long)/2; cnt > 0; cnt >>= 1) { |
||||
addr = base + cnt; /* pointer arith! */ |
||||
|
||||
*addr = ~cnt; |
||||
} |
||||
|
||||
/* write 0 to base address */ |
||||
addr = base; |
||||
*addr = 0; |
||||
|
||||
/* check at base address */ |
||||
if ((val = *addr) != 0) { |
||||
return (0); |
||||
} |
||||
|
||||
for (cnt = 1; cnt < maxsize/sizeof(long) ; cnt <<= 1) { |
||||
addr = base + cnt; /* pointer arith! */ |
||||
|
||||
val = *addr; |
||||
|
||||
if (val != (~cnt)) { |
||||
return (cnt * sizeof(long)); |
||||
} |
||||
} |
||||
return cnt * sizeof(long); |
||||
/* NOTREACHED */ |
||||
} |
||||
|
||||
void doc_init(void) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
||||
|
||||
upmconfig(UPMB, (uint *)static_table, sizeof(static_table)/sizeof(uint)); |
||||
memctl->memc_mbmr = MAMR_DSA_1_CYCL; |
||||
|
||||
doc_probe(FLASH_BASE1_PRELIM); |
||||
} |
||||
|
||||
@ -0,0 +1,133 @@ |
||||
/* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/mpc8xx/start.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_ppc/ppcstring.o (.text) |
||||
lib_generic/vsprintf.o (.text) |
||||
lib_generic/crc32.o (.text) |
||||
lib_generic/zlib.o (.text) |
||||
|
||||
. = env_offset; |
||||
common/environment.o(.text) |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,418 @@ |
||||
/*
|
||||
* (C) Copyright 2000, 2001 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* Modified by Udi Finkelstein udif@udif.com |
||||
* For the RBC823 board. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ |
||||
#define CONFIG_RBC823 1 /* ...on a RBC823 module */ |
||||
|
||||
|
||||
#if 0 |
||||
#define DEBUG 1 |
||||
#define CONFIG_LAST_STAGE_INIT |
||||
#endif |
||||
#define CONFIG_KEYBOARD 1 /* This board has a custom keybpard */ |
||||
#define CONFIG_LCD 1 /* use LCD controller ... */ |
||||
#define CONFIG_HITACHI_SP19X001_Z1A /* The LCD type we use */ |
||||
|
||||
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ |
||||
#undef CONFIG_8xx_CONS_SMC1 |
||||
#undef CONFIG_8xx_CONS_NONE |
||||
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ |
||||
#if 1 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#endif |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
#define CONFIG_8xx_GCLK_FREQ 48000000L |
||||
|
||||
#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"bootp; " \
|
||||
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
|
||||
"bootm" |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#define CONFIG_STATUS_LED 1 /* Status LED enabled */ |
||||
|
||||
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ |
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) |
||||
|
||||
#undef CONFIG_MAC_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
#undef CONFIG_RTC_MPC8xx /* don't use internal RTC of MPC8xx (no battery) */ |
||||
|
||||
#define CONFIG_HARD_I2C |
||||
#define CFG_I2C_SPEED 40000 |
||||
#define CFG_I2C_SLAVE 0xfe |
||||
#define CFG_I2C_EEPROM_ADDR 0x50 |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 |
||||
#define CFG_EEPROM_WRITE_BITS 4 |
||||
#define CFG_EEPROM_WRITE_DELAY_MS 10 |
||||
|
||||
#define CONFIG_COMMANDS ( CFG_CMD_ALL & \ |
||||
~CFG_CMD_PCMCIA & \
|
||||
~CFG_CMD_IDE & \
|
||||
~CFG_CMD_PCI & \
|
||||
~CFG_CMD_FDC & \
|
||||
~CFG_CMD_HWFLOW & \
|
||||
~CFG_CMD_FDOS & \
|
||||
~CFG_CMD_SCSI & \
|
||||
~CFG_CMD_SETGETDCR & \
|
||||
~CFG_CMD_BSP & \
|
||||
~CFG_CMD_USB & \
|
||||
~CFG_CMD_VFD & \
|
||||
~CFG_CMD_SPI & \
|
||||
/* ~CFG_CMD_I2C & */ \
|
||||
~CFG_CMD_IRQ & \
|
||||
~CFG_CMD_NAND & \
|
||||
~CFG_CMD_JFFS2 & \
|
||||
~CFG_CMD_DTT & \
|
||||
~CFG_CMD_MII & \
|
||||
/*~CFG_CMD_NET &*/ \
|
||||
/*~CFG_CMD_ELF &*/ \
|
||||
/* ~CFG_CMD_EEPROM & */ \
|
||||
~CFG_CMD_DATE ) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x0100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xFF000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0xFFF00000 |
||||
#if defined(DEBUG) |
||||
#define CFG_MONITOR_LEN (384 << 10) /* Reserve 256 kB for Monitor */ |
||||
#else |
||||
#define CFG_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */ |
||||
#endif |
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ |
||||
#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
/*
|
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
*/ |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWRI | SYPCR_SWP) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_FRC) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit |
||||
* |
||||
*/ |
||||
|
||||
/*
|
||||
* for 48 MHz, we use a 4 MHz clock * 12 |
||||
*/ |
||||
#define CFG_PLPRCR \ |
||||
( (12-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_LOLRE ) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
#define CFG_SCCR (SCCR_RTDIV | SCCR_RTSEL | SCCR_CRQEN | \ |
||||
SCCR_PRQEN | SCCR_EBDF00 | \
|
||||
SCCR_COM01 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD001 | \
|
||||
SCCR_DFALCD00) |
||||
|
||||
#ifdef NOT_USED |
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CFG_PCMCIA_MEM_ADDR (0xE0000000) |
||||
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_DMA_ADDR (0xE4000000) |
||||
#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) |
||||
#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_IO_ADDR (0xEC000000) |
||||
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
#define CONFIG_IDE_PCCARD 1 /* Use IDE with PC Card Adapter */ |
||||
|
||||
#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */ |
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */ |
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */ |
||||
|
||||
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
||||
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ |
||||
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000 |
||||
|
||||
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR |
||||
|
||||
/* Offset for data I/O */ |
||||
#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) |
||||
|
||||
/* Offset for normal register accesses */ |
||||
#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) |
||||
|
||||
/* Offset for alternate registers */ |
||||
#define CFG_ATA_ALT_OFFSET 0x0100 |
||||
|
||||
#endif |
||||
|
||||
/************************************************************
|
||||
* Disk-On-Chip configuration |
||||
************************************************************/ |
||||
#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ |
||||
#define CFG_DOC_SHORT_TIMEOUT |
||||
#define CFG_DOC_SUPPORT_2000 |
||||
#define CFG_DOC_SUPPORT_MILLENNIUM |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
/*#define CFG_DER 0x2002000F*/ |
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#define CFG_DER 0 |
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|
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/*
|
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* Init Memory Controller: |
||||
* |
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* BR0/1 and OR0/1 (FLASH) |
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*/ |
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|
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#define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */ |
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#define FLASH_BASE1_PRELIM 0x04000000 /* D.O.C Millenium */ |
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|
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/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any) |
||||
* but not too much to meddle with FLASH accesses |
||||
*/ |
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#define CFG_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */ |
||||
|
||||
/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 7, EHTR = 1 */ |
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR) |
||||
|
||||
#define CFG_OR_TIMING_MSYS (OR_ACS_DIV1 | OR_BI) |
||||
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) |
||||
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V) |
||||
|
||||
#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_MSYS) |
||||
#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | \ |
||||
BR_PS_8 | BR_V) |
||||
|
||||
/*
|
||||
* BR4 and OR4 (SDRAM) |
||||
* |
||||
*/ |
||||
#define SDRAM_BASE4_PRELIM 0x00000000 /* SDRAM bank #0 */ |
||||
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ |
||||
|
||||
/*
|
||||
* SDRAM timing: |
||||
*/ |
||||
#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM) |
||||
|
||||
#define CFG_OR4_PRELIM (~(SDRAM_MAX_SIZE-1) | CFG_OR_TIMING_SDRAM ) |
||||
#define CFG_BR4_PRELIM ((SDRAM_BASE4_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
*/ |
||||
|
||||
/* periodic timer for refresh */ |
||||
#define CFG_MAMR_PTA 187 /* start with divider for 48 MHz */ |
||||
|
||||
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ |
||||
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
||||
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
||||
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
||||
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM |
||||
*/ |
||||
|
||||
/* 8 column SDRAM */ |
||||
#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
/* 9 column SDRAM */ |
||||
#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
|
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue