TI: DaVinci DM646x: Update flag used to represent DM646x SOC's

In the DaVinci specific code, we use both CONFIG_SOC_DM646X and
CONFIG_SOC_DM646x to represent DM646x specific code.
This patch changes occurrences of CONFIG_SOC_DM646x to
CONFIG_SOC_DM646X. This is because for DM644x series of SOCs we use
the flag CONFIG_SOC_DM644X. We want some uniformity.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Acked-by: Tom Rix <Tom.Rix@windriver.com>
master
Sandeep Paulraj 15 years ago committed by Tom Rix
parent 3d6436abc3
commit 6824fda182
  1. 4
      include/asm-arm/arch-davinci/emac_defs.h
  2. 2
      include/asm-arm/arch-davinci/nand_defs.h

@ -50,7 +50,7 @@
#define EMAC_MDIO_BASE_ADDR (0x01c84000)
#endif
#ifdef CONFIG_SOC_DM646x
#ifdef CONFIG_SOC_DM646X
/* MDIO module input frequency */
#define EMAC_MDIO_BUS_FREQ 76500000
/* MDIO clock output frequency */
@ -283,7 +283,7 @@ typedef struct {
/* EMAC Wrapper Registers Structure */
typedef struct {
#if defined(CONFIG_SOC_DM646x) || defined(CONFIG_SOC_DM365)
#if defined(CONFIG_SOC_DM646X) || defined(CONFIG_SOC_DM365)
dv_reg IDVER;
dv_reg SOFTRST;
dv_reg EMCTRL;

@ -28,7 +28,7 @@
#include <asm/arch/hardware.h>
#ifdef CONFIG_SOC_DM646x
#ifdef CONFIG_SOC_DM646X
#define MASK_CLE 0x80000
#define MASK_ALE 0x40000
#else

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