Move FPGA driver which is Gen5 specific code into Gen5 driver file and keeping common FPGA driver intact. All the changes are still keeping in driver/fpga/ and no functional change. Subsequent patch would move FPGA manager driver from arch/arm into driver/fpga/. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>master
Tien Fong Chee
7 years ago
committed by
Marek Vasut
parent
6a34af5b41
commit
6867e19a43
@ -0,0 +1,68 @@ |
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/*
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* Copyright (C) 2012-2017 Altera Corporation <www.altera.com> |
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* All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#ifndef _FPGA_MANAGER_GEN5_H_ |
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#define _FPGA_MANAGER_GEN5_H_ |
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#define FPGAMGRREGS_STAT_MODE_MASK 0x7 |
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#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8 |
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#define FPGAMGRREGS_STAT_MSEL_LSB 3 |
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#define FPGAMGRREGS_CTRL_CFGWDTH_MASK BIT(9) |
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#define FPGAMGRREGS_CTRL_AXICFGEN_MASK BIT(8) |
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#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK BIT(2) |
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#define FPGAMGRREGS_CTRL_NCE_MASK BIT(1) |
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#define FPGAMGRREGS_CTRL_EN_MASK BIT(0) |
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#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6 |
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#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK BIT(3) |
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#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK BIT(2) |
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#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK BIT(1) |
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#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK BIT(0) |
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/* FPGA Mode */ |
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#define FPGAMGRREGS_MODE_FPGAOFF 0x0 |
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#define FPGAMGRREGS_MODE_RESETPHASE 0x1 |
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#define FPGAMGRREGS_MODE_CFGPHASE 0x2 |
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#define FPGAMGRREGS_MODE_INITPHASE 0x3 |
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#define FPGAMGRREGS_MODE_USERMODE 0x4 |
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#define FPGAMGRREGS_MODE_UNKNOWN 0x5 |
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#ifndef __ASSEMBLY__ |
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struct socfpga_fpga_manager { |
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/* FPGA Manager Module */ |
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u32 stat; /* 0x00 */ |
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u32 ctrl; |
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u32 dclkcnt; |
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u32 dclkstat; |
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u32 gpo; /* 0x10 */ |
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u32 gpi; |
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u32 misci; /* 0x18 */ |
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u32 _pad_0x1c_0x82c[517]; |
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/* Configuration Monitor (MON) Registers */ |
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u32 gpio_inten; /* 0x830 */ |
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u32 gpio_intmask; |
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u32 gpio_inttype_level; |
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u32 gpio_int_polarity; |
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u32 gpio_intstatus; /* 0x840 */ |
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u32 gpio_raw_intstatus; |
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u32 _pad_0x848; |
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u32 gpio_porta_eoi; |
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u32 gpio_ext_porta; /* 0x850 */ |
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u32 _pad_0x854_0x85c[3]; |
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u32 gpio_1s_sync; /* 0x860 */ |
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u32 _pad_0x864_0x868[2]; |
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u32 gpio_ver_id_code; |
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u32 gpio_config_reg2; /* 0x870 */ |
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u32 gpio_config_reg1; |
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}; |
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#endif /* __ASSEMBLY__ */ |
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#endif /* _FPGA_MANAGER_GEN5_H_ */ |
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@ -0,0 +1,252 @@ |
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/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com> |
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* All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <linux/errno.h> |
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#include <asm/arch/fpga_manager.h> |
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#include <asm/arch/reset_manager.h> |
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#include <asm/arch/system_manager.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#define FPGA_TIMEOUT_CNT 0x1000000 |
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static struct socfpga_fpga_manager *fpgamgr_regs = |
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(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS; |
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static struct socfpga_system_manager *sysmgr_regs = |
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(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; |
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/* Set CD ratio */ |
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static void fpgamgr_set_cd_ratio(unsigned long ratio) |
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{ |
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clrsetbits_le32(&fpgamgr_regs->ctrl, |
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0x3 << FPGAMGRREGS_CTRL_CDRATIO_LSB, |
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(ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB); |
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} |
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/* Start the FPGA programming by initialize the FPGA Manager */ |
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static int fpgamgr_program_init(void) |
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{ |
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unsigned long msel, i; |
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/* Get the MSEL value */ |
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msel = readl(&fpgamgr_regs->stat); |
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msel &= FPGAMGRREGS_STAT_MSEL_MASK; |
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msel >>= FPGAMGRREGS_STAT_MSEL_LSB; |
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/*
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* Set the cfg width |
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* If MSEL[3] = 1, cfg width = 32 bit |
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*/ |
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if (msel & 0x8) { |
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setbits_le32(&fpgamgr_regs->ctrl, |
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FPGAMGRREGS_CTRL_CFGWDTH_MASK); |
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/* To determine the CD ratio */ |
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/* MSEL[1:0] = 0, CD Ratio = 1 */ |
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if ((msel & 0x3) == 0x0) |
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fpgamgr_set_cd_ratio(CDRATIO_x1); |
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/* MSEL[1:0] = 1, CD Ratio = 4 */ |
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else if ((msel & 0x3) == 0x1) |
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fpgamgr_set_cd_ratio(CDRATIO_x4); |
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/* MSEL[1:0] = 2, CD Ratio = 8 */ |
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else if ((msel & 0x3) == 0x2) |
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fpgamgr_set_cd_ratio(CDRATIO_x8); |
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} else { /* MSEL[3] = 0 */ |
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clrbits_le32(&fpgamgr_regs->ctrl, |
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FPGAMGRREGS_CTRL_CFGWDTH_MASK); |
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/* To determine the CD ratio */ |
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/* MSEL[1:0] = 0, CD Ratio = 1 */ |
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if ((msel & 0x3) == 0x0) |
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fpgamgr_set_cd_ratio(CDRATIO_x1); |
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/* MSEL[1:0] = 1, CD Ratio = 2 */ |
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else if ((msel & 0x3) == 0x1) |
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fpgamgr_set_cd_ratio(CDRATIO_x2); |
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/* MSEL[1:0] = 2, CD Ratio = 4 */ |
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else if ((msel & 0x3) == 0x2) |
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fpgamgr_set_cd_ratio(CDRATIO_x4); |
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} |
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/* To enable FPGA Manager configuration */ |
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clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK); |
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/* To enable FPGA Manager drive over configuration line */ |
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setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK); |
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/* Put FPGA into reset phase */ |
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setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK); |
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/* (1) wait until FPGA enter reset phase */ |
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for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { |
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if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_RESETPHASE) |
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break; |
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} |
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/* If not in reset state, return error */ |
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if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_RESETPHASE) { |
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puts("FPGA: Could not reset\n"); |
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return -1; |
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} |
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/* Release FPGA from reset phase */ |
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clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK); |
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/* (2) wait until FPGA enter configuration phase */ |
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for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { |
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if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_CFGPHASE) |
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break; |
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} |
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/* If not in configuration state, return error */ |
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if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_CFGPHASE) { |
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puts("FPGA: Could not configure\n"); |
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return -2; |
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} |
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/* Clear all interrupts in CB Monitor */ |
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writel(0xFFF, &fpgamgr_regs->gpio_porta_eoi); |
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/* Enable AXI configuration */ |
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setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK); |
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return 0; |
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} |
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/* Ensure the FPGA entering config done */ |
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static int fpgamgr_program_poll_cd(void) |
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{ |
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const uint32_t mask = FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK | |
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FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK; |
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unsigned long reg, i; |
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/* (3) wait until full config done */ |
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for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { |
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reg = readl(&fpgamgr_regs->gpio_ext_porta); |
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/* Config error */ |
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if (!(reg & mask)) { |
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printf("FPGA: Configuration error.\n"); |
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return -3; |
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} |
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/* Config done without error */ |
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if (reg & mask) |
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break; |
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} |
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/* Timeout happened, return error */ |
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if (i == FPGA_TIMEOUT_CNT) { |
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printf("FPGA: Timeout waiting for program.\n"); |
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return -4; |
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} |
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/* Disable AXI configuration */ |
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clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK); |
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return 0; |
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} |
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/* Ensure the FPGA entering init phase */ |
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static int fpgamgr_program_poll_initphase(void) |
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{ |
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unsigned long i; |
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/* Additional clocks for the CB to enter initialization phase */ |
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if (fpgamgr_dclkcnt_set(0x4)) |
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return -5; |
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/* (4) wait until FPGA enter init phase or user mode */ |
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for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { |
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if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_INITPHASE) |
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break; |
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if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE) |
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break; |
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} |
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/* If not in configuration state, return error */ |
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if (i == FPGA_TIMEOUT_CNT) |
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return -6; |
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return 0; |
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} |
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/* Ensure the FPGA entering user mode */ |
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static int fpgamgr_program_poll_usermode(void) |
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{ |
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unsigned long i; |
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/* Additional clocks for the CB to exit initialization phase */ |
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if (fpgamgr_dclkcnt_set(0x5000)) |
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return -7; |
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/* (5) wait until FPGA enter user mode */ |
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for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { |
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if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE) |
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break; |
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} |
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/* If not in configuration state, return error */ |
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if (i == FPGA_TIMEOUT_CNT) |
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return -8; |
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/* To release FPGA Manager drive over configuration line */ |
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clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK); |
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return 0; |
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} |
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/*
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* FPGA Manager to program the FPGA. This is the interface used by FPGA driver. |
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* Return 0 for sucess, non-zero for error. |
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*/ |
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int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) |
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{ |
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unsigned long status; |
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if ((uint32_t)rbf_data & 0x3) { |
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puts("FPGA: Unaligned data, realign to 32bit boundary.\n"); |
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return -EINVAL; |
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} |
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/* Prior programming the FPGA, all bridges need to be shut off */ |
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/* Disable all signals from hps peripheral controller to fpga */ |
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writel(0, &sysmgr_regs->fpgaintfgrp_module); |
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/* Disable all signals from FPGA to HPS SDRAM */ |
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#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080 |
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writel(0, SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_FPGAPORTRST_ADDRESS); |
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/* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */ |
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socfpga_bridges_reset(1); |
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/* Unmap the bridges from NIC-301 */ |
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writel(0x1, SOCFPGA_L3REGS_ADDRESS); |
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/* Initialize the FPGA Manager */ |
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status = fpgamgr_program_init(); |
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if (status) |
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return status; |
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/* Write the RBF data to FPGA Manager */ |
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fpgamgr_program_write(rbf_data, rbf_size); |
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/* Ensure the FPGA entering config done */ |
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status = fpgamgr_program_poll_cd(); |
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if (status) |
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return status; |
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/* Ensure the FPGA entering init phase */ |
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status = fpgamgr_program_poll_initphase(); |
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if (status) |
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return status; |
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/* Ensure the FPGA entering user mode */ |
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return fpgamgr_program_poll_usermode(); |
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} |
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