Markus Klotzbcher
19 years ago
committed by
Markus Klotzbcher
parent
0377dca227
commit
6949328d7d
@ -1,434 +0,0 @@ |
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/*
|
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* (C) Copyright 2001 |
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
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* |
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* (C) Copyright 2001 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <linux/byteorder/swab.h> |
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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/* Board support for 1 or 2 flash devices */ |
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#define FLASH_PORT_WIDTH32 |
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#undef FLASH_PORT_WIDTH16 |
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#ifdef FLASH_PORT_WIDTH16 |
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#define FLASH_PORT_WIDTH ushort |
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#define FLASH_PORT_WIDTHV vu_short |
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#define SWAP(x) __swab16(x) |
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#else |
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#define FLASH_PORT_WIDTH ulong |
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#define FLASH_PORT_WIDTHV vu_long |
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#define SWAP(x) __swab32(x) |
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#endif |
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|
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#define FPW FLASH_PORT_WIDTH |
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#define FPWV FLASH_PORT_WIDTHV |
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#define mb() __asm__ __volatile__ ("" : : : "memory") |
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|
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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static ulong flash_get_size (FPW *addr, flash_info_t *info); |
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static int write_data (flash_info_t *info, ulong dest, FPW data); |
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static void flash_get_offsets (ulong base, flash_info_t *info); |
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void inline spin_wheel (void); |
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|
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/*-----------------------------------------------------------------------
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*/ |
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unsigned long flash_init (void) |
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{ |
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#if 0 |
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int i; |
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ulong size = 0; |
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for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { |
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switch (i) { |
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case 0: |
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flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); |
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flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); |
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break; |
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case 1: |
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flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]); |
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flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); |
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break; |
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default: |
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panic ("configured too many flash banks!\n"); |
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break; |
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} |
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size += flash_info[i].size; |
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} |
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|
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/* Protect monitor and environment sectors
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*/ |
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flash_protect ( FLAG_PROTECT_SET, |
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CFG_FLASH_BASE, |
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CFG_FLASH_BASE + monitor_flash_len - 1, |
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&flash_info[0] ); |
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flash_protect ( FLAG_PROTECT_SET, |
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CFG_ENV_ADDR, |
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CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] ); |
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return size; |
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#endif |
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return 0; |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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static void flash_get_offsets (ulong base, flash_info_t *info) |
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{ |
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int i; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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return; |
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} |
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { |
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for (i = 0; i < info->sector_count; i++) { |
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info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); |
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info->protect[i] = 0; |
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} |
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} |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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void flash_print_info (flash_info_t *info) |
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{ |
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int i; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("missing or unknown FLASH type\n"); |
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return; |
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} |
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switch (info->flash_id & FLASH_VENDMASK) { |
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case FLASH_MAN_INTEL: |
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printf ("INTEL "); |
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break; |
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default: |
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printf ("Unknown Vendor "); |
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break; |
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} |
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switch (info->flash_id & FLASH_TYPEMASK) { |
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case FLASH_28F128J3A: |
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printf ("28F128J3A\n"); |
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break; |
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default: |
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printf ("Unknown Chip Type\n"); |
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break; |
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} |
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printf (" Size: %ld MB in %d Sectors\n", |
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info->size >> 20, info->sector_count); |
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printf (" Sector Start Addresses:"); |
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for (i = 0; i < info->sector_count; ++i) { |
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if ((i % 5) == 0) |
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printf ("\n "); |
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printf (" %08lX%s", |
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info->start[i], |
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info->protect[i] ? " (RO)" : " "); |
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} |
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printf ("\n"); |
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return; |
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} |
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/*
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* The following code cannot be run from FLASH! |
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*/ |
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static ulong flash_get_size (FPW *addr, flash_info_t *info) |
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{ |
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volatile FPW value; |
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/* Write auto select command: read Manufacturer ID */ |
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addr[0x5555] = (FPW) 0x00AA00AA; |
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addr[0x2AAA] = (FPW) 0x00550055; |
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addr[0x5555] = (FPW) 0x00900090; |
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mb (); |
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value = addr[0]; |
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switch (value) { |
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case (FPW) INTEL_MANUFACT: |
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info->flash_id = FLASH_MAN_INTEL; |
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break; |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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info->sector_count = 0; |
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info->size = 0; |
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addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ |
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return (0); /* no or unknown flash */ |
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} |
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mb (); |
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value = addr[1]; /* device ID */ |
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switch (value) { |
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case (FPW) INTEL_ID_28F128J3A: |
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info->flash_id += FLASH_28F128J3A; |
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info->sector_count = 128; |
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info->size = 0x02000000; |
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break; /* => 16 MB */ |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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break; |
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} |
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if (info->sector_count > CFG_MAX_FLASH_SECT) { |
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printf ("** ERROR: sector count %d > max (%d) **\n", |
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info->sector_count, CFG_MAX_FLASH_SECT); |
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info->sector_count = CFG_MAX_FLASH_SECT; |
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} |
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addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ |
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return (info->size); |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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int flash_erase (flash_info_t *info, int s_first, int s_last) |
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{ |
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int flag, prot, sect; |
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ulong type, start, last; |
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int rcode = 0; |
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if ((s_first < 0) || (s_first > s_last)) { |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("- missing\n"); |
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} else { |
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printf ("- no sectors to erase\n"); |
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} |
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return 1; |
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} |
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type = (info->flash_id & FLASH_VENDMASK); |
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if ((type != FLASH_MAN_INTEL)) { |
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printf ("Can't erase unknown flash type %08lx - aborted\n", |
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info->flash_id); |
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return 1; |
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} |
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prot = 0; |
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for (sect = s_first; sect <= s_last; ++sect) { |
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if (info->protect[sect]) { |
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prot++; |
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} |
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} |
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if (prot) { |
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printf ("- Warning: %d protected sectors will not be erased!\n", |
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prot); |
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} else { |
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printf ("\n"); |
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} |
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start = get_timer (0); |
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last = start; |
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts (); |
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/* Start erase on unprotected sectors */ |
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for (sect = s_first; sect <= s_last; sect++) { |
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if (info->protect[sect] == 0) { /* not protected */ |
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FPWV *addr = (FPWV *) (info->start[sect]); |
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FPW status; |
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printf ("Erasing sector %2d ... ", sect); |
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/* arm simple, non interrupt dependent timer */ |
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reset_timer_masked (); |
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*addr = (FPW) 0x00500050; /* clear status register */ |
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*addr = (FPW) 0x00200020; /* erase setup */ |
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*addr = (FPW) 0x00D000D0; /* erase confirm */ |
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while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { |
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if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { |
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printf ("Timeout\n"); |
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*addr = (FPW) 0x00B000B0; /* suspend erase */ |
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*addr = (FPW) 0x00FF00FF; /* reset to read mode */ |
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rcode = 1; |
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break; |
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} |
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} |
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*addr = 0x00500050; /* clear status register cmd. */ |
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*addr = 0x00FF00FF; /* resest to read mode */ |
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printf (" done\n"); |
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} |
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} |
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return rcode; |
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} |
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/*-----------------------------------------------------------------------
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* Copy memory to flash, returns: |
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* 0 - OK |
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* 1 - write timeout |
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* 2 - Flash not erased |
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* 4 - Flash not identified |
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*/ |
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int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
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{ |
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ulong cp, wp; |
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FPW data; |
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int count, i, l, rc, port_width; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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return 4; |
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} |
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/* get lower word aligned address */ |
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#ifdef FLASH_PORT_WIDTH16 |
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wp = (addr & ~1); |
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port_width = 2; |
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#else |
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wp = (addr & ~3); |
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port_width = 4; |
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#endif |
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/*
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* handle unaligned start bytes |
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*/ |
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if ((l = addr - wp) != 0) { |
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data = 0; |
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for (i = 0, cp = wp; i < l; ++i, ++cp) { |
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data = (data << 8) | (*(uchar *) cp); |
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} |
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for (; i < port_width && cnt > 0; ++i) { |
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data = (data << 8) | *src++; |
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--cnt; |
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++cp; |
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} |
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for (; cnt == 0 && i < port_width; ++i, ++cp) { |
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data = (data << 8) | (*(uchar *) cp); |
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} |
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if ((rc = write_data (info, wp, SWAP (data))) != 0) { |
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return (rc); |
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} |
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wp += port_width; |
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} |
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/*
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* handle word aligned part |
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*/ |
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count = 0; |
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while (cnt >= port_width) { |
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data = 0; |
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for (i = 0; i < port_width; ++i) { |
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data = (data << 8) | *src++; |
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} |
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if ((rc = write_data (info, wp, SWAP (data))) != 0) { |
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return (rc); |
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} |
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wp += port_width; |
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cnt -= port_width; |
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if (count++ > 0x800) { |
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spin_wheel (); |
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count = 0; |
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} |
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} |
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if (cnt == 0) { |
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return (0); |
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} |
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/*
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* handle unaligned tail bytes |
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*/ |
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data = 0; |
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for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { |
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data = (data << 8) | *src++; |
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--cnt; |
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} |
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for (; i < port_width; ++i, ++cp) { |
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data = (data << 8) | (*(uchar *) cp); |
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} |
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return (write_data (info, wp, SWAP (data))); |
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} |
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/*-----------------------------------------------------------------------
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* Write a word or halfword to Flash, returns: |
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* 0 - OK |
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* 1 - write timeout |
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* 2 - Flash not erased |
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*/ |
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static int write_data (flash_info_t *info, ulong dest, FPW data) |
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{ |
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FPWV *addr = (FPWV *) dest; |
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ulong status; |
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int flag; |
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/* Check if Flash is (sufficiently) erased */ |
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if ((*addr & data) != data) { |
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printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); |
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return (2); |
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} |
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts (); |
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*addr = (FPW) 0x00400040; /* write setup */ |
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*addr = data; |
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/* arm simple, non interrupt dependent timer */ |
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reset_timer_masked (); |
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/* wait while polling the status register */ |
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while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { |
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if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { |
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*addr = (FPW) 0x00FF00FF; /* restore read mode */ |
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return (1); |
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} |
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} |
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*addr = (FPW) 0x00FF00FF; /* restore read mode */ |
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return (0); |
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} |
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void inline spin_wheel (void) |
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{ |
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static int p = 0; |
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static char w[] = "\\/-"; |
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printf ("\010%c", w[p]); |
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(++p == 3) ? (p = 0) : 0; |
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} |
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@ -0,0 +1,306 @@ |
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/*
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* (C) Copyright 2006 DENX Software Engineering |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#if (CONFIG_COMMANDS & CFG_CMD_NAND) |
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#ifdef CONFIG_NEW_NAND_CODE |
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#include <nand.h> |
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#include <asm/arch/pxa-regs.h> |
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/*
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* hardware specific access to control-lines |
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* function borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c) |
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*/ |
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static void delta_hwcontrol(struct mtd_info *mtdinfo, int cmd) |
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{ |
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#if 0 |
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struct nand_chip *this = mtdinfo->priv; |
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ulong base = (ulong) this->IO_ADDR_W; |
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|
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switch(cmd) { |
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case NAND_CTL_SETCLE: |
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MACRO_NAND_CTL_SETCLE((unsigned long)base); |
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break; |
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case NAND_CTL_CLRCLE: |
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MACRO_NAND_CTL_CLRCLE((unsigned long)base); |
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break; |
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case NAND_CTL_SETALE: |
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MACRO_NAND_CTL_SETALE((unsigned long)base); |
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break; |
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case NAND_CTL_CLRALE: |
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MACRO_NAND_CTL_CLRALE((unsigned long)base); |
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break; |
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case NAND_CTL_SETNCE: |
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MACRO_NAND_ENABLE_CE((unsigned long)base); |
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break; |
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case NAND_CTL_CLRNCE: |
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MACRO_NAND_DISABLE_CE((unsigned long)base); |
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break; |
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} |
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#endif |
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} |
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|
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|
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/* read device ready pin */ |
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static int delta_device_ready(struct mtd_info *mtdinfo) |
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{ |
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if(NDSR & NDSR_RDY) |
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return 1; |
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else |
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return 0; |
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#if 0 |
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struct nand_chip *this = mtdinfo->priv; |
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ulong rb_gpio_pin; |
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|
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/* use the base addr to find out which chip are we dealing with */ |
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switch((ulong) this->IO_ADDR_W) { |
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case CFG_NAND0_BASE: |
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rb_gpio_pin = CFG_NAND0_RDY; |
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break; |
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case CFG_NAND1_BASE: |
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rb_gpio_pin = CFG_NAND1_RDY; |
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break; |
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default: /* this should never happen */ |
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return 0; |
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break; |
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} |
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|
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if (in32(GPIO0_IR) & rb_gpio_pin) |
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return 1; |
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#endif |
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return 0; |
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} |
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|
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static u_char delta_read_byte(struct mtd_info *mtd) |
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{ |
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/* struct nand_chip *this = mtd->priv; */ |
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unsigned long tmp; |
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|
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/* wait for read request */ |
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while(1) { |
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if(NDSR & NDSR_RDDREQ) { |
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NDSR |= NDSR_RDDREQ; |
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break; |
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} |
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} |
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|
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tmp = NDDB; |
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printk("delta_read_byte: 0x%x.\n", tmp);
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return (u_char) tmp; |
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} |
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|
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/* this is really monahans, not board specific ... */ |
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static void delta_cmdfunc(struct mtd_info *mtd, unsigned command,
|
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int column, int page_addr) |
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{ |
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/* register struct nand_chip *this = mtd->priv; */ |
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unsigned long ndcb0=0, ndcb1=0, ndcb2=0; |
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uchar command2; |
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|
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/* Clear NDSR */ |
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NDSR = 0xFFF; |
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|
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/* apparently NDCR[NDRUN] needs to be set before writing to NDCBx */ |
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NDCR |= NDCR_ND_RUN; |
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|
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/* wait for write command request
|
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* hmm, might be nice if this could time-out. mk@tbd |
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*/ |
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while(1) { |
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if(NDSR & NDSR_WRCMDREQ) { |
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NDSR |= NDSR_WRCMDREQ; /* Ack */ |
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break; |
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} |
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} |
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|
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/* if command is a double byte cmd, we set bit double cmd bit 19 */ |
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command2 = (command>>8) & 0xFF; |
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ndcb0 = command | ((command2 ? 1 : 0) << 19); |
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|
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switch (command) { |
||||
case NAND_CMD_READID: |
||||
printk("delta_cmdfunc: NAND_CMD_READID.\n"); |
||||
ndcb0 |= ((3 << 21) | (2 << 16)); |
||||
break; |
||||
case NAND_CMD_PAGEPROG: |
||||
case NAND_CMD_ERASE1: |
||||
case NAND_CMD_ERASE2: |
||||
case NAND_CMD_SEQIN: |
||||
case NAND_CMD_STATUS: |
||||
return; |
||||
case NAND_CMD_RESET: |
||||
return; |
||||
default: |
||||
printk("delta_cmdfunc: error, unkown command issued.\n"); |
||||
return; |
||||
} |
||||
|
||||
NDCB0 = ndcb0; |
||||
NDCB1 = ndcb1; |
||||
NDCB2 = ndcb2;
|
||||
} |
||||
|
||||
/*
|
||||
* Board-specific NAND initialization. The following members of the |
||||
* argument are board-specific (per include/linux/mtd/nand_new.h): |
||||
* - IO_ADDR_R?: address to read the 8 I/O lines of the flash device |
||||
* - IO_ADDR_W?: address to write the 8 I/O lines of the flash device |
||||
* - hwcontrol: hardwarespecific function for accesing control-lines |
||||
* - dev_ready: hardwarespecific function for accesing device ready/busy line |
||||
* - enable_hwecc?: function to enable (reset) hardware ecc generator. Must |
||||
* only be provided if a hardware ECC is available |
||||
* - eccmode: mode of ecc, see defines |
||||
* - chip_delay: chip dependent delay for transfering data from array to |
||||
* read regs (tR) |
||||
* - options: various chip options. They can partly be set to inform |
||||
* nand_scan about special functionality. See the defines for further |
||||
* explanation |
||||
* Members with a "?" were not set in the merged testing-NAND branch, |
||||
* so they are not set here either. |
||||
*/ |
||||
void board_nand_init(struct nand_chip *nand) |
||||
{ |
||||
unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR; |
||||
|
||||
/* set up GPIO Control Registers */ |
||||
|
||||
/* turn on the NAND Controller Clock (104 MHz @ D0) */ |
||||
CKENA |= (CKENA_4_NAND | CKENA_9_SMC); |
||||
|
||||
/* NAND Timing Parameters (in ns) */ |
||||
#define NAND_TIMING_tCH 10 |
||||
#define NAND_TIMING_tCS 0 |
||||
#define NAND_TIMING_tWH 20 |
||||
#define NAND_TIMING_tWP 40 |
||||
#define NAND_TIMING_tRH 20 |
||||
#define NAND_TIMING_tRP 40 |
||||
#define NAND_TIMING_tR 11123 |
||||
#define NAND_TIMING_tWHR 110 |
||||
#define NAND_TIMING_tAR 10 |
||||
|
||||
/* Maximum values for NAND Interface Timing Registers in DFC clock
|
||||
* periods */ |
||||
#define DFC_MAX_tCH 7 |
||||
#define DFC_MAX_tCS 7 |
||||
#define DFC_MAX_tWH 7 |
||||
#define DFC_MAX_tWP 7 |
||||
#define DFC_MAX_tRH 7 |
||||
#define DFC_MAX_tRP 15 |
||||
#define DFC_MAX_tR 65535 |
||||
#define DFC_MAX_tWHR 15 |
||||
#define DFC_MAX_tAR 15 |
||||
|
||||
#define DFC_CLOCK 104 /* DFC Clock is 104 MHz */ |
||||
#define DFC_CLK_PER_US DFC_CLOCK/1000 /* clock period in ns */ |
||||
#define MIN(x, y) ((x < y) ? x : y) |
||||
|
||||
|
||||
tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
|
||||
DFC_MAX_tCH); |
||||
tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
|
||||
DFC_MAX_tCS); |
||||
tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1), |
||||
DFC_MAX_tWH); |
||||
tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1), |
||||
DFC_MAX_tWP); |
||||
tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1), |
||||
DFC_MAX_tRH); |
||||
tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1), |
||||
DFC_MAX_tRP); |
||||
tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1), |
||||
DFC_MAX_tR); |
||||
tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1), |
||||
DFC_MAX_tWHR); |
||||
tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1), |
||||
DFC_MAX_tAR); |
||||
|
||||
|
||||
/* tRP value is split in the register */ |
||||
if(tRP & (1 << 4)) { |
||||
tRP_high = 1; |
||||
tRP &= ~(1 << 4); |
||||
} else { |
||||
tRP_high = 0; |
||||
} |
||||
|
||||
NDTR0CS0 = (tCH << 19) | |
||||
(tCS << 16) | |
||||
(tWH << 11) | |
||||
(tWP << 8) | |
||||
(tRP_high << 6) | |
||||
(tRH << 3) | |
||||
(tRP << 0); |
||||
|
||||
NDTR1CS0 = (tR << 16) | |
||||
(tWHR << 4) | |
||||
(tAR << 0); |
||||
|
||||
|
||||
|
||||
/* If it doesn't work (unlikely) think about:
|
||||
* - ecc enable |
||||
* - chip select don't care |
||||
* - read id byte count |
||||
* |
||||
* Intentionally enabled by not setting bits: |
||||
* - dma (DMA_EN) |
||||
* - page size = 512 |
||||
* - cs don't care, see if we can enable later! |
||||
* - row address start position (after second cycle) |
||||
* - pages per block = 32 |
||||
*/ |
||||
NDCR = (NDCR_ND_ARB_EN | /* enable bus arbiter */ |
||||
NDCR_SPARE_EN | /* use the spare area */ |
||||
NDCR_DWIDTH_C | /* 16bit DFC data bus width */ |
||||
NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */ |
||||
(2 << 16) | /* read id count = 7 ???? mk@tbd */ |
||||
NDCE_RDYM | /* flash device ready ir masked */ |
||||
NDCE_CS0_PAGEDM | /* ND_nCSx page done ir masked */ |
||||
NDCE_CS1_PAGEDM | |
||||
NDCE_CS0_CMDDM | /* ND_CSx command done ir masked */ |
||||
NDCE_CS1_CMDDM | |
||||
NDCE_CS0_BBDM | /* ND_CSx bad block detect ir masked */ |
||||
NDCE_CS1_BBDM | |
||||
NDCE_DBERRM | /* double bit error ir masked */
|
||||
NDCE_SBERRM | /* single bit error ir masked */ |
||||
NDCE_WRDREQM | /* write data request ir masked */ |
||||
NDCE_RDDREQM | /* read data request ir masked */ |
||||
NDCE_WRCMDREQM); /* write command request ir masked */ |
||||
|
||||
|
||||
|
||||
nand->hwcontrol = delta_hwcontrol; |
||||
nand->dev_ready = delta_device_ready; |
||||
nand->eccmode = NAND_ECC_SOFT; |
||||
nand->chip_delay = NAND_DELAY_US; |
||||
nand->options = NAND_BUSWIDTH_16; |
||||
nand->read_byte = delta_read_byte; |
||||
nand->cmdfunc = delta_cmdfunc; |
||||
/* nand->options = NAND_SAMSUNG_LP_OPTIONS; */ |
||||
} |
||||
|
||||
#else |
||||
#error "U-Boot legacy NAND support not available for delta board." |
||||
#endif |
||||
#endif |
||||
Loading…
Reference in new issue