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@ -41,6 +41,7 @@ enum clk_ids { |
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CLK_S2, |
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CLK_S3, |
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CLK_SDSRC, |
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CLK_RPCSRC, |
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CLK_SSPSRC, |
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/* Module Clocks */ |
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@ -67,6 +68,7 @@ static const struct cpg_core_clk r8a77995_core_clks[] = { |
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DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1), |
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DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), |
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DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1), |
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DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1), |
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/* Core Clock Outputs */ |
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DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1), |
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@ -89,6 +91,8 @@ static const struct cpg_core_clk r8a77995_core_clks[] = { |
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DEF_FIXED("osc", R8A77995_CLK_OSC, CLK_EXTAL, 384, 1), |
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DEF_FIXED("r", R8A77995_CLK_R, CLK_EXTAL, 1536, 1), |
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DEF_GEN3_RPC("rpc", R8A77995_CLK_RPC, CLK_RPCSRC, 0x238), |
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DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2), |
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DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1), |
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DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2), |
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@ -153,6 +157,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = { |
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DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2), |
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DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4), |
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DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4), |
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DEF_MOD("rpc", 917, R8A77995_CLK_RPC), |
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DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2), |
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DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2), |
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DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2), |
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