This patch adds support for stm32f7 family usart peripheral. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>master
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/*
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* (C) Copyright 2016 |
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* Vikas Manocha, <vikas.manocha@st.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <asm/io.h> |
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#include <serial.h> |
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#include <dm/platform_data/serial_stm32x7.h> |
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#include "serial_stm32x7.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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static int stm32_serial_setbrg(struct udevice *dev, int baudrate) |
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{ |
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struct stm32x7_serial_platdata *plat = dev->platdata; |
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struct stm32_usart *const usart = plat->base; |
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writel(plat->clock/baudrate, &usart->brr); |
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return 0; |
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} |
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static int stm32_serial_getc(struct udevice *dev) |
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{ |
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struct stm32x7_serial_platdata *plat = dev->platdata; |
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struct stm32_usart *const usart = plat->base; |
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if ((readl(&usart->sr) & USART_SR_FLAG_RXNE) == 0) |
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return -EAGAIN; |
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return readl(&usart->rd_dr); |
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} |
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static int stm32_serial_putc(struct udevice *dev, const char c) |
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{ |
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struct stm32x7_serial_platdata *plat = dev->platdata; |
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struct stm32_usart *const usart = plat->base; |
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if ((readl(&usart->sr) & USART_SR_FLAG_TXE) == 0) |
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return -EAGAIN; |
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writel(c, &usart->tx_dr); |
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return 0; |
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} |
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static int stm32_serial_pending(struct udevice *dev, bool input) |
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{ |
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struct stm32x7_serial_platdata *plat = dev->platdata; |
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struct stm32_usart *const usart = plat->base; |
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if (input) |
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return readl(&usart->sr) & USART_SR_FLAG_RXNE ? 1 : 0; |
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else |
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return readl(&usart->sr) & USART_SR_FLAG_TXE ? 0 : 1; |
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} |
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static int stm32_serial_probe(struct udevice *dev) |
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{ |
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struct stm32x7_serial_platdata *plat = dev->platdata; |
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struct stm32_usart *const usart = plat->base; |
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setbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE); |
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return 0; |
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} |
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static const struct dm_serial_ops stm32_serial_ops = { |
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.putc = stm32_serial_putc, |
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.pending = stm32_serial_pending, |
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.getc = stm32_serial_getc, |
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.setbrg = stm32_serial_setbrg, |
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}; |
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U_BOOT_DRIVER(serial_stm32) = { |
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.name = "serial_stm32x7", |
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.id = UCLASS_SERIAL, |
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.ops = &stm32_serial_ops, |
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.probe = stm32_serial_probe, |
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.flags = DM_FLAG_PRE_RELOC, |
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}; |
@ -0,0 +1,37 @@ |
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/*
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* (C) Copyright 2016 |
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* Vikas Manocha, <vikas.manocha@st.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _SERIAL_STM32_X7_ |
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#define _SERIAL_STM32_X7_ |
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struct stm32_usart { |
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u32 cr1; |
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u32 cr2; |
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u32 cr3; |
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u32 brr; |
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u32 gtpr; |
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u32 rtor; |
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u32 rqr; |
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u32 sr; |
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u32 icr; |
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u32 rd_dr; |
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u32 tx_dr; |
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}; |
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#define USART_CR1_RE (1 << 2) |
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#define USART_CR1_TE (1 << 3) |
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#define USART_CR1_UE (1 << 0) |
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#define USART_SR_FLAG_RXNE (1 << 5) |
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#define USART_SR_FLAG_TXE (1 << 7) |
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#define USART_BRR_F_MASK 0xFF |
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#define USART_BRR_M_SHIFT 4 |
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#define USART_BRR_M_MASK 0xFFF0 |
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#endif |
@ -0,0 +1,17 @@ |
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/*
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* (C) Copyright 2016 |
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* Vikas Manocha, <vikas.manocha@st.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __SERIAL_STM32x7_H |
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#define __SERIAL_STM32x7_H |
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/* Information about a serial port */ |
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struct stm32x7_serial_platdata { |
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struct stm32_usart *base; /* address of registers in physical memory */ |
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unsigned int clock; |
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}; |
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#endif /* __SERIAL_STM32x7_H */ |
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