am3517_evm: activate Ethernet PHY

Pin 30 is connected to PHY's RESET# signal, so it must be
put to high. Otherwise PHY won't be found via MDIO interface.

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>

board/logicpd/am3517evm/am3517evm.c

@@ -22,6 +22,7 @@
 #include <asm/arch/musb.h>
 #include <asm/mach-types.h>
 #include <asm/errno.h>
+#include <asm/gpio.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
 #include <linux/usb/musb.h>
@@ -31,6 +32,9 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define AM3517_IP_SW_RESET	0x48002598
+#define CPGMACSS_SW_RST		(1 << 1)
+
 /*
  * Routine: board_init
  * Description: Early hardware init.
@@ -98,6 +102,9 @@ static void am3517_evm_musb_init(void)
  */
 int misc_init_r(void)
 {
+	volatile unsigned int ctr;
+	u32 reset;
+
 #ifdef CONFIG_SYS_I2C_OMAP34XX
 	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 #endif
@@ -106,6 +113,31 @@ int misc_init_r(void)
 
 	am3517_evm_musb_init();
 
+	/* activate PHY reset */
+	gpio_direction_output(30, 0);
+	gpio_set_value(30, 0);
+
+	ctr  = 0;
+	do {
+		udelay(1000);
+		ctr++;
+	} while (ctr < 300);
+
+	/* deactivate PHY reset */
+	gpio_set_value(30, 1);
+
+	/* allow the PHY to stabilize and settle down */
+	ctr = 0;
+	do {
+		udelay(1000);
+		ctr++;
+	} while (ctr < 300);
+
+	/* ensure that the module is out of reset */
+	reset = readl(AM3517_IP_SW_RESET);
+	reset &= (~CPGMACSS_SW_RST);
+	writel(reset,AM3517_IP_SW_RESET);
+
 	return 0;
 }
 

board/logicpd/am3517evm/am3517evm.h

@@ -315,7 +315,7 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) \
 	/*SYS_nRESWARM */\
-	MUX_VAL(CP(SYS_NRESWARM),     	(IDIS | PTU | DIS | M4)) \
+	MUX_VAL(CP(SYS_NRESWARM),     	(IDIS | PTU | EN | M4)) \
 							/* - GPIO30 */\
 	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
 							 /* - PEN_IRQ */\

include/configs/am3517_evm.h

@@ -58,6 +58,11 @@
  */
 
 /*
+ * OMAP GPIO configuration
+ */
+#define CONFIG_OMAP_GPIO
+
+/*
  * NS16550 Configuration
  */
 #define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */